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-- $Header: /syn/cvs/rcs/compilers/vhdl/vhd/synattr.vhd,v 1.90.2.14.2.1 2003/07/08 18:06:01 akapoor Exp $
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-----------------------------------------------------------------------------
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-- --
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-- Copyright (c) 1997-2003 by Synplicity, Inc. All rights reserved. --
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-- --
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-- This source file may be used and distributed without restriction --
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-- provided that this copyright statement is not removed from the file --
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-- and that any derivative work contains this copyright notice. --
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-- --
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-- --
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-- Library name: synplify --
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-- Package name: attributes --
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-- --
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-- Description: This package contains declarations for synplify --
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-- attributes --
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-- --
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-- --
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-- --
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-----------------------------------------------------------------------------
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--
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-- Definitions used for Scope Integration ----------------
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--{tcl set actel "act* 40* 42* 32* 54* ex* ax*"}
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--{tcl set altera "max* flex* acex*"}
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--{tcl set altera_retiming "flex* acex* apex* mercury* excalibur*"}
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--{tcl set apex "apex20k apexii excalibur*"}
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--{tcl set apexe "apex20kc apex20ke mercury* stratix* cyclone"}
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--{tcl set apex20k "apex20k*"}
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--{tcl set lattice "pLSI*"}
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--{tcl set mach "mach* isp* gal*"}
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--{tcl set quicklogic "pasic* quick* eclipse*"}
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--{tcl set lucent "orca*"}
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--{tcl set xilinx "xc* vir* spart*"}
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--{tcl set virtex "vir* spartan*"}
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--{tcl set virtex2 "virtex2*"}
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--{tcl set stratix "stratix*"}
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--{tcl set triscend "triscend*" }
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--{tcl set asic "asic*" }
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--{tcl set atmel "fpslic" }
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--{tcl set cp_only "apex20k* excalibur* mercury apexii stratix* cyclone spartan* virtex*" }
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-------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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package attributes is
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-- Compiler attributes
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-- {family *}
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attribute phys_pin_loc : string; -- pin loacatin {objtype port} {desc Placement constarint for pin or pad} {physattr 1}
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attribute phys_pin_hslots : string; -- pin loacatin {objtype module} {desc Set of slots or placable IO locations} {physattr 1}
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attribute phys_pin_vslots : string; -- pin loacatin {objtype module} {desc Set of slots or placable IO locations} {physattr 1}
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attribute phys_halo : string; -- pin loacatin {objtype module cell } {desc Halo to be used for the macros} {physattr 1}
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-- syn_enum_encoding specifies the encoding for an enumeration type
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attribute syn_enum_encoding : string; -- "onehot", "sequential", "gray" {noscope}
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-- syn_encoding specifies the encoding for a state register
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attribute syn_encoding : string; -- "onehot", "sequential", "gray", "safe" {objtype fsm} {desc FSM encoding (onehot, sequential, gray, safe)} {default gray} {enum onehot sequential gray safe safe,onehot safe,sequential safe,gray default}
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-- syn_allow_retiming specifies if the register can be moved for retiming purpose
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-- {family $altera_retiming $virtex $virtex2 $stratix }
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attribute syn_allow_retiming : boolean; -- {objtype register} {desc Controls retiming of registers} {default 0}
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attribute syn_state_machine : boolean; -- marks reg for SM extraction {noscope}
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--
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-- syn_preserve prevents optimization across registers it is
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-- applied to. syn_preserve on a module/arch is applied to all
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-- registers in the module/arch. syn_preserve on a register
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-- will preserve redundant copies.
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-- Can also be used to preserve redundant copies of instantiated
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-- combinational cells.
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attribute syn_preserve : boolean; -- {noscope}
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-- syn_keep is used on signals keep the signal through optimization
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-- so that timing constraints can be placed on the signal later.
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-- The timing constraints can be multi-cycle path and clock.
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attribute syn_keep : boolean; -- {noscope}
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attribute syn_sharing : string; -- "off" or "on" {noscope}
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-- syn_evaleffort is used on modules to define the effort to be used in
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-- evaluating conditions for control structures. This is useful for
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-- those modules that contain while loop or if-then-else conditions
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-- that may evaluate to a constant if more effort is applied.
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-- The higher this number, the higher the evaluation effort,
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-- and consequently the memory requirement and CPU time. The default
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-- value is 4.
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-- This attribute is not recommended!
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attribute syn_evaleffort : integer; -- an integer between 0 and 100 {noscope}
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-- syn_cpueffort is used on modules to define the cpu effort to be used in
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-- various optimizations (such as BDDs). It may take a value from 1 to 10,
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-- with the default being 5. A value of 1 to 4 would result in less CPU
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-- time and most likely less optimization, while a value of 6 to 10 would
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-- result in longer CPU time and possibly more optimization.
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--
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-- This attribute is not recommended!
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attribute syn_cpueffort : integer; -- an integer between 1 and 10 {noscope}
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-- syn_looplimit my be attached to a loop label. It represents the maximum
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-- number of loop iterations that are allowed. Use this attribute when
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-- Synplify errors out after reaching the maximum loop limit.
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attribute syn_looplimit : integer; -- the maximum loop count allowed {noscope}
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-- the syn_pmux_slice attribute is used to enable the pmux optimization
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-- code on/off. If on at the last architecture, it is carried on the
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-- hierarcy chain until it finds an architecture in which the attribute
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-- is expicitly set to off.
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attribute syn_pmux_slice : boolean; -- a boolean value {noscope}
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attribute syn_isclock : boolean; -- {noscope}
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-- turn on or off priority mux code
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attribute syn_primux : boolean; -- {noscope}
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-- General mapping attributes
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-- inst/module/arch
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--{family *}
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attribute syn_resources : string; -- spec resources used by module {noscope} {objtype cell} {desc Specifies resources used by module/architecture}
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attribute syn_area : string; -- spec resources used by module {noscope}
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attribute syn_noprune : boolean; -- keep object even if outputs unused {noscope} {objtype cell} {desc Retain instance when outputs are unused}
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attribute syn_probe : string; -- {objtype signal} {app ~synplify_asic} {desc Send a signal to output port for testing} {enum 0 1}
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attribute syn_direct_enable : boolean; -- {objtype signal} {app ~synplify_asic} {desc Prefered clock enable} {default 1} {enum 1}
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-- registers
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attribute syn_useenables : boolean; -- set to false to disable enable use {objtype register} {app ~synplify_asic} {desc Generate with clock enable pin}
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-- registers
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attribute syn_reference_clock : string; -- set to the name of the reference clock {objtype register} {desc Override the default clock with the given clock }
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-- I/O registers
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-- {family $lucent $apex $apexe $xilinx $quicklogic}
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attribute syn_useioff : boolean; -- set to false to disable use of I/O FF {objtype global port register} {desc Embed flip-flps in the IO ring}
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-- {family $xilinx $apex $apexe}
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attribute syn_forward_io_constraints : boolean; -- set to true to forward annotate IO constraints {objtype global} {desc Forward annotate IO constraints}
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-- used to specify implementations for dff in actel for now
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-- {family $actel}
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attribute syn_implement : string; -- "dff", "dffr", "dffs", "dffrs" {noscope}
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attribute syn_radhardlevel : string; -- "none", "cc", "tmr", "tmr_cc" {objtype register } {desc Radiation-hardened implementation style} {enum none cc tmr tmr_cc}
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-- {family asic}
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attribute syn_ideal_net : string; -- {objtype signal} {desc Do not buffer this net during optimization} {enum 1}
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-- {family asic}
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attribute syn_ideal_network : string; -- {objtype signal} {desc Do not buffer this network during optimization} {enum 1}
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-- {family asic}
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attribute syn_no_reopt : string; -- {objtype module} {desc Do not resize during reoptimization} {enum 1}
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-- {family asic}
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attribute syn_wire_load : string; -- {objtype module} {desc Set the wire load model to use for this module} {enum -read-wireloads-}
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-- {family *}
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-- black box attributes
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attribute syn_black_box : boolean; -- disables automatic black box warning {noscope}
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-- OLD black box attributes
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attribute black_box : boolean; -- disables automatic black box warning {noscope}
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attribute black_box_pad_pin : string; -- names of I/O pad connections {noscope}
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attribute black_box_tri_pins : string; -- names of tristate ports {noscope}
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-- Black box timing attributes
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-- tpd : timing propagation delay
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-- tsu : timing setup delay
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-- tco : timing clock to output delay
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attribute syn_tpd1 : string; -- {noscope}
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attribute syn_tpd2 : string; -- {noscope}
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attribute syn_tpd3 : string; -- {noscope}
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attribute syn_tpd4 : string; -- {noscope}
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attribute syn_tpd5 : string; -- {noscope}
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attribute syn_tpd6 : string; -- {noscope}
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attribute syn_tpd7 : string; -- {noscope}
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attribute syn_tpd8 : string; -- {noscope}
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attribute syn_tpd9 : string; -- {noscope}
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attribute syn_tpd10 : string; -- {noscope}
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attribute syn_tsu1 : string; -- {noscope}
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attribute syn_tsu2 : string; -- {noscope}
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attribute syn_tsu3 : string; -- {noscope}
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attribute syn_tsu4 : string; -- {noscope}
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attribute syn_tsu5 : string; -- {noscope}
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attribute syn_tsu6 : string; -- {noscope}
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attribute syn_tsu7 : string; -- {noscope}
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attribute syn_tsu8 : string; -- {noscope}
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attribute syn_tsu9 : string; -- {noscope}
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attribute syn_tsu10 : string; -- {noscope}
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attribute syn_tco1 : string; -- {noscope}
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attribute syn_tco2 : string; -- {noscope}
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attribute syn_tco3 : string; -- {noscope}
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attribute syn_tco4 : string; -- {noscope}
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attribute syn_tco5 : string; -- {noscope}
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attribute syn_tco6 : string; -- {noscope}
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attribute syn_tco7 : string; -- {noscope}
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attribute syn_tco8 : string; -- {noscope}
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attribute syn_tco9 : string; -- {noscope}
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attribute syn_tco10 : string; -- {noscope}
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-- Mapping attributes
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-- {family $actel $xilinx $lucent $quicklogic $altera $apex $apexe}
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attribute syn_maxfan : integer; -- {objtype input_port register_output cell} {desc Overrides the default fanout}
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-- {family $actel $xilinx $lucent $quicklogic $lattice $mach $virtex $virtex2 $triscend $asic $atmel $cp_only}
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attribute syn_noclockbuf : boolean; -- {objtype global cell input_port module} {app ~synplify_asic} {desc Use normal input buffer}
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-- {family $virtex stratix* }
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attribute syn_srlstyle : string; -- {objtype cell global module} {desc Determines how seq. shift comp. are implemented} {default select_srl} {enum virtex (select_srl registers noextractff_srl) stratix(select_srl registers noextractff_srl altshift_tap)}
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-- set syn_ramstyle to a value of "registers" to force the ram
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-- to be implemented with registers.
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-- {family $altera $apex $apexe $xilinx $lucent $quicklogic stratix* }
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attribute syn_ramstyle : string; -- {objtype cell global module} {desc Map inferred RAM to registers} {default registers} {desc Special implementation of inferred RAM} {enum Virtex virtex-E spartan2 spartan2e virtex2 virtex2-pro(registers block_ram no_rw_check select_ram) xilinx_default (registers select_ram) stratix (registers block_ram no_rw_check) altera_default (registers block_ram) default (registers) all_enums (registers block_ram no_rw_check select_ram)}
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-- {family $virtex2 $altera $apex $apexe $apex20k $lattice $lucent $mach excalibur*}
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attribute syn_multstyle : string; -- {objtype cell global module} {default block_mult} {desc Special implementation of multipliers} {enum Virtex virtex-E spartan2 spartan2e virtex2 virtex2-pro(logic block_mult) stratix(logic lpm_mult block_mult) altera_default (logic lpm_mult) all_enums (logic block_mult lpm_mult)}
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-- {family $virtex $virtex2}
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attribute syn_tops_region_size : integer; -- {objtype global} {desc max. size of valid TOPS region in LUTs} {app amplify}
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-- set syn_romstyle to a value of "logic" to force the rom
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-- to be implemented with logic, select_rom/block_rom
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-- {family $altera $apex $apexe $xilinx}
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attribute syn_romstyle : string; -- {objtype cell global module} {desc Controls mapping of inferred ROM} {default logic} {desc Special implementation of inferred ROM} {enum xilinx_default (logic select_rom) altera_default(logic block_rom lpm_rom) default(logic) all_enums (logic select_rom block_rom) }
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-- set syn_pipeline to a value 1 to pipeline the module front of it
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-- {family $altera $apex $apexe $xilinx}
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attribute syn_pipeline : boolean; -- {objtype register} {desc Controls pipelining of registers} {default 1} {desc Special implementation of pipelined module}
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-- controls EDIF format. Set true on top level to disable array ports
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-- {family *}
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attribute syn_noarrayports : boolean; -- {objtype global} {app ~synplify_asic} {desc Disable array ports}
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-- controls EDIF port name length. Currently used in Altera
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-- {family $altera}
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attribute syn_edif_name_length : string; -- {enum Restricted Unrestricted} {default Restricted} {objtype global} {desc Use Restricted for MAXII; Unrestricted for quartus}
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-- {family *}
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-- controls reconstruction of hierarchy. Set false on top level
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-- to disable hierarchy reconstruction.
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attribute syn_netlist_hierarchy : boolean; -- {objtype global} {app ~synplify_asic} {desc Enable hierarchy reconstruction}
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--
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-- syn_hier on an instance/module/architecture can be used
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-- to control treatment of the level of hierarchy.
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-- "macro" - preserve instantiated netlist
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-- "hard" - preserves the interface of the design unit with no exceptions.
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-- "remove"- removes level of hierarchy
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-- "soft" - managed by Synplify (default)
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-- "firm" - preserve during opt, but allow mapping across boundary
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--
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-- {family *}
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attribute syn_hier: string; -- {objtype module} {desc Control hierarchy flattening} {enum proASIC (soft remove flatten firm) xilinx_default(hard soft remove flatten firm) actel_default altera_default all_enums(hard soft macro remove flatten firm) lucent_default (soft macro remove flatten firm) quicklogic_default(soft macro remove flatten firm) default(soft remove flatten firm)}
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-- syn_flatten on a module/architecture will flatten out the
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-- module all the way down to primitives.
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attribute syn_flatten : boolean; -- {noscope}
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-- {family $cp_only }
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attribute syn_allowed_resources : string; -- {objtype module} {desc Control resource usage in a compile point}
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-- Architecture specific attributes
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-- Actel
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-- {family $actel}
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--
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-- syn_preserve_sr_priority is used if you want to preserve
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-- reset over set priority for DFFRS. Actel FF models produce
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-- an X for set and reset active. This attribute costs gates and delay.
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attribute syn_preserve_sr_priority : boolean; -- {noscope}
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attribute alspin : string ; --{objtype port} {desc Pin locations for Actel I/Os}
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attribute alspreserve : boolean ; --{objtype signal} {desc Not collapse a net in Actel}
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attribute alsfc : string ; --{noscope}
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attribute alsdc : string ; --{noscope}
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attribute alsloc : string ; --{noscope}
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attribute alscrt : string ; --{noscope}
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-- Altera
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290 |
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-- {family $altera $apex $apexe}
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291 |
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|
292 |
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attribute altera_implement_style : string; -- placement {noscope}
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293 |
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attribute altera_clique : string; -- placement {noscope}
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294 |
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attribute altera_chip_pin_lc : string; -- placement {objtype port} {desc I/O pin location}
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295 |
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-- inst/module/arch: put comb logic into rom
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296 |
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attribute altera_implement_in_eab : boolean; -- {objtype cell} {desc Implment in Altera EABs, apply to module/component instance name only} {default 1}
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297 |
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attribute altera_lcell: string; -- arch attribute with values of "lut" and "car" {noscope}
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298 |
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-- for lcell config
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299 |
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attribute altera_auto_use_eab : boolean; -- {objtype global} {desc Use EABs automatically} {default 1}
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300 |
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attribute altera_auto_use_esb : boolean; -- {objtype global} {desc Use ESBs automatically} {default 1}
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301 |
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302 |
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-- Apex
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303 |
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-- {family $apex $apexe}
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304 |
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305 |
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attribute altera_implement_in_esb : boolean; -- {objtype cell} {desc Implment in Altera ESBs, apply to module/component instance name only} {default 1}
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306 |
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307 |
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-- Apex
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308 |
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-- {family $apex $apexe}
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309 |
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|
310 |
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attribute altera_logiclock_location : string; -- {objtype module} {desc Give the location of LogicLock region } {default floating}
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311 |
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312 |
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313 |
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-- Apex
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314 |
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-- {family $apex $apexe}
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315 |
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316 |
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attribute altera_logiclock_size : string; -- {objtype module} {desc Give the size of LogicLock region} {default auto}
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317 |
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318 |
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319 |
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-- {family apex20kc apex20ke excalibur* mercury* cyclone stratix* acex* flex10k* }
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320 |
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attribute altera_io_opendrain : boolean; -- set to true to get opendrain port in APEX {objtype port} {desc Use opendrain capability on port or bit-port.}
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321 |
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322 |
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-- {family $altera_retiming}
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323 |
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attribute altera_io_powerup : string; -- set to high to get IO FF to powerup high in APEX {objtype port} {desc Powerup high or low on port or bit-port in APEX20KE.}
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324 |
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325 |
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-- Lattice
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326 |
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-- {family $lattice $quicklogic}
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327 |
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|
328 |
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attribute lock: string; -- pin placement {objtype port} {desc Pin locations for Lattice I/Os}
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329 |
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|
330 |
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-- Lucent
|
331 |
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-- {family $lucent}
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332 |
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|
333 |
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attribute din : string; -- orca2 FF placement attribute, use value "" {objtype input_port} {desc Input register goes next to I/O pad}
|
334 |
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attribute dout : string; -- orca2 FF placement attribute, use value "" {objtype output_port} {desc Output register goes next to I/O pad}
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335 |
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attribute orca_padtype : string; -- value selects synth pad type {objtype port} {desc Pad type for I/O}
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336 |
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attribute orca_props : string; -- attributes to pass for instance {objtype cell port} {desc Forward annotate attributes to ORCA back-end}
|
337 |
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|
338 |
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-- Both Lucent and Mach
|
339 |
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-- {family $lucent $mach}
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340 |
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attribute loc : string; -- placment attribute {objtype port} {desc Pin location}
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341 |
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|
342 |
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|
343 |
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-- Quicklogic
|
344 |
|
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-- {family $quicklogic}
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345 |
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|
346 |
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-- I/O attributes
|
347 |
|
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attribute ql_padtype : string; -- {objtype port} {desc Override default pad types (use BIDIR, INPUT, CLOCK)} {enum BIDIR INPUT CLOCK}
|
348 |
|
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attribute ql_placement : string; -- {objtype port cell} {desc Placement location}
|
349 |
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|
350 |
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|
351 |
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-- Xilinx
|
352 |
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-- {family $xilinx}
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353 |
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|
354 |
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-- Instance Placement attributes
|
355 |
|
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attribute xc_loc : string; -- placement (pads) {objtype port} {desc Port placement}
|
356 |
|
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attribute xc_rloc : string; -- see RPMs in xilinx doc {objtype cell} {desc Relative placement specification, use with xc_uset}
|
357 |
|
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attribute xc_uset : string; -- see RPMs in xilinx doc {objtype cell} {desc Assign group name for placement, use with xc_rloc}
|
358 |
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-- I/O attributes
|
359 |
|
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attribute xc_fast : boolean; -- {objtype output_port} {desc Fast transition time}
|
360 |
|
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attribute xc_ioff : boolean; -- {noscope}
|
361 |
|
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attribute xc_nodelay : boolean; -- {objtype input_port} {desc Remove input delay}
|
362 |
|
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attribute xc_slow : boolean; -- {objtype output_port} {desc Slow transition time}
|
363 |
|
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attribute xc_ttl : boolean; -- {noscope}
|
364 |
|
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attribute xc_cmos : boolean; -- {noscope}
|
365 |
|
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attribute xc_pullup : boolean; -- add a pullup to I/O {objtype port} {desc Add a pullup}
|
366 |
|
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attribute xc_pulldown : boolean; -- add a pulldown to I/O {objtype port} {desc Add a pulldown}
|
367 |
|
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attribute xc_clockbuftype : string; -- {objtype input_port} {default BUFGDLL} {desc Use the Xilinx BUFGDLL clock buffer}
|
368 |
|
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attribute xc_padtype : string; -- {objtype port} {desc Applies an I/O standard to an I/O buffer}
|
369 |
|
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|
370 |
|
|
-- Top level architecture attributes
|
371 |
|
|
-- number of global buffers, used only for XC4000, XC4000E
|
372 |
|
|
attribute syn_global_buffers : integer; -- {objtype global} {desc Number of global buffers}
|
373 |
|
|
attribute xc_use_timespec_for_io : boolean; -- {objtype global} {desc Enable use of from-to timepsec instead of offset for I/O constraint} {default 0}
|
374 |
|
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|
375 |
|
|
-- Xilinx Modular Design Flow --
|
376 |
|
|
attribute xc_pseudo_pin_loc : string; -- {objtype signal} {default CLB_RrrCcc:CLB_RrrCcc} {desc Pseudo pin location on place and route block }
|
377 |
|
|
attribute xc_modular_design : boolean; -- {objtype global } {default 1} {desc Enable modular design flow }
|
378 |
|
|
attribute xc_modular_region : string; -- {objtype cell } {default rr#cc#rr#cc} {desc Specifies the number of CLB's for a modular region}
|
379 |
|
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|
380 |
|
|
-- Xilinx Incremental Design Flow --
|
381 |
|
|
attribute xc_area_group : string; -- {objtype cell } {default rr#cc#rr#cc} {desc Specifies the region where instance should be placed}
|
382 |
|
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|
383 |
|
|
-- Black box attributes
|
384 |
|
|
-- {family $xilinx}
|
385 |
|
|
attribute xc_alias : string; -- cell name change in XNF writer {noscope}
|
386 |
|
|
attribute xc_props : string; -- extra XNF attributes to pass for instance {objtype cell} {desc Extra XNF attributes to pass for instance}
|
387 |
|
|
attribute xc_map : string; -- used to map entity to fmap/hmap/lut {objtype module} {desc Map entity to fmap/hmap/lut} {enum fmap hmap lut}
|
388 |
|
|
attribute xc_isgsr : boolean; -- used to mark port of core with built in GSR {noscope}
|
389 |
|
|
|
390 |
|
|
attribute syn_tristatetomux : integer ; -- {objtype module global} {desc Threshold for converting tristates to mux}
|
391 |
|
|
attribute syn_edif_bit_format : string ; -- {objtype global} {desc Format bus names} {enum %u<%i> %u[%i] %u(%i) %u_%i %u%i %d<%i> %d[%i] %d(%i) %d_%i %d%i %n<%i> %n[%i] %n(%i) %n_%i %n%i}
|
392 |
|
|
|
393 |
|
|
attribute syn_edif_scalar_format : string; -- {objtype global} {desc Format scaler names} {enum %u %n %d}
|
394 |
|
|
|
395 |
|
|
attribute xc_fast_auto : boolean; -- {objtype global} {desc Enable automatic fast output buffer use}
|
396 |
|
|
|
397 |
|
|
-- Triscend
|
398 |
|
|
-- {family $triscend}
|
399 |
|
|
|
400 |
|
|
attribute tr_map : string; -- used to map entity to LUT {objtype module} {desc Map entity to LUT}
|
401 |
|
|
|
402 |
|
|
attribute syn_props : string; -- extra attributes to pass to EDIF for instance {objtype cell} {desc Extra attributes to pass to EDIF for instance}
|
403 |
|
|
|
404 |
|
|
-- syn_replicate controls replication of registers
|
405 |
|
|
-- {family $virtex $virtex2 $altera $apex $apexe $apex20k}
|
406 |
|
|
attribute syn_replicate : boolean; -- {objtype global register} {desc Controls replication of registers} {default 0}
|
407 |
|
|
|
408 |
|
|
-- {family $xilinx}
|
409 |
|
|
attribute syn_verification_options : string; -- {objtype module} {default black_box} {desc Allows a module to be defined as a black_box for verification }
|
410 |
|
|
|
411 |
|
|
|
412 |
|
|
end attributes;
|