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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [altera/] [simprims/] [altera_primitives_components.vhd] - Blame information for rev 2

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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
 
 
-- Quartus II 7.1 Build 156 04/30/2007
 
 
----------------------------------------------------------------------------
-- ALtera Primitives Component Declaration File
----------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
 
package dffeas_pack is
 
-- default generic values
    CONSTANT DefWireDelay        : VitalDelayType01      := (0 ns, 0 ns);
    CONSTANT DefPropDelay01      : VitalDelayType01      := (0 ns, 0 ns);
    CONSTANT DefPropDelay01Z     : VitalDelayType01Z     := (OTHERS => 0 ns);
    CONSTANT DefSetupHoldCnst    : TIME := 0 ns;
    CONSTANT DefPulseWdthCnst    : TIME := 0 ns;
    CONSTANT DefGlitchMode       : VitalGlitchKindType   := VitalTransport;
    CONSTANT DefGlitchMsgOn      : BOOLEAN       := FALSE;
    CONSTANT DefGlitchXOn        : BOOLEAN       := FALSE;
    CONSTANT DefMsgOnChecks      : BOOLEAN       := TRUE;
    CONSTANT DefXOnChecks        : BOOLEAN       := TRUE;
 
end dffeas_pack;
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.dffeas_pack.all;
 
package altera_primitives_components is
 
component carry
    port (
        a_in : in std_logic;
        a_out : out std_logic );
end component;
 
component cascade
    port (
        a_in : in std_logic;
        a_out : out std_logic );
end component;
 
component global
    port (
        a_in : in std_logic;
        a_out : out std_logic);
end component;
 
component tri
    port(
        a_in  :  in    std_logic;
        oe    :  in    std_logic;
        a_out :  out   std_logic);
end component;
 
component carry_sum
    port (
        sin : in std_logic;
        cin : in std_logic;
        sout : out std_logic;
        cout : out std_logic );
end component;
 
component exp
    port (
        a_in : in std_logic;
        a_out : out std_logic);
end component;
 
component soft
    port (
        a_in : in std_logic;
        a_out : out std_logic );
end component;
 
component opndrn
    port (
        a_in : in std_logic;
        a_out : out std_logic );
end component;
 
component row_global
    port (
        a_in : in std_logic;
        a_out : out std_logic );
end component;
 
component lut_input
    port(
        a_in  :  in    std_logic;
        a_out :  out   std_logic);
end component;
 
component lut_output
    port(
        a_in  :  in    std_logic;
        a_out :  out   std_logic);
end component;
 
component dlatch
    port(
        d    :  in    std_logic;
        ena  :  in    std_logic;
        clrn :  in    std_logic;
        prn  :  in    std_logic;
        q    :  out   std_logic);
end component;
 
component latch
    port(
        d   :  in    std_logic;
        ena :  in    std_logic;
        q   :  out   std_logic);
end component;
 
component dff
    port(
        d, clk, clrn, prn :  in  std_logic;
        q                 :  out std_logic);
end component;
 
component dffe
    port(
        d, clk, ena, clrn, prn :  in  std_logic;
        q                      :  out std_logic);
end component;
 
component dffea
    port(
        d, clk, ena, clrn, prn, aload, adata :  in  std_logic;
        q                                    :  out std_logic);
end component;
 
component dffeas
    generic (
        power_up : string := "DONT_CARE";
        is_wysiwyg : string := "false";
        x_on_violation : string := "on";
        lpm_type : string := "DFFEAS";
        tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
        tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
        tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
        tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
        tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
        tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
        tipd_clk : VitalDelayType01 := DefPropDelay01;
        tipd_d : VitalDelayType01 := DefPropDelay01;
        tipd_asdata : VitalDelayType01 := DefPropDelay01;
        tipd_sclr : VitalDelayType01 := DefPropDelay01;
        tipd_sload : VitalDelayType01 := DefPropDelay01;
        tipd_clrn : VitalDelayType01 := DefPropDelay01;
        tipd_prn : VitalDelayType01 := DefPropDelay01;
        tipd_aload : VitalDelayType01 := DefPropDelay01;
        tipd_ena : VitalDelayType01 := DefPropDelay01;
        TimingChecksOn: Boolean := True;
        MsgOn: Boolean := DefGlitchMsgOn;
        XOn: Boolean := DefGlitchXOn;
        MsgOnChecks: Boolean := DefMsgOnChecks;
        XOnChecks: Boolean := DefXOnChecks;
        InstancePath: STRING := "*" );
 
    port (
        d : in std_logic := '0';
        clk : in std_logic := '0';
        ena : in std_logic := '1';
        clrn : in std_logic := '1';
        prn : in std_logic := '1';
        aload : in std_logic := '0';
        asdata : in std_logic := '1';
        sclr : in std_logic := '0';
        sload : in std_logic := '0';
        devclrn : in std_logic := '1';
        devpor : in std_logic := '1';
        q : out std_logic );
end component;
 
component tff
    port(
        t, clk, clrn, prn :  in  std_logic;
        q                 :  out std_logic);
end component;
 
component tffe
    port(
        t, clk, ena, clrn, prn :  in  std_logic;
        q                      :  out std_logic);
end component;
 
component jkff
    port(
        j, k, clk, clrn, prn :  in  std_logic;
        q                    :  out std_logic);
end component;
 
component jkffe
    port(
        j, k, clk, ena, clrn, prn :  in  std_logic;
        q                         :  out std_logic);
end component;
 
component srff
    port(
        s, r, clk, clrn, prn :  in  std_logic;
        q                    :  out std_logic);
end component;
 
component srffe
    port(
        s, r, clk, ena, clrn, prn :  in  std_logic;
        q                         :  out std_logic);
end component;
 
component clklock
    generic(
        input_frequency       : natural := 10000;
        clockboost            : natural := 1);
 
    port(
        inclk   : in std_logic;
        outclk  : out std_logic);
end component;
 
component alt_inbuf
    generic(
        io_standard           : string := "NONE";
        location              : string := "NONE";
        enable_bus_hold       : string := "NONE";
        weak_pull_up_resistor : string := "NONE";
        termination           : string := "NONE";
        lpm_type              : string := "alt_inbuf" );
 
    port(
        i  : in std_logic;
        o  : out std_logic);
end component;
 
component alt_outbuf
    generic(
        io_standard           : string  := "NONE";
        current_strength      : string  := "NONE";
        current_strength_new  : string  := "NONE";
        slew_rate             : integer := -1;
        slow_slew_rate        : string  := "NONE";
        location              : string  := "NONE";
        enable_bus_hold       : string  := "NONE";
        weak_pull_up_resistor : string  := "NONE";
        termination           : string  := "NONE";
        lpm_type              : string := "alt_outbuf" );
 
    port(
        i  : in std_logic;
        o  : out std_logic);
end component;
 
component alt_outbuf_tri
    generic(
        io_standard           : string  := "NONE";
        current_strength      : string  := "NONE";
        current_strength_new  : string  := "NONE";
        slew_rate             : integer := -1;
        slow_slew_rate        : string  := "NONE";
        location              : string  := "NONE";
        enable_bus_hold       : string  := "NONE";
        weak_pull_up_resistor : string  := "NONE";
        termination           : string  := "NONE";
        lpm_type              : string := "alt_outbuf_tri" );
 
    port(
        i  : in std_logic;
        oe : in std_logic;
        o  : out std_logic);
end component;
 
component alt_iobuf
    generic(
        io_standard           : string  := "NONE";
        current_strength      : string  := "NONE";
        current_strength_new  : string  := "NONE";
        slew_rate             : integer := -1;
        slow_slew_rate        : string  := "NONE";
        location              : string  := "NONE";
        enable_bus_hold       : string  := "NONE";
        weak_pull_up_resistor : string  := "NONE";
        termination           : string  := "NONE";
        input_termination     : string  := "NONE";
        output_termination    : string  := "NONE";
        lpm_type              : string := "alt_iobuf" );
 
    port(
        i  : in std_logic;
        oe : in std_logic;
        io : inout std_logic;
        o  : out std_logic);
end component;
 
component alt_inbuf_diff
    generic(
        io_standard           : string := "NONE";
        location              : string := "NONE";
        enable_bus_hold       : string := "NONE";
        weak_pull_up_resistor : string := "NONE";
        termination           : string := "NONE";
        lpm_type              : string := "alt_inbuf_diff" );
 
    port(
        i    : in std_logic;
        ibar : in std_logic;
        o    : out std_logic);
end component;
 
component alt_outbuf_diff
    generic (
        io_standard           : string  := "NONE";
        current_strength      : string  := "NONE";
        current_strength_new  : string  := "NONE";
        slew_rate             : integer := -1;
        location              : string  := "NONE";
        enable_bus_hold       : string  := "NONE";
        weak_pull_up_resistor : string  := "NONE";
        termination           : string  := "NONE";
        lpm_type              : string := "alt_outbuf_diff" );
 
    port(
        i    : in std_logic;
        o    : out std_logic;
        obar : out std_logic );
end component;
 
component alt_outbuf_tri_diff
    generic (
        io_standard           : string  := "NONE";
        current_strength      : string  := "NONE";
        current_strength_new  : string  := "NONE";
        slew_rate             : integer := -1;
        location              : string  := "NONE";
        enable_bus_hold       : string  := "NONE";
        weak_pull_up_resistor : string  := "NONE";
        termination           : string  := "NONE";
        lpm_type              : string := "alt_outbuf_tri_diff" );
    port(
        i    : in std_logic;
        oe   : in std_logic;
        o    : out std_logic;
        obar : out std_logic );
end component;
 
component alt_iobuf_diff
    generic (
        io_standard           : string  := "NONE";
        current_strength      : string  := "NONE";
        current_strength_new  : string  := "NONE";
        slew_rate             : integer := -1;
        location              : string  := "NONE";
        enable_bus_hold       : string  := "NONE";
        weak_pull_up_resistor : string  := "NONE";
        termination           : string  := "NONE";
        input_termination     : string  := "NONE";
        output_termination    : string  := "NONE";
        lpm_type              : string := "alt_iobuf_diff" );
    port(
        i     : in std_logic;
        oe    : in std_logic;
        io    : inout std_logic;
        iobar : inout std_logic;
        o     : out std_logic );
end component;
 
component alt_bidir_diff
    generic (
        io_standard           : string  := "NONE";
        current_strength      : string  := "NONE";
        current_strength_new  : string  := "NONE";
        slew_rate             : integer := -1;
        location              : string  := "NONE";
        enable_bus_hold       : string  := "NONE";
        weak_pull_up_resistor : string  := "NONE";
        termination           : string  := "NONE";
        input_termination     : string  := "NONE";
        output_termination    : string  := "NONE";
        lpm_type              : string := "alt_bidir_diff" );
    port(
        oe      : in std_logic;
        bidirin : inout std_logic;
        io      : inout std_logic;
        iobar   : inout std_logic );
end component;
 
component alt_bidir_buf
    generic (
        io_standard           : string  := "NONE";
        current_strength      : string  := "NONE";
        current_strength_new  : string  := "NONE";
        slew_rate             : integer := -1;
        location              : string  := "NONE";
        enable_bus_hold       : string  := "NONE";
        weak_pull_up_resistor : string  := "NONE";
        termination           : string  := "NONE";
        input_termination     : string  := "NONE";
        output_termination    : string  := "NONE";
        lpm_type              : string := "alt_bidir_buf" );
    port(
        oe      : in std_logic;
        bidirin : inout std_logic;
        io      : inout std_logic );
end component;
 
end altera_primitives_components;
 

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [altera/] [simprims/] [altera_primitives_components.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`-- Copyright (C) 1991-2007 Altera Corporation`
2			`-- Your use of Altera Corporation's design tools, logic functions`
3			`-- and other software and tools, and its AMPP partner logic`
4			`-- functions, and any output files from any of the foregoing`
5			`-- (including device programming or simulation files), and any`
6			`-- associated documentation or information are expressly subject`
7			`-- to the terms and conditions of the Altera Program License`
8			`-- Subscription Agreement, Altera MegaCore Function License`
9			`-- Agreement, or other applicable license agreement, including,`
10			`-- without limitation, that your use is for the sole purpose of`
11			`-- programming logic devices manufactured by Altera and sold by`
12			`-- Altera or its authorized distributors. Please refer to the`
13			`-- applicable agreement for further details.`
14
15
16			`-- Quartus II 7.1 Build 156 04/30/2007`
17
18
19			`----------------------------------------------------------------------------`
20			`-- ALtera Primitives Component Declaration File`
21			`----------------------------------------------------------------------------`
22
23			`library IEEE;`
24			`use IEEE.std_logic_1164.all;`
25			`use IEEE.VITAL_Timing.all;`
26			`use IEEE.VITAL_Primitives.all;`
27
28			`package dffeas_pack is`
29
30			`-- default generic values`
31			`CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);`
32			`CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);`
33			`CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);`
34			`CONSTANT DefSetupHoldCnst : TIME := 0 ns;`
35			`CONSTANT DefPulseWdthCnst : TIME := 0 ns;`
36			`CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;`
37			`CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;`
38			`CONSTANT DefGlitchXOn : BOOLEAN := FALSE;`
39			`CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;`
40			`CONSTANT DefXOnChecks : BOOLEAN := TRUE;`
41
42			`end dffeas_pack;`
43
44			`library ieee;`
45			`use ieee.std_logic_1164.all;`
46			`use IEEE.VITAL_Timing.all;`
47			`use work.dffeas_pack.all;`
48
49			`package altera_primitives_components is`
50
51			`component carry`
52			`port (`
53			`a_in : in std_logic;`
54			`a_out : out std_logic );`
55			`end component;`
56
57			`component cascade`
58			`port (`
59			`a_in : in std_logic;`
60			`a_out : out std_logic );`
61			`end component;`
62
63			`component global`
64			`port (`
65			`a_in : in std_logic;`
66			`a_out : out std_logic);`
67			`end component;`
68
69			`component tri`
70			`port(`
71			`a_in : in std_logic;`
72			`oe : in std_logic;`
73			`a_out : out std_logic);`
74			`end component;`
75
76			`component carry_sum`
77			`port (`
78			`sin : in std_logic;`
79			`cin : in std_logic;`
80			`sout : out std_logic;`
81			`cout : out std_logic );`
82			`end component;`
83
84			`component exp`
85			`port (`
86			`a_in : in std_logic;`
87			`a_out : out std_logic);`
88			`end component;`
89
90			`component soft`
91			`port (`
92			`a_in : in std_logic;`
93			`a_out : out std_logic );`
94			`end component;`
95
96			`component opndrn`
97			`port (`
98			`a_in : in std_logic;`
99			`a_out : out std_logic );`
100			`end component;`
101
102			`component row_global`
103			`port (`
104			`a_in : in std_logic;`
105			`a_out : out std_logic );`
106			`end component;`
107
108			`component lut_input`
109			`port(`
110			`a_in : in std_logic;`
111			`a_out : out std_logic);`
112			`end component;`
113
114			`component lut_output`
115			`port(`
116			`a_in : in std_logic;`
117			`a_out : out std_logic);`
118			`end component;`
119
120			`component dlatch`
121			`port(`
122			`d : in std_logic;`
123			`ena : in std_logic;`
124			`clrn : in std_logic;`
125			`prn : in std_logic;`
126			`q : out std_logic);`
127			`end component;`
128
129			`component latch`
130			`port(`
131			`d : in std_logic;`
132			`ena : in std_logic;`
133			`q : out std_logic);`
134			`end component;`
135
136			`component dff`
137			`port(`
138			`d, clk, clrn, prn : in std_logic;`
139			`q : out std_logic);`
140			`end component;`
141
142			`component dffe`
143			`port(`
144			`d, clk, ena, clrn, prn : in std_logic;`
145			`q : out std_logic);`
146			`end component;`
147
148			`component dffea`
149			`port(`
150			`d, clk, ena, clrn, prn, aload, adata : in std_logic;`
151			`q : out std_logic);`
152			`end component;`
153
154			`component dffeas`
155			`generic (`
156			`power_up : string := "DONT_CARE";`
157			`is_wysiwyg : string := "false";`
158			`x_on_violation : string := "on";`
159			`lpm_type : string := "DFFEAS";`
160			`tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
161			`tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
162			`tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
163			`tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
164			`tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
165			`thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
166			`thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
167			`thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
168			`thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
169			`thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;`
170			`tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;`
171			`tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;`
172			`tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;`
173			`tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;`
174			`tpd_asdata_q: VitalDelayType01 := DefPropDelay01;`
175			`tipd_clk : VitalDelayType01 := DefPropDelay01;`
176			`tipd_d : VitalDelayType01 := DefPropDelay01;`
177			`tipd_asdata : VitalDelayType01 := DefPropDelay01;`
178			`tipd_sclr : VitalDelayType01 := DefPropDelay01;`
179			`tipd_sload : VitalDelayType01 := DefPropDelay01;`
180			`tipd_clrn : VitalDelayType01 := DefPropDelay01;`
181			`tipd_prn : VitalDelayType01 := DefPropDelay01;`
182			`tipd_aload : VitalDelayType01 := DefPropDelay01;`
183			`tipd_ena : VitalDelayType01 := DefPropDelay01;`
184			`TimingChecksOn: Boolean := True;`
185			`MsgOn: Boolean := DefGlitchMsgOn;`
186			`XOn: Boolean := DefGlitchXOn;`
187			`MsgOnChecks: Boolean := DefMsgOnChecks;`
188			`XOnChecks: Boolean := DefXOnChecks;`
189			`InstancePath: STRING := "*" );`
190
191			`port (`
192			`d : in std_logic := '0';`
193			`clk : in std_logic := '0';`
194			`ena : in std_logic := '1';`
195			`clrn : in std_logic := '1';`
196			`prn : in std_logic := '1';`
197			`aload : in std_logic := '0';`
198			`asdata : in std_logic := '1';`
199			`sclr : in std_logic := '0';`
200			`sload : in std_logic := '0';`
201			`devclrn : in std_logic := '1';`
202			`devpor : in std_logic := '1';`
203			`q : out std_logic );`
204			`end component;`
205
206			`component tff`
207			`port(`
208			`t, clk, clrn, prn : in std_logic;`
209			`q : out std_logic);`
210			`end component;`
211
212			`component tffe`
213			`port(`
214			`t, clk, ena, clrn, prn : in std_logic;`
215			`q : out std_logic);`
216			`end component;`
217
218			`component jkff`
219			`port(`
220			`j, k, clk, clrn, prn : in std_logic;`
221			`q : out std_logic);`
222			`end component;`
223
224			`component jkffe`
225			`port(`
226			`j, k, clk, ena, clrn, prn : in std_logic;`
227			`q : out std_logic);`
228			`end component;`
229
230			`component srff`
231			`port(`
232			`s, r, clk, clrn, prn : in std_logic;`
233			`q : out std_logic);`
234			`end component;`
235
236			`component srffe`
237			`port(`
238			`s, r, clk, ena, clrn, prn : in std_logic;`
239			`q : out std_logic);`
240			`end component;`
241
242			`component clklock`
243			`generic(`
244			`input_frequency : natural := 10000;`
245			`clockboost : natural := 1);`
246
247			`port(`
248			`inclk : in std_logic;`
249			`outclk : out std_logic);`
250			`end component;`
251
252			`component alt_inbuf`
253			`generic(`
254			`io_standard : string := "NONE";`
255			`location : string := "NONE";`
256			`enable_bus_hold : string := "NONE";`
257			`weak_pull_up_resistor : string := "NONE";`
258			`termination : string := "NONE";`
259			`lpm_type : string := "alt_inbuf" );`
260
261			`port(`
262			`i : in std_logic;`
263			`o : out std_logic);`
264			`end component;`
265
266			`component alt_outbuf`
267			`generic(`
268			`io_standard : string := "NONE";`
269			`current_strength : string := "NONE";`
270			`current_strength_new : string := "NONE";`
271			`slew_rate : integer := -1;`
272			`slow_slew_rate : string := "NONE";`
273			`location : string := "NONE";`
274			`enable_bus_hold : string := "NONE";`
275			`weak_pull_up_resistor : string := "NONE";`
276			`termination : string := "NONE";`
277			`lpm_type : string := "alt_outbuf" );`
278
279			`port(`
280			`i : in std_logic;`
281			`o : out std_logic);`
282			`end component;`
283
284			`component alt_outbuf_tri`
285			`generic(`
286			`io_standard : string := "NONE";`
287			`current_strength : string := "NONE";`
288			`current_strength_new : string := "NONE";`
289			`slew_rate : integer := -1;`
290			`slow_slew_rate : string := "NONE";`
291			`location : string := "NONE";`
292			`enable_bus_hold : string := "NONE";`
293			`weak_pull_up_resistor : string := "NONE";`
294			`termination : string := "NONE";`
295			`lpm_type : string := "alt_outbuf_tri" );`
296
297			`port(`
298			`i : in std_logic;`
299			`oe : in std_logic;`
300			`o : out std_logic);`
301			`end component;`
302
303			`component alt_iobuf`
304			`generic(`
305			`io_standard : string := "NONE";`
306			`current_strength : string := "NONE";`
307			`current_strength_new : string := "NONE";`
308			`slew_rate : integer := -1;`
309			`slow_slew_rate : string := "NONE";`
310			`location : string := "NONE";`
311			`enable_bus_hold : string := "NONE";`
312			`weak_pull_up_resistor : string := "NONE";`
313			`termination : string := "NONE";`
314			`input_termination : string := "NONE";`
315			`output_termination : string := "NONE";`
316			`lpm_type : string := "alt_iobuf" );`
317
318			`port(`
319			`i : in std_logic;`
320			`oe : in std_logic;`
321			`io : inout std_logic;`
322			`o : out std_logic);`
323			`end component;`
324
325			`component alt_inbuf_diff`
326			`generic(`
327			`io_standard : string := "NONE";`
328			`location : string := "NONE";`
329			`enable_bus_hold : string := "NONE";`
330			`weak_pull_up_resistor : string := "NONE";`
331			`termination : string := "NONE";`
332			`lpm_type : string := "alt_inbuf_diff" );`
333
334			`port(`
335			`i : in std_logic;`
336			`ibar : in std_logic;`
337			`o : out std_logic);`
338			`end component;`
339
340			`component alt_outbuf_diff`
341			`generic (`
342			`io_standard : string := "NONE";`
343			`current_strength : string := "NONE";`
344			`current_strength_new : string := "NONE";`
345			`slew_rate : integer := -1;`
346			`location : string := "NONE";`
347			`enable_bus_hold : string := "NONE";`
348			`weak_pull_up_resistor : string := "NONE";`
349			`termination : string := "NONE";`
350			`lpm_type : string := "alt_outbuf_diff" );`
351
352			`port(`
353			`i : in std_logic;`
354			`o : out std_logic;`
355			`obar : out std_logic );`
356			`end component;`
357
358			`component alt_outbuf_tri_diff`
359			`generic (`
360			`io_standard : string := "NONE";`
361			`current_strength : string := "NONE";`
362			`current_strength_new : string := "NONE";`
363			`slew_rate : integer := -1;`
364			`location : string := "NONE";`
365			`enable_bus_hold : string := "NONE";`
366			`weak_pull_up_resistor : string := "NONE";`
367			`termination : string := "NONE";`
368			`lpm_type : string := "alt_outbuf_tri_diff" );`
369			`port(`
370			`i : in std_logic;`
371			`oe : in std_logic;`
372			`o : out std_logic;`
373			`obar : out std_logic );`
374			`end component;`
375
376			`component alt_iobuf_diff`
377			`generic (`
378			`io_standard : string := "NONE";`
379			`current_strength : string := "NONE";`
380			`current_strength_new : string := "NONE";`
381			`slew_rate : integer := -1;`
382			`location : string := "NONE";`
383			`enable_bus_hold : string := "NONE";`
384			`weak_pull_up_resistor : string := "NONE";`
385			`termination : string := "NONE";`
386			`input_termination : string := "NONE";`
387			`output_termination : string := "NONE";`
388			`lpm_type : string := "alt_iobuf_diff" );`
389			`port(`
390			`i : in std_logic;`
391			`oe : in std_logic;`
392			`io : inout std_logic;`
393			`iobar : inout std_logic;`
394			`o : out std_logic );`
395			`end component;`
396
397			`component alt_bidir_diff`
398			`generic (`
399			`io_standard : string := "NONE";`
400			`current_strength : string := "NONE";`
401			`current_strength_new : string := "NONE";`
402			`slew_rate : integer := -1;`
403			`location : string := "NONE";`
404			`enable_bus_hold : string := "NONE";`
405			`weak_pull_up_resistor : string := "NONE";`
406			`termination : string := "NONE";`
407			`input_termination : string := "NONE";`
408			`output_termination : string := "NONE";`
409			`lpm_type : string := "alt_bidir_diff" );`
410			`port(`
411			`oe : in std_logic;`
412			`bidirin : inout std_logic;`
413			`io : inout std_logic;`
414			`iobar : inout std_logic );`
415			`end component;`
416
417			`component alt_bidir_buf`
418			`generic (`
419			`io_standard : string := "NONE";`
420			`current_strength : string := "NONE";`
421			`current_strength_new : string := "NONE";`
422			`slew_rate : integer := -1;`
423			`location : string := "NONE";`
424			`enable_bus_hold : string := "NONE";`
425			`weak_pull_up_resistor : string := "NONE";`
426			`termination : string := "NONE";`
427			`input_termination : string := "NONE";`
428			`output_termination : string := "NONE";`
429			`lpm_type : string := "alt_bidir_buf" );`
430			`port(`
431			`oe : in std_logic;`
432			`bidirin : inout std_logic;`
433			`io : inout std_logic );`
434			`end component;`
435
436			`end altera_primitives_components;`
437