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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [altera_mf/] [simprims/] [altera_mf_components.vhd] - Blame information for rev 2

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1 2 dimamali 
-- Copyright (C) 1991-2007 Altera Corporation
2 
-- Your use of Altera Corporation's design tools, logic functions
3 
-- and other software and tools, and its AMPP partner logic
4 
-- functions, and any output files from any of the foregoing
5 
-- (including device programming or simulation files), and any
6 
-- associated documentation or information are expressly subject
7 
-- to the terms and conditions of the Altera Program License
8 
-- Subscription Agreement, Altera MegaCore Function License
9 
-- Agreement, or other applicable license agreement, including,
10 
-- without limitation, that your use is for the sole purpose of
11 
-- programming logic devices manufactured by Altera and sold by
12 
-- Altera or its authorized distributors.  Please refer to the
13 
-- applicable agreement for further details.
14 
 
15 
 
16 
-- Quartus II 7.1 Build 156 04/30/2007
17 
 
18 
----------------------------------------------------------------------------
19 
-- ALtera Megafunction Component Declaration File
20 
----------------------------------------------------------------------------
21 
 
22 
library ieee;
23 
use ieee.std_logic_1164.all;
24 
 
25 
package altera_mf_components is
26 
-- pragma translate_off
27 
 
28 
type altera_mf_logic_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
29 
 
30 
component lcell
31 
    port (
32 
        a_in : in std_logic;
33 
        a_out : out std_logic);
34 
end component;
35 
 
36 
component altcam
37 
    generic (
38 
        width          : natural := 1;
39 
        widthad        : natural := 1;
40 
        numwords       : natural := 1;
41 
        lpm_file       : string := "UNUSED";
42 
        lpm_filex      : string := "UNUSED";
43 
        match_mode     : string := "MULTIPLE";
44 
        output_reg     : string := "UNREGISTERED";
45 
        output_aclr    : string := "ON";
46 
        pattern_reg    : string := "INCLOCK";
47 
        pattern_aclr   : string := "ON";
48 
        wraddress_aclr : string := "ON";
49 
        wrx_reg        : string := "INCLOCK";
50 
        wrx_aclr       : string := "ON";
51 
        wrcontrol_aclr : string := "ON";
52 
        use_eab        : string := "ON";
53 
        lpm_hint       : string := "UNUSED";
54 
        lpm_type       : string := "altcam" );
55 
    port (
56 
        pattern    : in std_logic_vector(width-1 downto 0);
57 
        wrx        : in std_logic_vector(width-1 downto 0) := (others => 'Z');
58 
        wrxused    : in std_logic := '1';
59 
        wrdelete   : in std_logic := '0';
60 
        wraddress  : in std_logic_vector(widthad-1 downto 0);
61 
        wren       : in std_logic;
62 
        inclock    : in std_logic;
63 
        inclocken  : in std_logic := '1';
64 
        inaclr     : in std_logic := '0';
65 
        outclock   : in std_logic := '0';
66 
        outclocken : in std_logic := '1';
67 
        outaclr    : in std_logic := '0';
68 
        mstart     : in std_logic := 'X';
69 
        mnext      : in std_logic := '0';
70 
        maddress   : out std_logic_vector(widthad-1 downto 0);
71 
        mbits      : out std_logic_vector(numwords-1 downto 0);
72 
        mfound     : out std_logic;
73 
        mcount     : out std_logic_vector(widthad-1 downto 0);
74 
        rdbusy     : out std_logic;
75 
        wrbusy     : out std_logic );
76 
end component;
77 
 
78 
component altclklock
79 
    generic (
80 
        inclock_period          : natural := 10000;   -- units in ps
81 
        inclock_settings        : string := "UNUSED";
82 
        valid_lock_cycles       : natural := 5;
83 
        invalid_lock_cycles     : natural := 5;
84 
        valid_lock_multiplier   : natural := 5;
85 
        invalid_lock_multiplier : natural := 5;
86 
        operation_mode          : string := "NORMAL";
87 
        clock0_boost            : natural := 1;
88 
        clock0_divide           : natural := 1;
89 
        clock0_settings         : string := "UNUSED";
90 
        clock0_time_delay       : string := "0";
91 
        clock1_boost            : natural := 1;
92 
        clock1_divide           : natural := 1;
93 
        clock1_settings         : string := "UNUSED";
94 
        clock1_time_delay       : string := "0";
95 
        clock2_boost            : natural := 1;
96 
        clock2_divide           : natural := 1;
97 
        clock2_settings         : string := "UNUSED";
98 
        clock2_time_delay       : string := "0";
99 
        clock_ext_boost         : natural := 1;
100 
        clock_ext_divide        : natural := 1;
101 
        clock_ext_settings      : string := "UNUSED";
102 
        clock_ext_time_delay    : string := "0";
103 
        outclock_phase_shift    : natural := 0;   -- units in ps
104 
        intended_device_family  : string := "APEX20KE" ;
105 
        lpm_hint                : string  := "UNUSED";
106 
        lpm_type                : string := "altclklock" );
107 
    port(
108 
        inclock   : in std_logic;  -- required port, input reference clock
109 
        inclocken : in std_logic := '1';  -- PLL enable signal
110 
        fbin      : in std_logic := '1';  -- feedback input for the PLL
111 
        clock0    : out std_logic;  -- clock0 output
112 
        clock1    : out std_logic;  -- clock1 output
113 
        clock2    : out std_logic;  -- clock2 output, for Mercury only
114 
        clock_ext : out std_logic;  -- external clock output, for Mercury only
115 
        locked    : out std_logic );  -- PLL lock signal
116 
end component;
117 
 
118 
component altlvds_rx
119 
    generic (
120 
        number_of_channels          : natural;
121 
        deserialization_factor      : natural;
122 
        inclock_boost               : natural:= 0;
123 
        registered_output           : string := "ON";
124 
        inclock_period              : natural;
125 
        cds_mode                    : string := "UNUSED";
126 
        intended_device_family      : string := "APEX20KE";
127 
        input_data_rate             : natural:= 0;
128 
        inclock_data_alignment      : string := "EDGE_ALIGNED";
129 
        registered_data_align_input : string :="ON";
130 
        common_rx_tx_pll            : string :="ON";
131 
        enable_dpa_mode             : string := "OFF";
132 
        enable_dpa_fifo             : string := "ON";
133 
        use_dpll_rawperror          : string := "OFF";
134 
        use_coreclock_input         : string := "OFF";
135 
        dpll_lock_count             : natural:= 0;
136 
        dpll_lock_window            : natural:= 0;
137 
        outclock_resource           : string := "AUTO";
138 
        data_align_rollover         : natural := 10;
139 
        lose_lock_on_one_change     : string  := "OFF";
140 
        reset_fifo_at_first_lock    : string  := "ON";
141 
        use_external_pll            : string  := "OFF";
142 
        implement_in_les            : string  := "OFF";
143 
        buffer_implementation       : string  := "RAM";
144 
        port_rx_data_align          : string  := "PORT_CONNECTIVITY";
145 
        pll_operation_mode          : string  := "NORMAL";
146 
        x_on_bitslip                : string  := "ON";
147 
        use_no_phase_shift          : string  := "ON";
148 
        rx_align_data_reg           : string  := "RISING_EDGE";
149 
        inclock_phase_shift         : integer := 0;
150 
        enable_soft_cdr_mode        : string  := "OFF";
151 
        sim_dpa_output_clock_phase_shift : integer := 0;
152 
        lpm_hint                    : string := "UNUSED";
153 
        lpm_type                    : string := "altlvds_rx";
154 
        clk_src_is_pll              : string := "off" );
155 
    port (
156 
        rx_in                 : in std_logic_vector(number_of_channels-1 downto 0);
157 
        rx_inclock            : in std_logic := '0';
158 
        rx_syncclock          : in std_logic := '0';
159 
        rx_readclock          : in std_logic := '0';
160 
        rx_enable             : in std_logic := '1';
161 
        rx_deskew             : in std_logic := '0';
162 
        rx_pll_enable         : in std_logic := '1';
163 
        rx_data_align         : in std_logic := '0';
164 
        rx_reset              : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
165 
        rx_dpll_reset         : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
166 
        rx_dpll_hold          : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
167 
        rx_dpll_enable        : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
168 
        rx_fifo_reset         : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
169 
        rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
170 
        rx_cda_reset          : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
171 
        rx_coreclk            : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
172 
        pll_areset            : in std_logic := '0';
173 
        rx_out                : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
174 
        rx_outclock           : out std_logic;
175 
        rx_locked             : out std_logic;
176 
        rx_dpa_locked         : out std_logic_vector(number_of_channels-1 downto 0);
177 
        rx_cda_max            : out std_logic_vector(number_of_channels-1 downto 0);
178 
        rx_divfwdclk          : out std_logic_vector(number_of_channels-1 downto 0) );
179 
end component;
180 
 
181 
component altlvds_tx
182 
    generic (
183 
        number_of_channels     : natural;
184 
        deserialization_factor : natural:= 4;
185 
        inclock_boost          : natural := 0;
186 
        outclock_divide_by     : positive:= 1;
187 
        registered_input       : string := "ON";
188 
        multi_clock            : string := "OFF";
189 
        inclock_period         : natural;
190 
        center_align_msb       : string := "UNUSED";
191 
        intended_device_family : string := "APEX20KE";
192 
        output_data_rate       : natural:= 0;
193 
        outclock_resource      : string := "AUTO";
194 
        common_rx_tx_pll       : string := "ON";
195 
        inclock_data_alignment : string := "EDGE_ALIGNED";
196 
        outclock_alignment     : string := "EDGE_ALIGNED";
197 
        use_external_pll       : string := "OFF";
198 
        implement_in_les       : STRING  := "OFF";
199 
        preemphasis_setting    : natural := 0;
200 
        vod_setting            : natural := 0;
201 
        differential_drive     : natural := 0;
202 
        outclock_multiply_by   : natural := 1;
203 
        coreclock_divide_by    : natural := 2;
204 
        outclock_duty_cycle    : natural := 50;
205 
        inclock_phase_shift    : integer := 0;
206 
        outclock_phase_shift   : integer := 0;
207 
        use_no_phase_shift     : string  := "ON";
208 
        lpm_hint               : string  := "UNUSED";
209 
        lpm_type               : string := "altlvds_tx";
210 
        clk_src_is_pll         : string := "off" );
211 
    port (
212 
        tx_in           : in std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
213 
        tx_inclock      : in std_logic := '0';
214 
        tx_syncclock    : in std_logic := '0';
215 
        tx_enable       : in std_logic := '1';
216 
        sync_inclock    : in std_logic := '0';
217 
        tx_pll_enable   : in std_logic := '1';
218 
        pll_areset      : in std_logic := '0';
219 
        tx_out          : out std_logic_vector(number_of_channels-1 downto 0);
220 
        tx_outclock     : out std_logic;
221 
        tx_coreclock    : out std_logic;
222 
        tx_locked       : out std_logic );
223 
end component;
224 
 
225 
component altdpram
226 
    generic (
227 
        width                               : natural;
228 
        widthad                             : natural;
229 
        numwords                            : natural := 0;
230 
        lpm_file                            : string := "UNUSED";
231 
        lpm_hint                            : string := "USE_EAB=ON";
232 
        use_eab                             : string := "ON";
233 
        indata_reg                          : string := "INCLOCK";
234 
        indata_aclr                         : string := "ON";
235 
        wraddress_reg                       : string := "INCLOCK";
236 
        wraddress_aclr                      : string := "ON";
237 
        wrcontrol_reg                       : string := "INCLOCK";
238 
        wrcontrol_aclr                      : string := "ON";
239 
        rdaddress_reg                       : string := "OUTCLOCK";
240 
        rdaddress_aclr                      : string := "ON";
241 
        rdcontrol_reg                       : string := "OUTCLOCK";
242 
        rdcontrol_aclr                      : string := "ON";
243 
        outdata_reg                         : string := "UNREGISTERED";
244 
        outdata_aclr                        : string := "ON";
245 
        ram_block_type                      : string := "AUTO";
246 
        width_byteena                       : natural := 1;
247 
        byte_size                           : natural := 5;
248 
        read_during_write_mode_mixed_ports  : string := "DONT_CARE";
249 
        intended_device_family              : string := "APEX20KE";
250 
        lpm_type                            : string := "altdpram" );
251 
    port(
252 
        wren            : in std_logic := '0';
253 
        data            : in std_logic_vector(width-1 downto 0);
254 
        wraddress       : in std_logic_vector(widthad-1 downto 0);
255 
        wraddressstall  : in std_logic := '0';
256 
        inclock         : in std_logic := '0';
257 
        inclocken       : in std_logic := '1';
258 
        rden            : in std_logic := '1';
259 
        rdaddress       : in std_logic_vector(widthad-1 downto 0);
260 
        rdaddressstall  : in std_logic := '0';
261 
        byteena         : in std_logic_vector(width_byteena-1 downto 0) := (others => '1');
262 
        outclock        : in std_logic := '0';
263 
        outclocken      : in std_logic := '1';
264 
        aclr            : in std_logic := '0';
265 
        q               : out std_logic_vector(width-1 downto 0) );
266 
end component;
267 
 
268 
 
269 
component alt3pram
270 
    generic (
271 
        width                  : natural;
272 
        widthad                : natural;
273 
        numwords               : natural := 0;
274 
        lpm_file               : string := "UNUSED";
275 
        lpm_hint               : string := "USE_EAB=ON";
276 
        indata_reg             : string := "UNREGISTERED";
277 
        indata_aclr            : string := "OFF";
278 
        write_reg              : string := "UNREGISTERED";
279 
        write_aclr             : string := "OFF";
280 
        rdaddress_reg_a        : string := "UNREGISTERED";
281 
        rdaddress_aclr_a       : string := "OFF";
282 
        rdaddress_reg_b        : string := "UNREGISTERED";
283 
        rdaddress_aclr_b       : string := "OFF";
284 
        rdcontrol_reg_a        : string := "UNREGISTERED";
285 
        rdcontrol_aclr_a       : string := "OFF";
286 
        rdcontrol_reg_b        : string := "UNREGISTERED";
287 
        rdcontrol_aclr_b       : string := "OFF";
288 
        outdata_reg_a          : string := "UNREGISTERED";
289 
        outdata_aclr_a         : string := "OFF";
290 
        outdata_reg_b          : string := "UNREGISTERED";
291 
        outdata_aclr_b         : string := "OFF";
292 
        intended_device_family : string := "APEX20KE";
293 
        ram_block_type         : string  := "AUTO";
294 
        maximum_depth          : integer := 0;
295 
        lpm_type : string      := "alt3pram" );
296 
    port (
297 
        wren        : in std_logic := '0';
298 
        data        : in std_logic_vector(width-1 downto 0);
299 
        wraddress   : in std_logic_vector(widthad-1 downto 0);
300 
        inclock     : in std_logic := '0';
301 
        inclocken   : in std_logic := '1';
302 
        rden_a      : in std_logic := '1';
303 
        rden_b      : in std_logic := '1';
304 
        rdaddress_a : in std_logic_vector(widthad-1 downto 0);
305 
        rdaddress_b : in std_logic_vector(widthad-1 downto 0);
306 
        outclock    : in std_logic := '0';
307 
        outclocken  : in std_logic := '1';
308 
        aclr        : in std_logic := '0';
309 
        qa          : out std_logic_vector(width-1 downto 0);
310 
        qb          : out std_logic_vector(width-1 downto 0) );
311 
end component;
312 
 
313 
component altqpram
314 
    generic (
315 
        operation_mode            : string := "QUAD_PORT";
316 
        width_write_a             : natural := 1;
317 
        widthad_write_a           : natural := 1;
318 
        numwords_write_a          : natural := 0;  -- default = 2^widthad_write_a
319 
        indata_reg_a              : string := "INCLOCK_A";
320 
        indata_aclr_a             : string := "INACLR_A";
321 
        wrcontrol_wraddress_reg_a : string := "INCLOCK_A";
322 
        wrcontrol_aclr_a          : string := "INACLR_A";
323 
        wraddress_aclr_a          : string := "INACLR_A";
324 
        width_write_b             : natural := 1;  -- default = width_write_a
325 
        widthad_write_b           : natural := 1;  -- default = widthad_write_a
326 
        numwords_write_b          : natural := 0;  -- default = 2^widthad_write_b
327 
        indata_reg_b              : string := "INCLOCK_B";
328 
        indata_aclr_b             : string := "INACLR_B";
329 
        wrcontrol_wraddress_reg_b : string := "INCLOCK_B";
330 
        wrcontrol_aclr_b          : string := "INACLR_B";
331 
        wraddress_aclr_b          : string := "INACLR_B";
332 
        width_read_a              : natural := 1;
333 
        widthad_read_a            : natural := 1;
334 
        numwords_read_a           : natural := 0;  -- default = 2^widthad_read_a
335 
        rdcontrol_reg_a           : string := "OUTCLOCK_A";
336 
        rdcontrol_aclr_a          : string := "OUTACLR_A";
337 
        rdaddress_reg_a           : string := "OUTCLOCK_A";
338 
        rdaddress_aclr_a          : string := "OUTACLR_A";
339 
        outdata_reg_a             : string := "UNREGISTERED";
340 
        outdata_aclr_a            : string := "OUTACLR_A";
341 
        width_read_b              : natural := 1;  -- default = width_read_a
342 
        widthad_read_b            : natural := 1;  -- default = widthad_read_a
343 
        numwords_read_b           : natural := 0;  -- default = 2^widthad_read_b
344 
        rdcontrol_reg_b           : string := "OUTCLOCK_B";
345 
        rdcontrol_aclr_b          : string := "OUTACLR_B";
346 
        rdaddress_reg_b           : string := "OUTCLOCK_B";
347 
        rdaddress_aclr_b          : string := "OUTACLR_B";
348 
        outdata_reg_b             : string := "UNREGISTERED";
349 
        outdata_aclr_b            : string := "OUTACLR_B";
350 
        init_file                 : string := "UNUSED";
351 
        lpm_hint                  : string := "UNUSED";
352 
        lpm_type                  : string := "altqpram" );
353 
    port (
354 
        wren_a       : in std_logic := '0';
355 
        wren_b       : in std_logic := '0';
356 
        data_a       : in std_logic_vector(width_write_a-1 downto 0) := (OTHERS => '0');
357 
        data_b       : in std_logic_vector(width_write_b-1 downto 0) := (OTHERS => '0');
358 
        wraddress_a  : in std_logic_vector(widthad_write_a-1 downto 0) := (OTHERS => '0');
359 
        wraddress_b  : in std_logic_vector(widthad_write_b-1 downto 0) := (OTHERS => '0');
360 
        inclock_a    : in std_logic := '0';
361 
        inclock_b    : in std_logic := '0';
362 
        inclocken_a  : in std_logic := '1';
363 
        inclocken_b  : in std_logic := '1';
364 
        rden_a       : in std_logic := '1';
365 
        rden_b       : in std_logic := '1';
366 
        rdaddress_a  : in std_logic_vector(widthad_read_a-1 downto 0) := (OTHERS => '0');
367 
        rdaddress_b  : in std_logic_vector(widthad_read_b-1 downto 0) := (OTHERS => '0');
368 
        outclock_a   : in std_logic := '0';
369 
        outclock_b   : in std_logic := '0';
370 
        outclocken_a : in std_logic := '1';
371 
        outclocken_b : in std_logic := '1';
372 
        inaclr_a     : in std_logic := '0';
373 
        inaclr_b     : in std_logic := '0';
374 
        outaclr_a    : in std_logic := '0';
375 
        outaclr_b    : in std_logic := '0';
376 
        q_a          : out std_logic_vector(width_read_a-1 downto 0);
377 
        q_b          : out std_logic_vector(width_read_b-1 downto 0) );
378 
end component;
379 
 
380 
component scfifo
381 
    generic (
382 
        lpm_width               : natural;
383 
        lpm_widthu              : natural;
384 
        lpm_numwords            : natural;
385 
        lpm_showahead           : string := "OFF";
386 
        lpm_hint                : string := "USE_EAB=ON";
387 
        intended_device_family  : string := "NON_STRATIX";
388 
        almost_full_value       : natural := 0;
389 
        almost_empty_value      : natural := 0;
390 
        overflow_checking       : string := "ON";
391 
        underflow_checking      : string := "ON";
392 
        allow_rwcycle_when_full : string := "OFF";
393 
        add_ram_output_register : string  := "OFF";
394 
        use_eab                 : string := "ON";
395 
        lpm_type                : string := "scfifo";
396 
        maximum_depth           : natural := 0 );
397 
    port (
398 
        data         : in std_logic_vector(lpm_width-1 downto 0);
399 
        clock        : in std_logic;
400 
        wrreq        : in std_logic;
401 
        rdreq        : in std_logic;
402 
        aclr         : in std_logic := '0';
403 
        sclr         : in std_logic := '0';
404 
        full         : out std_logic;
405 
        almost_full  : out std_logic;
406 
        empty        : out std_logic;
407 
        almost_empty : out std_logic;
408 
        q            : out std_logic_vector(lpm_width-1 downto 0);
409 
        usedw        : out std_logic_vector(lpm_widthu-1 downto 0) );
410 
end component;
411 
 
412 
component dcfifo_mixed_widths
413 
    generic (
414 
        lpm_width               : natural;
415 
        lpm_widthu              : natural;
416 
        lpm_width_r             : natural := 0;
417 
        lpm_widthu_r            : natural := 0;
418 
        lpm_numwords            : natural;
419 
        lpm_showahead           : string := "OFF";
420 
        lpm_hint                : string := "USE_EAB=ON";
421 
        overflow_checking       : string := "ON";
422 
        underflow_checking      : string := "ON";
423 
        delay_rdusedw           : natural := 1;
424 
        delay_wrusedw           : natural := 1;
425 
        rdsync_delaypipe        : natural := 3;
426 
        wrsync_delaypipe        : natural := 3;
427 
        use_eab                 : string := "ON";
428 
        add_ram_output_register : string := "OFF";
429 
        add_width               : natural := 1;
430 
        clocks_are_synchronized : string := "FALSE";
431 
        ram_block_type          : string := "AUTO";
432 
        add_usedw_msb_bit       : string := "OFF";
433 
        write_aclr_synch        : string := "OFF";
434 
        lpm_type                : string := "dcfifo_mixed_widths";
435 
        intended_device_family  : string := "NON_STRATIX" );
436 
    port (
437 
        data    : in std_logic_vector(lpm_width-1 downto 0);
438 
        rdclk   : in std_logic;
439 
        wrclk   : in std_logic;
440 
        wrreq   : in std_logic;
441 
        rdreq   : in std_logic;
442 
        aclr    : in std_logic := '0';
443 
        rdfull  : out std_logic;
444 
        wrfull  : out std_logic;
445 
        wrempty : out std_logic;
446 
        rdempty : out std_logic;
447 
        q       : out std_logic_vector(lpm_width_r-1 downto 0);
448 
        rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0);
449 
        wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
450 
end component;
451 
 
452 
component dcfifo
453 
    generic (
454 
        lpm_width               : natural;
455 
        lpm_widthu              : natural;
456 
        lpm_numwords            : natural;
457 
        lpm_showahead           : string := "OFF";
458 
        lpm_hint                : string := "USE_EAB=ON";
459 
        overflow_checking       : string := "ON";
460 
        underflow_checking      : string := "ON";
461 
        delay_rdusedw           : natural := 1;
462 
        delay_wrusedw           : natural := 1;
463 
        rdsync_delaypipe        : natural := 3;
464 
        wrsync_delaypipe        : natural := 3;
465 
        use_eab                 : string := "ON";
466 
        add_ram_output_register : string := "OFF";
467 
        add_width               : natural := 1;
468 
        clocks_are_synchronized : string := "FALSE";
469 
        ram_block_type          : string := "AUTO";
470 
        add_usedw_msb_bit       : string := "OFF";
471 
        write_aclr_synch        : string := "OFF";
472 
        lpm_type                : string := "dcfifo";
473 
        intended_device_family  : string := "NON_STRATIX" );
474 
    port (
475 
        data    : in std_logic_vector(lpm_width-1 downto 0);
476 
        rdclk   : in std_logic;
477 
        wrclk   : in std_logic;
478 
        wrreq   : in std_logic;
479 
        rdreq   : in std_logic;
480 
        aclr    : in std_logic := '0';
481 
        rdfull  : out std_logic;
482 
        wrfull  : out std_logic;
483 
        wrempty : out std_logic;
484 
        rdempty : out std_logic;
485 
        q       : out std_logic_vector(lpm_width-1 downto 0);
486 
        rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
487 
        wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
488 
end component;
489 
 
490 
component altddio_in
491 
    generic (
492 
        width                  : positive; -- required parameter
493 
        invert_input_clocks    : string := "OFF";
494 
        intended_device_family : string := "MERCURY";
495 
        power_up_high          : string := "OFF";
496 
        lpm_hint               : string := "UNUSED";
497 
        lpm_type               : string := "altddio_in" );
498 
    port (
499 
        datain    : in std_logic_vector(width-1 downto 0);
500 
        inclock   : in std_logic;
501 
        inclocken : in std_logic := '1';
502 
        aset      : in std_logic := '0';
503 
        aclr      : in std_logic := '0';
504 
        sset      : in std_logic := '0';
505 
        sclr      : in std_logic := '0';
506 
        dataout_h : out std_logic_vector(width-1 downto 0);
507 
        dataout_l : out std_logic_vector(width-1 downto 0) );
508 
end component;
509 
 
510 
component altddio_out
511 
    generic (
512 
        width                  : positive;  -- required parameter
513 
        power_up_high          : string := "OFF";
514 
        oe_reg                 : string := "UNUSED";
515 
        extend_oe_disable      : string := "UNUSED";
516 
        invert_output          : string := "OFF";
517 
        intended_device_family : string := "MERCURY";
518 
        lpm_hint               : string := "UNUSED";
519 
        lpm_type               : string := "altddio_out" );
520 
    port (
521 
        datain_h   : in std_logic_vector(width-1 downto 0);
522 
        datain_l   : in std_logic_vector(width-1 downto 0);
523 
        outclock   : in std_logic;
524 
        outclocken : in std_logic := '1';
525 
        aset       : in std_logic := '0';
526 
        aclr       : in std_logic := '0';
527 
        sset       : in std_logic := '0';
528 
        sclr       : in std_logic := '0';
529 
        oe         : in std_logic := '1';
530 
        dataout    : out std_logic_vector(width-1 downto 0);
531 
        oe_out    : out std_logic_vector(width-1 downto 0) );
532 
end component;
533 
 
534 
component altddio_bidir
535 
    generic(
536 
        width                    : positive; -- required parameter
537 
        power_up_high            : string := "OFF";
538 
        oe_reg                   : string := "UNUSED";
539 
        extend_oe_disable        : string := "UNUSED";
540 
        implement_input_in_lcell : string := "UNUSED";
541 
        invert_output            : string := "OFF";
542 
        intended_device_family   : string := "MERCURY";
543 
        lpm_hint                 : string := "UNUSED";
544 
        lpm_type                 : string := "altddio_bidir" );
545 
    port (
546 
        datain_h   : in std_logic_vector(width-1 downto 0);
547 
        datain_l   : in std_logic_vector(width-1 downto 0);
548 
        inclock    : in std_logic := '0';
549 
        inclocken  : in std_logic := '1';
550 
        outclock   : in std_logic;
551 
        outclocken : in std_logic := '1';
552 
        aset       : in std_logic := '0';
553 
        aclr       : in std_logic := '0';
554 
        sset       : in std_logic := '0';
555 
        sclr       : in std_logic := '0';
556 
        oe         : in std_logic := '1';
557 
        dataout_h  : out std_logic_vector(width-1 downto 0);
558 
        dataout_l  : out std_logic_vector(width-1 downto 0);
559 
        combout    : out std_logic_vector(width-1 downto 0);
560 
        oe_out     : out std_logic_vector(width-1 downto 0);
561 
        dqsundelayedout : out std_logic_vector(width-1 downto 0);
562 
        padio      : inout std_logic_vector(width-1 downto 0) );
563 
end component;
564 
 
565 
component altcdr_rx
566 
    generic (
567 
        number_of_channels     : positive := 1;
568 
        deserialization_factor : positive := 1;
569 
        inclock_period         : positive;
570 
        inclock_boost          : positive := 1;
571 
        run_length             : integer := 62;
572 
        bypass_fifo            : string := "OFF";
573 
        intended_device_family : string := "MERCURY";
574 
        lpm_hint               : string := "UNUSED";
575 
        lpm_type               : string := "altcdr_rx" );
576 
    port (
577 
        rx_in        : in std_logic_vector(number_of_channels-1 downto 0);
578 
        rx_inclock   : in std_logic;
579 
        rx_coreclock : in std_logic;
580 
        rx_aclr      : in std_logic := '0';
581 
        rx_pll_aclr  : in std_logic := '0';
582 
        rx_fifo_rden : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
583 
        rx_out       : out std_logic_vector(deserialization_factor*number_of_channels-1 downto 0);
584 
        rx_outclock  : out std_logic;
585 
        rx_pll_locked: out std_logic;
586 
        rx_locklost  : out std_logic_vector(number_of_channels-1 downto 0);
587 
        rx_rlv       : out std_logic_vector(number_of_channels-1 downto 0);
588 
        rx_full      : out std_logic_vector(number_of_channels-1 downto 0);
589 
        rx_empty     : out std_logic_vector(number_of_channels-1 downto 0);
590 
        rx_rec_clk   : out std_logic_vector(number_of_channels-1 downto 0) );
591 
end component;
592 
 
593 
component altcdr_tx
594 
    generic (
595 
        number_of_channels     : positive := 1;
596 
        deserialization_factor : positive := 1;
597 
        inclock_period         : positive;  -- required parameter
598 
        inclock_boost          : positive := 1;
599 
        bypass_fifo            : string := "OFF";
600 
        intended_device_family : string := "MERCURY";
601 
        lpm_hint               : string := "UNUSED";
602 
        lpm_type               : string := "altcdr_tx" );
603 
    port (
604 
        tx_in        : in std_logic_vector(deserialization_factor*number_of_channels-1 downto 0);
605 
        tx_inclock   : in std_logic;
606 
        tx_coreclock : in std_logic;
607 
        tx_aclr      : in std_logic := '0';
608 
        tx_pll_aclr  : in std_logic := '0';
609 
        tx_fifo_wren : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
610 
 
611 
        tx_out       : out std_logic_vector(number_of_channels-1 downto 0);
612 
        tx_outclock  : out std_logic;
613 
        tx_pll_locked: out std_logic;
614 
        tx_empty     : out std_logic_vector(number_of_channels-1 downto 0);
615 
        tx_full      : out std_logic_vector(number_of_channels-1 downto 0) );
616 
end component;
617 
 
618 
component altshift_taps
619 
    generic (
620 
        number_of_taps    : integer := 4;
621 
        tap_distance      : integer := 3;
622 
        width             : integer := 8;
623 
        power_up_state : string := "CLEARED";
624 
        lpm_hint          : string := "UNUSED";
625 
        lpm_type          : string := "altshift_taps" );
626 
    port (
627 
        shiftin  : in std_logic_vector (width-1 downto 0);
628 
        clock    : in std_logic;
629 
        clken    : in std_logic := '1';
630 
        shiftout : out std_logic_vector (width-1 downto 0);
631 
        taps     : out std_logic_vector ((width*number_of_taps)-1 downto 0));
632 
end component;
633 
 
634 
component altmult_add
635 
    generic (
636 
        WIDTH_A                      : integer := 1;
637 
        WIDTH_B                      : integer := 1;
638 
        WIDTH_RESULT                 : integer := 1;
639 
        NUMBER_OF_MULTIPLIERS        : integer := 1;
640 
 
641 
    -- A inputs
642 
        INPUT_REGISTER_A0            : string := "CLOCK0";
643 
        INPUT_ACLR_A0                : string := "ACLR3";
644 
        INPUT_SOURCE_A0              : string := "DATAA";
645 
 
646 
        INPUT_REGISTER_A1            : string := "CLOCK0";
647 
        INPUT_ACLR_A1                : string := "ACLR3";
648 
        INPUT_SOURCE_A1              : string := "DATAA";
649 
 
650 
        INPUT_REGISTER_A2            : string := "CLOCK0";
651 
        INPUT_ACLR_A2                : string := "ACLR3";
652 
        INPUT_SOURCE_A2              : string := "DATAA";
653 
 
654 
        INPUT_REGISTER_A3            : string := "CLOCK0";
655 
        INPUT_ACLR_A3                : string := "ACLR3";
656 
        INPUT_SOURCE_A3              : string := "DATAA";
657 
 
658 
        PORT_SIGNA                   : string := "PORT_CONNECTIVITY";
659 
        REPRESENTATION_A             : string := "UNSIGNED";
660 
        SIGNED_REGISTER_A            : string := "CLOCK0";
661 
        SIGNED_ACLR_A                : string := "ACLR3";
662 
        SIGNED_PIPELINE_REGISTER_A   : string := "CLOCK0";
663 
        SIGNED_PIPELINE_ACLR_A       : string := "ACLR3";
664 
 
665 
    -- B inputs
666 
        INPUT_REGISTER_B0            : string := "CLOCK0";
667 
        INPUT_ACLR_B0                : string := "ACLR3";
668 
        INPUT_SOURCE_B0              : string := "DATAB";
669 
 
670 
        INPUT_REGISTER_B1            : string := "CLOCK0";
671 
        INPUT_ACLR_B1                : string := "ACLR3";
672 
        INPUT_SOURCE_B1              : string := "DATAB";
673 
 
674 
        INPUT_REGISTER_B2            : string := "CLOCK0";
675 
        INPUT_ACLR_B2                : string := "ACLR3";
676 
        INPUT_SOURCE_B2              : string := "DATAB";
677 
 
678 
        INPUT_REGISTER_B3            : string := "CLOCK0";
679 
        INPUT_ACLR_B3                : string := "ACLR3";
680 
        INPUT_SOURCE_B3              : string := "DATAB";
681 
 
682 
        PORT_SIGNB                   : string := "PORT_CONNECTIVITY";
683 
        REPRESENTATION_B             : string := "UNSIGNED";
684 
        SIGNED_REGISTER_B            : string := "CLOCK0";
685 
        SIGNED_ACLR_B                : string := "ACLR3";
686 
        SIGNED_PIPELINE_REGISTER_B   : string := "CLOCK0";
687 
        SIGNED_PIPELINE_ACLR_B       : string := "ACLR3";
688 
 
689 
        MULTIPLIER_REGISTER0         : string := "CLOCK0";
690 
        MULTIPLIER_ACLR0             : string := "ACLR3";
691 
        MULTIPLIER_REGISTER1         : string := "CLOCK0";
692 
        MULTIPLIER_ACLR1             : string := "ACLR3";
693 
        MULTIPLIER_REGISTER2         : string := "CLOCK0";
694 
        MULTIPLIER_ACLR2             : string := "ACLR3";
695 
        MULTIPLIER_REGISTER3         : string := "CLOCK0";
696 
        MULTIPLIER_ACLR3             : string := "ACLR3";
697 
 
698 
        PORT_ADDNSUB1                : string := "PORT_CONNECTIVITY";
699 
        ADDNSUB_MULTIPLIER_REGISTER1 : string := "CLOCK0";
700 
        ADDNSUB_MULTIPLIER_ACLR1     : string := "ACLR3";
701 
        ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 : string := "CLOCK0";
702 
        ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 : string := "ACLR3";
703 
 
704 
        PORT_ADDNSUB3                : string := "PORT_CONNECTIVITY";
705 
        ADDNSUB_MULTIPLIER_REGISTER3 : string := "CLOCK0";
706 
        ADDNSUB_MULTIPLIER_ACLR3     : string := "ACLR3";
707 
        ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3: string := "CLOCK0";
708 
        ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 : string := "ACLR3";
709 
 
710 
        ADDNSUB1_ROUND_ACLR                   : string := "ACLR3";
711 
        ADDNSUB1_ROUND_PIPELINE_ACLR          : string := "ACLR3";
712 
        ADDNSUB1_ROUND_REGISTER               : string := "CLOCK0";
713 
        ADDNSUB1_ROUND_PIPELINE_REGISTER      : string := "CLOCK0";
714 
        ADDNSUB3_ROUND_ACLR                   : string := "ACLR3";
715 
        ADDNSUB3_ROUND_PIPELINE_ACLR          : string := "ACLR3";
716 
        ADDNSUB3_ROUND_REGISTER               : string := "CLOCK0";
717 
        ADDNSUB3_ROUND_PIPELINE_REGISTER      : string := "CLOCK0";
718 
 
719 
        MULT01_ROUND_ACLR                     : string := "ACLR3";
720 
        MULT01_ROUND_REGISTER                 : string := "CLOCK0";
721 
        MULT01_SATURATION_REGISTER            : string := "CLOCK0";
722 
        MULT01_SATURATION_ACLR                : string := "ACLR3";
723 
        MULT23_ROUND_REGISTER                 : string := "CLOCK0";
724 
        MULT23_ROUND_ACLR                     : string := "ACLR3";
725 
        MULT23_SATURATION_REGISTER            : string := "CLOCK0";
726 
        MULT23_SATURATION_ACLR                : string := "ACLR3";
727 
 
728 
        multiplier1_direction        : string := "ADD";
729 
        multiplier3_direction        : string := "ADD";
730 
 
731 
        OUTPUT_REGISTER              : string := "CLOCK0";
732 
        OUTPUT_ACLR                  : string := "ACLR0";
733 
 
734 
        -- StratixII parameters
735 
        multiplier01_rounding    : string := "NO";
736 
        multiplier01_saturation : string := "NO";
737 
        multiplier23_rounding    : string := "NO";
738 
        multiplier23_saturation : string := "NO";
739 
        adder1_rounding         : string := "NO";
740 
        adder3_rounding         : string := "NO";
741 
        port_mult0_is_saturated : string := "UNUSED";
742 
        port_mult1_is_saturated : string := "UNUSED";
743 
        port_mult2_is_saturated : string := "UNUSED";
744 
        port_mult3_is_saturated : string := "UNUSED";
745 
 
746 
        -- Stratix III parameters
747 
        scanouta_register : string := "UNREGISTERED";
748 
        scanouta_aclr     : string := "NONE";
749 
 
750 
        -- Rounding parameters
751 
        output_rounding : string := "NO";
752 
        output_round_type : string := "NEAREST_INTEGER";
753 
        width_msb : integer := 17;
754 
        output_round_register : string := "UNREGISTERED";
755 
        output_round_aclr : string := "NONE";
756 
        output_round_pipeline_register : string := "UNREGISTERED";
757 
        output_round_pipeline_aclr : string := "NONE";
758 
 
759 
        chainout_rounding : string := "NO";
760 
        chainout_round_register : string := "UNREGISTERED";
761 
        chainout_round_aclr : string := "NONE";
762 
        chainout_round_pipeline_register : string := "UNREGISTERED";
763 
        chainout_round_pipeline_aclr : string := "NONE";
764 
        chainout_round_output_register : string := "UNREGISTERED";
765 
        chainout_round_output_aclr : string := "NONE";
766 
 
767 
        -- saturation parameters
768 
        port_output_is_overflow : string := "PORT_UNUSED";
769 
        port_chainout_sat_is_overflow : string := "PORT_UNUSED";
770 
        output_saturation : string := "NO";
771 
        output_saturate_type : string := "ASYMMETRIC";
772 
        width_saturate_sign : integer := 1;
773 
        output_saturate_register : string := "UNREGISTERED";
774 
        output_saturate_aclr : string := "NONE";
775 
        output_saturate_pipeline_register : string := "UNREGISTERED";
776 
        output_saturate_pipeline_aclr : string := "NONE";
777 
 
778 
        chainout_saturation : string := "NO";
779 
        chainout_saturate_register : string := "UNREGISTERED";
780 
        chainout_saturate_aclr : string := "NONE";
781 
        chainout_saturate_pipeline_register : string := "UNREGISTERED";
782 
        chainout_saturate_pipeline_aclr : string := "NONE";
783 
        chainout_saturate_output_register : string := "UNREGISTERED";
784 
        chainout_saturate_output_aclr : string := "NONE";
785 
 
786 
        -- chainout parameters
787 
        chainout_adder : string := "NO";
788 
        chainout_register : string := "UNREGISTERED";
789 
        chainout_aclr : string := "NONE";
790 
        width_chainin : integer := 1;
791 
        zero_chainout_output_register : string := "UNREGISTERED";
792 
        zero_chainout_output_aclr : string := "NONE";
793 
 
794 
        -- rotate & shift parameters
795 
        shift_mode : string := "NO";
796 
        rotate_aclr : string := "NONE";
797 
        rotate_register : string := "UNREGISTERED";
798 
        rotate_pipeline_register : string := "UNREGISTERED";
799 
        rotate_pipeline_aclr : string := "NONE";
800 
        rotate_output_register : string := "UNREGISTERED";
801 
        rotate_output_aclr : string := "NONE";
802 
        shift_right_register : string := "UNREGISTERED";
803 
        shift_right_aclr : string := "NONE";
804 
        shift_right_pipeline_register : string := "UNREGISTERED";
805 
        shift_right_pipeline_aclr : string := "NONE";
806 
        shift_right_output_register : string := "UNREGISTERED";
807 
        shift_right_output_aclr : string := "NONE";
808 
 
809 
        -- loopback parameters
810 
        zero_loopback_register : string := "UNREGISTERED";
811 
        zero_loopback_aclr : string := "NONE";
812 
        zero_loopback_pipeline_register : string := "UNREGISTERED";
813 
        zero_loopback_pipeline_aclr : string := "NONE";
814 
        zero_loopback_output_register : string := "UNREGISTERED";
815 
        zero_loopback_output_aclr : string := "NONE";
816 
 
817 
        -- accumulator parameters
818 
        accum_sload_register : string := "UNREGISTERED";
819 
        accum_sload_aclr : string := "NONE";
820 
        accum_sload_pipeline_register : string := "UNREGISTERED";
821 
        accum_sload_pipeline_aclr : string := "NONE";
822 
        accum_direction : string := "ADD";
823 
        accumulator : string := "NO";
824 
 
825 
        EXTRA_LATENCY                : integer :=0;
826 
        DEDICATED_MULTIPLIER_CIRCUITRY:string  := "AUTO";
827 
        DSP_BLOCK_BALANCING          : string := "AUTO";
828 
        lpm_hint                     : string := "UNUSED";
829 
        lpm_type                     : string := "altmult_add";
830 
        intended_device_family       : string := "Stratix" );
831 
    port (
832 
        dataa : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_A -1 downto 0);
833 
        datab : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 downto 0);
834 
 
835 
        scanina : in std_logic_vector(width_a -1 downto 0) := (others => '0');
836 
        scaninb : in std_logic_vector(width_b -1 downto 0) := (others => '0');
837 
 
838 
        sourcea : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
839 
        sourceb : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
840 
 
841 
 
842 
        -- clock ports
843 
        clock3     : in std_logic := '1';
844 
        clock2     : in std_logic := '1';
845 
        clock1     : in std_logic := '1';
846 
        clock0     : in std_logic := '1';
847 
        aclr3      : in std_logic := '0';
848 
        aclr2      : in std_logic := '0';
849 
        aclr1      : in std_logic := '0';
850 
        aclr0      : in std_logic := '0';
851 
        ena3       : in std_logic := '1';
852 
        ena2       : in std_logic := '1';
853 
        ena1       : in std_logic := '1';
854 
        ena0       : in std_logic := '1';
855 
 
856 
        -- control signals
857 
        signa      : in std_logic := 'Z';
858 
        signb      : in std_logic := 'Z';
859 
        addnsub1   : in std_logic := 'Z';
860 
        addnsub3   : in std_logic := 'Z';
861 
 
862 
        -- StratixII only input ports
863 
        mult01_round        : in std_logic := '0';
864 
        mult23_round        : in std_logic := '0';
865 
        mult01_saturation   : in std_logic := '0';
866 
        mult23_saturation   : in std_logic := '0';
867 
        addnsub1_round      : in std_logic := '0';
868 
        addnsub3_round      : in std_logic := '0';
869 
 
870 
        -- Stratix III only input ports
871 
        output_round : in std_logic := '0';
872 
        chainout_round : in std_logic := '0';
873 
        output_saturate : in std_logic := '0';
874 
        chainout_saturate : in std_logic := '0';
875 
        chainin : in std_logic_vector (width_chainin - 1 downto 0) := (others => '0');
876 
        zero_chainout : in std_logic := '0';
877 
        rotate : in std_logic := '0';
878 
        shift_right : in std_logic := '0';
879 
        zero_loopback : in std_logic := '0';
880 
        accum_sload : in std_logic := '0';
881 
 
882 
        -- output ports
883 
        result     : out std_logic_vector(WIDTH_RESULT -1 downto 0);
884 
        scanouta   : out std_logic_vector (WIDTH_A -1 downto 0);
885 
        scanoutb   : out std_logic_vector (WIDTH_B -1 downto 0);
886 
 
887 
        -- StratixII only output ports
888 
        mult0_is_saturated : out std_logic := '0';
889 
        mult1_is_saturated : out std_logic := '0';
890 
        mult2_is_saturated : out std_logic := '0';
891 
        mult3_is_saturated : out std_logic := '0';
892 
 
893 
        -- Stratix III only output ports
894 
        overflow : out std_logic := '0';
895 
        chainout_sat_overflow : out std_logic := '0');
896 
end component;
897 
 
898 
component altmult_accum
899 
    generic (
900 
        width_a                        : integer := 1;
901 
        width_b                        : integer := 1;
902 
        width_result                   : integer := 2;
903 
        width_upper_data               : integer := 1;
904 
        input_source_a                 : string  := "DATAA";
905 
        input_source_b                 : string  := "DATAB";
906 
        input_reg_a                    : string := "CLOCK0";
907 
        input_aclr_a                   : string := "ACLR3";
908 
        input_reg_b                    : string := "CLOCK0";
909 
        input_aclr_b                   : string := "ACLR3";
910 
        port_addnsub                   : string := "PORT_CONNECTIVITY";
911 
        addnsub_reg                    : string := "CLOCK0";
912 
        addnsub_aclr                   : string := "ACLR3";
913 
        addnsub_pipeline_reg           : string := "CLOCK0";
914 
        addnsub_pipeline_aclr          : string := "ACLR3";
915 
        accum_direction                : string := "ADD";
916 
        accum_sload_reg                : string := "CLOCK0";
917 
        accum_sload_aclr               : string := "ACLR3";
918 
        accum_sload_pipeline_reg       : string := "CLOCK0";
919 
        accum_sload_pipeline_aclr      : string := "ACLR3";
920 
        representation_a               : string := "UNSIGNED";
921 
        port_signa                     : string := "PORT_CONNECTIVITY";
922 
        sign_reg_a                     : string := "CLOCK0";
923 
        sign_aclr_a                    : string := "ACLR3";
924 
        sign_pipeline_reg_a            : string := "CLOCK0";
925 
        sign_pipeline_aclr_a           : string := "ACLR3";
926 
        representation_b               : string := "UNSIGNED";
927 
        port_signb                     : string := "PORT_CONNECTIVITY";
928 
        sign_reg_b                     : string := "CLOCK0";
929 
        sign_aclr_b                    : string := "ACLR3";
930 
        sign_pipeline_reg_b            : string := "CLOCK0";
931 
        sign_pipeline_aclr_b           : string := "ACLR3";
932 
        multiplier_reg                 : string := "CLOCK0";
933 
        multiplier_aclr                : string := "ACLR3";
934 
        output_reg                     : string := "CLOCK0";
935 
        output_aclr                    : string := "ACLR0";
936 
        extra_multiplier_latency       : integer := 0;
937 
        extra_accumulator_latency      : integer := 0;
938 
        dedicated_multiplier_circuitry : string  := "AUTO";
939 
        dsp_block_balancing            : string := "AUTO";
940 
        lpm_hint                       : string := "UNUSED";
941 
        lpm_type                       : string  := "altmult_accum";
942 
        intended_device_family         : string  := "Stratix";
943 
        multiplier_rounding            : string  := "NO";
944 
        multiplier_saturation          : string  := "NO";
945 
        accumulator_rounding           : string  := "NO";
946 
        accumulator_saturation         : string  := "NO";
947 
        port_mult_is_saturated         : string  := "UNUSED";
948 
        port_accum_is_saturated        : string  := "UNUSED";
949 
        mult_round_aclr                : string  := "ACLR3";
950 
        mult_round_reg                 : string  := "CLOCK0";
951 
        mult_saturation_aclr           : string  := "ACLR3";
952 
        mult_saturation_reg            : string  := "CLOCK0";
953 
        accum_round_aclr               : string  := "ACLR3";
954 
        accum_round_reg                : string  := "CLOCK3";
955 
        accum_round_pipeline_aclr      : string  := "ACLR3";
956 
        accum_round_pipeline_reg       : string  := "CLOCK0";
957 
        accum_saturation_aclr          : string  := "ACLR3";
958 
        accum_saturation_reg           : string  := "CLOCK0";
959 
        accum_saturation_pipeline_aclr : string  := "ACLR3";
960 
        accum_saturation_pipeline_reg  : string  := "CLOCK0";
961 
        accum_sload_upper_data_aclr    : string  := "ACLR3";
962 
        accum_sload_upper_data_pipeline_aclr : string  := "ACLR3";
963 
        accum_sload_upper_data_pipeline_reg  : string  := "CLOCK0";
964 
        accum_sload_upper_data_reg     : string  := "CLOCK0" );
965 
 
966 
    port (
967 
        dataa        : in std_logic_vector(width_a -1 downto 0);
968 
        datab        : in std_logic_vector(width_b -1 downto 0);
969 
        scanina      : in std_logic_vector(width_a -1 downto 0) := (others => 'Z');
970 
        scaninb      : in std_logic_vector(width_b -1 downto 0) := (others => 'Z');
971 
        accum_sload_upper_data : in std_logic_vector(width_result -1 downto width_result - width_upper_data) := (others => '0');
972 
        sourcea      : in std_logic := '1';
973 
        sourceb      : in std_logic := '1';
974 
        -- control signals
975 
        addnsub      : in std_logic := 'Z';
976 
        accum_sload  : in std_logic := '0';
977 
        signa        : in std_logic := 'Z';
978 
        signb        : in std_logic := 'Z';
979 
        -- clock ports
980 
        clock0       : in std_logic := '1';
981 
        clock1       : in std_logic := '1';
982 
        clock2       : in std_logic := '1';
983 
        clock3       : in std_logic := '1';
984 
        ena0         : in std_logic := '1';
985 
        ena1         : in std_logic := '1';
986 
        ena2         : in std_logic := '1';
987 
        ena3         : in std_logic := '1';
988 
        aclr0        : in std_logic := '0';
989 
        aclr1        : in std_logic := '0';
990 
        aclr2        : in std_logic := '0';
991 
        aclr3        : in std_logic := '0';
992 
        -- round and saturation ports
993 
        mult_round       : in std_logic := '0';
994 
        mult_saturation  : in std_logic := '0';
995 
        accum_round      : in std_logic := '0';
996 
        accum_saturation : in std_logic := '0';
997 
        -- output ports
998 
        result       : out std_logic_vector(width_result -1 downto 0);
999 
        overflow     : out std_logic;
1000 
        scanouta     : out std_logic_vector (width_a -1 downto 0);
1001 
        scanoutb     : out std_logic_vector (width_b -1 downto 0);
1002 
        mult_is_saturated  : out std_logic := '0';
1003 
        accum_is_saturated : out std_logic := '0' );
1004 
end component;
1005 
 
1006 
component altaccumulate
1007 
    generic (
1008 
        width_in           : integer:= 4;
1009 
        width_out          : integer:= 8;
1010 
        lpm_representation : string := "UNSIGNED";
1011 
        extra_latency      : integer:= 0;
1012 
        use_wys            : string := "ON";
1013 
        lpm_hint           : string := "UNUSED";
1014 
        lpm_type           : string := "altaccumulate" );
1015 
 
1016 
    port (
1017 
        -- Input ports
1018 
        cin       : in std_logic := 'Z';
1019 
        data      : in std_logic_vector(width_in -1 downto 0);  -- Required port
1020 
        add_sub   : in std_logic := '1';
1021 
        clock     : in std_logic;   -- Required port
1022 
        sload     : in std_logic := '0';
1023 
        clken     : in std_logic := '1';
1024 
        sign_data : in std_logic := '0';
1025 
        aclr      : in std_logic := '0';
1026 
 
1027 
        -- Output ports
1028 
        result    : out std_logic_vector(width_out -1 downto 0) := (others => '0');
1029 
        cout      : out std_logic := '0';
1030 
        overflow  : out std_logic := '0' );
1031 
end component;
1032 
 
1033 
component altsyncram
1034 
    generic (
1035 
        operation_mode                 : string := "BIDIR_DUAL_PORT";
1036 
        -- port a parameters
1037 
        width_a                        : integer := 1;
1038 
        widthad_a                      : integer := 1;
1039 
        numwords_a                     : integer := 0;
1040 
        -- registering parameters
1041 
        -- port a read parameters
1042 
        outdata_reg_a                  : string := "UNREGISTERED";
1043 
        -- clearing parameters
1044 
        address_aclr_a                 : string := "NONE";
1045 
        outdata_aclr_a                 : string := "NONE";
1046 
        -- clearing parameters
1047 
        -- port a write parameters
1048 
        indata_aclr_a                  : string := "NONE";
1049 
        wrcontrol_aclr_a               : string := "NONE";
1050 
        -- clear for the byte enable port reigsters which are clocked by clk0
1051 
        byteena_aclr_a                 : string := "NONE";
1052 
        -- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
1053 
        width_byteena_a                : integer := 1;
1054 
        -- port b parameters
1055 
        width_b                        : integer := 1;
1056 
        widthad_b                      : integer := 1;
1057 
        numwords_b                     : integer := 0;
1058 
        -- registering parameters
1059 
        -- port b read parameters
1060 
        rdcontrol_reg_b                : string := "CLOCK1";
1061 
        address_reg_b                  : string := "CLOCK1";
1062 
        outdata_reg_b                  : string := "UNREGISTERED";
1063 
        -- clearing parameters
1064 
        outdata_aclr_b                 : string := "NONE";
1065 
        rdcontrol_aclr_b               : string := "NONE";
1066 
        -- registering parameters
1067 
        -- port b write parameters
1068 
        indata_reg_b                   : string := "CLOCK1";
1069 
        wrcontrol_wraddress_reg_b      : string := "CLOCK1";
1070 
        -- registering parameter for the byte enable reister for port b
1071 
        byteena_reg_b                  : string := "CLOCK1";
1072 
        -- clearing parameters
1073 
        indata_aclr_b                  : string := "NONE";
1074 
        wrcontrol_aclr_b               : string := "NONE";
1075 
        address_aclr_b                 : string := "NONE";
1076 
        -- clear parameter for byte enable port register
1077 
        byteena_aclr_b                 : string := "NONE";
1078 
        -- StratixII only : to bypass clock enable or using clock enable
1079 
        clock_enable_input_a           : string := "NORMAL";
1080 
        clock_enable_output_a          : string := "NORMAL";
1081 
        clock_enable_input_b           : string := "NORMAL";
1082 
        clock_enable_output_b          : string := "NORMAL";
1083 
        -- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
1084 
        width_byteena_b                : integer := 1;
1085 
        -- clock enable setting for the core
1086 
        clock_enable_core_a            : string := "USE_INPUT_CLKEN";
1087 
        clock_enable_core_b            : string := "USE_INPUT_CLKEN";
1088 
        -- read-during-write-same-port setting
1089 
        read_during_write_mode_port_a  : string := "NEW_DATA_NO_NBE_READ";
1090 
        read_during_write_mode_port_b  : string := "NEW_DATA_NO_NBE_READ";
1091 
        -- ECC status ports setting
1092 
        enable_ecc                     : string := "FALSE";
1093 
        -- global parameters
1094 
        -- width of a byte for byte enables
1095 
        byte_size                      : integer := 0;
1096 
        read_during_write_mode_mixed_ports: string := "DONT_CARE";
1097 
        -- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM"
1098 
        ram_block_type                 : string := "AUTO";
1099 
        -- determine whether LE support is turned on or off for altsyncram
1100 
        implement_in_les               : string := "OFF";
1101 
        -- determine whether RAM would be power up to uninitialized or not
1102 
        power_up_uninitialized         : string := "FALSE";
1103 
 
1104 
        -- general operation parameters
1105 
        init_file                      : string := "UNUSED";
1106 
        init_file_layout               : string := "UNUSED";
1107 
        maximum_depth                  : integer := 0;
1108 
        intended_device_family         : string := "Stratix";
1109 
        lpm_hint                       : string := "UNUSED";
1110 
        lpm_type                       : string := "altsyncram" );
1111 
    port (
1112 
        wren_a    : in std_logic := '0';
1113 
        wren_b    : in std_logic := '0';
1114 
        rden_a    : in std_logic := '1';
1115 
        rden_b    : in std_logic := '1';
1116 
        data_a    : in std_logic_vector(width_a - 1 downto 0):= (others => '1');
1117 
        data_b    : in std_logic_vector(width_b - 1 downto 0):= (others => '1');
1118 
        address_a : in std_logic_vector(widthad_a - 1 downto 0);
1119 
        address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1');
1120 
 
1121 
        clock0    : in std_logic := '1';
1122 
        clock1    : in std_logic := '1';
1123 
        clocken0  : in std_logic := '1';
1124 
        clocken1  : in std_logic := '1';
1125 
        clocken2  : in std_logic := '1';
1126 
        clocken3  : in std_logic := '1';
1127 
        aclr0     : in std_logic := '0';
1128 
        aclr1     : in std_logic := '0';
1129 
        byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1');
1130 
        byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => '1');
1131 
 
1132 
        addressstall_a : in std_logic := '0';
1133 
        addressstall_b : in std_logic := '0';
1134 
 
1135 
        q_a            : out std_logic_vector(width_a - 1 downto 0);
1136 
        q_b            : out std_logic_vector(width_b - 1 downto 0);
1137 
 
1138 
        eccstatus      : out std_logic_vector(2 downto 0) );
1139 
end component;
1140 
 
1141 
component altpll
1142 
    generic (
1143 
        intended_device_family     : string := "Stratix" ;
1144 
        operation_mode             : string := "NORMAL" ;
1145 
        pll_type                   : string := "AUTO" ;
1146 
        qualify_conf_done          : string := "OFF" ;
1147 
        compensate_clock           : string := "CLK0" ;
1148 
        scan_chain                 : string := "LONG";
1149 
        primary_clock              : string := "inclk0" ;
1150 
        inclk0_input_frequency     : natural;   -- required parameter
1151 
        inclk1_input_frequency     : natural := 0;
1152 
        gate_lock_signal           : string := "NO";
1153 
        gate_lock_counter          : integer := 0;
1154 
        lock_high                  : natural := 1;
1155 
        lock_low                   : natural := 5;
1156 
        valid_lock_multiplier      : natural := 1;
1157 
        invalid_lock_multiplier    : natural := 5;
1158 
        switch_over_type           : string := "AUTO";
1159 
        switch_over_on_lossclk     : string := "OFF" ;
1160 
        switch_over_on_gated_lock  : string := "OFF" ;
1161 
        enable_switch_over_counter : string := "OFF";
1162 
        switch_over_counter        : natural := 0;
1163 
        feedback_source            : string := "EXTCLK0" ;
1164 
        bandwidth                  : natural := 0;
1165 
        bandwidth_type             : string := "UNUSED";
1166 
        spread_frequency           : natural := 0;
1167 
        down_spread                : string := "0.0";
1168 
        self_reset_on_gated_loss_lock : string := "OFF";
1169 
        self_reset_on_loss_lock      : string := "OFF";
1170 
        self_reset_on_loss_clock     : string := "OFF";
1171 
        lock_window_ui             : string := "0.05";
1172 
        width_clock                : natural := 6;
1173 
        width_phasecounterselect   : natural := 4;
1174 
        charge_pump_current_bits   : natural := 9999;
1175 
        loop_filter_c_bits         : natural := 9999;
1176 
        loop_filter_r_bits         : natural := 9999;
1177 
 
1178 
        -- simulation-only parameters
1179 
        simulation_type            : string := "functional";
1180 
        source_is_pll              : string := "off";
1181 
        skip_vco                   : string := "off";
1182 
 
1183 
        -- internal clock specifications
1184 
        clk9_multiply_by           : natural := 1;
1185 
        clk8_multiply_by           : natural := 1;
1186 
        clk7_multiply_by           : natural := 1;
1187 
        clk6_multiply_by           : natural := 1;
1188 
        clk5_multiply_by           : natural := 1;
1189 
        clk4_multiply_by           : natural := 1;
1190 
        clk3_multiply_by           : natural := 1;
1191 
        clk2_multiply_by           : natural := 1;
1192 
        clk1_multiply_by           : natural := 1;
1193 
        clk0_multiply_by           : natural := 1;
1194 
        clk9_divide_by             : natural := 1;
1195 
        clk8_divide_by             : natural := 1;
1196 
        clk7_divide_by             : natural := 1;
1197 
        clk6_divide_by             : natural := 1;
1198 
        clk5_divide_by             : natural := 1;
1199 
        clk4_divide_by             : natural := 1;
1200 
        clk3_divide_by             : natural := 1;
1201 
        clk2_divide_by             : natural := 1;
1202 
        clk1_divide_by             : natural := 1;
1203 
        clk0_divide_by             : natural := 1;
1204 
        clk9_phase_shift           : string := "0";
1205 
        clk8_phase_shift           : string := "0";
1206 
        clk7_phase_shift           : string := "0";
1207 
        clk6_phase_shift           : string := "0";
1208 
        clk5_phase_shift           : string := "0";
1209 
        clk4_phase_shift           : string := "0";
1210 
        clk3_phase_shift           : string := "0";
1211 
        clk2_phase_shift           : string := "0";
1212 
        clk1_phase_shift           : string := "0";
1213 
        clk0_phase_shift           : string := "0";
1214 
        clk5_time_delay            : string := "0";
1215 
        clk4_time_delay            : string := "0";
1216 
        clk3_time_delay            : string := "0";
1217 
        clk2_time_delay            : string := "0";
1218 
        clk1_time_delay            : string := "0";
1219 
        clk0_time_delay            : string := "0";
1220 
        clk9_duty_cycle            : natural := 50;
1221 
        clk8_duty_cycle            : natural := 50;
1222 
        clk7_duty_cycle            : natural := 50;
1223 
        clk6_duty_cycle            : natural := 50;
1224 
        clk5_duty_cycle            : natural := 50;
1225 
        clk4_duty_cycle            : natural := 50;
1226 
        clk3_duty_cycle            : natural := 50;
1227 
        clk2_duty_cycle            : natural := 50;
1228 
        clk1_duty_cycle            : natural := 50;
1229 
        clk0_duty_cycle            : natural := 50;
1230 
        clk2_output_frequency      : natural := 0;
1231 
        clk1_output_frequency      : natural := 0;
1232 
        clk0_output_frequency      : natural := 0;
1233 
        clk9_use_even_counter_mode : string := "OFF";
1234 
        clk8_use_even_counter_mode : string := "OFF";
1235 
        clk7_use_even_counter_mode : string := "OFF";
1236 
        clk6_use_even_counter_mode : string := "OFF";
1237 
        clk5_use_even_counter_mode : string := "OFF";
1238 
        clk4_use_even_counter_mode : string := "OFF";
1239 
        clk3_use_even_counter_mode : string := "OFF";
1240 
        clk2_use_even_counter_mode : string := "OFF";
1241 
        clk1_use_even_counter_mode : string := "OFF";
1242 
        clk0_use_even_counter_mode : string := "OFF";
1243 
        clk9_use_even_counter_value  : string := "OFF";
1244 
        clk8_use_even_counter_value  : string := "OFF";
1245 
        clk7_use_even_counter_value  : string := "OFF";
1246 
        clk6_use_even_counter_value  : string := "OFF";
1247 
        clk5_use_even_counter_value  : string := "OFF";
1248 
        clk4_use_even_counter_value  : string := "OFF";
1249 
        clk3_use_even_counter_value  : string := "OFF";
1250 
        clk2_use_even_counter_value  : string := "OFF";
1251 
        clk1_use_even_counter_value  : string := "OFF";
1252 
        clk0_use_even_counter_value  : string := "OFF";
1253 
 
1254 
        -- external clock specifications
1255 
        extclk3_multiply_by        : natural := 1;
1256 
        extclk2_multiply_by        : natural := 1;
1257 
        extclk1_multiply_by        : natural := 1;
1258 
        extclk0_multiply_by        : natural := 1;
1259 
        extclk3_divide_by          : natural := 1;
1260 
        extclk2_divide_by          : natural := 1;
1261 
        extclk1_divide_by          : natural := 1;
1262 
        extclk0_divide_by          : natural := 1;
1263 
        extclk3_phase_shift        : string := "0";
1264 
        extclk2_phase_shift        : string := "0";
1265 
        extclk1_phase_shift        : string := "0";
1266 
        extclk0_phase_shift        : string := "0";
1267 
        extclk3_time_delay         : string := "0";
1268 
        extclk2_time_delay         : string := "0";
1269 
        extclk1_time_delay         : string := "0";
1270 
        extclk0_time_delay         : string := "0";
1271 
        extclk3_duty_cycle         : natural := 50;
1272 
        extclk2_duty_cycle         : natural := 50;
1273 
        extclk1_duty_cycle         : natural := 50;
1274 
        extclk0_duty_cycle         : natural := 50;
1275 
        vco_multiply_by            : integer := 0;
1276 
        vco_divide_by              : integer := 0;
1277 
        sclkout0_phase_shift       : string := "0";
1278 
        sclkout1_phase_shift       : string := "0";
1279 
 
1280 
        -- advanced user parameters
1281 
        vco_min                    : natural := 0;
1282 
        vco_max                    : natural := 0;
1283 
        vco_center                 : natural := 0;
1284 
        pfd_min                    : natural := 0;
1285 
        pfd_max                    : natural := 0;
1286 
        m_initial                  : natural := 1;
1287 
        m                          : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself
1288 
        n                          : natural := 1;
1289 
        m2                         : natural := 1;
1290 
        n2                         : natural := 1;
1291 
        ss                         : natural := 0;
1292 
        c0_high                    : natural := 1;
1293 
        c1_high                    : natural := 1;
1294 
        c2_high                    : natural := 1;
1295 
        c3_high                    : natural := 1;
1296 
        c4_high                    : natural := 1;
1297 
        c5_high                    : natural := 1;
1298 
        c6_high                    : natural := 1;
1299 
        c7_high                    : natural := 1;
1300 
        c8_high                    : natural := 1;
1301 
        c9_high                    : natural := 1;
1302 
        l0_high                    : natural := 1;
1303 
        l1_high                    : natural := 1;
1304 
        g0_high                    : natural := 1;
1305 
        g1_high                    : natural := 1;
1306 
        g2_high                    : natural := 1;
1307 
        g3_high                    : natural := 1;
1308 
        e0_high                    : natural := 1;
1309 
        e1_high                    : natural := 1;
1310 
        e2_high                    : natural := 1;
1311 
        e3_high                    : natural := 1;
1312 
        c0_low                     : natural := 1;
1313 
        c1_low                     : natural := 1;
1314 
        c2_low                     : natural := 1;
1315 
        c3_low                     : natural := 1;
1316 
        c4_low                     : natural := 1;
1317 
        c5_low                     : natural := 1;
1318 
        c6_low                     : natural := 1;
1319 
        c7_low                     : natural := 1;
1320 
        c8_low                     : natural := 1;
1321 
        c9_low                     : natural := 1;
1322 
        l0_low                     : natural := 1;
1323 
        l1_low                     : natural := 1;
1324 
        g0_low                     : natural := 1;
1325 
        g1_low                     : natural := 1;
1326 
        g2_low                     : natural := 1;
1327 
        g3_low                     : natural := 1;
1328 
        e0_low                     : natural := 1;
1329 
        e1_low                     : natural := 1;
1330 
        e2_low                     : natural := 1;
1331 
        e3_low                     : natural := 1;
1332 
        c0_initial                 : natural := 1;
1333 
        c1_initial                 : natural := 1;
1334 
        c2_initial                 : natural := 1;
1335 
        c3_initial                 : natural := 1;
1336 
        c4_initial                 : natural := 1;
1337 
        c5_initial                 : natural := 1;
1338 
        c6_initial                 : natural := 1;
1339 
        c7_initial                 : natural := 1;
1340 
        c8_initial                 : natural := 1;
1341 
        c9_initial                 : natural := 1;
1342 
        l0_initial                 : natural := 1;
1343 
        l1_initial                 : natural := 1;
1344 
        g0_initial                 : natural := 1;
1345 
        g1_initial                 : natural := 1;
1346 
        g2_initial                 : natural := 1;
1347 
        g3_initial                 : natural := 1;
1348 
        e0_initial                 : natural := 1;
1349 
        e1_initial                 : natural := 1;
1350 
        e2_initial                 : natural := 1;
1351 
        e3_initial                 : natural := 1;
1352 
        c0_mode                    : string := "bypass" ;
1353 
        c1_mode                    : string := "bypass" ;
1354 
        c2_mode                    : string := "bypass" ;
1355 
        c3_mode                    : string := "bypass" ;
1356 
        c4_mode                    : string := "bypass" ;
1357 
        c5_mode                    : string := "bypass" ;
1358 
        c6_mode                    : string := "bypass" ;
1359 
        c7_mode                    : string := "bypass" ;
1360 
        c8_mode                    : string := "bypass" ;
1361 
        c9_mode                    : string := "bypass" ;
1362 
        l0_mode                    : string := "bypass" ;
1363 
        l1_mode                    : string := "bypass" ;
1364 
        g0_mode                    : string := "bypass" ;
1365 
        g1_mode                    : string := "bypass" ;
1366 
        g2_mode                    : string := "bypass" ;
1367 
        g3_mode                    : string := "bypass" ;
1368 
        e0_mode                    : string := "bypass" ;
1369 
        e1_mode                    : string := "bypass" ;
1370 
        e2_mode                    : string := "bypass" ;
1371 
        e3_mode                    : string := "bypass" ;
1372 
        c0_ph                      : natural := 0;
1373 
        c1_ph                      : natural := 0;
1374 
        c2_ph                      : natural := 0;
1375 
        c3_ph                      : natural := 0;
1376 
        c4_ph                      : natural := 0;
1377 
        c5_ph                      : natural := 0;
1378 
        c6_ph                      : natural := 0;
1379 
        c7_ph                      : natural := 0;
1380 
        c8_ph                      : natural := 0;
1381 
        c9_ph                      : natural := 0;
1382 
        l0_ph                      : natural := 0;
1383 
        l1_ph                      : natural := 0;
1384 
        g0_ph                      : natural := 0;
1385 
        g1_ph                      : natural := 0;
1386 
        g2_ph                      : natural := 0;
1387 
        g3_ph                      : natural := 0;
1388 
        e0_ph                      : natural := 0;
1389 
        e1_ph                      : natural := 0;
1390 
        e2_ph                      : natural := 0;
1391 
        e3_ph                      : natural := 0;
1392 
        m_ph                       : natural := 0;
1393 
        l0_time_delay              : natural := 0;
1394 
        l1_time_delay              : natural := 0;
1395 
        g0_time_delay              : natural := 0;
1396 
        g1_time_delay              : natural := 0;
1397 
        g2_time_delay              : natural := 0;
1398 
        g3_time_delay              : natural := 0;
1399 
        e0_time_delay              : natural := 0;
1400 
        e1_time_delay              : natural := 0;
1401 
        e2_time_delay              : natural := 0;
1402 
        e3_time_delay              : natural := 0;
1403 
        m_time_delay               : natural := 0;
1404 
        n_time_delay               : natural := 0;
1405 
        c1_use_casc_in             : string := "off";
1406 
        c2_use_casc_in             : string := "off";
1407 
        c3_use_casc_in             : string := "off";
1408 
        c4_use_casc_in             : string := "off";
1409 
        c5_use_casc_in             : string := "off";
1410 
        c6_use_casc_in             : string := "off";
1411 
        c7_use_casc_in             : string := "off";
1412 
        c8_use_casc_in             : string := "off";
1413 
        c9_use_casc_in             : string := "off";
1414 
        m_test_source              : integer := 5;
1415 
        c0_test_source             : integer := 5;
1416 
        c1_test_source             : integer := 5;
1417 
        c2_test_source             : integer := 5;
1418 
        c3_test_source             : integer := 5;
1419 
        c4_test_source             : integer := 5;
1420 
        c5_test_source             : integer := 5;
1421 
        c6_test_source             : integer := 5;
1422 
        c7_test_source             : integer := 5;
1423 
        c8_test_source             : integer := 5;
1424 
        c9_test_source             : integer := 5;
1425 
        extclk3_counter            : string := "e3" ;
1426 
        extclk2_counter            : string := "e2" ;
1427 
        extclk1_counter            : string := "e1" ;
1428 
        extclk0_counter            : string := "e0" ;
1429 
        clk9_counter               : string := "c9" ;
1430 
        clk8_counter               : string := "c8" ;
1431 
        clk7_counter               : string := "c7" ;
1432 
        clk6_counter               : string := "c6" ;
1433 
        clk5_counter               : string := "l1" ;
1434 
        clk4_counter               : string := "l0" ;
1435 
        clk3_counter               : string := "g3" ;
1436 
        clk2_counter               : string := "g2" ;
1437 
        clk1_counter               : string := "g1" ;
1438 
        clk0_counter               : string := "g0" ;
1439 
        enable0_counter            : string := "l0";
1440 
        enable1_counter            : string := "l0";
1441 
        charge_pump_current        : natural := 2;
1442 
        loop_filter_r              : string := " 1.000000";
1443 
        loop_filter_c              : natural := 5;
1444 
        vco_post_scale             : natural := 0;
1445 
        vco_frequency_control      : string := "AUTO";
1446 
        vco_phase_shift_step       : natural := 0;
1447 
        lpm_hint                   : string := "UNUSED";
1448 
        lpm_type                   : string := "altpll";
1449 
        port_clkena0 : string := "PORT_CONNECTIVITY";
1450 
        port_clkena1 : string := "PORT_CONNECTIVITY";
1451 
        port_clkena2 : string := "PORT_CONNECTIVITY";
1452 
        port_clkena3 : string := "PORT_CONNECTIVITY";
1453 
        port_clkena4 : string := "PORT_CONNECTIVITY";
1454 
        port_clkena5 : string := "PORT_CONNECTIVITY";
1455 
        port_clkena6 : string := "PORT_CONNECTIVITY";
1456 
        port_clkena7 : string := "PORT_CONNECTIVITY";
1457 
        port_clkena8 : string := "PORT_CONNECTIVITY";
1458 
        port_clkena9 : string := "PORT_CONNECTIVITY";
1459 
        port_extclkena0 : string := "PORT_CONNECTIVITY";
1460 
        port_extclkena1 : string := "PORT_CONNECTIVITY";
1461 
        port_extclkena2 : string := "PORT_CONNECTIVITY";
1462 
        port_extclkena3 : string := "PORT_CONNECTIVITY";
1463 
        port_extclk0 : string := "PORT_CONNECTIVITY";
1464 
        port_extclk1 : string := "PORT_CONNECTIVITY";
1465 
        port_extclk2 : string := "PORT_CONNECTIVITY";
1466 
        port_extclk3 : string := "PORT_CONNECTIVITY";
1467 
        port_clkbad0 : string := "PORT_CONNECTIVITY";
1468 
        port_clkbad1 : string := "PORT_CONNECTIVITY";
1469 
        port_clk0 : string := "PORT_CONNECTIVITY";
1470 
        port_clk1 : string := "PORT_CONNECTIVITY";
1471 
        port_clk2 : string := "PORT_CONNECTIVITY";
1472 
        port_clk3 : string := "PORT_CONNECTIVITY";
1473 
        port_clk4 : string := "PORT_CONNECTIVITY";
1474 
        port_clk5 : string := "PORT_CONNECTIVITY";
1475 
        port_clk6 : string := "PORT_CONNECTIVITY";
1476 
        port_clk7 : string := "PORT_CONNECTIVITY";
1477 
        port_clk8 : string := "PORT_CONNECTIVITY";
1478 
        port_clk9 : string := "PORT_CONNECTIVITY";
1479 
        port_scandata : string := "PORT_CONNECTIVITY";
1480 
        port_scandataout : string := "PORT_CONNECTIVITY";
1481 
        port_scandone : string := "PORT_CONNECTIVITY";
1482 
        port_sclkout1 : string := "PORT_CONNECTIVITY";
1483 
        port_sclkout0 : string := "PORT_CONNECTIVITY";
1484 
        port_activeclock : string := "PORT_CONNECTIVITY";
1485 
        port_clkloss : string := "PORT_CONNECTIVITY";
1486 
        port_inclk1 : string := "PORT_CONNECTIVITY";
1487 
        port_inclk0 : string := "PORT_CONNECTIVITY";
1488 
        port_fbin : string := "PORT_CONNECTIVITY";
1489 
        port_fbout : string := "PORT_CONNECTIVITY";
1490 
        port_pllena : string := "PORT_CONNECTIVITY";
1491 
        port_clkswitch : string := "PORT_CONNECTIVITY";
1492 
        port_areset : string := "PORT_CONNECTIVITY";
1493 
        port_pfdena : string := "PORT_CONNECTIVITY";
1494 
        port_scanclk : string := "PORT_CONNECTIVITY";
1495 
        port_scanaclr : string := "PORT_CONNECTIVITY";
1496 
        port_scanread : string := "PORT_CONNECTIVITY";
1497 
        port_scanwrite : string := "PORT_CONNECTIVITY";
1498 
        port_enable0 : string := "PORT_CONNECTIVITY";
1499 
        port_enable1 : string := "PORT_CONNECTIVITY";
1500 
        port_locked : string := "PORT_CONNECTIVITY";
1501 
        port_configupdate : string := "PORT_CONNECTIVITY";
1502 
        port_phasecounterselect : string := "PORT_CONNECTIVITY";
1503 
        port_phasedone : string := "PORT_CONNECTIVITY";
1504 
        port_phasestep : string := "PORT_CONNECTIVITY";
1505 
        port_phaseupdown : string := "PORT_CONNECTIVITY";
1506 
        port_vcooverrange : string := "PORT_CONNECTIVITY";
1507 
        port_vcounderrange : string := "PORT_CONNECTIVITY";
1508 
        port_scanclkena : string := "PORT_CONNECTIVITY";
1509 
        using_fbmimicbidir_port : string := "ON";
1510 
        sim_gate_lock_device_behavior : string := "OFF" );
1511 
    port (
1512 
        inclk       : in std_logic_vector(1 downto 0) := (others => '0');
1513 
        fbin        : in std_logic := '1';
1514 
        pllena      : in std_logic := '1';
1515 
        clkswitch   : in std_logic := '0';
1516 
        areset      : in std_logic := '0';
1517 
        pfdena      : in std_logic := '1';
1518 
        clkena      : in std_logic_vector(5 downto 0) := (others => '1');
1519 
        extclkena   : in std_logic_vector(3 downto 0) := (others => '1');
1520 
        scanclk     : in std_logic := '0';
1521 
        scanclkena  : in std_logic := '1';
1522 
        scanaclr    : in std_logic := '0';
1523 
        scanread    : in std_logic := '0';
1524 
        scanwrite   : in std_logic := '0';
1525 
        scandata    : in std_logic := '0';
1526 
        phasecounterselect : in std_logic_vector(width_phasecounterselect-1 downto 0) := (others => '1');
1527 
        phaseupdown  : in std_logic := '1';
1528 
        phasestep    : in std_logic := '1';
1529 
        configupdate : in std_logic := '0';
1530 
        fbmimicbidir : inout std_logic := '1';
1531 
        clk         : out std_logic_vector(width_clock-1 downto 0);
1532 
        extclk      : out std_logic_vector(3 downto 0);
1533 
        clkbad      : out std_logic_vector(1 downto 0);
1534 
        enable0     : out std_logic;
1535 
        enable1     : out std_logic;
1536 
        activeclock : out std_logic;
1537 
        clkloss     : out std_logic;
1538 
        locked      : out std_logic;
1539 
        scandataout : out std_logic;
1540 
        scandone    : out std_logic;
1541 
        sclkout0    : out std_logic;
1542 
        sclkout1    : out std_logic;
1543 
        phasedone     : out std_logic;
1544 
        vcooverrange  : out std_logic;
1545 
        vcounderrange : out std_logic;
1546 
        fbout         : out std_logic );
1547 
end component;
1548 
 
1549 
component altfp_mult
1550 
    generic (
1551 
        width_exp               : integer := 11;
1552 
        width_man               : integer := 31;
1553 
        dedicated_multiplier_circuitry  : string := "AUTO";
1554 
        reduced_functionality           : string := "NO";
1555 
        pipeline                        : natural := 5;
1556 
        denormal_support                : string := "YES";
1557 
        exception_handling              : string := "YES";
1558 
        lpm_hint                        : string := "UNUSED";
1559 
        lpm_type                        : string := "altfp_mult" );
1560 
    port (
1561 
        clock       : in std_logic;
1562 
        clk_en      : in std_logic := '1';
1563 
        aclr        : in std_logic := '0';
1564 
        dataa       : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
1565 
        datab       : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
1566 
        result      : out std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
1567 
        overflow    : out std_logic ;
1568 
        underflow   : out std_logic ;
1569 
        zero        : out std_logic ;
1570 
        denormal    : out std_logic ;
1571 
        indefinite  : out std_logic ;
1572 
        nan         : out std_logic );
1573 
end component;
1574 
 
1575 
component altsqrt
1576 
    generic (
1577 
        q_port_width  : integer := 1;
1578 
        r_port_width  : integer := 1;
1579 
        width       : integer := 1;
1580 
        pipeline    : integer := 0;
1581 
        lpm_hint    : string := "UNUSED";
1582 
        lpm_type    : string := "altsqrt" );
1583 
    port (
1584 
        radical     : in std_logic_vector(width - 1 downto 0) ;
1585 
        clk         : in std_logic := '1';
1586 
        ena         : in std_logic := '1';
1587 
        aclr        : in std_logic := '0';
1588 
        q           : out std_logic_vector( q_port_width - 1 downto 0) ;
1589 
        remainder   : out std_logic_vector( r_port_width - 1 downto 0) );
1590 
end component;
1591 
 
1592 
component parallel_add
1593 
    generic (
1594 
        width             : natural := 4;
1595 
        size              : natural := 2;
1596 
        widthr            : natural := 4;
1597 
        shift             : natural := 0;
1598 
        msw_subtract      : string  := "NO";
1599 
        representation    : string  := "UNSIGNED";
1600 
        pipeline          : natural := 0;
1601 
        result_alignment  : string  := "LSB";
1602 
        lpm_hint          : string  := "UNUSED";
1603 
        lpm_type          : string  := "parallel_add" );
1604 
    port (
1605 
        data   : in altera_mf_logic_2D(size - 1 downto 0, width - 1 downto 0);
1606 
        clock  : in std_logic := '1';
1607 
        aclr   : in std_logic := '0';
1608 
        clken  : in std_logic := '1';
1609 
        result : out std_logic_vector(widthr - 1 downto 0) );
1610 
end component;
1611 
 
1612 
component a_graycounter
1613 
    generic (
1614 
        width     : natural;
1615 
        pvalue    : natural;
1616 
        lpm_hint  : string := "UNUSED";
1617 
        lpm_type  : string := "a_graycounter" );
1618 
    port (
1619 
        clock   : in std_logic;
1620 
        clk_en  : in std_logic := '1';
1621 
        cnt_en  : in std_logic := '1';
1622 
        updown  : in std_logic := '1';
1623 
        aclr    : in std_logic := '0';
1624 
        sclr    : in std_logic := '0';
1625 
        qbin    : out std_logic_vector(width-1 downto 0);
1626 
        q       : out std_logic_vector(width-1 downto 0) );
1627 
end component;
1628 
 
1629 
component altsquare
1630 
    generic (
1631 
        data_width     :    natural;
1632 
        pipeline       :    natural;
1633 
        representation :    string := "UNSIGNED";
1634 
        result_width   :    natural;
1635 
        lpm_hint       :    string := "UNUSED";
1636 
        lpm_type       :    string := "altsquare"
1637 
    );
1638 
    port(
1639 
        aclr    :   in std_logic := '0';
1640 
        clock   :   in std_logic := '1';
1641 
        data    :   in std_logic_vector(data_width-1 downto 0);
1642 
        ena     :   in std_logic := '1';
1643 
        result  :   out std_logic_vector(result_width-1 downto 0)
1644 
    );
1645 
end component;
1646 
 
1647 
component sld_virtual_jtag
1648 
    generic (
1649 
        lpm_type                : string;
1650 
        lpm_hint                : string;
1651 
        sld_auto_instance_index : string;
1652 
        sld_instance_index      : integer;
1653 
        sld_ir_width            : integer;
1654 
        sld_sim_n_scan          : integer;
1655 
        sld_sim_total_length    : integer;
1656 
        sld_sim_action          : string);
1657 
    port (
1658 
        tdo   : in  std_logic := '0';
1659 
        ir_out : in  std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
1660 
        tck                : out std_logic;
1661 
        tdi                : out std_logic;
1662 
        ir_in              : out std_logic_vector(sld_ir_width - 1 downto 0);
1663 
        virtual_state_cdr  : out std_logic;
1664 
        virtual_state_sdr  : out std_logic;
1665 
        virtual_state_e1dr : out std_logic;
1666 
        virtual_state_pdr  : out std_logic;
1667 
        virtual_state_e2dr : out std_logic;
1668 
        virtual_state_udr  : out std_logic;
1669 
        virtual_state_cir  : out std_logic;
1670 
        virtual_state_uir  : out std_logic;
1671 
        jtag_state_tlr     : out std_logic;
1672 
        jtag_state_rti     : out std_logic;
1673 
        jtag_state_sdrs    : out std_logic;
1674 
        jtag_state_cdr     : out std_logic;
1675 
        jtag_state_sdr     : out std_logic;
1676 
        jtag_state_e1dr    : out std_logic;
1677 
        jtag_state_pdr     : out std_logic;
1678 
        jtag_state_e2dr    : out std_logic;
1679 
        jtag_state_udr     : out std_logic;
1680 
        jtag_state_sirs    : out std_logic;
1681 
        jtag_state_cir     : out std_logic;
1682 
        jtag_state_sir     : out std_logic;
1683 
        jtag_state_e1ir    : out std_logic;
1684 
        jtag_state_pir     : out std_logic;
1685 
        jtag_state_e2ir    : out std_logic;
1686 
        jtag_state_uir     : out std_logic;
1687 
        tms                : out std_logic);
1688 
end component;
1689 
 
1690 
component sld_virtual_jtag_basic
1691 
    generic (
1692 
        lpm_type                : string;
1693 
        lpm_hint                : string;
1694 
        sld_mfg_id              : natural range 0 to 2047;
1695 
        sld_type_id             : natural range 0 to 255;
1696 
        sld_version             : natural range 0 to 31;
1697 
        sld_auto_instance_index : string;
1698 
        sld_instance_index      : integer;
1699 
        sld_ir_width            : integer;
1700 
        sld_sim_n_scan          : integer;
1701 
        sld_sim_total_length    : integer;
1702 
        sld_sim_action          : string);
1703 
    port (
1704 
        tdo                : in  std_logic                                   := '0';
1705 
        ir_out             : in  std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
1706 
        tck                : out std_logic;
1707 
        tdi                : out std_logic;
1708 
        ir_in              : out std_logic_vector(sld_ir_width - 1 downto 0);
1709 
        virtual_state_cdr  : out std_logic;
1710 
        virtual_state_sdr  : out std_logic;
1711 
        virtual_state_e1dr : out std_logic;
1712 
        virtual_state_pdr  : out std_logic;
1713 
        virtual_state_e2dr : out std_logic;
1714 
        virtual_state_udr  : out std_logic;
1715 
        virtual_state_cir  : out std_logic;
1716 
        virtual_state_uir  : out std_logic;
1717 
        jtag_state_tlr     : out std_logic;
1718 
        jtag_state_rti     : out std_logic;
1719 
        jtag_state_sdrs    : out std_logic;
1720 
        jtag_state_cdr     : out std_logic;
1721 
        jtag_state_sdr     : out std_logic;
1722 
        jtag_state_e1dr    : out std_logic;
1723 
        jtag_state_pdr     : out std_logic;
1724 
        jtag_state_e2dr    : out std_logic;
1725 
        jtag_state_udr     : out std_logic;
1726 
        jtag_state_sirs    : out std_logic;
1727 
        jtag_state_cir     : out std_logic;
1728 
        jtag_state_sir     : out std_logic;
1729 
        jtag_state_e1ir    : out std_logic;
1730 
        jtag_state_pir     : out std_logic;
1731 
        jtag_state_e2ir    : out std_logic;
1732 
        jtag_state_uir     : out std_logic;
1733 
        tms                : out std_logic);
1734 
end component;
1735 
 
1736 
 
1737 
 
1738 
 
1739 
 
1740 
 
1741 
 
1742 
    constant    ELA_STATUS_BITS    :    natural    :=    4;
1743 
    constant    MAX_NUMBER_OF_BITS_FOR_TRIGGERS    :    natural    :=    4;
1744 
    constant    SLD_IR_BITS    :    natural    :=    ELA_STATUS_BITS + MAX_NUMBER_OF_BITS_FOR_TRIGGERS;
1745 
 
1746 
component    sld_signaltap
1747 
    generic    (
1748 
        SLD_ADVANCED_TRIGGER_5    :    string    :=    "NONE";
1749 
        SLD_NODE_CRC_LOWORD    :    natural    :=    50132;
1750 
        SLD_INVERSION_MASK    :    std_logic_vector    :=    "0";
1751 
        SLD_TRIGGER_BITS    :    natural    :=    8;
1752 
        SLD_POWER_UP_TRIGGER    :    natural    :=    0;
1753 
        SLD_ADVANCED_TRIGGER_6    :    string    :=    "NONE";
1754 
        SLD_ADVANCED_TRIGGER_10    :    string    :=    "NONE";
1755 
        SLD_ADVANCED_TRIGGER_9    :    string    :=    "NONE";
1756 
        SLD_ADVANCED_TRIGGER_7    :    string    :=    "NONE";
1757 
        SLD_INCREMENTAL_ROUTING    :    natural    :=    0;
1758 
        SLD_MEM_ADDRESS_BITS    :    natural    :=    7;
1759 
        SLD_ADVANCED_TRIGGER_ENTITY    :    string    :=    "basic";
1760 
        SLD_TRIGGER_IN_ENABLED    :    natural    :=    1;
1761 
        SLD_ADVANCED_TRIGGER_4    :    string    :=    "NONE";
1762 
        SLD_ADVANCED_TRIGGER_8    :    string    :=    "NONE";
1763 
        SLD_TRIGGER_LEVEL    :    natural    :=    1;
1764 
        SLD_ADVANCED_TRIGGER_2    :    string    :=    "NONE";
1765 
        SLD_RAM_BLOCK_TYPE    :    string    :=    "AUTO";
1766 
        SLD_ADVANCED_TRIGGER_1    :    string    :=    "NONE";
1767 
        SLD_DATA_BIT_CNTR_BITS    :    natural    :=    4;
1768 
        SLD_INVERSION_MASK_LENGTH    :    integer    :=    1;
1769 
        SLD_SAMPLE_DEPTH    :    natural    :=    128;
1770 
        SLD_NODE_CRC_BITS    :    natural    :=    32;
1771 
        lpm_type    :    string    :=    "sld_signaltap";
1772 
        SLD_DATA_BITS    :    natural    :=    8;
1773 
        SLD_ENABLE_ADVANCED_TRIGGER    :    natural    :=    0;
1774 
        SLD_NODE_INFO    :    natural    :=    0;
1775 
        SLD_ADVANCED_TRIGGER_3    :    string    :=    "NONE";
1776 
        SLD_TRIGGER_LEVEL_PIPELINE    :    natural    :=    1;
1777 
        SLD_NODE_CRC_HIWORD    :    natural    :=    41394
1778 
    );
1779 
    port    (
1780 
        jtag_state_sdr    :    in    std_logic    :=    '0';
1781 
        ir_out    :    out    std_logic_vector(SLD_IR_BITS-1 downto 0);
1782 
        jtag_state_cdr    :    in    std_logic    :=    '0';
1783 
        ir_in    :    in    std_logic_vector(SLD_IR_BITS-1 downto 0)   :=   (others => '0');
1784 
        tdi    :    in    std_logic    :=    '0';
1785 
        acq_trigger_out    :    out    std_logic_vector(SLD_TRIGGER_BITS-1 downto 0);
1786 
        jtag_state_uir    :    in    std_logic    :=    '0';
1787 
        acq_trigger_in    :    in    std_logic_vector(SLD_TRIGGER_BITS-1 downto 0)   :=   (others => '0');
1788 
        trigger_out    :    out    std_logic;
1789 
        acq_data_out    :    out    std_logic_vector(SLD_DATA_BITS-1 downto 0);
1790 
        acq_data_in    :    in    std_logic_vector(SLD_DATA_BITS-1 downto 0)   :=   (others => '0');
1791 
        jtag_state_udr    :    in    std_logic    :=    '0';
1792 
        tdo    :    out    std_logic;
1793 
        clrn    :    in    std_logic    :=    '0';
1794 
        crc    :    in    std_logic_vector(SLD_NODE_CRC_BITS-1 downto 0)   :=   (others => '0');
1795 
        jtag_state_e1dr    :    in    std_logic    :=    '0';
1796 
        raw_tck    :    in    std_logic    :=    '0';
1797 
        usr1    :    in    std_logic    :=    '0';
1798 
        acq_clk    :    in    std_logic;
1799 
        shift    :    in    std_logic    :=    '0';
1800 
        ena    :    in    std_logic    :=    '0';
1801 
        trigger_in    :    in    std_logic    :=    '0';
1802 
        update    :    in    std_logic    :=    '0';
1803 
        rti    :    in    std_logic    :=    '0'
1804 
    );
1805 
end component; --sld_signaltap
1806 
 
1807 
 
1808 
component    altstratixii_oct
1809 
    generic    (
1810 
        lpm_type    :    string    :=    "altstratixii_oct"
1811 
    );
1812 
    port    (
1813 
        terminationenable    :    in    std_logic;
1814 
        terminationclock    :    in    std_logic;
1815 
        rdn    :    in    std_logic;
1816 
        rup    :    in    std_logic
1817 
    );
1818 
end component; --altstratixii_oct
1819 
 
1820 
    constant    TOP_PFL_IR_BITS    :    natural    :=    5;
1821 
 
1822 
component    altparallel_flash_loader
1823 
    generic    (
1824 
        flash_data_width    :    natural    :=    16;
1825 
        safe_mode_revert    :    natural    :=    0;
1826 
        dclk_divisor    :    natural    :=    1;
1827 
        safe_mode_retry    :    natural    :=    1;
1828 
        features_cfg    :    natural    :=    1;
1829 
        burst_mode_intel    :    natural    :=    0;
1830 
        burst_mode    :    natural    :=    0;
1831 
        clk_divisor    :    natural    :=    1;
1832 
        addr_width    :    natural    :=    20;
1833 
        option_bits_start_address    :    natural    :=    0;
1834 
        safe_mode_revert_addr    :    natural    :=    0;
1835 
        lpm_type    :    string    :=    "ALTPARALLEL_FLASH_LOADER";
1836 
        features_pgm    :    natural    :=    1;
1837 
        burst_mode_spansion    :    natural    :=    0;
1838 
        auto_restart    :    STRING    :=    "OFF";
1839 
        conf_data_width    :    natural    :=    1;
1840 
        TRISTATE_CHECKBOX    :    natural    :=    0;
1841 
        safe_mode_halt    :    natural    :=    0
1842 
    );
1843 
    port    (
1844 
        fpga_data    :    out    std_logic_vector(conf_data_width-1 downto 0);
1845 
        fpga_dclk    :    out    std_logic;
1846 
        flash_nce    :    out    std_logic;
1847 
        fpga_nstatus    :    in    std_logic    :=    '0';
1848 
        pfl_clk    :    in    std_logic    :=    '0';
1849 
        fpga_nconfig    :    out    std_logic;
1850 
        flash_noe    :    out    std_logic;
1851 
        flash_nwe    :    out    std_logic;
1852 
        fpga_conf_done    :    in    std_logic    :=    '0';
1853 
        pfl_flash_access_granted    :    in    std_logic    :=    '0';
1854 
        pfl_nreconfigure    :    in    std_logic    :=    '1';
1855 
        flash_nreset    :    out    std_logic;
1856 
        pfl_nreset    :    in    std_logic    :=    '0';
1857 
        flash_data    :    inout    std_logic_vector(flash_data_width-1 downto 0);
1858 
        flash_nadv    :    out    std_logic;
1859 
        flash_clk    :    out    std_logic;
1860 
        flash_addr    :    out    std_logic_vector(addr_width-1 downto 0);
1861 
        pfl_flash_access_request    :    out    std_logic;
1862 
        fpga_pgm    :    in    std_logic_vector(2 downto 0)   :=   (others => '0')
1863 
    );
1864 
end component; --altparallel_flash_loader
1865 
 
1866 
 
1867 
component    altserial_flash_loader
1868 
    generic    (
1869 
        enable_shared_access    :    STRING    :=    "OFF";
1870 
        lpm_type    :    STRING    :=    "ALTSERIAL_FLASH_LOADER"
1871 
    );
1872 
    port    (
1873 
        noe    :    in    std_logic    :=    '0';
1874 
        asmi_access_granted    :    in    std_logic    :=    '1';
1875 
        sdoin    :    in    std_logic    :=    '0';
1876 
        asmi_access_request    :    out    std_logic;
1877 
        data0out    :    out    std_logic;
1878 
        scein    :    in    std_logic    :=    '0';
1879 
        dclkin    :    in    std_logic    :=    '0'
1880 
    );
1881 
end component; --altserial_flash_loader
1882 
 
1883 
-- pragma translate_on
1884 
 
1885 
component alt_dummy
1886 
port (
1887 
        inclk       : in std_logic_vector(1 downto 0);
1888 
        sclkout1     : out std_logic
1889 
     );
1890 
end component;
1891 
 
1892 
end altera_mf_components;

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