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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [axcelerator/] [components/] [axcelerator_components_full.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
--------------------------------------------------------------------
2 
--       Actel Axcelerator VITAL Library
3 
--       NAME: axcelerator.vhd
4 
--       DATE: Friday, February 11, 2005
5 
---------------------------------------------------------------------/
6 
 
7 
library IEEE;
8 
use IEEE.std_logic_1164.all;
9 
--pragma translate_off
10 
use IEEE.VITAL_Timing.all;
11 
--pragma translate_on
12 
 
13 
package COMPONENTS is
14 
 
15 
--pragma translate_off
16 
constant DefaultTimingChecksOn : Boolean := True;
17 
constant DefaultXGenerationOn : Boolean := False;
18 
constant DefaultXon : Boolean := False;
19 
constant DefaultMsgOn : Boolean := True;
20 
--pragma translate_on
21 
 
22 
 
23 
 
24 
------ Component ADD1 ------
25 
 component ADD1
26 
--pragma translate_off
27 
    generic(
28 
                TimingChecksOn:Boolean := True;
29 
                Xon: Boolean := False;
30 
                InstancePath: STRING :="*";
31 
                MsgOn: Boolean := True;
32 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
33 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
34 
                tpd_FCI_S               : VitalDelayType01 := (0.100 ns, 0.100 ns);
35 
                tpd_A_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
36 
                tpd_B_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
37 
                tpd_FCI_FCO             : VitalDelayType01 := (0.100 ns, 0.100 ns);
38 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
39 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
40 
                tipd_FCI                : VitalDelayType01 := (0.000 ns, 0.000 ns));
41 
 
42 
 
43 
--pragma translate_on
44 
    port(
45 
                A               : in    STD_ULOGIC;
46 
                B               : in    STD_ULOGIC;
47 
                FCI             : in    STD_ULOGIC;
48 
                S               : out    STD_ULOGIC;
49 
                FCO             : out    STD_ULOGIC);
50 
 end component;
51 
 
52 
 
53 
------ Component AND2 ------
54 
 component AND2
55 
--pragma translate_off
56 
    generic(
57 
                TimingChecksOn:Boolean := True;
58 
                Xon: Boolean := False;
59 
                InstancePath: STRING :="*";
60 
                MsgOn: Boolean := True;
61 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
62 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
63 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
64 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
65 
 
66 
 
67 
--pragma translate_on
68 
    port(
69 
                A               : in    STD_ULOGIC;
70 
                B               : in    STD_ULOGIC;
71 
                Y               : out    STD_ULOGIC);
72 
 end component;
73 
 
74 
 
75 
------ Component AND2A ------
76 
 component AND2A
77 
--pragma translate_off
78 
    generic(
79 
                TimingChecksOn:Boolean := True;
80 
                Xon: Boolean := False;
81 
                InstancePath: STRING :="*";
82 
                MsgOn: Boolean := True;
83 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
84 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
85 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
86 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
87 
 
88 
 
89 
--pragma translate_on
90 
    port(
91 
                A               : in    STD_ULOGIC;
92 
                B               : in    STD_ULOGIC;
93 
                Y               : out    STD_ULOGIC);
94 
 end component;
95 
 
96 
 
97 
------ Component AND2B ------
98 
 component AND2B
99 
--pragma translate_off
100 
    generic(
101 
                TimingChecksOn:Boolean := True;
102 
                Xon: Boolean := False;
103 
                InstancePath: STRING :="*";
104 
                MsgOn: Boolean := True;
105 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
106 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
107 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
108 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
109 
 
110 
 
111 
--pragma translate_on
112 
    port(
113 
                A               : in    STD_ULOGIC;
114 
                B               : in    STD_ULOGIC;
115 
                Y               : out    STD_ULOGIC);
116 
 end component;
117 
 
118 
 
119 
------ Component AND3 ------
120 
 component AND3
121 
--pragma translate_off
122 
    generic(
123 
                TimingChecksOn:Boolean := True;
124 
                Xon: Boolean := False;
125 
                InstancePath: STRING :="*";
126 
                MsgOn: Boolean := True;
127 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
128 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
129 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
130 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
131 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
132 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
133 
 
134 
 
135 
--pragma translate_on
136 
    port(
137 
                A               : in    STD_ULOGIC;
138 
                B               : in    STD_ULOGIC;
139 
                C               : in    STD_ULOGIC;
140 
                Y               : out    STD_ULOGIC);
141 
 end component;
142 
 
143 
 
144 
------ Component AND3A ------
145 
 component AND3A
146 
--pragma translate_off
147 
    generic(
148 
                TimingChecksOn:Boolean := True;
149 
                Xon: Boolean := False;
150 
                InstancePath: STRING :="*";
151 
                MsgOn: Boolean := True;
152 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
153 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
154 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
155 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
156 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
157 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
158 
 
159 
 
160 
--pragma translate_on
161 
    port(
162 
                A               : in    STD_ULOGIC;
163 
                B               : in    STD_ULOGIC;
164 
                C               : in    STD_ULOGIC;
165 
                Y               : out    STD_ULOGIC);
166 
 end component;
167 
 
168 
 
169 
------ Component AND3B ------
170 
 component AND3B
171 
--pragma translate_off
172 
    generic(
173 
                TimingChecksOn:Boolean := True;
174 
                Xon: Boolean := False;
175 
                InstancePath: STRING :="*";
176 
                MsgOn: Boolean := True;
177 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
178 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
179 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
180 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
181 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
182 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
183 
 
184 
 
185 
--pragma translate_on
186 
    port(
187 
                A               : in    STD_ULOGIC;
188 
                B               : in    STD_ULOGIC;
189 
                C               : in    STD_ULOGIC;
190 
                Y               : out    STD_ULOGIC);
191 
 end component;
192 
 
193 
 
194 
------ Component AND3C ------
195 
 component AND3C
196 
--pragma translate_off
197 
    generic(
198 
                TimingChecksOn:Boolean := True;
199 
                Xon: Boolean := False;
200 
                InstancePath: STRING :="*";
201 
                MsgOn: Boolean := True;
202 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
203 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
204 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
205 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
206 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
207 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
208 
 
209 
 
210 
--pragma translate_on
211 
    port(
212 
                A               : in    STD_ULOGIC;
213 
                B               : in    STD_ULOGIC;
214 
                C               : in    STD_ULOGIC;
215 
                Y               : out    STD_ULOGIC);
216 
 end component;
217 
 
218 
 
219 
------ Component AND4 ------
220 
 component AND4
221 
--pragma translate_off
222 
    generic(
223 
                TimingChecksOn:Boolean := True;
224 
                Xon: Boolean := False;
225 
                InstancePath: STRING :="*";
226 
                MsgOn: Boolean := True;
227 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
228 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
229 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
230 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
231 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
232 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
233 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
234 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
235 
 
236 
 
237 
--pragma translate_on
238 
    port(
239 
                A               : in    STD_ULOGIC;
240 
                B               : in    STD_ULOGIC;
241 
                C               : in    STD_ULOGIC;
242 
                D               : in    STD_ULOGIC;
243 
                Y               : out    STD_ULOGIC);
244 
 end component;
245 
 
246 
 
247 
------ Component AND4A ------
248 
 component AND4A
249 
--pragma translate_off
250 
    generic(
251 
                TimingChecksOn:Boolean := True;
252 
                Xon: Boolean := False;
253 
                InstancePath: STRING :="*";
254 
                MsgOn: Boolean := True;
255 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
256 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
257 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
258 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
259 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
260 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
261 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
262 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
263 
 
264 
 
265 
--pragma translate_on
266 
    port(
267 
                A               : in    STD_ULOGIC;
268 
                B               : in    STD_ULOGIC;
269 
                C               : in    STD_ULOGIC;
270 
                D               : in    STD_ULOGIC;
271 
                Y               : out    STD_ULOGIC);
272 
 end component;
273 
 
274 
 
275 
------ Component AND4B ------
276 
 component AND4B
277 
--pragma translate_off
278 
    generic(
279 
                TimingChecksOn:Boolean := True;
280 
                Xon: Boolean := False;
281 
                InstancePath: STRING :="*";
282 
                MsgOn: Boolean := True;
283 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
284 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
285 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
286 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
287 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
288 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
289 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
290 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
291 
 
292 
 
293 
--pragma translate_on
294 
    port(
295 
                A               : in    STD_ULOGIC;
296 
                B               : in    STD_ULOGIC;
297 
                C               : in    STD_ULOGIC;
298 
                D               : in    STD_ULOGIC;
299 
                Y               : out    STD_ULOGIC);
300 
 end component;
301 
 
302 
 
303 
------ Component AND4C ------
304 
 component AND4C
305 
--pragma translate_off
306 
    generic(
307 
                TimingChecksOn:Boolean := True;
308 
                Xon: Boolean := False;
309 
                InstancePath: STRING :="*";
310 
                MsgOn: Boolean := True;
311 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
312 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
313 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
314 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
315 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
316 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
317 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
318 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
319 
 
320 
 
321 
--pragma translate_on
322 
    port(
323 
                A               : in    STD_ULOGIC;
324 
                B               : in    STD_ULOGIC;
325 
                C               : in    STD_ULOGIC;
326 
                D               : in    STD_ULOGIC;
327 
                Y               : out    STD_ULOGIC);
328 
 end component;
329 
 
330 
 
331 
------ Component AND4D ------
332 
 component AND4D
333 
--pragma translate_off
334 
    generic(
335 
                TimingChecksOn:Boolean := True;
336 
                Xon: Boolean := False;
337 
                InstancePath: STRING :="*";
338 
                MsgOn: Boolean := True;
339 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
340 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
341 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
342 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
343 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
344 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
345 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
346 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
347 
 
348 
 
349 
--pragma translate_on
350 
    port(
351 
                A               : in    STD_ULOGIC;
352 
                B               : in    STD_ULOGIC;
353 
                C               : in    STD_ULOGIC;
354 
                D               : in    STD_ULOGIC;
355 
                Y               : out    STD_ULOGIC);
356 
 end component;
357 
 
358 
 
359 
------ Component AND5A ------
360 
 component AND5A
361 
--pragma translate_off
362 
    generic(
363 
                TimingChecksOn:Boolean := True;
364 
                Xon: Boolean := False;
365 
                InstancePath: STRING :="*";
366 
                MsgOn: Boolean := True;
367 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
368 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
369 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
370 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
371 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
372 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
373 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
374 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
375 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
376 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
377 
 
378 
 
379 
--pragma translate_on
380 
    port(
381 
                A               : in    STD_ULOGIC;
382 
                B               : in    STD_ULOGIC;
383 
                C               : in    STD_ULOGIC;
384 
                D               : in    STD_ULOGIC;
385 
                E               : in    STD_ULOGIC;
386 
                Y               : out    STD_ULOGIC);
387 
 end component;
388 
 
389 
 
390 
------ Component AND5B ------
391 
 component AND5B
392 
--pragma translate_off
393 
    generic(
394 
                TimingChecksOn:Boolean := True;
395 
                Xon: Boolean := False;
396 
                InstancePath: STRING :="*";
397 
                MsgOn: Boolean := True;
398 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
399 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
400 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
401 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
402 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
403 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
404 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
405 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
406 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
407 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
408 
 
409 
 
410 
--pragma translate_on
411 
    port(
412 
                A               : in    STD_ULOGIC;
413 
                B               : in    STD_ULOGIC;
414 
                C               : in    STD_ULOGIC;
415 
                D               : in    STD_ULOGIC;
416 
                E               : in    STD_ULOGIC;
417 
                Y               : out    STD_ULOGIC);
418 
 end component;
419 
 
420 
 
421 
------ Component AND5C ------
422 
 component AND5C
423 
--pragma translate_off
424 
    generic(
425 
                TimingChecksOn:Boolean := True;
426 
                Xon: Boolean := False;
427 
                InstancePath: STRING :="*";
428 
                MsgOn: Boolean := True;
429 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
430 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
431 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
432 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
433 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
434 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
435 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
436 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
437 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
438 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
439 
 
440 
 
441 
--pragma translate_on
442 
    port(
443 
                A               : in    STD_ULOGIC;
444 
                B               : in    STD_ULOGIC;
445 
                C               : in    STD_ULOGIC;
446 
                D               : in    STD_ULOGIC;
447 
                E               : in    STD_ULOGIC;
448 
                Y               : out    STD_ULOGIC);
449 
 end component;
450 
 
451 
 
452 
------ Component AO1 ------
453 
 component AO1
454 
--pragma translate_off
455 
    generic(
456 
                TimingChecksOn:Boolean := True;
457 
                Xon: Boolean := False;
458 
                InstancePath: STRING :="*";
459 
                MsgOn: Boolean := True;
460 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
461 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
462 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
463 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
464 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
465 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
466 
 
467 
 
468 
--pragma translate_on
469 
    port(
470 
                A               : in    STD_ULOGIC;
471 
                B               : in    STD_ULOGIC;
472 
                C               : in    STD_ULOGIC;
473 
                Y               : out    STD_ULOGIC);
474 
 end component;
475 
 
476 
 
477 
------ Component AO10 ------
478 
 component AO10
479 
--pragma translate_off
480 
    generic(
481 
                TimingChecksOn:Boolean := True;
482 
                Xon: Boolean := False;
483 
                InstancePath: STRING :="*";
484 
                MsgOn: Boolean := True;
485 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
486 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
487 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
488 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
489 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
490 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
491 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
492 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
493 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
494 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
495 
 
496 
 
497 
--pragma translate_on
498 
    port(
499 
                A               : in    STD_ULOGIC;
500 
                B               : in    STD_ULOGIC;
501 
                C               : in    STD_ULOGIC;
502 
                D               : in    STD_ULOGIC;
503 
                E               : in    STD_ULOGIC;
504 
                Y               : out    STD_ULOGIC);
505 
 end component;
506 
 
507 
 
508 
------ Component AO11 ------
509 
 component AO11
510 
--pragma translate_off
511 
    generic(
512 
                TimingChecksOn:Boolean := True;
513 
                Xon: Boolean := False;
514 
                InstancePath: STRING :="*";
515 
                MsgOn: Boolean := True;
516 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
517 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
518 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
519 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
520 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
521 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
522 
 
523 
 
524 
--pragma translate_on
525 
    port(
526 
                A               : in    STD_ULOGIC;
527 
                B               : in    STD_ULOGIC;
528 
                C               : in    STD_ULOGIC;
529 
                Y               : out    STD_ULOGIC);
530 
 end component;
531 
 
532 
 
533 
------ Component AO12 ------
534 
 component AO12
535 
--pragma translate_off
536 
    generic(
537 
                TimingChecksOn:Boolean := True;
538 
                Xon: Boolean := False;
539 
                InstancePath: STRING :="*";
540 
                MsgOn: Boolean := True;
541 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
542 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
543 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
544 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
545 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
546 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
547 
 
548 
 
549 
--pragma translate_on
550 
    port(
551 
                A               : in    STD_ULOGIC;
552 
                B               : in    STD_ULOGIC;
553 
                C               : in    STD_ULOGIC;
554 
                Y               : out    STD_ULOGIC);
555 
 end component;
556 
 
557 
 
558 
------ Component AO13 ------
559 
 component AO13
560 
--pragma translate_off
561 
    generic(
562 
                TimingChecksOn:Boolean := True;
563 
                Xon: Boolean := False;
564 
                InstancePath: STRING :="*";
565 
                MsgOn: Boolean := True;
566 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
567 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
568 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
569 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
570 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
571 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
572 
 
573 
 
574 
--pragma translate_on
575 
    port(
576 
                A               : in    STD_ULOGIC;
577 
                B               : in    STD_ULOGIC;
578 
                C               : in    STD_ULOGIC;
579 
                Y               : out    STD_ULOGIC);
580 
 end component;
581 
 
582 
 
583 
------ Component AO14 ------
584 
 component AO14
585 
--pragma translate_off
586 
    generic(
587 
                TimingChecksOn:Boolean := True;
588 
                Xon: Boolean := False;
589 
                InstancePath: STRING :="*";
590 
                MsgOn: Boolean := True;
591 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
592 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
593 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
594 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
595 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
596 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
597 
 
598 
 
599 
--pragma translate_on
600 
    port(
601 
                A               : in    STD_ULOGIC;
602 
                B               : in    STD_ULOGIC;
603 
                C               : in    STD_ULOGIC;
604 
                Y               : out    STD_ULOGIC);
605 
 end component;
606 
 
607 
 
608 
------ Component AO15 ------
609 
 component AO15
610 
--pragma translate_off
611 
    generic(
612 
                TimingChecksOn:Boolean := True;
613 
                Xon: Boolean := False;
614 
                InstancePath: STRING :="*";
615 
                MsgOn: Boolean := True;
616 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
617 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
618 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
619 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
620 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
621 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
622 
 
623 
 
624 
--pragma translate_on
625 
    port(
626 
                A               : in    STD_ULOGIC;
627 
                B               : in    STD_ULOGIC;
628 
                C               : in    STD_ULOGIC;
629 
                Y               : out    STD_ULOGIC);
630 
 end component;
631 
 
632 
 
633 
------ Component AO16 ------
634 
 component AO16
635 
--pragma translate_off
636 
    generic(
637 
                TimingChecksOn:Boolean := True;
638 
                Xon: Boolean := False;
639 
                InstancePath: STRING :="*";
640 
                MsgOn: Boolean := True;
641 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
642 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
643 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
644 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
645 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
646 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
647 
 
648 
 
649 
--pragma translate_on
650 
    port(
651 
                A               : in    STD_ULOGIC;
652 
                B               : in    STD_ULOGIC;
653 
                C               : in    STD_ULOGIC;
654 
                Y               : out    STD_ULOGIC);
655 
 end component;
656 
 
657 
 
658 
------ Component AO17 ------
659 
 component AO17
660 
--pragma translate_off
661 
    generic(
662 
                TimingChecksOn:Boolean := True;
663 
                Xon: Boolean := False;
664 
                InstancePath: STRING :="*";
665 
                MsgOn: Boolean := True;
666 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
667 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
668 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
669 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
670 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
671 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
672 
 
673 
 
674 
--pragma translate_on
675 
    port(
676 
                A               : in    STD_ULOGIC;
677 
                B               : in    STD_ULOGIC;
678 
                C               : in    STD_ULOGIC;
679 
                Y               : out    STD_ULOGIC);
680 
 end component;
681 
 
682 
 
683 
------ Component AO18 ------
684 
 component AO18
685 
--pragma translate_off
686 
    generic(
687 
                TimingChecksOn:Boolean := True;
688 
                Xon: Boolean := False;
689 
                InstancePath: STRING :="*";
690 
                MsgOn: Boolean := True;
691 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
692 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
693 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
694 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
695 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
696 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
697 
 
698 
 
699 
--pragma translate_on
700 
    port(
701 
                A               : in    STD_ULOGIC;
702 
                B               : in    STD_ULOGIC;
703 
                C               : in    STD_ULOGIC;
704 
                Y               : out    STD_ULOGIC);
705 
 end component;
706 
 
707 
 
708 
------ Component AO1A ------
709 
 component AO1A
710 
--pragma translate_off
711 
    generic(
712 
                TimingChecksOn:Boolean := True;
713 
                Xon: Boolean := False;
714 
                InstancePath: STRING :="*";
715 
                MsgOn: Boolean := True;
716 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
717 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
718 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
719 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
720 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
721 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
722 
 
723 
 
724 
--pragma translate_on
725 
    port(
726 
                A               : in    STD_ULOGIC;
727 
                B               : in    STD_ULOGIC;
728 
                C               : in    STD_ULOGIC;
729 
                Y               : out    STD_ULOGIC);
730 
 end component;
731 
 
732 
 
733 
------ Component AO1B ------
734 
 component AO1B
735 
--pragma translate_off
736 
    generic(
737 
                TimingChecksOn:Boolean := True;
738 
                Xon: Boolean := False;
739 
                InstancePath: STRING :="*";
740 
                MsgOn: Boolean := True;
741 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
742 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
743 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
744 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
745 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
746 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
747 
 
748 
 
749 
--pragma translate_on
750 
    port(
751 
                A               : in    STD_ULOGIC;
752 
                B               : in    STD_ULOGIC;
753 
                C               : in    STD_ULOGIC;
754 
                Y               : out    STD_ULOGIC);
755 
 end component;
756 
 
757 
 
758 
------ Component AO1C ------
759 
 component AO1C
760 
--pragma translate_off
761 
    generic(
762 
                TimingChecksOn:Boolean := True;
763 
                Xon: Boolean := False;
764 
                InstancePath: STRING :="*";
765 
                MsgOn: Boolean := True;
766 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
767 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
768 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
769 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
770 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
771 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
772 
 
773 
 
774 
--pragma translate_on
775 
    port(
776 
                A               : in    STD_ULOGIC;
777 
                B               : in    STD_ULOGIC;
778 
                C               : in    STD_ULOGIC;
779 
                Y               : out    STD_ULOGIC);
780 
 end component;
781 
 
782 
 
783 
------ Component AO1D ------
784 
 component AO1D
785 
--pragma translate_off
786 
    generic(
787 
                TimingChecksOn:Boolean := True;
788 
                Xon: Boolean := False;
789 
                InstancePath: STRING :="*";
790 
                MsgOn: Boolean := True;
791 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
792 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
793 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
794 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
795 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
796 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
797 
 
798 
 
799 
--pragma translate_on
800 
    port(
801 
                A               : in    STD_ULOGIC;
802 
                B               : in    STD_ULOGIC;
803 
                C               : in    STD_ULOGIC;
804 
                Y               : out    STD_ULOGIC);
805 
 end component;
806 
 
807 
 
808 
------ Component AO1E ------
809 
 component AO1E
810 
--pragma translate_off
811 
    generic(
812 
                TimingChecksOn:Boolean := True;
813 
                Xon: Boolean := False;
814 
                InstancePath: STRING :="*";
815 
                MsgOn: Boolean := True;
816 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
817 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
818 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
819 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
820 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
821 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
822 
 
823 
 
824 
--pragma translate_on
825 
    port(
826 
                A               : in    STD_ULOGIC;
827 
                B               : in    STD_ULOGIC;
828 
                C               : in    STD_ULOGIC;
829 
                Y               : out    STD_ULOGIC);
830 
 end component;
831 
 
832 
 
833 
------ Component AO2 ------
834 
 component AO2
835 
--pragma translate_off
836 
    generic(
837 
                TimingChecksOn:Boolean := True;
838 
                Xon: Boolean := False;
839 
                InstancePath: STRING :="*";
840 
                MsgOn: Boolean := True;
841 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
842 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
843 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
844 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
845 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
846 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
847 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
848 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
849 
 
850 
 
851 
--pragma translate_on
852 
    port(
853 
                A               : in    STD_ULOGIC;
854 
                B               : in    STD_ULOGIC;
855 
                C               : in    STD_ULOGIC;
856 
                D               : in    STD_ULOGIC;
857 
                Y               : out    STD_ULOGIC);
858 
 end component;
859 
 
860 
 
861 
------ Component AO2A ------
862 
 component AO2A
863 
--pragma translate_off
864 
    generic(
865 
                TimingChecksOn:Boolean := True;
866 
                Xon: Boolean := False;
867 
                InstancePath: STRING :="*";
868 
                MsgOn: Boolean := True;
869 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
870 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
871 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
872 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
873 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
874 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
875 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
876 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
877 
 
878 
 
879 
--pragma translate_on
880 
    port(
881 
                A               : in    STD_ULOGIC;
882 
                B               : in    STD_ULOGIC;
883 
                C               : in    STD_ULOGIC;
884 
                D               : in    STD_ULOGIC;
885 
                Y               : out    STD_ULOGIC);
886 
 end component;
887 
 
888 
 
889 
------ Component AO2B ------
890 
 component AO2B
891 
--pragma translate_off
892 
    generic(
893 
                TimingChecksOn:Boolean := True;
894 
                Xon: Boolean := False;
895 
                InstancePath: STRING :="*";
896 
                MsgOn: Boolean := True;
897 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
898 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
899 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
900 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
901 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
902 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
903 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
904 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
905 
 
906 
 
907 
--pragma translate_on
908 
    port(
909 
                A               : in    STD_ULOGIC;
910 
                B               : in    STD_ULOGIC;
911 
                C               : in    STD_ULOGIC;
912 
                D               : in    STD_ULOGIC;
913 
                Y               : out    STD_ULOGIC);
914 
 end component;
915 
 
916 
 
917 
------ Component AO2C ------
918 
 component AO2C
919 
--pragma translate_off
920 
    generic(
921 
                TimingChecksOn:Boolean := True;
922 
                Xon: Boolean := False;
923 
                InstancePath: STRING :="*";
924 
                MsgOn: Boolean := True;
925 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
926 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
927 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
928 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
929 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
930 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
931 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
932 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
933 
 
934 
 
935 
--pragma translate_on
936 
    port(
937 
                A               : in    STD_ULOGIC;
938 
                B               : in    STD_ULOGIC;
939 
                C               : in    STD_ULOGIC;
940 
                D               : in    STD_ULOGIC;
941 
                Y               : out    STD_ULOGIC);
942 
 end component;
943 
 
944 
 
945 
------ Component AO2D ------
946 
 component AO2D
947 
--pragma translate_off
948 
    generic(
949 
                TimingChecksOn:Boolean := True;
950 
                Xon: Boolean := False;
951 
                InstancePath: STRING :="*";
952 
                MsgOn: Boolean := True;
953 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
954 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
955 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
956 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
957 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
958 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
959 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
960 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
961 
 
962 
 
963 
--pragma translate_on
964 
    port(
965 
                A               : in    STD_ULOGIC;
966 
                B               : in    STD_ULOGIC;
967 
                C               : in    STD_ULOGIC;
968 
                D               : in    STD_ULOGIC;
969 
                Y               : out    STD_ULOGIC);
970 
 end component;
971 
 
972 
 
973 
------ Component AO2E ------
974 
 component AO2E
975 
--pragma translate_off
976 
    generic(
977 
                TimingChecksOn:Boolean := True;
978 
                Xon: Boolean := False;
979 
                InstancePath: STRING :="*";
980 
                MsgOn: Boolean := True;
981 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
982 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
983 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
984 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
985 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
986 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
987 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
988 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
989 
 
990 
 
991 
--pragma translate_on
992 
    port(
993 
                A               : in    STD_ULOGIC;
994 
                B               : in    STD_ULOGIC;
995 
                C               : in    STD_ULOGIC;
996 
                D               : in    STD_ULOGIC;
997 
                Y               : out    STD_ULOGIC);
998 
 end component;
999 
 
1000 
 
1001 
------ Component AO3 ------
1002 
 component AO3
1003 
--pragma translate_off
1004 
    generic(
1005 
                TimingChecksOn:Boolean := True;
1006 
                Xon: Boolean := False;
1007 
                InstancePath: STRING :="*";
1008 
                MsgOn: Boolean := True;
1009 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1010 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1011 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1012 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1013 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1014 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1015 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1016 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1017 
 
1018 
 
1019 
--pragma translate_on
1020 
    port(
1021 
                A               : in    STD_ULOGIC;
1022 
                B               : in    STD_ULOGIC;
1023 
                C               : in    STD_ULOGIC;
1024 
                D               : in    STD_ULOGIC;
1025 
                Y               : out    STD_ULOGIC);
1026 
 end component;
1027 
 
1028 
 
1029 
------ Component AO3A ------
1030 
 component AO3A
1031 
--pragma translate_off
1032 
    generic(
1033 
                TimingChecksOn:Boolean := True;
1034 
                Xon: Boolean := False;
1035 
                InstancePath: STRING :="*";
1036 
                MsgOn: Boolean := True;
1037 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1038 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1039 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1040 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1041 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1042 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1043 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1044 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1045 
 
1046 
 
1047 
--pragma translate_on
1048 
    port(
1049 
                A               : in    STD_ULOGIC;
1050 
                B               : in    STD_ULOGIC;
1051 
                C               : in    STD_ULOGIC;
1052 
                D               : in    STD_ULOGIC;
1053 
                Y               : out    STD_ULOGIC);
1054 
 end component;
1055 
 
1056 
 
1057 
------ Component AO3B ------
1058 
 component AO3B
1059 
--pragma translate_off
1060 
    generic(
1061 
                TimingChecksOn:Boolean := True;
1062 
                Xon: Boolean := False;
1063 
                InstancePath: STRING :="*";
1064 
                MsgOn: Boolean := True;
1065 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1066 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1067 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1068 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1069 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1070 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1071 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1072 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1073 
 
1074 
 
1075 
--pragma translate_on
1076 
    port(
1077 
                A               : in    STD_ULOGIC;
1078 
                B               : in    STD_ULOGIC;
1079 
                C               : in    STD_ULOGIC;
1080 
                D               : in    STD_ULOGIC;
1081 
                Y               : out    STD_ULOGIC);
1082 
 end component;
1083 
 
1084 
 
1085 
------ Component AO3C ------
1086 
 component AO3C
1087 
--pragma translate_off
1088 
    generic(
1089 
                TimingChecksOn:Boolean := True;
1090 
                Xon: Boolean := False;
1091 
                InstancePath: STRING :="*";
1092 
                MsgOn: Boolean := True;
1093 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1094 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1095 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1096 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1097 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1098 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1099 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1100 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1101 
 
1102 
 
1103 
--pragma translate_on
1104 
    port(
1105 
                A               : in    STD_ULOGIC;
1106 
                B               : in    STD_ULOGIC;
1107 
                C               : in    STD_ULOGIC;
1108 
                D               : in    STD_ULOGIC;
1109 
                Y               : out    STD_ULOGIC);
1110 
 end component;
1111 
 
1112 
 
1113 
------ Component AO4A ------
1114 
 component AO4A
1115 
--pragma translate_off
1116 
    generic(
1117 
                TimingChecksOn:Boolean := True;
1118 
                Xon: Boolean := False;
1119 
                InstancePath: STRING :="*";
1120 
                MsgOn: Boolean := True;
1121 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1122 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1123 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1124 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1125 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1126 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1127 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1128 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1129 
 
1130 
 
1131 
--pragma translate_on
1132 
    port(
1133 
                A               : in    STD_ULOGIC;
1134 
                B               : in    STD_ULOGIC;
1135 
                C               : in    STD_ULOGIC;
1136 
                D               : in    STD_ULOGIC;
1137 
                Y               : out    STD_ULOGIC);
1138 
 end component;
1139 
 
1140 
 
1141 
------ Component AO5A ------
1142 
 component AO5A
1143 
--pragma translate_off
1144 
    generic(
1145 
                TimingChecksOn:Boolean := True;
1146 
                Xon: Boolean := False;
1147 
                InstancePath: STRING :="*";
1148 
                MsgOn: Boolean := True;
1149 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1150 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1151 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1152 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1153 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1154 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1155 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1156 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1157 
 
1158 
 
1159 
--pragma translate_on
1160 
    port(
1161 
                A               : in    STD_ULOGIC;
1162 
                B               : in    STD_ULOGIC;
1163 
                C               : in    STD_ULOGIC;
1164 
                D               : in    STD_ULOGIC;
1165 
                Y               : out    STD_ULOGIC);
1166 
 end component;
1167 
 
1168 
 
1169 
------ Component AO6 ------
1170 
 component AO6
1171 
--pragma translate_off
1172 
    generic(
1173 
                TimingChecksOn:Boolean := True;
1174 
                Xon: Boolean := False;
1175 
                InstancePath: STRING :="*";
1176 
                MsgOn: Boolean := True;
1177 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1178 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1179 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1180 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1181 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1182 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1183 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1184 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1185 
 
1186 
 
1187 
--pragma translate_on
1188 
    port(
1189 
                A               : in    STD_ULOGIC;
1190 
                B               : in    STD_ULOGIC;
1191 
                C               : in    STD_ULOGIC;
1192 
                D               : in    STD_ULOGIC;
1193 
                Y               : out    STD_ULOGIC);
1194 
 end component;
1195 
 
1196 
 
1197 
------ Component AO6A ------
1198 
 component AO6A
1199 
--pragma translate_off
1200 
    generic(
1201 
                TimingChecksOn:Boolean := True;
1202 
                Xon: Boolean := False;
1203 
                InstancePath: STRING :="*";
1204 
                MsgOn: Boolean := True;
1205 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1206 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1207 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1208 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1209 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1210 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1211 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1212 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1213 
 
1214 
 
1215 
--pragma translate_on
1216 
    port(
1217 
                A               : in    STD_ULOGIC;
1218 
                B               : in    STD_ULOGIC;
1219 
                C               : in    STD_ULOGIC;
1220 
                D               : in    STD_ULOGIC;
1221 
                Y               : out    STD_ULOGIC);
1222 
 end component;
1223 
 
1224 
 
1225 
------ Component AO7 ------
1226 
 component AO7
1227 
--pragma translate_off
1228 
    generic(
1229 
                TimingChecksOn:Boolean := True;
1230 
                Xon: Boolean := False;
1231 
                InstancePath: STRING :="*";
1232 
                MsgOn: Boolean := True;
1233 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1234 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1235 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1236 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1237 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1238 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1239 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1240 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1241 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1242 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1243 
 
1244 
 
1245 
--pragma translate_on
1246 
    port(
1247 
                A               : in    STD_ULOGIC;
1248 
                B               : in    STD_ULOGIC;
1249 
                C               : in    STD_ULOGIC;
1250 
                D               : in    STD_ULOGIC;
1251 
                E               : in    STD_ULOGIC;
1252 
                Y               : out    STD_ULOGIC);
1253 
 end component;
1254 
 
1255 
 
1256 
------ Component AO8 ------
1257 
 component AO8
1258 
--pragma translate_off
1259 
    generic(
1260 
                TimingChecksOn:Boolean := True;
1261 
                Xon: Boolean := False;
1262 
                InstancePath: STRING :="*";
1263 
                MsgOn: Boolean := True;
1264 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1265 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1266 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1267 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1268 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1269 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1270 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1271 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1272 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1273 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1274 
 
1275 
 
1276 
--pragma translate_on
1277 
    port(
1278 
                A               : in    STD_ULOGIC;
1279 
                B               : in    STD_ULOGIC;
1280 
                C               : in    STD_ULOGIC;
1281 
                D               : in    STD_ULOGIC;
1282 
                E               : in    STD_ULOGIC;
1283 
                Y               : out    STD_ULOGIC);
1284 
 end component;
1285 
 
1286 
 
1287 
------ Component AO9 ------
1288 
 component AO9
1289 
--pragma translate_off
1290 
    generic(
1291 
                TimingChecksOn:Boolean := True;
1292 
                Xon: Boolean := False;
1293 
                InstancePath: STRING :="*";
1294 
                MsgOn: Boolean := True;
1295 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1296 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1297 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1298 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1299 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1300 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1301 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1302 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1303 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1304 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1305 
 
1306 
 
1307 
--pragma translate_on
1308 
    port(
1309 
                A               : in    STD_ULOGIC;
1310 
                B               : in    STD_ULOGIC;
1311 
                C               : in    STD_ULOGIC;
1312 
                D               : in    STD_ULOGIC;
1313 
                E               : in    STD_ULOGIC;
1314 
                Y               : out    STD_ULOGIC);
1315 
 end component;
1316 
 
1317 
 
1318 
------ Component AOI1 ------
1319 
 component AOI1
1320 
--pragma translate_off
1321 
    generic(
1322 
                TimingChecksOn:Boolean := True;
1323 
                Xon: Boolean := False;
1324 
                InstancePath: STRING :="*";
1325 
                MsgOn: Boolean := True;
1326 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1327 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1328 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1329 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1330 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1331 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1332 
 
1333 
 
1334 
--pragma translate_on
1335 
    port(
1336 
                A               : in    STD_ULOGIC;
1337 
                B               : in    STD_ULOGIC;
1338 
                C               : in    STD_ULOGIC;
1339 
                Y               : out    STD_ULOGIC);
1340 
 end component;
1341 
 
1342 
 
1343 
------ Component AOI1A ------
1344 
 component AOI1A
1345 
--pragma translate_off
1346 
    generic(
1347 
                TimingChecksOn:Boolean := True;
1348 
                Xon: Boolean := False;
1349 
                InstancePath: STRING :="*";
1350 
                MsgOn: Boolean := True;
1351 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1352 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1353 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1354 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1355 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1356 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1357 
 
1358 
 
1359 
--pragma translate_on
1360 
    port(
1361 
                A               : in    STD_ULOGIC;
1362 
                B               : in    STD_ULOGIC;
1363 
                C               : in    STD_ULOGIC;
1364 
                Y               : out    STD_ULOGIC);
1365 
 end component;
1366 
 
1367 
 
1368 
------ Component AOI1B ------
1369 
 component AOI1B
1370 
--pragma translate_off
1371 
    generic(
1372 
                TimingChecksOn:Boolean := True;
1373 
                Xon: Boolean := False;
1374 
                InstancePath: STRING :="*";
1375 
                MsgOn: Boolean := True;
1376 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1377 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1378 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1379 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1380 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1381 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1382 
 
1383 
 
1384 
--pragma translate_on
1385 
    port(
1386 
                A               : in    STD_ULOGIC;
1387 
                B               : in    STD_ULOGIC;
1388 
                C               : in    STD_ULOGIC;
1389 
                Y               : out    STD_ULOGIC);
1390 
 end component;
1391 
 
1392 
 
1393 
------ Component AOI1C ------
1394 
 component AOI1C
1395 
--pragma translate_off
1396 
    generic(
1397 
                TimingChecksOn:Boolean := True;
1398 
                Xon: Boolean := False;
1399 
                InstancePath: STRING :="*";
1400 
                MsgOn: Boolean := True;
1401 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1402 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1403 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1404 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1405 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1406 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1407 
 
1408 
 
1409 
--pragma translate_on
1410 
    port(
1411 
                A               : in    STD_ULOGIC;
1412 
                B               : in    STD_ULOGIC;
1413 
                C               : in    STD_ULOGIC;
1414 
                Y               : out    STD_ULOGIC);
1415 
 end component;
1416 
 
1417 
 
1418 
------ Component AOI1D ------
1419 
 component AOI1D
1420 
--pragma translate_off
1421 
    generic(
1422 
                TimingChecksOn:Boolean := True;
1423 
                Xon: Boolean := False;
1424 
                InstancePath: STRING :="*";
1425 
                MsgOn: Boolean := True;
1426 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1427 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1428 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1429 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1430 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1431 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1432 
 
1433 
 
1434 
--pragma translate_on
1435 
    port(
1436 
                A               : in    STD_ULOGIC;
1437 
                B               : in    STD_ULOGIC;
1438 
                C               : in    STD_ULOGIC;
1439 
                Y               : out    STD_ULOGIC);
1440 
 end component;
1441 
 
1442 
 
1443 
------ Component AOI2A ------
1444 
 component AOI2A
1445 
--pragma translate_off
1446 
    generic(
1447 
                TimingChecksOn:Boolean := True;
1448 
                Xon: Boolean := False;
1449 
                InstancePath: STRING :="*";
1450 
                MsgOn: Boolean := True;
1451 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1452 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1453 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1454 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1455 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1456 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1457 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1458 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1459 
 
1460 
 
1461 
--pragma translate_on
1462 
    port(
1463 
                A               : in    STD_ULOGIC;
1464 
                B               : in    STD_ULOGIC;
1465 
                C               : in    STD_ULOGIC;
1466 
                D               : in    STD_ULOGIC;
1467 
                Y               : out    STD_ULOGIC);
1468 
 end component;
1469 
 
1470 
 
1471 
------ Component AOI2B ------
1472 
 component AOI2B
1473 
--pragma translate_off
1474 
    generic(
1475 
                TimingChecksOn:Boolean := True;
1476 
                Xon: Boolean := False;
1477 
                InstancePath: STRING :="*";
1478 
                MsgOn: Boolean := True;
1479 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1480 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1481 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1482 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1483 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1484 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1485 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1486 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1487 
 
1488 
 
1489 
--pragma translate_on
1490 
    port(
1491 
                A               : in    STD_ULOGIC;
1492 
                B               : in    STD_ULOGIC;
1493 
                C               : in    STD_ULOGIC;
1494 
                D               : in    STD_ULOGIC;
1495 
                Y               : out    STD_ULOGIC);
1496 
 end component;
1497 
 
1498 
 
1499 
------ Component AOI3A ------
1500 
 component AOI3A
1501 
--pragma translate_off
1502 
    generic(
1503 
                TimingChecksOn:Boolean := True;
1504 
                Xon: Boolean := False;
1505 
                InstancePath: STRING :="*";
1506 
                MsgOn: Boolean := True;
1507 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1508 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1509 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1510 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1511 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1512 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1513 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1514 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1515 
 
1516 
 
1517 
--pragma translate_on
1518 
    port(
1519 
                A               : in    STD_ULOGIC;
1520 
                B               : in    STD_ULOGIC;
1521 
                C               : in    STD_ULOGIC;
1522 
                D               : in    STD_ULOGIC;
1523 
                Y               : out    STD_ULOGIC);
1524 
 end component;
1525 
 
1526 
 
1527 
------ Component AOI4 ------
1528 
 component AOI4
1529 
--pragma translate_off
1530 
    generic(
1531 
                TimingChecksOn:Boolean := True;
1532 
                Xon: Boolean := False;
1533 
                InstancePath: STRING :="*";
1534 
                MsgOn: Boolean := True;
1535 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1536 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1537 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1538 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1539 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1540 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1541 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1542 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1543 
 
1544 
 
1545 
--pragma translate_on
1546 
    port(
1547 
                A               : in    STD_ULOGIC;
1548 
                B               : in    STD_ULOGIC;
1549 
                C               : in    STD_ULOGIC;
1550 
                D               : in    STD_ULOGIC;
1551 
                Y               : out    STD_ULOGIC);
1552 
 end component;
1553 
 
1554 
 
1555 
------ Component AOI4A ------
1556 
 component AOI4A
1557 
--pragma translate_off
1558 
    generic(
1559 
                TimingChecksOn:Boolean := True;
1560 
                Xon: Boolean := False;
1561 
                InstancePath: STRING :="*";
1562 
                MsgOn: Boolean := True;
1563 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1564 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1565 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1566 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1567 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1568 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1569 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1570 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1571 
 
1572 
 
1573 
--pragma translate_on
1574 
    port(
1575 
                A               : in    STD_ULOGIC;
1576 
                B               : in    STD_ULOGIC;
1577 
                C               : in    STD_ULOGIC;
1578 
                D               : in    STD_ULOGIC;
1579 
                Y               : out    STD_ULOGIC);
1580 
 end component;
1581 
 
1582 
 
1583 
------ Component AOI5 ------
1584 
 component AOI5
1585 
--pragma translate_off
1586 
    generic(
1587 
                TimingChecksOn:Boolean := True;
1588 
                Xon: Boolean := False;
1589 
                InstancePath: STRING :="*";
1590 
                MsgOn: Boolean := True;
1591 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1592 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1593 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1594 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1595 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1596 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1597 
 
1598 
 
1599 
--pragma translate_on
1600 
    port(
1601 
                A               : in    STD_ULOGIC;
1602 
                B               : in    STD_ULOGIC;
1603 
                C               : in    STD_ULOGIC;
1604 
                Y               : out    STD_ULOGIC);
1605 
 end component;
1606 
 
1607 
 
1608 
------ Component AFCNTECP1 ------
1609 
 component AFCNTECP1
1610 
--pragma translate_off
1611 
    generic(
1612 
                TimingChecksOn: Boolean := True;
1613 
                InstancePath: STRING := "*";
1614 
                Xon: Boolean := False;
1615 
                MsgOn: Boolean := True;
1616 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1617 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1618 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1619 
                tpd_UD_FCO              :   VitalDelayType01 := (0.100 ns, 0.100 ns);
1620 
                tpd_FCI_FCO             :   VitalDelayType01 := (0.100 ns, 0.100 ns);
1621 
                tsetup_Q_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
1622 
                thold_Q_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
1623 
                tsetup_UD_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
1624 
                thold_UD_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
1625 
                tsetup_FCI_CLK_posedge_negedge          :   VitalDelayType := 0.000 ns;
1626 
                thold_FCI_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
1627 
                tsetup_Q_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
1628 
                thold_Q_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
1629 
                tsetup_UD_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
1630 
                thold_UD_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
1631 
                tsetup_FCI_CLK_negedge_negedge          :   VitalDelayType := 0.000 ns;
1632 
                thold_FCI_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
1633 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
1634 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
1635 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
1636 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
1637 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
1638 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
1639 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
1640 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
1641 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
1642 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
1643 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
1644 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
1645 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1646 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1647 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1648 
                tipd_UD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1649 
                tipd_FCI                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1650 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
1651 
 
1652 
 
1653 
--pragma translate_on
1654 
    port(
1655 
                CLR             :   in    STD_ULOGIC;
1656 
                PRE             :   in    STD_ULOGIC;
1657 
                E               :   in    STD_ULOGIC;
1658 
                CLK             :   in    STD_ULOGIC;
1659 
                Q               :  out STD_ULOGIC;
1660 
                UD              :  in    STD_ULOGIC;
1661 
                FCI             :  in    STD_ULOGIC;
1662 
                FCO             :  out    STD_ULOGIC);
1663 
 
1664 
 end component;
1665 
 
1666 
 
1667 
------ Component ARCNTECP1 ------
1668 
 component ARCNTECP1
1669 
--pragma translate_off
1670 
    generic(
1671 
                TimingChecksOn: Boolean := True;
1672 
                InstancePath: STRING := "*";
1673 
                Xon: Boolean := False;
1674 
                MsgOn: Boolean := True;
1675 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1676 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1677 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1678 
                tpd_UD_FCO              :   VitalDelayType01 := (0.100 ns, 0.100 ns);
1679 
                tpd_FCI_FCO             :   VitalDelayType01 := (0.100 ns, 0.100 ns);
1680 
                tsetup_Q_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
1681 
                thold_Q_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
1682 
                tsetup_UD_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
1683 
                thold_UD_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
1684 
                tsetup_FCI_CLK_posedge_posedge          :   VitalDelayType := 0.000 ns;
1685 
                thold_FCI_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
1686 
                tsetup_Q_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
1687 
                thold_Q_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
1688 
                tsetup_UD_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
1689 
                thold_UD_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
1690 
                tsetup_FCI_CLK_negedge_posedge          :   VitalDelayType := 0.000 ns;
1691 
                thold_FCI_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
1692 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
1693 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
1694 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
1695 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
1696 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
1697 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
1698 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
1699 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
1700 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
1701 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
1702 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
1703 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
1704 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1705 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1706 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1707 
                tipd_UD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1708 
                tipd_FCI                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1709 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
1710 
 
1711 
 
1712 
--pragma translate_on
1713 
    port(
1714 
                CLR             :   in    STD_ULOGIC;
1715 
                PRE             :   in    STD_ULOGIC;
1716 
                E               :   in    STD_ULOGIC;
1717 
                CLK             :   in    STD_ULOGIC;
1718 
                Q               :  out STD_ULOGIC;
1719 
                UD              :  in    STD_ULOGIC;
1720 
                FCI             :  in    STD_ULOGIC;
1721 
                FCO             :  out    STD_ULOGIC);
1722 
 
1723 
 end component;
1724 
 
1725 
 
1726 
------ Component AFCNTELDCP1 ------
1727 
 component AFCNTELDCP1
1728 
--pragma translate_off
1729 
    generic(
1730 
                TimingChecksOn: Boolean := True;
1731 
                InstancePath: STRING := "*";
1732 
                Xon: Boolean := False;
1733 
                MsgOn: Boolean := True;
1734 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1735 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1736 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1737 
                tpd_UD_FCO              :   VitalDelayType01 := (0.100 ns, 0.100 ns);
1738 
                tpd_FCI_FCO             :   VitalDelayType01 := (0.100 ns, 0.100 ns);
1739 
                tsetup_LD_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
1740 
                thold_LD_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
1741 
                tsetup_Q_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
1742 
                thold_Q_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
1743 
                tsetup_UD_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
1744 
                thold_UD_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
1745 
                tsetup_FCI_CLK_posedge_negedge          :   VitalDelayType := 0.000 ns;
1746 
                thold_FCI_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
1747 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
1748 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
1749 
                tsetup_LD_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
1750 
                thold_LD_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
1751 
                tsetup_Q_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
1752 
                thold_Q_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
1753 
                tsetup_UD_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
1754 
                thold_UD_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
1755 
                tsetup_FCI_CLK_negedge_negedge          :   VitalDelayType := 0.000 ns;
1756 
                thold_FCI_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
1757 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
1758 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
1759 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
1760 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
1761 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
1762 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
1763 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
1764 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
1765 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
1766 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
1767 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
1768 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
1769 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
1770 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
1771 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1772 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1773 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1774 
                tipd_LD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1775 
                tipd_UD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1776 
                tipd_FCI                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1777 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1778 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
1779 
 
1780 
 
1781 
--pragma translate_on
1782 
    port(
1783 
                CLR             :   in    STD_ULOGIC;
1784 
                PRE             :   in    STD_ULOGIC;
1785 
                E               :   in    STD_ULOGIC;
1786 
                CLK             :   in    STD_ULOGIC;
1787 
                LD              :  in    STD_ULOGIC;
1788 
                Q               :  out STD_ULOGIC;
1789 
                UD              :  in    STD_ULOGIC;
1790 
                FCI             :  in    STD_ULOGIC;
1791 
                D               :  in    STD_ULOGIC;
1792 
                FCO             :  out    STD_ULOGIC);
1793 
 
1794 
 end component;
1795 
 
1796 
 
1797 
------ Component ARCNTELDCP1 ------
1798 
 component ARCNTELDCP1
1799 
--pragma translate_off
1800 
    generic(
1801 
                TimingChecksOn: Boolean := True;
1802 
                InstancePath: STRING := "*";
1803 
                Xon: Boolean := False;
1804 
                MsgOn: Boolean := True;
1805 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1806 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1807 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
1808 
                tpd_UD_FCO              :   VitalDelayType01 := (0.100 ns, 0.100 ns);
1809 
                tpd_FCI_FCO             :   VitalDelayType01 := (0.100 ns, 0.100 ns);
1810 
                tsetup_LD_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
1811 
                thold_LD_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
1812 
                tsetup_Q_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
1813 
                thold_Q_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
1814 
                tsetup_UD_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
1815 
                thold_UD_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
1816 
                tsetup_FCI_CLK_posedge_posedge          :   VitalDelayType := 0.000 ns;
1817 
                thold_FCI_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
1818 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
1819 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
1820 
                tsetup_LD_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
1821 
                thold_LD_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
1822 
                tsetup_Q_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
1823 
                thold_Q_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
1824 
                tsetup_UD_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
1825 
                thold_UD_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
1826 
                tsetup_FCI_CLK_negedge_posedge          :   VitalDelayType := 0.000 ns;
1827 
                thold_FCI_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
1828 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
1829 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
1830 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
1831 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
1832 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
1833 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
1834 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
1835 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
1836 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
1837 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
1838 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
1839 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
1840 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
1841 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
1842 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1843 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1844 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1845 
                tipd_LD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1846 
                tipd_UD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1847 
                tipd_FCI                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1848 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
1849 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
1850 
 
1851 
 
1852 
--pragma translate_on
1853 
    port(
1854 
                CLR             :   in    STD_ULOGIC;
1855 
                PRE             :   in    STD_ULOGIC;
1856 
                E               :   in    STD_ULOGIC;
1857 
                CLK             :   in    STD_ULOGIC;
1858 
                LD              :  in    STD_ULOGIC;
1859 
                Q               :  out STD_ULOGIC;
1860 
                UD              :  in    STD_ULOGIC;
1861 
                FCI             :  in    STD_ULOGIC;
1862 
                D               :  in    STD_ULOGIC;
1863 
                FCO             :  out    STD_ULOGIC);
1864 
 
1865 
 end component;
1866 
 
1867 
 
1868 
------ Component AX1 ------
1869 
 component AX1
1870 
--pragma translate_off
1871 
    generic(
1872 
                TimingChecksOn:Boolean := True;
1873 
                Xon: Boolean := False;
1874 
                InstancePath: STRING :="*";
1875 
                MsgOn: Boolean := True;
1876 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1877 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1878 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1879 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1880 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1881 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1882 
 
1883 
 
1884 
--pragma translate_on
1885 
    port(
1886 
                A               : in    STD_ULOGIC;
1887 
                B               : in    STD_ULOGIC;
1888 
                C               : in    STD_ULOGIC;
1889 
                Y               : out    STD_ULOGIC);
1890 
 end component;
1891 
 
1892 
 
1893 
------ Component AX1A ------
1894 
 component AX1A
1895 
--pragma translate_off
1896 
    generic(
1897 
                TimingChecksOn:Boolean := True;
1898 
                Xon: Boolean := False;
1899 
                InstancePath: STRING :="*";
1900 
                MsgOn: Boolean := True;
1901 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1902 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1903 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1904 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1905 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1906 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1907 
 
1908 
 
1909 
--pragma translate_on
1910 
    port(
1911 
                A               : in    STD_ULOGIC;
1912 
                B               : in    STD_ULOGIC;
1913 
                C               : in    STD_ULOGIC;
1914 
                Y               : out    STD_ULOGIC);
1915 
 end component;
1916 
 
1917 
 
1918 
------ Component AX1B ------
1919 
 component AX1B
1920 
--pragma translate_off
1921 
    generic(
1922 
                TimingChecksOn:Boolean := True;
1923 
                Xon: Boolean := False;
1924 
                InstancePath: STRING :="*";
1925 
                MsgOn: Boolean := True;
1926 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1927 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1928 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1929 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1930 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1931 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1932 
 
1933 
 
1934 
--pragma translate_on
1935 
    port(
1936 
                A               : in    STD_ULOGIC;
1937 
                B               : in    STD_ULOGIC;
1938 
                C               : in    STD_ULOGIC;
1939 
                Y               : out    STD_ULOGIC);
1940 
 end component;
1941 
 
1942 
 
1943 
------ Component AX1C ------
1944 
 component AX1C
1945 
--pragma translate_off
1946 
    generic(
1947 
                TimingChecksOn:Boolean := True;
1948 
                Xon: Boolean := False;
1949 
                InstancePath: STRING :="*";
1950 
                MsgOn: Boolean := True;
1951 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1952 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1953 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1954 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1955 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1956 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1957 
 
1958 
 
1959 
--pragma translate_on
1960 
    port(
1961 
                A               : in    STD_ULOGIC;
1962 
                B               : in    STD_ULOGIC;
1963 
                C               : in    STD_ULOGIC;
1964 
                Y               : out    STD_ULOGIC);
1965 
 end component;
1966 
 
1967 
 
1968 
------ Component AX1D ------
1969 
 component AX1D
1970 
--pragma translate_off
1971 
    generic(
1972 
                TimingChecksOn:Boolean := True;
1973 
                Xon: Boolean := False;
1974 
                InstancePath: STRING :="*";
1975 
                MsgOn: Boolean := True;
1976 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1977 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1978 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
1979 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1980 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
1981 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
1982 
 
1983 
 
1984 
--pragma translate_on
1985 
    port(
1986 
                A               : in    STD_ULOGIC;
1987 
                B               : in    STD_ULOGIC;
1988 
                C               : in    STD_ULOGIC;
1989 
                Y               : out    STD_ULOGIC);
1990 
 end component;
1991 
 
1992 
 
1993 
------ Component AX1E ------
1994 
 component AX1E
1995 
--pragma translate_off
1996 
    generic(
1997 
                TimingChecksOn:Boolean := True;
1998 
                Xon: Boolean := False;
1999 
                InstancePath: STRING :="*";
2000 
                MsgOn: Boolean := True;
2001 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2002 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2003 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2004 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2005 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2006 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2007 
 
2008 
 
2009 
--pragma translate_on
2010 
    port(
2011 
                A               : in    STD_ULOGIC;
2012 
                B               : in    STD_ULOGIC;
2013 
                C               : in    STD_ULOGIC;
2014 
                Y               : out    STD_ULOGIC);
2015 
 end component;
2016 
 
2017 
 
2018 
------ Component AXO1 ------
2019 
 component AXO1
2020 
--pragma translate_off
2021 
    generic(
2022 
                TimingChecksOn:Boolean := True;
2023 
                Xon: Boolean := False;
2024 
                InstancePath: STRING :="*";
2025 
                MsgOn: Boolean := True;
2026 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2027 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2028 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2029 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2030 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2031 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2032 
 
2033 
 
2034 
--pragma translate_on
2035 
    port(
2036 
                A               : in    STD_ULOGIC;
2037 
                B               : in    STD_ULOGIC;
2038 
                C               : in    STD_ULOGIC;
2039 
                Y               : out    STD_ULOGIC);
2040 
 end component;
2041 
 
2042 
 
2043 
------ Component AXO2 ------
2044 
 component AXO2
2045 
--pragma translate_off
2046 
    generic(
2047 
                TimingChecksOn:Boolean := True;
2048 
                Xon: Boolean := False;
2049 
                InstancePath: STRING :="*";
2050 
                MsgOn: Boolean := True;
2051 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2052 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2053 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2054 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2055 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2056 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2057 
 
2058 
 
2059 
--pragma translate_on
2060 
    port(
2061 
                A               : in    STD_ULOGIC;
2062 
                B               : in    STD_ULOGIC;
2063 
                C               : in    STD_ULOGIC;
2064 
                Y               : out    STD_ULOGIC);
2065 
 end component;
2066 
 
2067 
 
2068 
------ Component AXO3 ------
2069 
 component AXO3
2070 
--pragma translate_off
2071 
    generic(
2072 
                TimingChecksOn:Boolean := True;
2073 
                Xon: Boolean := False;
2074 
                InstancePath: STRING :="*";
2075 
                MsgOn: Boolean := True;
2076 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2077 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2078 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2079 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2080 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2081 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2082 
 
2083 
 
2084 
--pragma translate_on
2085 
    port(
2086 
                A               : in    STD_ULOGIC;
2087 
                B               : in    STD_ULOGIC;
2088 
                C               : in    STD_ULOGIC;
2089 
                Y               : out    STD_ULOGIC);
2090 
 end component;
2091 
 
2092 
 
2093 
------ Component AXO5 ------
2094 
 component AXO5
2095 
--pragma translate_off
2096 
    generic(
2097 
                TimingChecksOn:Boolean := True;
2098 
                Xon: Boolean := False;
2099 
                InstancePath: STRING :="*";
2100 
                MsgOn: Boolean := True;
2101 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2102 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2103 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2104 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2105 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2106 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2107 
 
2108 
 
2109 
--pragma translate_on
2110 
    port(
2111 
                A               : in    STD_ULOGIC;
2112 
                B               : in    STD_ULOGIC;
2113 
                C               : in    STD_ULOGIC;
2114 
                Y               : out    STD_ULOGIC);
2115 
 end component;
2116 
 
2117 
 
2118 
------ Component AXO6 ------
2119 
 component AXO6
2120 
--pragma translate_off
2121 
    generic(
2122 
                TimingChecksOn:Boolean := True;
2123 
                Xon: Boolean := False;
2124 
                InstancePath: STRING :="*";
2125 
                MsgOn: Boolean := True;
2126 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2127 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2128 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2129 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2130 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2131 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2132 
 
2133 
 
2134 
--pragma translate_on
2135 
    port(
2136 
                A               : in    STD_ULOGIC;
2137 
                B               : in    STD_ULOGIC;
2138 
                C               : in    STD_ULOGIC;
2139 
                Y               : out    STD_ULOGIC);
2140 
 end component;
2141 
 
2142 
 
2143 
------ Component AXO7 ------
2144 
 component AXO7
2145 
--pragma translate_off
2146 
    generic(
2147 
                TimingChecksOn:Boolean := True;
2148 
                Xon: Boolean := False;
2149 
                InstancePath: STRING :="*";
2150 
                MsgOn: Boolean := True;
2151 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2152 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2153 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2154 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2155 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2156 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2157 
 
2158 
 
2159 
--pragma translate_on
2160 
    port(
2161 
                A               : in    STD_ULOGIC;
2162 
                B               : in    STD_ULOGIC;
2163 
                C               : in    STD_ULOGIC;
2164 
                Y               : out    STD_ULOGIC);
2165 
 end component;
2166 
 
2167 
 
2168 
------ Component AXOI1 ------
2169 
 component AXOI1
2170 
--pragma translate_off
2171 
    generic(
2172 
                TimingChecksOn:Boolean := True;
2173 
                Xon: Boolean := False;
2174 
                InstancePath: STRING :="*";
2175 
                MsgOn: Boolean := True;
2176 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2177 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2178 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2179 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2180 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2181 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2182 
 
2183 
 
2184 
--pragma translate_on
2185 
    port(
2186 
                A               : in    STD_ULOGIC;
2187 
                B               : in    STD_ULOGIC;
2188 
                C               : in    STD_ULOGIC;
2189 
                Y               : out    STD_ULOGIC);
2190 
 end component;
2191 
 
2192 
 
2193 
------ Component AXOI2 ------
2194 
 component AXOI2
2195 
--pragma translate_off
2196 
    generic(
2197 
                TimingChecksOn:Boolean := True;
2198 
                Xon: Boolean := False;
2199 
                InstancePath: STRING :="*";
2200 
                MsgOn: Boolean := True;
2201 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2202 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2203 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2204 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2205 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2206 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2207 
 
2208 
 
2209 
--pragma translate_on
2210 
    port(
2211 
                A               : in    STD_ULOGIC;
2212 
                B               : in    STD_ULOGIC;
2213 
                C               : in    STD_ULOGIC;
2214 
                Y               : out    STD_ULOGIC);
2215 
 end component;
2216 
 
2217 
 
2218 
------ Component AXOI3 ------
2219 
 component AXOI3
2220 
--pragma translate_off
2221 
    generic(
2222 
                TimingChecksOn:Boolean := True;
2223 
                Xon: Boolean := False;
2224 
                InstancePath: STRING :="*";
2225 
                MsgOn: Boolean := True;
2226 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2227 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2228 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2229 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2230 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2231 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2232 
 
2233 
 
2234 
--pragma translate_on
2235 
    port(
2236 
                A               : in    STD_ULOGIC;
2237 
                B               : in    STD_ULOGIC;
2238 
                C               : in    STD_ULOGIC;
2239 
                Y               : out    STD_ULOGIC);
2240 
 end component;
2241 
 
2242 
 
2243 
------ Component AXOI4 ------
2244 
 component AXOI4
2245 
--pragma translate_off
2246 
    generic(
2247 
                TimingChecksOn:Boolean := True;
2248 
                Xon: Boolean := False;
2249 
                InstancePath: STRING :="*";
2250 
                MsgOn: Boolean := True;
2251 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2252 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2253 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2254 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2255 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2256 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2257 
 
2258 
 
2259 
--pragma translate_on
2260 
    port(
2261 
                A               : in    STD_ULOGIC;
2262 
                B               : in    STD_ULOGIC;
2263 
                C               : in    STD_ULOGIC;
2264 
                Y               : out    STD_ULOGIC);
2265 
 end component;
2266 
 
2267 
 
2268 
------ Component AXOI5 ------
2269 
 component AXOI5
2270 
--pragma translate_off
2271 
    generic(
2272 
                TimingChecksOn:Boolean := True;
2273 
                Xon: Boolean := False;
2274 
                InstancePath: STRING :="*";
2275 
                MsgOn: Boolean := True;
2276 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2277 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2278 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2279 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2280 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2281 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2282 
 
2283 
 
2284 
--pragma translate_on
2285 
    port(
2286 
                A               : in    STD_ULOGIC;
2287 
                B               : in    STD_ULOGIC;
2288 
                C               : in    STD_ULOGIC;
2289 
                Y               : out    STD_ULOGIC);
2290 
 end component;
2291 
 
2292 
 
2293 
------ Component AXOI7 ------
2294 
 component AXOI7
2295 
--pragma translate_off
2296 
    generic(
2297 
                TimingChecksOn:Boolean := True;
2298 
                Xon: Boolean := False;
2299 
                InstancePath: STRING :="*";
2300 
                MsgOn: Boolean := True;
2301 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2302 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2303 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
2304 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2305 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2306 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
2307 
 
2308 
 
2309 
--pragma translate_on
2310 
    port(
2311 
                A               : in    STD_ULOGIC;
2312 
                B               : in    STD_ULOGIC;
2313 
                C               : in    STD_ULOGIC;
2314 
                Y               : out    STD_ULOGIC);
2315 
 end component;
2316 
 
2317 
 
2318 
------ Component BIBUF ------
2319 
 component BIBUF
2320 
--pragma translate_off
2321 
    generic(
2322 
                TimingChecksOn:Boolean := True;
2323 
                Xon: Boolean := False;
2324 
                InstancePath: STRING :="*";
2325 
                MsgOn: Boolean := True;
2326 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2327 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2328 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2329 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2330 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2331 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2332 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2333 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2334 
 
2335 
 
2336 
--pragma translate_on
2337 
    port(
2338 
                D               : in    STD_ULOGIC;
2339 
                E               : in    STD_ULOGIC;
2340 
                PAD             : inout STD_ULOGIC;
2341 
                Y               : out    STD_ULOGIC);
2342 
 end component;
2343 
 
2344 
 
2345 
------ Component BIBUF_S_8 ------
2346 
 component BIBUF_S_8
2347 
--pragma translate_off
2348 
    generic(
2349 
                TimingChecksOn:Boolean := True;
2350 
                Xon: Boolean := False;
2351 
                InstancePath: STRING :="*";
2352 
                MsgOn: Boolean := True;
2353 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2354 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2355 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2356 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2357 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2358 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2359 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2360 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2361 
 
2362 
 
2363 
--pragma translate_on
2364 
    port(
2365 
                D               : in    STD_ULOGIC;
2366 
                E               : in    STD_ULOGIC;
2367 
                PAD             : inout STD_ULOGIC;
2368 
                Y               : out    STD_ULOGIC);
2369 
 end component;
2370 
 
2371 
 
2372 
------ Component BIBUF_S_8D ------
2373 
 component BIBUF_S_8D
2374 
--pragma translate_off
2375 
    generic(
2376 
                TimingChecksOn:Boolean := True;
2377 
                Xon: Boolean := False;
2378 
                InstancePath: STRING :="*";
2379 
                MsgOn: Boolean := True;
2380 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2381 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2382 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2383 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2384 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2385 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2386 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2387 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2388 
 
2389 
 
2390 
--pragma translate_on
2391 
    port(
2392 
                D               : in    STD_ULOGIC;
2393 
                E               : in    STD_ULOGIC;
2394 
                PAD             : inout STD_ULOGIC;
2395 
                Y               : out    STD_ULOGIC);
2396 
 end component;
2397 
 
2398 
 
2399 
------ Component BIBUF_S_8U ------
2400 
 component BIBUF_S_8U
2401 
--pragma translate_off
2402 
    generic(
2403 
                TimingChecksOn:Boolean := True;
2404 
                Xon: Boolean := False;
2405 
                InstancePath: STRING :="*";
2406 
                MsgOn: Boolean := True;
2407 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2408 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2409 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2410 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2411 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2412 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2413 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2414 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2415 
 
2416 
 
2417 
--pragma translate_on
2418 
    port(
2419 
                D               : in    STD_ULOGIC;
2420 
                E               : in    STD_ULOGIC;
2421 
                PAD             : inout STD_ULOGIC;
2422 
                Y               : out    STD_ULOGIC);
2423 
 end component;
2424 
 
2425 
 
2426 
------ Component BIBUF_S_12 ------
2427 
 component BIBUF_S_12
2428 
--pragma translate_off
2429 
    generic(
2430 
                TimingChecksOn:Boolean := True;
2431 
                Xon: Boolean := False;
2432 
                InstancePath: STRING :="*";
2433 
                MsgOn: Boolean := True;
2434 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2435 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2436 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2437 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2438 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2439 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2440 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2441 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2442 
 
2443 
 
2444 
--pragma translate_on
2445 
    port(
2446 
                D               : in    STD_ULOGIC;
2447 
                E               : in    STD_ULOGIC;
2448 
                PAD             : inout STD_ULOGIC;
2449 
                Y               : out    STD_ULOGIC);
2450 
 end component;
2451 
 
2452 
 
2453 
------ Component BIBUF_S_12D ------
2454 
 component BIBUF_S_12D
2455 
--pragma translate_off
2456 
    generic(
2457 
                TimingChecksOn:Boolean := True;
2458 
                Xon: Boolean := False;
2459 
                InstancePath: STRING :="*";
2460 
                MsgOn: Boolean := True;
2461 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2462 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2463 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2464 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2465 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2466 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2467 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2468 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2469 
 
2470 
 
2471 
--pragma translate_on
2472 
    port(
2473 
                D               : in    STD_ULOGIC;
2474 
                E               : in    STD_ULOGIC;
2475 
                PAD             : inout STD_ULOGIC;
2476 
                Y               : out    STD_ULOGIC);
2477 
 end component;
2478 
 
2479 
 
2480 
------ Component BIBUF_S_12U ------
2481 
 component BIBUF_S_12U
2482 
--pragma translate_off
2483 
    generic(
2484 
                TimingChecksOn:Boolean := True;
2485 
                Xon: Boolean := False;
2486 
                InstancePath: STRING :="*";
2487 
                MsgOn: Boolean := True;
2488 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2489 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2490 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2491 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2492 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2493 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2494 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2495 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2496 
 
2497 
 
2498 
--pragma translate_on
2499 
    port(
2500 
                D               : in    STD_ULOGIC;
2501 
                E               : in    STD_ULOGIC;
2502 
                PAD             : inout STD_ULOGIC;
2503 
                Y               : out    STD_ULOGIC);
2504 
 end component;
2505 
 
2506 
 
2507 
------ Component BIBUF_S_16 ------
2508 
 component BIBUF_S_16
2509 
--pragma translate_off
2510 
    generic(
2511 
                TimingChecksOn:Boolean := True;
2512 
                Xon: Boolean := False;
2513 
                InstancePath: STRING :="*";
2514 
                MsgOn: Boolean := True;
2515 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2516 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2517 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2518 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2519 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2520 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2521 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2522 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2523 
 
2524 
 
2525 
--pragma translate_on
2526 
    port(
2527 
                D               : in    STD_ULOGIC;
2528 
                E               : in    STD_ULOGIC;
2529 
                PAD             : inout STD_ULOGIC;
2530 
                Y               : out    STD_ULOGIC);
2531 
 end component;
2532 
 
2533 
 
2534 
------ Component BIBUF_S_16D ------
2535 
 component BIBUF_S_16D
2536 
--pragma translate_off
2537 
    generic(
2538 
                TimingChecksOn:Boolean := True;
2539 
                Xon: Boolean := False;
2540 
                InstancePath: STRING :="*";
2541 
                MsgOn: Boolean := True;
2542 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2543 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2544 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2545 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2546 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2547 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2548 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2549 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2550 
 
2551 
 
2552 
--pragma translate_on
2553 
    port(
2554 
                D               : in    STD_ULOGIC;
2555 
                E               : in    STD_ULOGIC;
2556 
                PAD             : inout STD_ULOGIC;
2557 
                Y               : out    STD_ULOGIC);
2558 
 end component;
2559 
 
2560 
 
2561 
------ Component BIBUF_S_16U ------
2562 
 component BIBUF_S_16U
2563 
--pragma translate_off
2564 
    generic(
2565 
                TimingChecksOn:Boolean := True;
2566 
                Xon: Boolean := False;
2567 
                InstancePath: STRING :="*";
2568 
                MsgOn: Boolean := True;
2569 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2570 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2571 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2572 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2573 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2574 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2575 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2576 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2577 
 
2578 
 
2579 
--pragma translate_on
2580 
    port(
2581 
                D               : in    STD_ULOGIC;
2582 
                E               : in    STD_ULOGIC;
2583 
                PAD             : inout STD_ULOGIC;
2584 
                Y               : out    STD_ULOGIC);
2585 
 end component;
2586 
 
2587 
 
2588 
------ Component BIBUF_S_24 ------
2589 
 component BIBUF_S_24
2590 
--pragma translate_off
2591 
    generic(
2592 
                TimingChecksOn:Boolean := True;
2593 
                Xon: Boolean := False;
2594 
                InstancePath: STRING :="*";
2595 
                MsgOn: Boolean := True;
2596 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2597 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2598 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2599 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2600 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2601 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2602 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2603 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2604 
 
2605 
 
2606 
--pragma translate_on
2607 
    port(
2608 
                D               : in    STD_ULOGIC;
2609 
                E               : in    STD_ULOGIC;
2610 
                PAD             : inout STD_ULOGIC;
2611 
                Y               : out    STD_ULOGIC);
2612 
 end component;
2613 
 
2614 
 
2615 
------ Component BIBUF_S_24D ------
2616 
 component BIBUF_S_24D
2617 
--pragma translate_off
2618 
    generic(
2619 
                TimingChecksOn:Boolean := True;
2620 
                Xon: Boolean := False;
2621 
                InstancePath: STRING :="*";
2622 
                MsgOn: Boolean := True;
2623 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2624 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2625 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2626 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2627 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2628 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2629 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2630 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2631 
 
2632 
 
2633 
--pragma translate_on
2634 
    port(
2635 
                D               : in    STD_ULOGIC;
2636 
                E               : in    STD_ULOGIC;
2637 
                PAD             : inout STD_ULOGIC;
2638 
                Y               : out    STD_ULOGIC);
2639 
 end component;
2640 
 
2641 
 
2642 
------ Component BIBUF_S_24U ------
2643 
 component BIBUF_S_24U
2644 
--pragma translate_off
2645 
    generic(
2646 
                TimingChecksOn:Boolean := True;
2647 
                Xon: Boolean := False;
2648 
                InstancePath: STRING :="*";
2649 
                MsgOn: Boolean := True;
2650 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2651 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2652 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2653 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2654 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2655 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2656 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2657 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2658 
 
2659 
 
2660 
--pragma translate_on
2661 
    port(
2662 
                D               : in    STD_ULOGIC;
2663 
                E               : in    STD_ULOGIC;
2664 
                PAD             : inout STD_ULOGIC;
2665 
                Y               : out    STD_ULOGIC);
2666 
 end component;
2667 
 
2668 
 
2669 
------ Component BIBUF_F_8 ------
2670 
 component BIBUF_F_8
2671 
--pragma translate_off
2672 
    generic(
2673 
                TimingChecksOn:Boolean := True;
2674 
                Xon: Boolean := False;
2675 
                InstancePath: STRING :="*";
2676 
                MsgOn: Boolean := True;
2677 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2678 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2679 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2680 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2681 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2682 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2683 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2684 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2685 
 
2686 
 
2687 
--pragma translate_on
2688 
    port(
2689 
                D               : in    STD_ULOGIC;
2690 
                E               : in    STD_ULOGIC;
2691 
                PAD             : inout STD_ULOGIC;
2692 
                Y               : out    STD_ULOGIC);
2693 
 end component;
2694 
 
2695 
 
2696 
------ Component BIBUF_F_8D ------
2697 
 component BIBUF_F_8D
2698 
--pragma translate_off
2699 
    generic(
2700 
                TimingChecksOn:Boolean := True;
2701 
                Xon: Boolean := False;
2702 
                InstancePath: STRING :="*";
2703 
                MsgOn: Boolean := True;
2704 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2705 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2706 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2707 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2708 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2709 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2710 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2711 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2712 
 
2713 
 
2714 
--pragma translate_on
2715 
    port(
2716 
                D               : in    STD_ULOGIC;
2717 
                E               : in    STD_ULOGIC;
2718 
                PAD             : inout STD_ULOGIC;
2719 
                Y               : out    STD_ULOGIC);
2720 
 end component;
2721 
 
2722 
 
2723 
------ Component BIBUF_F_8U ------
2724 
 component BIBUF_F_8U
2725 
--pragma translate_off
2726 
    generic(
2727 
                TimingChecksOn:Boolean := True;
2728 
                Xon: Boolean := False;
2729 
                InstancePath: STRING :="*";
2730 
                MsgOn: Boolean := True;
2731 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2732 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2733 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2734 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2735 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2736 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2737 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2738 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2739 
 
2740 
 
2741 
--pragma translate_on
2742 
    port(
2743 
                D               : in    STD_ULOGIC;
2744 
                E               : in    STD_ULOGIC;
2745 
                PAD             : inout STD_ULOGIC;
2746 
                Y               : out    STD_ULOGIC);
2747 
 end component;
2748 
 
2749 
 
2750 
------ Component BIBUF_F_12 ------
2751 
 component BIBUF_F_12
2752 
--pragma translate_off
2753 
    generic(
2754 
                TimingChecksOn:Boolean := True;
2755 
                Xon: Boolean := False;
2756 
                InstancePath: STRING :="*";
2757 
                MsgOn: Boolean := True;
2758 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2759 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2760 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2761 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2762 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2763 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2764 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2765 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2766 
 
2767 
 
2768 
--pragma translate_on
2769 
    port(
2770 
                D               : in    STD_ULOGIC;
2771 
                E               : in    STD_ULOGIC;
2772 
                PAD             : inout STD_ULOGIC;
2773 
                Y               : out    STD_ULOGIC);
2774 
 end component;
2775 
 
2776 
 
2777 
------ Component BIBUF_F_12D ------
2778 
 component BIBUF_F_12D
2779 
--pragma translate_off
2780 
    generic(
2781 
                TimingChecksOn:Boolean := True;
2782 
                Xon: Boolean := False;
2783 
                InstancePath: STRING :="*";
2784 
                MsgOn: Boolean := True;
2785 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2786 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2787 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2788 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2789 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2790 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2791 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2792 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2793 
 
2794 
 
2795 
--pragma translate_on
2796 
    port(
2797 
                D               : in    STD_ULOGIC;
2798 
                E               : in    STD_ULOGIC;
2799 
                PAD             : inout STD_ULOGIC;
2800 
                Y               : out    STD_ULOGIC);
2801 
 end component;
2802 
 
2803 
 
2804 
------ Component BIBUF_F_12U ------
2805 
 component BIBUF_F_12U
2806 
--pragma translate_off
2807 
    generic(
2808 
                TimingChecksOn:Boolean := True;
2809 
                Xon: Boolean := False;
2810 
                InstancePath: STRING :="*";
2811 
                MsgOn: Boolean := True;
2812 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2813 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2814 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2815 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2816 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2817 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2818 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2819 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2820 
 
2821 
 
2822 
--pragma translate_on
2823 
    port(
2824 
                D               : in    STD_ULOGIC;
2825 
                E               : in    STD_ULOGIC;
2826 
                PAD             : inout STD_ULOGIC;
2827 
                Y               : out    STD_ULOGIC);
2828 
 end component;
2829 
 
2830 
 
2831 
------ Component BIBUF_F_16 ------
2832 
 component BIBUF_F_16
2833 
--pragma translate_off
2834 
    generic(
2835 
                TimingChecksOn:Boolean := True;
2836 
                Xon: Boolean := False;
2837 
                InstancePath: STRING :="*";
2838 
                MsgOn: Boolean := True;
2839 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2840 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2841 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2842 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2843 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2844 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2845 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2846 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2847 
 
2848 
 
2849 
--pragma translate_on
2850 
    port(
2851 
                D               : in    STD_ULOGIC;
2852 
                E               : in    STD_ULOGIC;
2853 
                PAD             : inout STD_ULOGIC;
2854 
                Y               : out    STD_ULOGIC);
2855 
 end component;
2856 
 
2857 
 
2858 
------ Component BIBUF_F_16D ------
2859 
 component BIBUF_F_16D
2860 
--pragma translate_off
2861 
    generic(
2862 
                TimingChecksOn:Boolean := True;
2863 
                Xon: Boolean := False;
2864 
                InstancePath: STRING :="*";
2865 
                MsgOn: Boolean := True;
2866 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2867 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2868 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2869 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2870 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2871 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2872 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2873 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2874 
 
2875 
 
2876 
--pragma translate_on
2877 
    port(
2878 
                D               : in    STD_ULOGIC;
2879 
                E               : in    STD_ULOGIC;
2880 
                PAD             : inout STD_ULOGIC;
2881 
                Y               : out    STD_ULOGIC);
2882 
 end component;
2883 
 
2884 
 
2885 
------ Component BIBUF_F_16U ------
2886 
 component BIBUF_F_16U
2887 
--pragma translate_off
2888 
    generic(
2889 
                TimingChecksOn:Boolean := True;
2890 
                Xon: Boolean := False;
2891 
                InstancePath: STRING :="*";
2892 
                MsgOn: Boolean := True;
2893 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2894 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2895 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2896 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2897 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2898 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2899 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2900 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2901 
 
2902 
 
2903 
--pragma translate_on
2904 
    port(
2905 
                D               : in    STD_ULOGIC;
2906 
                E               : in    STD_ULOGIC;
2907 
                PAD             : inout STD_ULOGIC;
2908 
                Y               : out    STD_ULOGIC);
2909 
 end component;
2910 
 
2911 
 
2912 
------ Component BIBUF_F_24 ------
2913 
 component BIBUF_F_24
2914 
--pragma translate_off
2915 
    generic(
2916 
                TimingChecksOn:Boolean := True;
2917 
                Xon: Boolean := False;
2918 
                InstancePath: STRING :="*";
2919 
                MsgOn: Boolean := True;
2920 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2921 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2922 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2923 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2924 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2925 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2926 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2927 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2928 
 
2929 
 
2930 
--pragma translate_on
2931 
    port(
2932 
                D               : in    STD_ULOGIC;
2933 
                E               : in    STD_ULOGIC;
2934 
                PAD             : inout STD_ULOGIC;
2935 
                Y               : out    STD_ULOGIC);
2936 
 end component;
2937 
 
2938 
 
2939 
------ Component BIBUF_F_24D ------
2940 
 component BIBUF_F_24D
2941 
--pragma translate_off
2942 
    generic(
2943 
                TimingChecksOn:Boolean := True;
2944 
                Xon: Boolean := False;
2945 
                InstancePath: STRING :="*";
2946 
                MsgOn: Boolean := True;
2947 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2948 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2949 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2950 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2951 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2952 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2953 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2954 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2955 
 
2956 
 
2957 
--pragma translate_on
2958 
    port(
2959 
                D               : in    STD_ULOGIC;
2960 
                E               : in    STD_ULOGIC;
2961 
                PAD             : inout STD_ULOGIC;
2962 
                Y               : out    STD_ULOGIC);
2963 
 end component;
2964 
 
2965 
 
2966 
------ Component BIBUF_F_24U ------
2967 
 component BIBUF_F_24U
2968 
--pragma translate_off
2969 
    generic(
2970 
                TimingChecksOn:Boolean := True;
2971 
                Xon: Boolean := False;
2972 
                InstancePath: STRING :="*";
2973 
                MsgOn: Boolean := True;
2974 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2975 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
2976 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
2977 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2978 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
2979 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2980 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
2981 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
2982 
 
2983 
 
2984 
--pragma translate_on
2985 
    port(
2986 
                D               : in    STD_ULOGIC;
2987 
                E               : in    STD_ULOGIC;
2988 
                PAD             : inout STD_ULOGIC;
2989 
                Y               : out    STD_ULOGIC);
2990 
 end component;
2991 
 
2992 
 
2993 
------ Component BIBUF_LVCMOS25 ------
2994 
 component BIBUF_LVCMOS25
2995 
--pragma translate_off
2996 
    generic(
2997 
                TimingChecksOn:Boolean := True;
2998 
                Xon: Boolean := False;
2999 
                InstancePath: STRING :="*";
3000 
                MsgOn: Boolean := True;
3001 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3002 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3003 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3004 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3005 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3006 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3007 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3008 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3009 
 
3010 
 
3011 
--pragma translate_on
3012 
    port(
3013 
                D               : in    STD_ULOGIC;
3014 
                E               : in    STD_ULOGIC;
3015 
                PAD             : inout STD_ULOGIC;
3016 
                Y               : out    STD_ULOGIC);
3017 
 end component;
3018 
 
3019 
 
3020 
------ Component BIBUF_LVCMOS25D ------
3021 
 component BIBUF_LVCMOS25D
3022 
--pragma translate_off
3023 
    generic(
3024 
                TimingChecksOn:Boolean := True;
3025 
                Xon: Boolean := False;
3026 
                InstancePath: STRING :="*";
3027 
                MsgOn: Boolean := True;
3028 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3029 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3030 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3031 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3032 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3033 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3034 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3035 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3036 
 
3037 
 
3038 
--pragma translate_on
3039 
    port(
3040 
                D               : in    STD_ULOGIC;
3041 
                E               : in    STD_ULOGIC;
3042 
                PAD             : inout STD_ULOGIC;
3043 
                Y               : out    STD_ULOGIC);
3044 
 end component;
3045 
 
3046 
 
3047 
------ Component BIBUF_LVCMOS25U ------
3048 
 component BIBUF_LVCMOS25U
3049 
--pragma translate_off
3050 
    generic(
3051 
                TimingChecksOn:Boolean := True;
3052 
                Xon: Boolean := False;
3053 
                InstancePath: STRING :="*";
3054 
                MsgOn: Boolean := True;
3055 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3056 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3057 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3058 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3059 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3060 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3061 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3062 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3063 
 
3064 
 
3065 
--pragma translate_on
3066 
    port(
3067 
                D               : in    STD_ULOGIC;
3068 
                E               : in    STD_ULOGIC;
3069 
                PAD             : inout STD_ULOGIC;
3070 
                Y               : out    STD_ULOGIC);
3071 
 end component;
3072 
 
3073 
 
3074 
------ Component BIBUF_LVCMOS18 ------
3075 
 component BIBUF_LVCMOS18
3076 
--pragma translate_off
3077 
    generic(
3078 
                TimingChecksOn:Boolean := True;
3079 
                Xon: Boolean := False;
3080 
                InstancePath: STRING :="*";
3081 
                MsgOn: Boolean := True;
3082 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3083 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3084 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3085 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3086 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3087 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3088 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3089 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3090 
 
3091 
 
3092 
--pragma translate_on
3093 
    port(
3094 
                D               : in    STD_ULOGIC;
3095 
                E               : in    STD_ULOGIC;
3096 
                PAD             : inout STD_ULOGIC;
3097 
                Y               : out    STD_ULOGIC);
3098 
 end component;
3099 
 
3100 
 
3101 
------ Component BIBUF_LVCMOS18D ------
3102 
 component BIBUF_LVCMOS18D
3103 
--pragma translate_off
3104 
    generic(
3105 
                TimingChecksOn:Boolean := True;
3106 
                Xon: Boolean := False;
3107 
                InstancePath: STRING :="*";
3108 
                MsgOn: Boolean := True;
3109 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3110 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3111 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3112 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3113 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3114 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3115 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3116 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3117 
 
3118 
 
3119 
--pragma translate_on
3120 
    port(
3121 
                D               : in    STD_ULOGIC;
3122 
                E               : in    STD_ULOGIC;
3123 
                PAD             : inout STD_ULOGIC;
3124 
                Y               : out    STD_ULOGIC);
3125 
 end component;
3126 
 
3127 
 
3128 
------ Component BIBUF_LVCMOS18U ------
3129 
 component BIBUF_LVCMOS18U
3130 
--pragma translate_off
3131 
    generic(
3132 
                TimingChecksOn:Boolean := True;
3133 
                Xon: Boolean := False;
3134 
                InstancePath: STRING :="*";
3135 
                MsgOn: Boolean := True;
3136 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3137 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3138 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3139 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3140 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3141 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3142 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3143 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3144 
 
3145 
 
3146 
--pragma translate_on
3147 
    port(
3148 
                D               : in    STD_ULOGIC;
3149 
                E               : in    STD_ULOGIC;
3150 
                PAD             : inout STD_ULOGIC;
3151 
                Y               : out    STD_ULOGIC);
3152 
 end component;
3153 
 
3154 
 
3155 
------ Component BIBUF_LVCMOS15 ------
3156 
 component BIBUF_LVCMOS15
3157 
--pragma translate_off
3158 
    generic(
3159 
                TimingChecksOn:Boolean := True;
3160 
                Xon: Boolean := False;
3161 
                InstancePath: STRING :="*";
3162 
                MsgOn: Boolean := True;
3163 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3164 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3165 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3166 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3167 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3168 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3169 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3170 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3171 
 
3172 
 
3173 
--pragma translate_on
3174 
    port(
3175 
                D               : in    STD_ULOGIC;
3176 
                E               : in    STD_ULOGIC;
3177 
                PAD             : inout STD_ULOGIC;
3178 
                Y               : out    STD_ULOGIC);
3179 
 end component;
3180 
 
3181 
 
3182 
------ Component BIBUF_LVCMOS15D ------
3183 
 component BIBUF_LVCMOS15D
3184 
--pragma translate_off
3185 
    generic(
3186 
                TimingChecksOn:Boolean := True;
3187 
                Xon: Boolean := False;
3188 
                InstancePath: STRING :="*";
3189 
                MsgOn: Boolean := True;
3190 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3191 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3192 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3193 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3194 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3195 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3196 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3197 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3198 
 
3199 
 
3200 
--pragma translate_on
3201 
    port(
3202 
                D               : in    STD_ULOGIC;
3203 
                E               : in    STD_ULOGIC;
3204 
                PAD             : inout STD_ULOGIC;
3205 
                Y               : out    STD_ULOGIC);
3206 
 end component;
3207 
 
3208 
 
3209 
------ Component BIBUF_LVCMOS15U ------
3210 
 component BIBUF_LVCMOS15U
3211 
--pragma translate_off
3212 
    generic(
3213 
                TimingChecksOn:Boolean := True;
3214 
                Xon: Boolean := False;
3215 
                InstancePath: STRING :="*";
3216 
                MsgOn: Boolean := True;
3217 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3218 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3219 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3220 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3221 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3222 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3223 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3224 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3225 
 
3226 
 
3227 
--pragma translate_on
3228 
    port(
3229 
                D               : in    STD_ULOGIC;
3230 
                E               : in    STD_ULOGIC;
3231 
                PAD             : inout STD_ULOGIC;
3232 
                Y               : out    STD_ULOGIC);
3233 
 end component;
3234 
 
3235 
 
3236 
------ Component BIBUF_PCI ------
3237 
 component BIBUF_PCI
3238 
--pragma translate_off
3239 
    generic(
3240 
                TimingChecksOn:Boolean := True;
3241 
                Xon: Boolean := False;
3242 
                InstancePath: STRING :="*";
3243 
                MsgOn: Boolean := True;
3244 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3245 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3246 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3247 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3248 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3249 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3250 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3251 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3252 
 
3253 
 
3254 
--pragma translate_on
3255 
    port(
3256 
                D               : in    STD_ULOGIC;
3257 
                E               : in    STD_ULOGIC;
3258 
                PAD             : inout STD_ULOGIC;
3259 
                Y               : out    STD_ULOGIC);
3260 
 end component;
3261 
 
3262 
 
3263 
------ Component BIBUF_PCIX ------
3264 
 component BIBUF_PCIX
3265 
--pragma translate_off
3266 
    generic(
3267 
                TimingChecksOn:Boolean := True;
3268 
                Xon: Boolean := False;
3269 
                InstancePath: STRING :="*";
3270 
                MsgOn: Boolean := True;
3271 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3272 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3273 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3274 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3275 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3276 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3277 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3278 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3279 
 
3280 
 
3281 
--pragma translate_on
3282 
    port(
3283 
                D               : in    STD_ULOGIC;
3284 
                E               : in    STD_ULOGIC;
3285 
                PAD             : inout STD_ULOGIC;
3286 
                Y               : out    STD_ULOGIC);
3287 
 end component;
3288 
 
3289 
 
3290 
------ Component BIBUF_GTLP33 ------
3291 
 component BIBUF_GTLP33
3292 
--pragma translate_off
3293 
    generic(
3294 
                TimingChecksOn:Boolean := True;
3295 
                Xon: Boolean := False;
3296 
                InstancePath: STRING :="*";
3297 
                MsgOn: Boolean := True;
3298 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3299 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3300 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3301 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3302 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3303 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3304 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3305 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3306 
 
3307 
 
3308 
--pragma translate_on
3309 
    port(
3310 
                D               : in    STD_ULOGIC;
3311 
                E               : in    STD_ULOGIC;
3312 
                PAD             : inout STD_ULOGIC;
3313 
                Y               : out    STD_ULOGIC);
3314 
 end component;
3315 
 
3316 
 
3317 
------ Component BIBUF_GTLP25 ------
3318 
 component BIBUF_GTLP25
3319 
--pragma translate_off
3320 
    generic(
3321 
                TimingChecksOn:Boolean := True;
3322 
                Xon: Boolean := False;
3323 
                InstancePath: STRING :="*";
3324 
                MsgOn: Boolean := True;
3325 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3326 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3327 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3328 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3329 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3330 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3331 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
3332 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3333 
 
3334 
 
3335 
--pragma translate_on
3336 
    port(
3337 
                D               : in    STD_ULOGIC;
3338 
                E               : in    STD_ULOGIC;
3339 
                PAD             : inout STD_ULOGIC;
3340 
                Y               : out    STD_ULOGIC);
3341 
 end component;
3342 
 
3343 
 
3344 
------ Component BUFA ------
3345 
 component BUFA
3346 
--pragma translate_off
3347 
    generic(
3348 
                TimingChecksOn:Boolean := True;
3349 
                Xon: Boolean := False;
3350 
                InstancePath: STRING :="*";
3351 
                MsgOn: Boolean := True;
3352 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
3353 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
3354 
 
3355 
 
3356 
--pragma translate_on
3357 
    port(
3358 
                A               : in    STD_ULOGIC;
3359 
                Y               : out    STD_ULOGIC);
3360 
 end component;
3361 
 
3362 
 
3363 
------ Component BUFD ------
3364 
 component BUFD
3365 
--pragma translate_off
3366 
    generic(
3367 
                TimingChecksOn:Boolean := True;
3368 
                Xon: Boolean := False;
3369 
                InstancePath: STRING :="*";
3370 
                MsgOn: Boolean := True;
3371 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
3372 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
3373 
 
3374 
 
3375 
--pragma translate_on
3376 
    port(
3377 
                A               : in    STD_ULOGIC;
3378 
                Y               : out    STD_ULOGIC);
3379 
 end component;
3380 
 
3381 
 
3382 
------ Component CLKBIBUF ------
3383 
 component CLKBIBUF
3384 
--pragma translate_off
3385 
    generic(
3386 
                TimingChecksOn:Boolean := True;
3387 
                Xon: Boolean := False;
3388 
                InstancePath: STRING :="*";
3389 
                MsgOn: Boolean := True;
3390 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3391 
               tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
3392 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3393 
                tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3394 
                tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
3395 
                tipd_D                  : VitalDelayType01 := (0.000 ns, 0.000 ns);
3396 
                tipd_E                  : VitalDelayType01 := (0.000 ns, 0.000 ns);
3397 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3398 
 
3399 
 
3400 
--pragma translate_on
3401 
    port(
3402 
                PAD             : inout  STD_ULOGIC;
3403 
                D               : in     STD_ULOGIC;
3404 
                E               : in     STD_ULOGIC;
3405 
                Y               : out    STD_ULOGIC);
3406 
 end component;
3407 
 
3408 
 
3409 
------ Component CLKBUF ------
3410 
 component CLKBUF
3411 
--pragma translate_off
3412 
    generic(
3413 
                TimingChecksOn:Boolean := True;
3414 
                Xon: Boolean := False;
3415 
                InstancePath: STRING :="*";
3416 
                MsgOn: Boolean := True;
3417 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3418 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3419 
 
3420 
 
3421 
--pragma translate_on
3422 
    port(
3423 
                PAD             : in    STD_ULOGIC;
3424 
                Y               : out    STD_ULOGIC);
3425 
 end component;
3426 
 
3427 
 
3428 
------ Component CLKBUF_LVCMOS25 ------
3429 
 component CLKBUF_LVCMOS25
3430 
--pragma translate_off
3431 
    generic(
3432 
                TimingChecksOn:Boolean := True;
3433 
                Xon: Boolean := False;
3434 
                InstancePath: STRING :="*";
3435 
                MsgOn: Boolean := True;
3436 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3437 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3438 
 
3439 
 
3440 
--pragma translate_on
3441 
    port(
3442 
                PAD             : in    STD_ULOGIC;
3443 
                Y               : out    STD_ULOGIC);
3444 
 end component;
3445 
 
3446 
 
3447 
------ Component CLKBUF_LVCMOS18 ------
3448 
 component CLKBUF_LVCMOS18
3449 
--pragma translate_off
3450 
    generic(
3451 
                TimingChecksOn:Boolean := True;
3452 
                Xon: Boolean := False;
3453 
                InstancePath: STRING :="*";
3454 
                MsgOn: Boolean := True;
3455 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3456 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3457 
 
3458 
 
3459 
--pragma translate_on
3460 
    port(
3461 
                PAD             : in    STD_ULOGIC;
3462 
                Y               : out    STD_ULOGIC);
3463 
 end component;
3464 
 
3465 
 
3466 
------ Component CLKBUF_LVCMOS15 ------
3467 
 component CLKBUF_LVCMOS15
3468 
--pragma translate_off
3469 
    generic(
3470 
                TimingChecksOn:Boolean := True;
3471 
                Xon: Boolean := False;
3472 
                InstancePath: STRING :="*";
3473 
                MsgOn: Boolean := True;
3474 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3475 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3476 
 
3477 
 
3478 
--pragma translate_on
3479 
    port(
3480 
                PAD             : in    STD_ULOGIC;
3481 
                Y               : out    STD_ULOGIC);
3482 
 end component;
3483 
 
3484 
 
3485 
------ Component CLKBUF_PCI ------
3486 
 component CLKBUF_PCI
3487 
--pragma translate_off
3488 
    generic(
3489 
                TimingChecksOn:Boolean := True;
3490 
                Xon: Boolean := False;
3491 
                InstancePath: STRING :="*";
3492 
                MsgOn: Boolean := True;
3493 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3494 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3495 
 
3496 
 
3497 
--pragma translate_on
3498 
    port(
3499 
                PAD             : in    STD_ULOGIC;
3500 
                Y               : out    STD_ULOGIC);
3501 
 end component;
3502 
 
3503 
 
3504 
------ Component CLKBUF_PCIX ------
3505 
 component CLKBUF_PCIX
3506 
--pragma translate_off
3507 
    generic(
3508 
                TimingChecksOn:Boolean := True;
3509 
                Xon: Boolean := False;
3510 
                InstancePath: STRING :="*";
3511 
                MsgOn: Boolean := True;
3512 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3513 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3514 
 
3515 
 
3516 
--pragma translate_on
3517 
    port(
3518 
                PAD             : in    STD_ULOGIC;
3519 
                Y               : out    STD_ULOGIC);
3520 
 end component;
3521 
 
3522 
 
3523 
------ Component CLKBUF_GTLP33 ------
3524 
 component CLKBUF_GTLP33
3525 
--pragma translate_off
3526 
    generic(
3527 
                TimingChecksOn:Boolean := True;
3528 
                Xon: Boolean := False;
3529 
                InstancePath: STRING :="*";
3530 
                MsgOn: Boolean := True;
3531 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3532 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3533 
 
3534 
 
3535 
--pragma translate_on
3536 
    port(
3537 
                PAD             : in    STD_ULOGIC;
3538 
                Y               : out    STD_ULOGIC);
3539 
 end component;
3540 
 
3541 
 
3542 
------ Component CLKBUF_GTLP25 ------
3543 
 component CLKBUF_GTLP25
3544 
--pragma translate_off
3545 
    generic(
3546 
                TimingChecksOn:Boolean := True;
3547 
                Xon: Boolean := False;
3548 
                InstancePath: STRING :="*";
3549 
                MsgOn: Boolean := True;
3550 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3551 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3552 
 
3553 
 
3554 
--pragma translate_on
3555 
    port(
3556 
                PAD             : in    STD_ULOGIC;
3557 
                Y               : out    STD_ULOGIC);
3558 
 end component;
3559 
 
3560 
 
3561 
------ Component CLKBUF_HSTL_I ------
3562 
 component CLKBUF_HSTL_I
3563 
--pragma translate_off
3564 
    generic(
3565 
                TimingChecksOn:Boolean := True;
3566 
                Xon: Boolean := False;
3567 
                InstancePath: STRING :="*";
3568 
                MsgOn: Boolean := True;
3569 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3570 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3571 
 
3572 
 
3573 
--pragma translate_on
3574 
    port(
3575 
                PAD             : in    STD_ULOGIC;
3576 
                Y               : out    STD_ULOGIC);
3577 
 end component;
3578 
 
3579 
 
3580 
------ Component CLKBUF_SSTL3_I ------
3581 
 component CLKBUF_SSTL3_I
3582 
--pragma translate_off
3583 
    generic(
3584 
                TimingChecksOn:Boolean := True;
3585 
                Xon: Boolean := False;
3586 
                InstancePath: STRING :="*";
3587 
                MsgOn: Boolean := True;
3588 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3589 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3590 
 
3591 
 
3592 
--pragma translate_on
3593 
    port(
3594 
                PAD             : in    STD_ULOGIC;
3595 
                Y               : out    STD_ULOGIC);
3596 
 end component;
3597 
 
3598 
 
3599 
------ Component CLKBUF_SSTL3_II ------
3600 
 component CLKBUF_SSTL3_II
3601 
--pragma translate_off
3602 
    generic(
3603 
                TimingChecksOn:Boolean := True;
3604 
                Xon: Boolean := False;
3605 
                InstancePath: STRING :="*";
3606 
                MsgOn: Boolean := True;
3607 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3608 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3609 
 
3610 
 
3611 
--pragma translate_on
3612 
    port(
3613 
                PAD             : in    STD_ULOGIC;
3614 
                Y               : out    STD_ULOGIC);
3615 
 end component;
3616 
 
3617 
 
3618 
------ Component CLKBUF_SSTL2_I ------
3619 
 component CLKBUF_SSTL2_I
3620 
--pragma translate_off
3621 
    generic(
3622 
                TimingChecksOn:Boolean := True;
3623 
                Xon: Boolean := False;
3624 
                InstancePath: STRING :="*";
3625 
                MsgOn: Boolean := True;
3626 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3627 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3628 
 
3629 
 
3630 
--pragma translate_on
3631 
    port(
3632 
                PAD             : in    STD_ULOGIC;
3633 
                Y               : out    STD_ULOGIC);
3634 
 end component;
3635 
 
3636 
 
3637 
------ Component CLKBUF_SSTL2_II ------
3638 
 component CLKBUF_SSTL2_II
3639 
--pragma translate_off
3640 
    generic(
3641 
                TimingChecksOn:Boolean := True;
3642 
                Xon: Boolean := False;
3643 
                InstancePath: STRING :="*";
3644 
                MsgOn: Boolean := True;
3645 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3646 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3647 
 
3648 
 
3649 
--pragma translate_on
3650 
    port(
3651 
                PAD             : in    STD_ULOGIC;
3652 
                Y               : out    STD_ULOGIC);
3653 
 end component;
3654 
 
3655 
 
3656 
------ Component CM7 ------
3657 
 component CM7
3658 
--pragma translate_off
3659 
    generic(
3660 
                TimingChecksOn:Boolean := True;
3661 
                Xon: Boolean := False;
3662 
                InstancePath: STRING :="*";
3663 
                MsgOn: Boolean := True;
3664 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3665 
                tpd_S0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3666 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3667 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3668 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3669 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3670 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3671 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3672 
                tipd_S0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3673 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3674 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3675 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3676 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3677 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
3678 
 
3679 
 
3680 
--pragma translate_on
3681 
    port(
3682 
                D0              : in    STD_ULOGIC;
3683 
                S0              : in    STD_ULOGIC;
3684 
                D1              : in    STD_ULOGIC;
3685 
                S10             : in    STD_ULOGIC;
3686 
                S11             : in    STD_ULOGIC;
3687 
                D2              : in    STD_ULOGIC;
3688 
                D3              : in    STD_ULOGIC;
3689 
                Y               : out    STD_ULOGIC);
3690 
 end component;
3691 
 
3692 
 
3693 
------ Component CM8 ------
3694 
 component CM8
3695 
--pragma translate_off
3696 
    generic(
3697 
                TimingChecksOn:Boolean := True;
3698 
                Xon: Boolean := False;
3699 
                InstancePath: STRING :="*";
3700 
                MsgOn: Boolean := True;
3701 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3702 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3703 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3704 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3705 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3706 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3707 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3708 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3709 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3710 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3711 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3712 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3713 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3714 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3715 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3716 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
3717 
 
3718 
 
3719 
--pragma translate_on
3720 
    port(
3721 
                D0              : in    STD_ULOGIC;
3722 
                S00             : in    STD_ULOGIC;
3723 
                S01             : in    STD_ULOGIC;
3724 
                D1              : in    STD_ULOGIC;
3725 
                S10             : in    STD_ULOGIC;
3726 
                S11             : in    STD_ULOGIC;
3727 
                D2              : in    STD_ULOGIC;
3728 
                D3              : in    STD_ULOGIC;
3729 
                Y               : out    STD_ULOGIC);
3730 
 end component;
3731 
 
3732 
 
3733 
------ Component CM8BUFF ------
3734 
 component CM8BUFF
3735 
--pragma translate_off
3736 
    generic(
3737 
                TimingChecksOn:Boolean := True;
3738 
                Xon: Boolean := False;
3739 
                InstancePath: STRING :="*";
3740 
                MsgOn: Boolean := True;
3741 
                tpw_A_posedge   : VitalDelayType := 0.000 ns;
3742 
                tpw_A_negedge   : VitalDelayType := 0.000 ns;
3743 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
3744 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
3745 
 
3746 
 
3747 
--pragma translate_on
3748 
    port(
3749 
                A               : in    STD_ULOGIC;
3750 
                Y               : out    STD_ULOGIC);
3751 
 end component;
3752 
 
3753 
 
3754 
------ Component CM8INV ------
3755 
 component CM8INV
3756 
--pragma translate_off
3757 
    generic(
3758 
                TimingChecksOn:Boolean := True;
3759 
                Xon: Boolean := False;
3760 
                InstancePath: STRING :="*";
3761 
                MsgOn: Boolean := True;
3762 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
3763 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
3764 
 
3765 
 
3766 
--pragma translate_on
3767 
    port(
3768 
                A               : in    STD_ULOGIC;
3769 
                Y               : out    STD_ULOGIC);
3770 
 end component;
3771 
 
3772 
 
3773 
------ Component CMA9 ------
3774 
 component CMA9
3775 
--pragma translate_off
3776 
    generic(
3777 
                TimingChecksOn:Boolean := True;
3778 
                Xon: Boolean := False;
3779 
                InstancePath: STRING :="*";
3780 
                MsgOn: Boolean := True;
3781 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3782 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3783 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3784 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3785 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3786 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3787 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3788 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3789 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3790 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
3791 
 
3792 
 
3793 
--pragma translate_on
3794 
    port(
3795 
                D0              : in    STD_ULOGIC;
3796 
                DB              : in    STD_ULOGIC;
3797 
                S01             : in    STD_ULOGIC;
3798 
                S11             : in    STD_ULOGIC;
3799 
                D3              : in    STD_ULOGIC;
3800 
                Y               : out    STD_ULOGIC);
3801 
 end component;
3802 
 
3803 
 
3804 
------ Component CMAF ------
3805 
 component CMAF
3806 
--pragma translate_off
3807 
    generic(
3808 
                TimingChecksOn:Boolean := True;
3809 
                Xon: Boolean := False;
3810 
                InstancePath: STRING :="*";
3811 
                MsgOn: Boolean := True;
3812 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3813 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3814 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3815 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3816 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3817 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3818 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3819 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3820 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3821 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3822 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3823 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
3824 
 
3825 
 
3826 
--pragma translate_on
3827 
    port(
3828 
                D0              : in    STD_ULOGIC;
3829 
                DB              : in    STD_ULOGIC;
3830 
                S11             : in    STD_ULOGIC;
3831 
                D2              : in    STD_ULOGIC;
3832 
                S01             : in    STD_ULOGIC;
3833 
                D3              : in    STD_ULOGIC;
3834 
                Y               : out    STD_ULOGIC);
3835 
 end component;
3836 
 
3837 
 
3838 
------ Component CMB3 ------
3839 
 component CMB3
3840 
--pragma translate_off
3841 
    generic(
3842 
                TimingChecksOn:Boolean := True;
3843 
                Xon: Boolean := False;
3844 
                InstancePath: STRING :="*";
3845 
                MsgOn: Boolean := True;
3846 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3847 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3848 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3849 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3850 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3851 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3852 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3853 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3854 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3855 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3856 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3857 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns));
3858 
 
3859 
 
3860 
--pragma translate_on
3861 
    port(
3862 
                D0              : in    STD_ULOGIC;
3863 
                S00             : in    STD_ULOGIC;
3864 
                S01             : in    STD_ULOGIC;
3865 
                D1              : in    STD_ULOGIC;
3866 
                DB              : in    STD_ULOGIC;
3867 
                S11             : in    STD_ULOGIC;
3868 
                Y               : out    STD_ULOGIC);
3869 
 end component;
3870 
 
3871 
 
3872 
------ Component CMB7 ------
3873 
 component CMB7
3874 
--pragma translate_off
3875 
    generic(
3876 
                TimingChecksOn:Boolean := True;
3877 
                Xon: Boolean := False;
3878 
                InstancePath: STRING :="*";
3879 
                MsgOn: Boolean := True;
3880 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3881 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3882 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3883 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3884 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3885 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3886 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3887 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3888 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3889 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3890 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3891 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3892 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3893 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns));
3894 
 
3895 
 
3896 
--pragma translate_on
3897 
    port(
3898 
                D0              : in    STD_ULOGIC;
3899 
                S00             : in    STD_ULOGIC;
3900 
                S01             : in    STD_ULOGIC;
3901 
                D1              : in    STD_ULOGIC;
3902 
                DB              : in    STD_ULOGIC;
3903 
                S11             : in    STD_ULOGIC;
3904 
                D2              : in    STD_ULOGIC;
3905 
                Y               : out    STD_ULOGIC);
3906 
 end component;
3907 
 
3908 
 
3909 
------ Component CMBB ------
3910 
 component CMBB
3911 
--pragma translate_off
3912 
    generic(
3913 
                TimingChecksOn:Boolean := True;
3914 
                Xon: Boolean := False;
3915 
                InstancePath: STRING :="*";
3916 
                MsgOn: Boolean := True;
3917 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3918 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3919 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3920 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3921 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3922 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3923 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3924 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3925 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3926 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3927 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3928 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3929 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3930 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
3931 
 
3932 
 
3933 
--pragma translate_on
3934 
    port(
3935 
                D0              : in    STD_ULOGIC;
3936 
                S00             : in    STD_ULOGIC;
3937 
                S01             : in    STD_ULOGIC;
3938 
                D1              : in    STD_ULOGIC;
3939 
                DB              : in    STD_ULOGIC;
3940 
                S11             : in    STD_ULOGIC;
3941 
                D3              : in    STD_ULOGIC;
3942 
                Y               : out    STD_ULOGIC);
3943 
 end component;
3944 
 
3945 
 
3946 
------ Component CMBF ------
3947 
 component CMBF
3948 
--pragma translate_off
3949 
    generic(
3950 
                TimingChecksOn:Boolean := True;
3951 
                Xon: Boolean := False;
3952 
                InstancePath: STRING :="*";
3953 
                MsgOn: Boolean := True;
3954 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3955 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3956 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3957 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3958 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3959 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3960 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3961 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3962 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3963 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3964 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3965 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3966 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3967 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
3968 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
3969 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
3970 
 
3971 
 
3972 
--pragma translate_on
3973 
    port(
3974 
                D0              : in    STD_ULOGIC;
3975 
                S00             : in    STD_ULOGIC;
3976 
                S01             : in    STD_ULOGIC;
3977 
                D1              : in    STD_ULOGIC;
3978 
                DB              : in    STD_ULOGIC;
3979 
                S11             : in    STD_ULOGIC;
3980 
                D2              : in    STD_ULOGIC;
3981 
                D3              : in    STD_ULOGIC;
3982 
                Y               : out    STD_ULOGIC);
3983 
 end component;
3984 
 
3985 
 
3986 
------ Component CMEA ------
3987 
 component CMEA
3988 
--pragma translate_off
3989 
    generic(
3990 
                TimingChecksOn:Boolean := True;
3991 
                Xon: Boolean := False;
3992 
                InstancePath: STRING :="*";
3993 
                MsgOn: Boolean := True;
3994 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3995 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3996 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
3997 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3998 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
3999 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4000 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4001 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4002 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4003 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4004 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4005 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4006 
 
4007 
 
4008 
--pragma translate_on
4009 
    port(
4010 
                DB              : in    STD_ULOGIC;
4011 
                S01             : in    STD_ULOGIC;
4012 
                D1              : in    STD_ULOGIC;
4013 
                S10             : in    STD_ULOGIC;
4014 
                S11             : in    STD_ULOGIC;
4015 
                D3              : in    STD_ULOGIC;
4016 
                Y               : out    STD_ULOGIC);
4017 
 end component;
4018 
 
4019 
 
4020 
------ Component CMEB ------
4021 
 component CMEB
4022 
--pragma translate_off
4023 
    generic(
4024 
                TimingChecksOn:Boolean := True;
4025 
                Xon: Boolean := False;
4026 
                InstancePath: STRING :="*";
4027 
                MsgOn: Boolean := True;
4028 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4029 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4030 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4031 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4032 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4033 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4034 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4035 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4036 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4037 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4038 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4039 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4040 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4041 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4042 
 
4043 
 
4044 
--pragma translate_on
4045 
    port(
4046 
                D0              : in    STD_ULOGIC;
4047 
                DB              : in    STD_ULOGIC;
4048 
                S01             : in    STD_ULOGIC;
4049 
                D1              : in    STD_ULOGIC;
4050 
                S10             : in    STD_ULOGIC;
4051 
                S11             : in    STD_ULOGIC;
4052 
                D3              : in    STD_ULOGIC;
4053 
                Y               : out    STD_ULOGIC);
4054 
 end component;
4055 
 
4056 
 
4057 
------ Component CMEE ------
4058 
 component CMEE
4059 
--pragma translate_off
4060 
    generic(
4061 
                TimingChecksOn:Boolean := True;
4062 
                Xon: Boolean := False;
4063 
                InstancePath: STRING :="*";
4064 
                MsgOn: Boolean := True;
4065 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4066 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4067 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4068 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4069 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4070 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4071 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4072 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4073 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4074 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4075 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4076 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4077 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4078 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4079 
 
4080 
 
4081 
--pragma translate_on
4082 
    port(
4083 
                DB              : in    STD_ULOGIC;
4084 
                S01             : in    STD_ULOGIC;
4085 
                D1              : in    STD_ULOGIC;
4086 
                S10             : in    STD_ULOGIC;
4087 
                S11             : in    STD_ULOGIC;
4088 
                D2              : in    STD_ULOGIC;
4089 
                D3              : in    STD_ULOGIC;
4090 
                Y               : out    STD_ULOGIC);
4091 
 end component;
4092 
 
4093 
 
4094 
------ Component CMEF ------
4095 
 component CMEF
4096 
--pragma translate_off
4097 
    generic(
4098 
                TimingChecksOn:Boolean := True;
4099 
                Xon: Boolean := False;
4100 
                InstancePath: STRING :="*";
4101 
                MsgOn: Boolean := True;
4102 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4103 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4104 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4105 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4106 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4107 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4108 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4109 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4110 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4111 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4112 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4113 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4114 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4115 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4116 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4117 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4118 
 
4119 
 
4120 
--pragma translate_on
4121 
    port(
4122 
                D0              : in    STD_ULOGIC;
4123 
                DB              : in    STD_ULOGIC;
4124 
                S01             : in    STD_ULOGIC;
4125 
                D1              : in    STD_ULOGIC;
4126 
                S10             : in    STD_ULOGIC;
4127 
                S11             : in    STD_ULOGIC;
4128 
                D2              : in    STD_ULOGIC;
4129 
                D3              : in    STD_ULOGIC;
4130 
                Y               : out    STD_ULOGIC);
4131 
 end component;
4132 
 
4133 
 
4134 
------ Component CMF1 ------
4135 
 component CMF1
4136 
--pragma translate_off
4137 
    generic(
4138 
                TimingChecksOn:Boolean := True;
4139 
                Xon: Boolean := False;
4140 
                InstancePath: STRING :="*";
4141 
                MsgOn: Boolean := True;
4142 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4143 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4144 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4145 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4146 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4147 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4148 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4149 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4150 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4151 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4152 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4153 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns));
4154 
 
4155 
 
4156 
--pragma translate_on
4157 
    port(
4158 
                D0              : in    STD_ULOGIC;
4159 
                S00             : in    STD_ULOGIC;
4160 
                S01             : in    STD_ULOGIC;
4161 
                DB              : in    STD_ULOGIC;
4162 
                S10             : in    STD_ULOGIC;
4163 
                S11             : in    STD_ULOGIC;
4164 
                Y               : out    STD_ULOGIC);
4165 
 end component;
4166 
 
4167 
 
4168 
------ Component CMF2 ------
4169 
 component CMF2
4170 
--pragma translate_off
4171 
    generic(
4172 
                TimingChecksOn:Boolean := True;
4173 
                Xon: Boolean := False;
4174 
                InstancePath: STRING :="*";
4175 
                MsgOn: Boolean := True;
4176 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4177 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4178 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4179 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4180 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4181 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4182 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4183 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4184 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4185 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4186 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4187 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns));
4188 
 
4189 
 
4190 
--pragma translate_on
4191 
    port(
4192 
                DB              : in    STD_ULOGIC;
4193 
                S00             : in    STD_ULOGIC;
4194 
                S01             : in    STD_ULOGIC;
4195 
                D1              : in    STD_ULOGIC;
4196 
                S10             : in    STD_ULOGIC;
4197 
                S11             : in    STD_ULOGIC;
4198 
                Y               : out    STD_ULOGIC);
4199 
 end component;
4200 
 
4201 
 
4202 
------ Component CMF3 ------
4203 
 component CMF3
4204 
--pragma translate_off
4205 
    generic(
4206 
                TimingChecksOn:Boolean := True;
4207 
                Xon: Boolean := False;
4208 
                InstancePath: STRING :="*";
4209 
                MsgOn: Boolean := True;
4210 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4211 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4212 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4213 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4214 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4215 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4216 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4217 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4218 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4219 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4220 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4221 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4222 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4223 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4224 
 
4225 
 
4226 
--pragma translate_on
4227 
    port(
4228 
                D0              : in    STD_ULOGIC;
4229 
                S00             : in    STD_ULOGIC;
4230 
                S01             : in    STD_ULOGIC;
4231 
                D1              : in    STD_ULOGIC;
4232 
                S10             : in    STD_ULOGIC;
4233 
                S11             : in    STD_ULOGIC;
4234 
                DB              : in    STD_ULOGIC;
4235 
                Y               : out    STD_ULOGIC);
4236 
 end component;
4237 
 
4238 
 
4239 
------ Component CMF4 ------
4240 
 component CMF4
4241 
--pragma translate_off
4242 
    generic(
4243 
                TimingChecksOn:Boolean := True;
4244 
                Xon: Boolean := False;
4245 
                InstancePath: STRING :="*";
4246 
                MsgOn: Boolean := True;
4247 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4248 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4249 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4250 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4251 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4252 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4253 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4254 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4255 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4256 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4257 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4258 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns));
4259 
 
4260 
 
4261 
--pragma translate_on
4262 
    port(
4263 
                DB              : in    STD_ULOGIC;
4264 
                S10             : in    STD_ULOGIC;
4265 
                S11             : in    STD_ULOGIC;
4266 
                D2              : in    STD_ULOGIC;
4267 
                S00             : in    STD_ULOGIC;
4268 
                S01             : in    STD_ULOGIC;
4269 
                Y               : out    STD_ULOGIC);
4270 
 end component;
4271 
 
4272 
 
4273 
------ Component CMF5 ------
4274 
 component CMF5
4275 
--pragma translate_off
4276 
    generic(
4277 
                TimingChecksOn:Boolean := True;
4278 
                Xon: Boolean := False;
4279 
                InstancePath: STRING :="*";
4280 
                MsgOn: Boolean := True;
4281 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4282 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4283 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4284 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4285 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4286 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4287 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4288 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4289 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4290 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4291 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4292 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4293 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4294 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4295 
 
4296 
 
4297 
--pragma translate_on
4298 
    port(
4299 
                D0              : in    STD_ULOGIC;
4300 
                S10             : in    STD_ULOGIC;
4301 
                S11             : in    STD_ULOGIC;
4302 
                D2              : in    STD_ULOGIC;
4303 
                S00             : in    STD_ULOGIC;
4304 
                S01             : in    STD_ULOGIC;
4305 
                DB              : in    STD_ULOGIC;
4306 
                Y               : out    STD_ULOGIC);
4307 
 end component;
4308 
 
4309 
 
4310 
------ Component CMF6 ------
4311 
 component CMF6
4312 
--pragma translate_off
4313 
    generic(
4314 
                TimingChecksOn:Boolean := True;
4315 
                Xon: Boolean := False;
4316 
                InstancePath: STRING :="*";
4317 
                MsgOn: Boolean := True;
4318 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4319 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4320 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4321 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4322 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4323 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4324 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4325 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4326 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4327 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4328 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4329 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4330 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4331 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4332 
 
4333 
 
4334 
--pragma translate_on
4335 
    port(
4336 
                DB              : in    STD_ULOGIC;
4337 
                S00             : in    STD_ULOGIC;
4338 
                S01             : in    STD_ULOGIC;
4339 
                D1              : in    STD_ULOGIC;
4340 
                S10             : in    STD_ULOGIC;
4341 
                S11             : in    STD_ULOGIC;
4342 
                D2              : in    STD_ULOGIC;
4343 
                Y               : out    STD_ULOGIC);
4344 
 end component;
4345 
 
4346 
 
4347 
------ Component CMF7 ------
4348 
 component CMF7
4349 
--pragma translate_off
4350 
    generic(
4351 
                TimingChecksOn:Boolean := True;
4352 
                Xon: Boolean := False;
4353 
                InstancePath: STRING :="*";
4354 
                MsgOn: Boolean := True;
4355 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4356 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4357 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4358 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4359 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4360 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4361 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4362 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4363 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4364 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4365 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4366 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4367 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4368 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4369 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4370 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4371 
 
4372 
 
4373 
--pragma translate_on
4374 
    port(
4375 
                D0              : in    STD_ULOGIC;
4376 
                S00             : in    STD_ULOGIC;
4377 
                S01             : in    STD_ULOGIC;
4378 
                D1              : in    STD_ULOGIC;
4379 
                S10             : in    STD_ULOGIC;
4380 
                S11             : in    STD_ULOGIC;
4381 
                D2              : in    STD_ULOGIC;
4382 
                DB              : in    STD_ULOGIC;
4383 
                Y               : out    STD_ULOGIC);
4384 
 end component;
4385 
 
4386 
 
4387 
------ Component CMF8 ------
4388 
 component CMF8
4389 
--pragma translate_off
4390 
    generic(
4391 
                TimingChecksOn:Boolean := True;
4392 
                Xon: Boolean := False;
4393 
                InstancePath: STRING :="*";
4394 
                MsgOn: Boolean := True;
4395 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4396 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4397 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4398 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4399 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4400 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4401 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4402 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4403 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4404 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4405 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4406 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4407 
 
4408 
 
4409 
--pragma translate_on
4410 
    port(
4411 
                DB              : in    STD_ULOGIC;
4412 
                S10             : in    STD_ULOGIC;
4413 
                S11             : in    STD_ULOGIC;
4414 
                S00             : in    STD_ULOGIC;
4415 
                S01             : in    STD_ULOGIC;
4416 
                D3              : in    STD_ULOGIC;
4417 
                Y               : out    STD_ULOGIC);
4418 
 end component;
4419 
 
4420 
 
4421 
------ Component CMF9 ------
4422 
 component CMF9
4423 
--pragma translate_off
4424 
    generic(
4425 
                TimingChecksOn:Boolean := True;
4426 
                Xon: Boolean := False;
4427 
                InstancePath: STRING :="*";
4428 
                MsgOn: Boolean := True;
4429 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4430 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4431 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4432 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4433 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4434 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4435 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4436 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4437 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4438 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4439 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4440 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4441 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4442 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4443 
 
4444 
 
4445 
--pragma translate_on
4446 
    port(
4447 
                D0              : in    STD_ULOGIC;
4448 
                S00             : in    STD_ULOGIC;
4449 
                S01             : in    STD_ULOGIC;
4450 
                DB              : in    STD_ULOGIC;
4451 
                S10             : in    STD_ULOGIC;
4452 
                S11             : in    STD_ULOGIC;
4453 
                D3              : in    STD_ULOGIC;
4454 
                Y               : out    STD_ULOGIC);
4455 
 end component;
4456 
 
4457 
 
4458 
------ Component CMFA ------
4459 
 component CMFA
4460 
--pragma translate_off
4461 
    generic(
4462 
                TimingChecksOn:Boolean := True;
4463 
                Xon: Boolean := False;
4464 
                InstancePath: STRING :="*";
4465 
                MsgOn: Boolean := True;
4466 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4467 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4468 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4469 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4470 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4471 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4472 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4473 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4474 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4475 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4476 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4477 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4478 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4479 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4480 
 
4481 
 
4482 
--pragma translate_on
4483 
    port(
4484 
                DB              : in    STD_ULOGIC;
4485 
                S00             : in    STD_ULOGIC;
4486 
                S01             : in    STD_ULOGIC;
4487 
                D1              : in    STD_ULOGIC;
4488 
                S10             : in    STD_ULOGIC;
4489 
                S11             : in    STD_ULOGIC;
4490 
                D3              : in    STD_ULOGIC;
4491 
                Y               : out    STD_ULOGIC);
4492 
 end component;
4493 
 
4494 
 
4495 
------ Component CMFB ------
4496 
 component CMFB
4497 
--pragma translate_off
4498 
    generic(
4499 
                TimingChecksOn:Boolean := True;
4500 
                Xon: Boolean := False;
4501 
                InstancePath: STRING :="*";
4502 
                MsgOn: Boolean := True;
4503 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4504 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4505 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4506 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4507 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4508 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4509 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4510 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4511 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4512 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4513 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4514 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4515 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4516 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4517 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4518 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4519 
 
4520 
 
4521 
--pragma translate_on
4522 
    port(
4523 
                D0              : in    STD_ULOGIC;
4524 
                S00             : in    STD_ULOGIC;
4525 
                S01             : in    STD_ULOGIC;
4526 
                D1              : in    STD_ULOGIC;
4527 
                S10             : in    STD_ULOGIC;
4528 
                S11             : in    STD_ULOGIC;
4529 
                DB              : in    STD_ULOGIC;
4530 
                D3              : in    STD_ULOGIC;
4531 
                Y               : out    STD_ULOGIC);
4532 
 end component;
4533 
 
4534 
 
4535 
------ Component CMFC ------
4536 
 component CMFC
4537 
--pragma translate_off
4538 
    generic(
4539 
                TimingChecksOn:Boolean := True;
4540 
                Xon: Boolean := False;
4541 
                InstancePath: STRING :="*";
4542 
                MsgOn: Boolean := True;
4543 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4544 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4545 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4546 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4547 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4548 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4549 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4550 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4551 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4552 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4553 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4554 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4555 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4556 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4557 
 
4558 
 
4559 
--pragma translate_on
4560 
    port(
4561 
                DB              : in    STD_ULOGIC;
4562 
                S10             : in    STD_ULOGIC;
4563 
                S11             : in    STD_ULOGIC;
4564 
                D2              : in    STD_ULOGIC;
4565 
                S00             : in    STD_ULOGIC;
4566 
                S01             : in    STD_ULOGIC;
4567 
                D3              : in    STD_ULOGIC;
4568 
                Y               : out    STD_ULOGIC);
4569 
 end component;
4570 
 
4571 
 
4572 
------ Component CMFD ------
4573 
 component CMFD
4574 
--pragma translate_off
4575 
    generic(
4576 
                TimingChecksOn:Boolean := True;
4577 
                Xon: Boolean := False;
4578 
                InstancePath: STRING :="*";
4579 
                MsgOn: Boolean := True;
4580 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4581 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4582 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4583 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4584 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4585 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4586 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4587 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4588 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4589 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4590 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4591 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4592 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4593 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4594 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4595 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4596 
 
4597 
 
4598 
--pragma translate_on
4599 
    port(
4600 
                D0              : in    STD_ULOGIC;
4601 
                S00             : in    STD_ULOGIC;
4602 
                S01             : in    STD_ULOGIC;
4603 
                DB              : in    STD_ULOGIC;
4604 
                S10             : in    STD_ULOGIC;
4605 
                S11             : in    STD_ULOGIC;
4606 
                D2              : in    STD_ULOGIC;
4607 
                D3              : in    STD_ULOGIC;
4608 
                Y               : out    STD_ULOGIC);
4609 
 end component;
4610 
 
4611 
 
4612 
------ Component CMFE ------
4613 
 component CMFE
4614 
--pragma translate_off
4615 
    generic(
4616 
                TimingChecksOn:Boolean := True;
4617 
                Xon: Boolean := False;
4618 
                InstancePath: STRING :="*";
4619 
                MsgOn: Boolean := True;
4620 
                tpd_DB_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4621 
                tpd_S00_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4622 
                tpd_S01_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4623 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4624 
                tpd_S10_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4625 
                tpd_S11_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
4626 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4627 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4628 
                tipd_DB         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4629 
                tipd_S00                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4630 
                tipd_S01                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4631 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4632 
                tipd_S10                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4633 
                tipd_S11                : VitalDelayType01 := (0.000 ns, 0.000 ns);
4634 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4635 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4636 
 
4637 
 
4638 
--pragma translate_on
4639 
    port(
4640 
                DB              : in    STD_ULOGIC;
4641 
                S00             : in    STD_ULOGIC;
4642 
                S01             : in    STD_ULOGIC;
4643 
                D1              : in    STD_ULOGIC;
4644 
                S10             : in    STD_ULOGIC;
4645 
                S11             : in    STD_ULOGIC;
4646 
                D2              : in    STD_ULOGIC;
4647 
                D3              : in    STD_ULOGIC;
4648 
                Y               : out    STD_ULOGIC);
4649 
 end component;
4650 
 
4651 
 
4652 
------ Component CS1 ------
4653 
 component CS1
4654 
--pragma translate_off
4655 
    generic(
4656 
                TimingChecksOn:Boolean := True;
4657 
                Xon: Boolean := False;
4658 
                InstancePath: STRING :="*";
4659 
                MsgOn: Boolean := True;
4660 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4661 
                tpd_S_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4662 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4663 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4664 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4665 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
4666 
                tipd_S          : VitalDelayType01 := (0.000 ns, 0.000 ns);
4667 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
4668 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
4669 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
4670 
 
4671 
 
4672 
--pragma translate_on
4673 
    port(
4674 
                A               : in    STD_ULOGIC;
4675 
                S               : in    STD_ULOGIC;
4676 
                B               : in    STD_ULOGIC;
4677 
                C               : in    STD_ULOGIC;
4678 
                D               : in    STD_ULOGIC;
4679 
                Y               : out    STD_ULOGIC);
4680 
 end component;
4681 
 
4682 
 
4683 
------ Component CS2 ------
4684 
 component CS2
4685 
--pragma translate_off
4686 
    generic(
4687 
                TimingChecksOn:Boolean := True;
4688 
                Xon: Boolean := False;
4689 
                InstancePath: STRING :="*";
4690 
                MsgOn: Boolean := True;
4691 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4692 
                tpd_S_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4693 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4694 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4695 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
4696 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
4697 
                tipd_S          : VitalDelayType01 := (0.000 ns, 0.000 ns);
4698 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
4699 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
4700 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
4701 
 
4702 
 
4703 
--pragma translate_on
4704 
    port(
4705 
                A               : in    STD_ULOGIC;
4706 
                S               : in    STD_ULOGIC;
4707 
                B               : in    STD_ULOGIC;
4708 
                C               : in    STD_ULOGIC;
4709 
                D               : in    STD_ULOGIC;
4710 
                Y               : out    STD_ULOGIC);
4711 
 end component;
4712 
 
4713 
 
4714 
------ Component CY2A ------
4715 
 component CY2A
4716 
--pragma translate_off
4717 
    generic(
4718 
                TimingChecksOn:Boolean := True;
4719 
                Xon: Boolean := False;
4720 
                InstancePath: STRING :="*";
4721 
                MsgOn: Boolean := True;
4722 
                tpd_A1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4723 
                tpd_B1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4724 
                tpd_A0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4725 
                tpd_B0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4726 
                tipd_A1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4727 
                tipd_B1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4728 
                tipd_A0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4729 
                tipd_B0         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4730 
 
4731 
 
4732 
--pragma translate_on
4733 
    port(
4734 
                A1              : in    STD_ULOGIC;
4735 
                B1              : in    STD_ULOGIC;
4736 
                A0              : in    STD_ULOGIC;
4737 
                B0              : in    STD_ULOGIC;
4738 
                Y               : out    STD_ULOGIC);
4739 
 end component;
4740 
 
4741 
 
4742 
------ Component CY2B ------
4743 
 component CY2B
4744 
--pragma translate_off
4745 
    generic(
4746 
                TimingChecksOn:Boolean := True;
4747 
                Xon: Boolean := False;
4748 
                InstancePath: STRING :="*";
4749 
                MsgOn: Boolean := True;
4750 
                tpd_A1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4751 
                tpd_B1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4752 
                tpd_A0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4753 
                tpd_B0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
4754 
                tipd_A1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4755 
                tipd_B1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4756 
                tipd_A0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
4757 
                tipd_B0         : VitalDelayType01 := (0.000 ns, 0.000 ns));
4758 
 
4759 
 
4760 
--pragma translate_on
4761 
    port(
4762 
                A1              : in    STD_ULOGIC;
4763 
                B1              : in    STD_ULOGIC;
4764 
                A0              : in    STD_ULOGIC;
4765 
                B0              : in    STD_ULOGIC;
4766 
                Y               : out    STD_ULOGIC);
4767 
 end component;
4768 
 
4769 
 
4770 
------ Component DF1 ------
4771 
 component DF1
4772 
--pragma translate_off
4773 
    generic(
4774 
                TimingChecksOn: Boolean := True;
4775 
                InstancePath: STRING := "*";
4776 
                Xon: Boolean := False;
4777 
                MsgOn: Boolean := True;
4778 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4779 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
4780 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
4781 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
4782 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
4783 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
4784 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
4785 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4786 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
4787 
 
4788 
 
4789 
--pragma translate_on
4790 
    port(
4791 
                CLK             :   in    STD_ULOGIC;
4792 
                D               :  in    STD_ULOGIC;
4793 
                Q               :  out    STD_ULOGIC);
4794 
 
4795 
 end component;
4796 
 
4797 
 
4798 
------ Component DF1_CC ------
4799 
 component DF1_CC
4800 
--pragma translate_off
4801 
    generic(
4802 
                TimingChecksOn: Boolean := True;
4803 
                InstancePath: STRING := "*";
4804 
                Xon: Boolean := False;
4805 
                MsgOn: Boolean := True;
4806 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4807 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
4808 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
4809 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
4810 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
4811 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
4812 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
4813 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4814 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
4815 
 
4816 
 
4817 
--pragma translate_on
4818 
    port(
4819 
                CLK             :   in    STD_ULOGIC;
4820 
                D               :  in    STD_ULOGIC;
4821 
                Q               :  out    STD_ULOGIC);
4822 
 
4823 
 end component;
4824 
 
4825 
 
4826 
------ Component DF1B ------
4827 
 component DF1B
4828 
--pragma translate_off
4829 
    generic(
4830 
                TimingChecksOn: Boolean := True;
4831 
                InstancePath: STRING := "*";
4832 
                Xon: Boolean := False;
4833 
                MsgOn: Boolean := True;
4834 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4835 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
4836 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
4837 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
4838 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
4839 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
4840 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
4841 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4842 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
4843 
 
4844 
 
4845 
--pragma translate_on
4846 
    port(
4847 
                CLK             :   in    STD_ULOGIC;
4848 
                D               :  in    STD_ULOGIC;
4849 
                Q               :  out    STD_ULOGIC);
4850 
 
4851 
 end component;
4852 
 
4853 
 
4854 
------ Component DFC1B ------
4855 
 component DFC1B
4856 
--pragma translate_off
4857 
    generic(
4858 
                TimingChecksOn: Boolean := True;
4859 
                InstancePath: STRING := "*";
4860 
                Xon: Boolean := False;
4861 
                MsgOn: Boolean := True;
4862 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4863 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4864 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
4865 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
4866 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
4867 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
4868 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
4869 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
4870 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
4871 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
4872 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
4873 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4874 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4875 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
4876 
 
4877 
 
4878 
--pragma translate_on
4879 
    port(
4880 
                CLR             :   in    STD_ULOGIC;
4881 
                CLK             :   in    STD_ULOGIC;
4882 
                D               :  in    STD_ULOGIC;
4883 
                Q               :  out    STD_ULOGIC);
4884 
 
4885 
 end component;
4886 
 
4887 
 
4888 
------ Component DFC1B_CC ------
4889 
 component DFC1B_CC
4890 
--pragma translate_off
4891 
    generic(
4892 
                TimingChecksOn: Boolean := True;
4893 
                InstancePath: STRING := "*";
4894 
                Xon: Boolean := False;
4895 
                MsgOn: Boolean := True;
4896 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4897 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4898 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
4899 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
4900 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
4901 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
4902 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
4903 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
4904 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
4905 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
4906 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
4907 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4908 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4909 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
4910 
 
4911 
 
4912 
--pragma translate_on
4913 
    port(
4914 
                CLR             :   in    STD_ULOGIC;
4915 
                CLK             :   in    STD_ULOGIC;
4916 
                D               :  in    STD_ULOGIC;
4917 
                Q               :  out    STD_ULOGIC);
4918 
 
4919 
 end component;
4920 
 
4921 
 
4922 
------ Component DFC1D ------
4923 
 component DFC1D
4924 
--pragma translate_off
4925 
    generic(
4926 
                TimingChecksOn: Boolean := True;
4927 
                InstancePath: STRING := "*";
4928 
                Xon: Boolean := False;
4929 
                MsgOn: Boolean := True;
4930 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4931 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4932 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
4933 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
4934 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
4935 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
4936 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
4937 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
4938 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
4939 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
4940 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
4941 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4942 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4943 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
4944 
 
4945 
 
4946 
--pragma translate_on
4947 
    port(
4948 
                CLR             :   in    STD_ULOGIC;
4949 
                CLK             :   in    STD_ULOGIC;
4950 
                D               :  in    STD_ULOGIC;
4951 
                Q               :  out    STD_ULOGIC);
4952 
 
4953 
 end component;
4954 
 
4955 
 
4956 
------ Component DFE1C ------
4957 
 component DFE1C
4958 
--pragma translate_off
4959 
    generic(
4960 
                TimingChecksOn: Boolean := True;
4961 
                InstancePath: STRING := "*";
4962 
                Xon: Boolean := False;
4963 
                MsgOn: Boolean := True;
4964 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4965 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
4966 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
4967 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
4968 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
4969 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
4970 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
4971 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
4972 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
4973 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
4974 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
4975 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4976 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
4977 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
4978 
 
4979 
 
4980 
--pragma translate_on
4981 
    port(
4982 
                E               :   in    STD_ULOGIC;
4983 
                CLK             :   in    STD_ULOGIC;
4984 
                D               :  in    STD_ULOGIC;
4985 
                Q               :  out    STD_ULOGIC);
4986 
 
4987 
 end component;
4988 
 
4989 
 
4990 
------ Component DFE1B ------
4991 
 component DFE1B
4992 
--pragma translate_off
4993 
    generic(
4994 
                TimingChecksOn: Boolean := True;
4995 
                InstancePath: STRING := "*";
4996 
                Xon: Boolean := False;
4997 
                MsgOn: Boolean := True;
4998 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
4999 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5000 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5001 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5002 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5003 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5004 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5005 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5006 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5007 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5008 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5009 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5010 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5011 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5012 
 
5013 
 
5014 
--pragma translate_on
5015 
    port(
5016 
                E               :   in    STD_ULOGIC;
5017 
                CLK             :   in    STD_ULOGIC;
5018 
                D               :  in    STD_ULOGIC;
5019 
                Q               :  out    STD_ULOGIC);
5020 
 
5021 
 end component;
5022 
 
5023 
 
5024 
------ Component DFE3C ------
5025 
 component DFE3C
5026 
--pragma translate_off
5027 
    generic(
5028 
                TimingChecksOn: Boolean := True;
5029 
                InstancePath: STRING := "*";
5030 
                Xon: Boolean := False;
5031 
                MsgOn: Boolean := True;
5032 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5033 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5034 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5035 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5036 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5037 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5038 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5039 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5040 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5041 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5042 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
5043 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
5044 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5045 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5046 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5047 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5048 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5049 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5050 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5051 
 
5052 
 
5053 
--pragma translate_on
5054 
    port(
5055 
                CLR             :   in    STD_ULOGIC;
5056 
                E               :   in    STD_ULOGIC;
5057 
                CLK             :   in    STD_ULOGIC;
5058 
                D               :  in    STD_ULOGIC;
5059 
                Q               :  out    STD_ULOGIC);
5060 
 
5061 
 end component;
5062 
 
5063 
 
5064 
------ Component DFE3D ------
5065 
 component DFE3D
5066 
--pragma translate_off
5067 
    generic(
5068 
                TimingChecksOn: Boolean := True;
5069 
                InstancePath: STRING := "*";
5070 
                Xon: Boolean := False;
5071 
                MsgOn: Boolean := True;
5072 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5073 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5074 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
5075 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
5076 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
5077 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
5078 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
5079 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
5080 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
5081 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
5082 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
5083 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
5084 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5085 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5086 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5087 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5088 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5089 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5090 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5091 
 
5092 
 
5093 
--pragma translate_on
5094 
    port(
5095 
                CLR             :   in    STD_ULOGIC;
5096 
                E               :   in    STD_ULOGIC;
5097 
                CLK             :   in    STD_ULOGIC;
5098 
                D               :  in    STD_ULOGIC;
5099 
                Q               :  out    STD_ULOGIC);
5100 
 
5101 
 end component;
5102 
 
5103 
 
5104 
------ Component DFE4F ------
5105 
 component DFE4F
5106 
--pragma translate_off
5107 
    generic(
5108 
                TimingChecksOn: Boolean := True;
5109 
                InstancePath: STRING := "*";
5110 
                Xon: Boolean := False;
5111 
                MsgOn: Boolean := True;
5112 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5113 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5114 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5115 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5116 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5117 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5118 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5119 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5120 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5121 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5122 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
5123 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
5124 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5125 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5126 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
5127 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5128 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5129 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5130 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5131 
 
5132 
 
5133 
--pragma translate_on
5134 
    port(
5135 
                PRE             :   in    STD_ULOGIC;
5136 
                E               :   in    STD_ULOGIC;
5137 
                CLK             :   in    STD_ULOGIC;
5138 
                D               :  in    STD_ULOGIC;
5139 
                Q               :  out    STD_ULOGIC);
5140 
 
5141 
 end component;
5142 
 
5143 
 
5144 
------ Component DFE4G ------
5145 
 component DFE4G
5146 
--pragma translate_off
5147 
    generic(
5148 
                TimingChecksOn: Boolean := True;
5149 
                InstancePath: STRING := "*";
5150 
                Xon: Boolean := False;
5151 
                MsgOn: Boolean := True;
5152 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5153 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5154 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
5155 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
5156 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
5157 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
5158 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
5159 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
5160 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
5161 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
5162 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
5163 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
5164 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5165 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5166 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
5167 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5168 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5169 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5170 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5171 
 
5172 
 
5173 
--pragma translate_on
5174 
    port(
5175 
                PRE             :   in    STD_ULOGIC;
5176 
                E               :   in    STD_ULOGIC;
5177 
                CLK             :   in    STD_ULOGIC;
5178 
                D               :  in    STD_ULOGIC;
5179 
                Q               :  out    STD_ULOGIC);
5180 
 
5181 
 end component;
5182 
 
5183 
 
5184 
------ Component DFEG ------
5185 
 component DFEG
5186 
--pragma translate_off
5187 
    generic(
5188 
                TimingChecksOn: Boolean := True;
5189 
                InstancePath: STRING := "*";
5190 
                Xon: Boolean := False;
5191 
                MsgOn: Boolean := True;
5192 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5193 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5194 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5195 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5196 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5197 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5198 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5199 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5200 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5201 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5202 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5203 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
5204 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
5205 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
5206 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
5207 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5208 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5209 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
5210 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5211 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5212 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5213 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5214 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5215 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5216 
 
5217 
 
5218 
--pragma translate_on
5219 
    port(
5220 
                CLR             :   in    STD_ULOGIC;
5221 
                PRE             :   in    STD_ULOGIC;
5222 
                E               :   in    STD_ULOGIC;
5223 
                CLK             :   in    STD_ULOGIC;
5224 
                D               :  in    STD_ULOGIC;
5225 
                Q               :  out    STD_ULOGIC);
5226 
 
5227 
 end component;
5228 
 
5229 
 
5230 
------ Component DFEH ------
5231 
 component DFEH
5232 
--pragma translate_off
5233 
    generic(
5234 
                TimingChecksOn: Boolean := True;
5235 
                InstancePath: STRING := "*";
5236 
                Xon: Boolean := False;
5237 
                MsgOn: Boolean := True;
5238 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5239 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5240 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5241 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
5242 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
5243 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
5244 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
5245 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
5246 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
5247 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
5248 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
5249 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
5250 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
5251 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
5252 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
5253 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5254 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5255 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
5256 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5257 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5258 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5259 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5260 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5261 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5262 
 
5263 
 
5264 
--pragma translate_on
5265 
    port(
5266 
                CLR             :   in    STD_ULOGIC;
5267 
                PRE             :   in    STD_ULOGIC;
5268 
                E               :   in    STD_ULOGIC;
5269 
                CLK             :   in    STD_ULOGIC;
5270 
                D               :  in    STD_ULOGIC;
5271 
                Q               :  out    STD_ULOGIC);
5272 
 
5273 
 end component;
5274 
 
5275 
 
5276 
------ Component DFP1 ------
5277 
 component DFP1
5278 
--pragma translate_off
5279 
    generic(
5280 
                TimingChecksOn: Boolean := True;
5281 
                InstancePath: STRING := "*";
5282 
                Xon: Boolean := False;
5283 
                MsgOn: Boolean := True;
5284 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5285 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5286 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5287 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5288 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5289 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5290 
                thold_PRE_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
5291 
                trecovery_PRE_CLK_negedge_posedge               :   VitalDelayType := 0.000 ns;
5292 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5293 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5294 
                tpw_PRE_posedge         :  VitalDelayType := 0.000 ns;
5295 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5296 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5297 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5298 
 
5299 
 
5300 
--pragma translate_on
5301 
    port(
5302 
                PRE             :   in    STD_ULOGIC;
5303 
                CLK             :   in    STD_ULOGIC;
5304 
                D               :  in    STD_ULOGIC;
5305 
                Q               :  out    STD_ULOGIC);
5306 
 
5307 
 end component;
5308 
 
5309 
 
5310 
------ Component DFP1A ------
5311 
 component DFP1A
5312 
--pragma translate_off
5313 
    generic(
5314 
                TimingChecksOn: Boolean := True;
5315 
                InstancePath: STRING := "*";
5316 
                Xon: Boolean := False;
5317 
                MsgOn: Boolean := True;
5318 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5319 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5320 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
5321 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
5322 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
5323 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
5324 
                thold_PRE_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
5325 
                trecovery_PRE_CLK_negedge_negedge               :   VitalDelayType := 0.000 ns;
5326 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5327 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5328 
                tpw_PRE_posedge         :  VitalDelayType := 0.000 ns;
5329 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5330 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5331 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5332 
 
5333 
 
5334 
--pragma translate_on
5335 
    port(
5336 
                PRE             :   in    STD_ULOGIC;
5337 
                CLK             :   in    STD_ULOGIC;
5338 
                D               :  in    STD_ULOGIC;
5339 
                Q               :  out    STD_ULOGIC);
5340 
 
5341 
 end component;
5342 
 
5343 
 
5344 
------ Component DFP1B ------
5345 
 component DFP1B
5346 
--pragma translate_off
5347 
    generic(
5348 
                TimingChecksOn: Boolean := True;
5349 
                InstancePath: STRING := "*";
5350 
                Xon: Boolean := False;
5351 
                MsgOn: Boolean := True;
5352 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5353 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5354 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5355 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5356 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5357 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5358 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
5359 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
5360 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5361 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5362 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
5363 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5364 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5365 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5366 
 
5367 
 
5368 
--pragma translate_on
5369 
    port(
5370 
                PRE             :   in    STD_ULOGIC;
5371 
                CLK             :   in    STD_ULOGIC;
5372 
                D               :  in    STD_ULOGIC;
5373 
                Q               :  out    STD_ULOGIC);
5374 
 
5375 
 end component;
5376 
 
5377 
 
5378 
------ Component DFP1B_CC ------
5379 
 component DFP1B_CC
5380 
--pragma translate_off
5381 
    generic(
5382 
                TimingChecksOn: Boolean := True;
5383 
                InstancePath: STRING := "*";
5384 
                Xon: Boolean := False;
5385 
                MsgOn: Boolean := True;
5386 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5387 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5388 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5389 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5390 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5391 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5392 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
5393 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
5394 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5395 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5396 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
5397 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5398 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5399 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5400 
 
5401 
 
5402 
--pragma translate_on
5403 
    port(
5404 
                PRE             :   in    STD_ULOGIC;
5405 
                CLK             :   in    STD_ULOGIC;
5406 
                D               :  in    STD_ULOGIC;
5407 
                Q               :  out    STD_ULOGIC);
5408 
 
5409 
 end component;
5410 
 
5411 
 
5412 
------ Component DFP1D ------
5413 
 component DFP1D
5414 
--pragma translate_off
5415 
    generic(
5416 
                TimingChecksOn: Boolean := True;
5417 
                InstancePath: STRING := "*";
5418 
                Xon: Boolean := False;
5419 
                MsgOn: Boolean := True;
5420 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5421 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5422 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
5423 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
5424 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
5425 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
5426 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
5427 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
5428 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5429 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5430 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
5431 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5432 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5433 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5434 
 
5435 
 
5436 
--pragma translate_on
5437 
    port(
5438 
                PRE             :   in    STD_ULOGIC;
5439 
                CLK             :   in    STD_ULOGIC;
5440 
                D               :  in    STD_ULOGIC;
5441 
                Q               :  out    STD_ULOGIC);
5442 
 
5443 
 end component;
5444 
 
5445 
 
5446 
------ Component DFPC ------
5447 
 component DFPC
5448 
--pragma translate_off
5449 
    generic(
5450 
                TimingChecksOn: Boolean := True;
5451 
                InstancePath: STRING := "*";
5452 
                Xon: Boolean := False;
5453 
                MsgOn: Boolean := True;
5454 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5455 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5456 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5457 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5458 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5459 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5460 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5461 
                thold_PRE_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
5462 
                trecovery_PRE_CLK_negedge_posedge               :   VitalDelayType := 0.000 ns;
5463 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
5464 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
5465 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5466 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5467 
                tpw_PRE_posedge         :  VitalDelayType := 0.000 ns;
5468 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5469 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5470 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5471 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5472 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5473 
 
5474 
 
5475 
--pragma translate_on
5476 
    port(
5477 
                CLR             :   in    STD_ULOGIC;
5478 
                PRE             :   in    STD_ULOGIC;
5479 
                CLK             :   in    STD_ULOGIC;
5480 
                D               :  in    STD_ULOGIC;
5481 
                Q               :  out    STD_ULOGIC);
5482 
 
5483 
 end component;
5484 
 
5485 
 
5486 
------ Component DFPCB ------
5487 
 component DFPCB
5488 
--pragma translate_off
5489 
    generic(
5490 
                TimingChecksOn: Boolean := True;
5491 
                InstancePath: STRING := "*";
5492 
                Xon: Boolean := False;
5493 
                MsgOn: Boolean := True;
5494 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5495 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5496 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5497 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
5498 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
5499 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
5500 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
5501 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
5502 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
5503 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
5504 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
5505 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5506 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5507 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
5508 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5509 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5510 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5511 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5512 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5513 
 
5514 
 
5515 
--pragma translate_on
5516 
    port(
5517 
                CLR             :   in    STD_ULOGIC;
5518 
                PRE             :   in    STD_ULOGIC;
5519 
                CLK             :   in    STD_ULOGIC;
5520 
                D               :  in    STD_ULOGIC;
5521 
                Q               :  out    STD_ULOGIC);
5522 
 
5523 
 end component;
5524 
 
5525 
 
5526 
------ Component DFPCC ------
5527 
 component DFPCC
5528 
--pragma translate_off
5529 
    generic(
5530 
                TimingChecksOn: Boolean := True;
5531 
                InstancePath: STRING := "*";
5532 
                Xon: Boolean := False;
5533 
                MsgOn: Boolean := True;
5534 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5535 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5536 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5537 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
5538 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
5539 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
5540 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
5541 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
5542 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
5543 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
5544 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
5545 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
5546 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
5547 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
5548 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5549 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5550 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5551 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5552 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
5553 
 
5554 
 
5555 
--pragma translate_on
5556 
    port(
5557 
                CLR             :   in    STD_ULOGIC;
5558 
                PRE             :   in    STD_ULOGIC;
5559 
                CLK             :   in    STD_ULOGIC;
5560 
                D               :  in    STD_ULOGIC;
5561 
                Q               :  out    STD_ULOGIC);
5562 
 
5563 
 end component;
5564 
 
5565 
 
5566 
------ Component DL1 ------
5567 
 component DL1
5568 
--pragma translate_off
5569 
    generic(
5570 
                TimingChecksOn: Boolean := True;
5571 
                InstancePath: STRING := "*";
5572 
                Xon: Boolean := False;
5573 
                MsgOn: Boolean := True;
5574 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5575 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5576 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
5577 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
5578 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
5579 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
5580 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
5581 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
5582 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5583 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5584 
 
5585 
 
5586 
 --pragma translate_on
5587 
    port(
5588 
                D               :  in    STD_ULOGIC;
5589 
                G               :  in    STD_ULOGIC;
5590 
                Q               :  out    STD_ULOGIC);
5591 
 
5592 
 end component;
5593 
 
5594 
 
5595 
------ Component DL1A ------
5596 
 component DL1A
5597 
--pragma translate_off
5598 
    generic(
5599 
                TimingChecksOn: Boolean := True;
5600 
                InstancePath: STRING := "*";
5601 
                Xon: Boolean := False;
5602 
                MsgOn: Boolean := True;
5603 
                tpd_G_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5604 
                tpd_D_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5605 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
5606 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
5607 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
5608 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
5609 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
5610 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
5611 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5612 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5613 
 
5614 
 
5615 
 --pragma translate_on
5616 
    port(
5617 
                D               :  in    STD_ULOGIC;
5618 
                G               :  in    STD_ULOGIC;
5619 
                QN              :  out    STD_ULOGIC);
5620 
 
5621 
 end component;
5622 
 
5623 
 
5624 
------ Component DL1B ------
5625 
 component DL1B
5626 
--pragma translate_off
5627 
    generic(
5628 
                TimingChecksOn: Boolean := True;
5629 
                InstancePath: STRING := "*";
5630 
                Xon: Boolean := False;
5631 
                MsgOn: Boolean := True;
5632 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5633 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5634 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
5635 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
5636 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
5637 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
5638 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
5639 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
5640 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5641 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5642 
 
5643 
 
5644 
 --pragma translate_on
5645 
    port(
5646 
                D               :  in    STD_ULOGIC;
5647 
                G               :  in    STD_ULOGIC;
5648 
                Q               :  out    STD_ULOGIC);
5649 
 
5650 
 end component;
5651 
 
5652 
 
5653 
------ Component DL1C ------
5654 
 component DL1C
5655 
--pragma translate_off
5656 
    generic(
5657 
                TimingChecksOn: Boolean := True;
5658 
                InstancePath: STRING := "*";
5659 
                Xon: Boolean := False;
5660 
                MsgOn: Boolean := True;
5661 
                tpd_G_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5662 
                tpd_D_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5663 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
5664 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
5665 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
5666 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
5667 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
5668 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
5669 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5670 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5671 
 
5672 
 
5673 
 --pragma translate_on
5674 
    port(
5675 
                D               :  in    STD_ULOGIC;
5676 
                G               :  in    STD_ULOGIC;
5677 
                QN              :  out    STD_ULOGIC);
5678 
 
5679 
 end component;
5680 
 
5681 
 
5682 
------ Component DL2A ------
5683 
 component DL2A
5684 
--pragma translate_off
5685 
    generic(
5686 
                TimingChecksOn: Boolean := True;
5687 
                InstancePath: STRING := "*";
5688 
                Xon: Boolean := False;
5689 
                MsgOn: Boolean := True;
5690 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5691 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5692 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5693 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5694 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
5695 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
5696 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
5697 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
5698 
                thold_PRE_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
5699 
                trecovery_PRE_G_negedge_negedge         :   VitalDelayType := 0.000 ns;
5700 
                thold_CLR_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
5701 
                trecovery_CLR_G_posedge_negedge         :   VitalDelayType := 0.000 ns;
5702 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
5703 
                tpw_PRE_posedge         :  VitalDelayType := 0.000 ns;
5704 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5705 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
5706 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5707 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5708 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5709 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5710 
 
5711 
 
5712 
 --pragma translate_on
5713 
    port(
5714 
                D               :  in    STD_ULOGIC;
5715 
                CLR             :  in    STD_ULOGIC;
5716 
                PRE             :  in    STD_ULOGIC;
5717 
                G               :  in    STD_ULOGIC;
5718 
                Q               :  out    STD_ULOGIC);
5719 
 
5720 
 end component;
5721 
 
5722 
 
5723 
------ Component DL2C ------
5724 
 component DL2C
5725 
--pragma translate_off
5726 
    generic(
5727 
                TimingChecksOn: Boolean := True;
5728 
                InstancePath: STRING := "*";
5729 
                Xon: Boolean := False;
5730 
                MsgOn: Boolean := True;
5731 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5732 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5733 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5734 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5735 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
5736 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
5737 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
5738 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
5739 
                thold_PRE_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
5740 
                trecovery_PRE_G_negedge_posedge         :   VitalDelayType := 0.000 ns;
5741 
                thold_CLR_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
5742 
                trecovery_CLR_G_posedge_posedge         :   VitalDelayType := 0.000 ns;
5743 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
5744 
                tpw_PRE_posedge         :  VitalDelayType := 0.000 ns;
5745 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5746 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
5747 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5748 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5749 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5750 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5751 
 
5752 
 
5753 
 --pragma translate_on
5754 
    port(
5755 
                D               :  in    STD_ULOGIC;
5756 
                CLR             :  in    STD_ULOGIC;
5757 
                PRE             :  in    STD_ULOGIC;
5758 
                G               :  in    STD_ULOGIC;
5759 
                Q               :  out    STD_ULOGIC);
5760 
 
5761 
 end component;
5762 
 
5763 
 
5764 
------ Component DLC ------
5765 
 component DLC
5766 
--pragma translate_off
5767 
    generic(
5768 
                TimingChecksOn: Boolean := True;
5769 
                InstancePath: STRING := "*";
5770 
                Xon: Boolean := False;
5771 
                MsgOn: Boolean := True;
5772 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5773 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5774 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5775 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
5776 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
5777 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
5778 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
5779 
                thold_CLR_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
5780 
                trecovery_CLR_G_posedge_negedge         :   VitalDelayType := 0.000 ns;
5781 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
5782 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5783 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
5784 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5785 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5786 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5787 
 
5788 
 
5789 
 --pragma translate_on
5790 
    port(
5791 
                D               :  in    STD_ULOGIC;
5792 
                CLR             :  in    STD_ULOGIC;
5793 
                G               :  in    STD_ULOGIC;
5794 
                Q               :  out    STD_ULOGIC);
5795 
 
5796 
 end component;
5797 
 
5798 
 
5799 
------ Component DLC1 ------
5800 
 component DLC1
5801 
--pragma translate_off
5802 
    generic(
5803 
                TimingChecksOn: Boolean := True;
5804 
                InstancePath: STRING := "*";
5805 
                Xon: Boolean := False;
5806 
                MsgOn: Boolean := True;
5807 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5808 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5809 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5810 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
5811 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
5812 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
5813 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
5814 
                thold_CLR_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
5815 
                trecovery_CLR_G_negedge_negedge         :   VitalDelayType := 0.000 ns;
5816 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
5817 
                tpw_CLR_posedge         :  VitalDelayType := 0.000 ns;
5818 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
5819 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5820 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5821 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5822 
 
5823 
 
5824 
 --pragma translate_on
5825 
    port(
5826 
                D               :  in    STD_ULOGIC;
5827 
                CLR             :  in    STD_ULOGIC;
5828 
                G               :  in    STD_ULOGIC;
5829 
                Q               :  out    STD_ULOGIC);
5830 
 
5831 
 end component;
5832 
 
5833 
 
5834 
------ Component DLC1A ------
5835 
 component DLC1A
5836 
--pragma translate_off
5837 
    generic(
5838 
                TimingChecksOn: Boolean := True;
5839 
                InstancePath: STRING := "*";
5840 
                Xon: Boolean := False;
5841 
                MsgOn: Boolean := True;
5842 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5843 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5844 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5845 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
5846 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
5847 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
5848 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
5849 
                thold_CLR_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
5850 
                trecovery_CLR_G_negedge_posedge         :   VitalDelayType := 0.000 ns;
5851 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
5852 
                tpw_CLR_posedge         :  VitalDelayType := 0.000 ns;
5853 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
5854 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5855 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5856 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5857 
 
5858 
 
5859 
 --pragma translate_on
5860 
    port(
5861 
                D               :  in    STD_ULOGIC;
5862 
                CLR             :  in    STD_ULOGIC;
5863 
                G               :  in    STD_ULOGIC;
5864 
                Q               :  out    STD_ULOGIC);
5865 
 
5866 
 end component;
5867 
 
5868 
 
5869 
------ Component DLC1F ------
5870 
 component DLC1F
5871 
--pragma translate_off
5872 
    generic(
5873 
                TimingChecksOn: Boolean := True;
5874 
                InstancePath: STRING := "*";
5875 
                Xon: Boolean := False;
5876 
                MsgOn: Boolean := True;
5877 
                tpd_CLR_QN              :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5878 
                tpd_G_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5879 
                tpd_D_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5880 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
5881 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
5882 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
5883 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
5884 
                thold_CLR_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
5885 
                trecovery_CLR_G_negedge_negedge         :   VitalDelayType := 0.000 ns;
5886 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
5887 
                tpw_CLR_posedge         :  VitalDelayType := 0.000 ns;
5888 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
5889 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5890 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5891 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5892 
 
5893 
 
5894 
 --pragma translate_on
5895 
    port(
5896 
                D               :  in    STD_ULOGIC;
5897 
                CLR             :  in    STD_ULOGIC;
5898 
                G               :  in    STD_ULOGIC;
5899 
                QN              :  out    STD_ULOGIC);
5900 
 
5901 
 end component;
5902 
 
5903 
 
5904 
------ Component DLC1G ------
5905 
 component DLC1G
5906 
--pragma translate_off
5907 
    generic(
5908 
                TimingChecksOn: Boolean := True;
5909 
                InstancePath: STRING := "*";
5910 
                Xon: Boolean := False;
5911 
                MsgOn: Boolean := True;
5912 
                tpd_CLR_QN              :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5913 
                tpd_G_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5914 
                tpd_D_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5915 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
5916 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
5917 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
5918 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
5919 
                thold_CLR_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
5920 
                trecovery_CLR_G_negedge_posedge         :   VitalDelayType := 0.000 ns;
5921 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
5922 
                tpw_CLR_posedge         :  VitalDelayType := 0.000 ns;
5923 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
5924 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5925 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5926 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5927 
 
5928 
 
5929 
 --pragma translate_on
5930 
    port(
5931 
                D               :  in    STD_ULOGIC;
5932 
                CLR             :  in    STD_ULOGIC;
5933 
                G               :  in    STD_ULOGIC;
5934 
                QN              :  out    STD_ULOGIC);
5935 
 
5936 
 end component;
5937 
 
5938 
 
5939 
------ Component DLCA ------
5940 
 component DLCA
5941 
--pragma translate_off
5942 
    generic(
5943 
                TimingChecksOn: Boolean := True;
5944 
                InstancePath: STRING := "*";
5945 
                Xon: Boolean := False;
5946 
                MsgOn: Boolean := True;
5947 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5948 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5949 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5950 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
5951 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
5952 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
5953 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
5954 
                thold_CLR_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
5955 
                trecovery_CLR_G_posedge_posedge         :   VitalDelayType := 0.000 ns;
5956 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
5957 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
5958 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
5959 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5960 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5961 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5962 
 
5963 
 
5964 
 --pragma translate_on
5965 
    port(
5966 
                D               :  in    STD_ULOGIC;
5967 
                CLR             :  in    STD_ULOGIC;
5968 
                G               :  in    STD_ULOGIC;
5969 
                Q               :  out    STD_ULOGIC);
5970 
 
5971 
 end component;
5972 
 
5973 
 
5974 
------ Component DLE ------
5975 
 component DLE
5976 
--pragma translate_off
5977 
    generic(
5978 
                TimingChecksOn: Boolean := True;
5979 
                InstancePath: STRING := "*";
5980 
                Xon: Boolean := False;
5981 
                MsgOn: Boolean := True;
5982 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5983 
                tpd_E_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5984 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
5985 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
5986 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
5987 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
5988 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
5989 
                tsetup_E_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
5990 
                thold_E_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
5991 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
5992 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
5993 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5994 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
5995 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
5996 
 
5997 
 
5998 
 --pragma translate_on
5999 
    port(
6000 
                D               :  in    STD_ULOGIC;
6001 
                E               :  in    STD_ULOGIC;
6002 
                G               :  in    STD_ULOGIC;
6003 
                Q               :  out    STD_ULOGIC);
6004 
 
6005 
 end component;
6006 
 
6007 
 
6008 
------ Component DLE1D ------
6009 
 component DLE1D
6010 
--pragma translate_off
6011 
    generic(
6012 
                TimingChecksOn: Boolean := True;
6013 
                InstancePath: STRING := "*";
6014 
                Xon: Boolean := False;
6015 
                MsgOn: Boolean := True;
6016 
                tpd_G_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6017 
                tpd_E_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6018 
                tpd_D_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6019 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6020 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6021 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6022 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6023 
                tsetup_E_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6024 
                thold_E_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6025 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6026 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6027 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6028 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6029 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6030 
 
6031 
 
6032 
 --pragma translate_on
6033 
    port(
6034 
                D               :  in    STD_ULOGIC;
6035 
                E               :  in    STD_ULOGIC;
6036 
                G               :  in    STD_ULOGIC;
6037 
                QN              :  out    STD_ULOGIC);
6038 
 
6039 
 end component;
6040 
 
6041 
 
6042 
------ Component DLE2B ------
6043 
 component DLE2B
6044 
--pragma translate_off
6045 
    generic(
6046 
                TimingChecksOn: Boolean := True;
6047 
                InstancePath: STRING := "*";
6048 
                Xon: Boolean := False;
6049 
                MsgOn: Boolean := True;
6050 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6051 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6052 
                tpd_E_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6053 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6054 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6055 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6056 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6057 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6058 
                tsetup_E_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6059 
                thold_E_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6060 
                thold_CLR_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6061 
                trecovery_CLR_G_posedge_posedge         :   VitalDelayType := 0.000 ns;
6062 
                thold_CLR_E_posedge_posedge             :   VitalDelayType := 0.000 ns;
6063 
                trecovery_CLR_E_posedge_posedge         :   VitalDelayType := 0.000 ns;
6064 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6065 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
6066 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6067 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6068 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6069 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6070 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6071 
 
6072 
 
6073 
 --pragma translate_on
6074 
    port(
6075 
                D               :  in    STD_ULOGIC;
6076 
                CLR             :  in    STD_ULOGIC;
6077 
                E               :  in    STD_ULOGIC;
6078 
                G               :  in    STD_ULOGIC;
6079 
                Q               :  out    STD_ULOGIC);
6080 
 
6081 
 end component;
6082 
 
6083 
 
6084 
------ Component DLE2C ------
6085 
 component DLE2C
6086 
--pragma translate_off
6087 
    generic(
6088 
                TimingChecksOn: Boolean := True;
6089 
                InstancePath: STRING := "*";
6090 
                Xon: Boolean := False;
6091 
                MsgOn: Boolean := True;
6092 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6093 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6094 
                tpd_E_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6095 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6096 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6097 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6098 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6099 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6100 
                tsetup_E_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6101 
                thold_E_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6102 
                thold_CLR_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6103 
                trecovery_CLR_G_negedge_posedge         :   VitalDelayType := 0.000 ns;
6104 
                thold_CLR_E_negedge_posedge             :   VitalDelayType := 0.000 ns;
6105 
                trecovery_CLR_E_negedge_posedge         :   VitalDelayType := 0.000 ns;
6106 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6107 
                tpw_CLR_posedge         :  VitalDelayType := 0.000 ns;
6108 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6109 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6110 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6111 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6112 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6113 
 
6114 
 
6115 
 --pragma translate_on
6116 
    port(
6117 
                D               :  in    STD_ULOGIC;
6118 
                CLR             :  in    STD_ULOGIC;
6119 
                E               :  in    STD_ULOGIC;
6120 
                G               :  in    STD_ULOGIC;
6121 
                Q               :  out    STD_ULOGIC);
6122 
 
6123 
 end component;
6124 
 
6125 
 
6126 
------ Component DLE3B ------
6127 
 component DLE3B
6128 
--pragma translate_off
6129 
    generic(
6130 
                TimingChecksOn: Boolean := True;
6131 
                InstancePath: STRING := "*";
6132 
                Xon: Boolean := False;
6133 
                MsgOn: Boolean := True;
6134 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6135 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6136 
                tpd_E_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6137 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6138 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6139 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6140 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6141 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6142 
                tsetup_E_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6143 
                thold_E_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6144 
                thold_PRE_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6145 
                trecovery_PRE_G_negedge_posedge         :   VitalDelayType := 0.000 ns;
6146 
                thold_PRE_E_negedge_posedge             :   VitalDelayType := 0.000 ns;
6147 
                trecovery_PRE_E_negedge_posedge         :   VitalDelayType := 0.000 ns;
6148 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6149 
                tpw_PRE_posedge         :  VitalDelayType := 0.000 ns;
6150 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6151 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6152 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6153 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6154 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6155 
 
6156 
 
6157 
 --pragma translate_on
6158 
    port(
6159 
                D               :  in    STD_ULOGIC;
6160 
                PRE             :  in    STD_ULOGIC;
6161 
                E               :  in    STD_ULOGIC;
6162 
                G               :  in    STD_ULOGIC;
6163 
                Q               :  out    STD_ULOGIC);
6164 
 
6165 
 end component;
6166 
 
6167 
 
6168 
------ Component DLE3C ------
6169 
 component DLE3C
6170 
--pragma translate_off
6171 
    generic(
6172 
                TimingChecksOn: Boolean := True;
6173 
                InstancePath: STRING := "*";
6174 
                Xon: Boolean := False;
6175 
                MsgOn: Boolean := True;
6176 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6177 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6178 
                tpd_E_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6179 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6180 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6181 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6182 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6183 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6184 
                tsetup_E_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6185 
                thold_E_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6186 
                thold_PRE_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6187 
                trecovery_PRE_G_posedge_posedge         :   VitalDelayType := 0.000 ns;
6188 
                thold_PRE_E_posedge_posedge             :   VitalDelayType := 0.000 ns;
6189 
                trecovery_PRE_E_posedge_posedge         :   VitalDelayType := 0.000 ns;
6190 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6191 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
6192 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6193 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6194 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6195 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6196 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6197 
 
6198 
 
6199 
 --pragma translate_on
6200 
    port(
6201 
                D               :  in    STD_ULOGIC;
6202 
                PRE             :  in    STD_ULOGIC;
6203 
                E               :  in    STD_ULOGIC;
6204 
                G               :  in    STD_ULOGIC;
6205 
                Q               :  out    STD_ULOGIC);
6206 
 
6207 
 end component;
6208 
 
6209 
 
6210 
------ Component DLEA ------
6211 
 component DLEA
6212 
--pragma translate_off
6213 
    generic(
6214 
                TimingChecksOn: Boolean := True;
6215 
                InstancePath: STRING := "*";
6216 
                Xon: Boolean := False;
6217 
                MsgOn: Boolean := True;
6218 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6219 
                tpd_E_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6220 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6221 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6222 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6223 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6224 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6225 
                tsetup_E_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6226 
                thold_E_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6227 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
6228 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
6229 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6230 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6231 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6232 
 
6233 
 
6234 
 --pragma translate_on
6235 
    port(
6236 
                D               :  in    STD_ULOGIC;
6237 
                E               :  in    STD_ULOGIC;
6238 
                G               :  in    STD_ULOGIC;
6239 
                Q               :  out    STD_ULOGIC);
6240 
 
6241 
 end component;
6242 
 
6243 
 
6244 
------ Component DLEB ------
6245 
 component DLEB
6246 
--pragma translate_off
6247 
    generic(
6248 
                TimingChecksOn: Boolean := True;
6249 
                InstancePath: STRING := "*";
6250 
                Xon: Boolean := False;
6251 
                MsgOn: Boolean := True;
6252 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6253 
                tpd_E_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6254 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6255 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6256 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6257 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6258 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6259 
                tsetup_E_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6260 
                thold_E_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6261 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6262 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6263 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6264 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6265 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6266 
 
6267 
 
6268 
 --pragma translate_on
6269 
    port(
6270 
                D               :  in    STD_ULOGIC;
6271 
                E               :  in    STD_ULOGIC;
6272 
                G               :  in    STD_ULOGIC;
6273 
                Q               :  out    STD_ULOGIC);
6274 
 
6275 
 end component;
6276 
 
6277 
 
6278 
------ Component DLEC ------
6279 
 component DLEC
6280 
--pragma translate_off
6281 
    generic(
6282 
                TimingChecksOn: Boolean := True;
6283 
                InstancePath: STRING := "*";
6284 
                Xon: Boolean := False;
6285 
                MsgOn: Boolean := True;
6286 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6287 
                tpd_E_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6288 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6289 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6290 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6291 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6292 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6293 
                tsetup_E_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6294 
                thold_E_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6295 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6296 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6297 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6298 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6299 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6300 
 
6301 
 
6302 
 --pragma translate_on
6303 
    port(
6304 
                D               :  in    STD_ULOGIC;
6305 
                E               :  in    STD_ULOGIC;
6306 
                G               :  in    STD_ULOGIC;
6307 
                Q               :  out    STD_ULOGIC);
6308 
 
6309 
 end component;
6310 
 
6311 
 
6312 
------ Component DLM ------
6313 
 component DLM
6314 
--pragma translate_off
6315 
    generic(
6316 
                TimingChecksOn: Boolean := True;
6317 
                InstancePath: STRING := "*";
6318 
                Xon: Boolean := False;
6319 
                MsgOn: Boolean := True;
6320 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6321 
                tpd_A_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6322 
                tpd_S_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6323 
                tpd_B_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6324 
                tsetup_A_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6325 
                thold_A_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6326 
                tsetup_A_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6327 
                thold_A_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6328 
                tsetup_S_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6329 
                thold_S_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6330 
                tsetup_S_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6331 
                thold_S_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6332 
                tsetup_B_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6333 
                thold_B_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6334 
                tsetup_B_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6335 
                thold_B_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6336 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
6337 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
6338 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6339 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6340 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6341 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6342 
 
6343 
 
6344 
 --pragma translate_on
6345 
    port(
6346 
                A               :  in    STD_ULOGIC;
6347 
                S               :  in    STD_ULOGIC;
6348 
                B               :  in    STD_ULOGIC;
6349 
                G               :  in    STD_ULOGIC;
6350 
                Q               :  out    STD_ULOGIC);
6351 
 
6352 
 end component;
6353 
 
6354 
 
6355 
------ Component DLM2 ------
6356 
 component DLM2
6357 
--pragma translate_off
6358 
    generic(
6359 
                TimingChecksOn: Boolean := True;
6360 
                InstancePath: STRING := "*";
6361 
                Xon: Boolean := False;
6362 
                MsgOn: Boolean := True;
6363 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6364 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6365 
                tpd_A_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6366 
                tpd_S_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6367 
                tpd_B_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6368 
                tsetup_A_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6369 
                thold_A_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6370 
                tsetup_A_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6371 
                thold_A_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6372 
                tsetup_S_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6373 
                thold_S_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6374 
                tsetup_S_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6375 
                thold_S_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6376 
                tsetup_B_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6377 
                thold_B_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6378 
                tsetup_B_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6379 
                thold_B_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6380 
                thold_CLR_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6381 
                trecovery_CLR_G_posedge_negedge         :   VitalDelayType := 0.000 ns;
6382 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
6383 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
6384 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
6385 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6386 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6387 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6388 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6389 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6390 
 
6391 
 
6392 
 --pragma translate_on
6393 
    port(
6394 
                A               :  in    STD_ULOGIC;
6395 
                S               :  in    STD_ULOGIC;
6396 
                B               :  in    STD_ULOGIC;
6397 
                CLR             :  in    STD_ULOGIC;
6398 
                G               :  in    STD_ULOGIC;
6399 
                Q               :  out    STD_ULOGIC);
6400 
 
6401 
 end component;
6402 
 
6403 
 
6404 
------ Component DLM2B ------
6405 
 component DLM2B
6406 
--pragma translate_off
6407 
    generic(
6408 
                TimingChecksOn: Boolean := True;
6409 
                InstancePath: STRING := "*";
6410 
                Xon: Boolean := False;
6411 
                MsgOn: Boolean := True;
6412 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6413 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6414 
                tpd_A_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6415 
                tpd_S_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6416 
                tpd_B_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6417 
                tsetup_A_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6418 
                thold_A_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6419 
                tsetup_A_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6420 
                thold_A_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6421 
                tsetup_S_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6422 
                thold_S_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6423 
                tsetup_S_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6424 
                thold_S_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6425 
                tsetup_B_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6426 
                thold_B_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6427 
                tsetup_B_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6428 
                thold_B_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6429 
                thold_CLR_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6430 
                trecovery_CLR_G_posedge_posedge         :   VitalDelayType := 0.000 ns;
6431 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6432 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
6433 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6434 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6435 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6436 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6437 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6438 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6439 
 
6440 
 
6441 
 --pragma translate_on
6442 
    port(
6443 
                A               :  in    STD_ULOGIC;
6444 
                S               :  in    STD_ULOGIC;
6445 
                B               :  in    STD_ULOGIC;
6446 
                CLR             :  in    STD_ULOGIC;
6447 
                G               :  in    STD_ULOGIC;
6448 
                Q               :  out    STD_ULOGIC);
6449 
 
6450 
 end component;
6451 
 
6452 
 
6453 
------ Component DLM3 ------
6454 
 component DLM3
6455 
--pragma translate_off
6456 
    generic(
6457 
                TimingChecksOn: Boolean := True;
6458 
                InstancePath: STRING := "*";
6459 
                Xon: Boolean := False;
6460 
                MsgOn: Boolean := True;
6461 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6462 
                tpd_D0_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6463 
                tpd_S0_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6464 
                tpd_D1_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6465 
                tpd_S1_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6466 
                tpd_D2_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6467 
                tpd_D3_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6468 
                tsetup_D0_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6469 
                thold_D0_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6470 
                tsetup_D0_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6471 
                thold_D0_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6472 
                tsetup_S0_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6473 
                thold_S0_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6474 
                tsetup_S0_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6475 
                thold_S0_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6476 
                tsetup_D1_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6477 
                thold_D1_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6478 
                tsetup_D1_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6479 
                thold_D1_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6480 
                tsetup_S1_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6481 
                thold_S1_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6482 
                tsetup_S1_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6483 
                thold_S1_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6484 
                tsetup_D2_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6485 
                thold_D2_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6486 
                tsetup_D2_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6487 
                thold_D2_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6488 
                tsetup_D3_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6489 
                thold_D3_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6490 
                tsetup_D3_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6491 
                thold_D3_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6492 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
6493 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
6494 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6495 
                tipd_D0         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6496 
                tipd_S0         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6497 
                tipd_D1         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6498 
                tipd_S1         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6499 
                tipd_D2         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6500 
                tipd_D3         :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6501 
 
6502 
 
6503 
 --pragma translate_on
6504 
    port(
6505 
                D0              :  in    STD_ULOGIC;
6506 
                S0              :  in    STD_ULOGIC;
6507 
                D1              :  in    STD_ULOGIC;
6508 
                S1              :  in    STD_ULOGIC;
6509 
                D2              :  in    STD_ULOGIC;
6510 
                D3              :  in    STD_ULOGIC;
6511 
                G               :  in    STD_ULOGIC;
6512 
                Q               :  out    STD_ULOGIC);
6513 
 
6514 
 end component;
6515 
 
6516 
 
6517 
------ Component DLM3A ------
6518 
 component DLM3A
6519 
--pragma translate_off
6520 
    generic(
6521 
                TimingChecksOn: Boolean := True;
6522 
                InstancePath: STRING := "*";
6523 
                Xon: Boolean := False;
6524 
                MsgOn: Boolean := True;
6525 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6526 
                tpd_D0_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6527 
                tpd_S0_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6528 
                tpd_D1_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6529 
                tpd_S1_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6530 
                tpd_D2_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6531 
                tpd_D3_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6532 
                tsetup_D0_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6533 
                thold_D0_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6534 
                tsetup_D0_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6535 
                thold_D0_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6536 
                tsetup_S0_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6537 
                thold_S0_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6538 
                tsetup_S0_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6539 
                thold_S0_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6540 
                tsetup_D1_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6541 
                thold_D1_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6542 
                tsetup_D1_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6543 
                thold_D1_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6544 
                tsetup_S1_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6545 
                thold_S1_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6546 
                tsetup_S1_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6547 
                thold_S1_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6548 
                tsetup_D2_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6549 
                thold_D2_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6550 
                tsetup_D2_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6551 
                thold_D2_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6552 
                tsetup_D3_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6553 
                thold_D3_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6554 
                tsetup_D3_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6555 
                thold_D3_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6556 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6557 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6558 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6559 
                tipd_D0         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6560 
                tipd_S0         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6561 
                tipd_D1         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6562 
                tipd_S1         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6563 
                tipd_D2         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6564 
                tipd_D3         :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6565 
 
6566 
 
6567 
 --pragma translate_on
6568 
    port(
6569 
                D0              :  in    STD_ULOGIC;
6570 
                S0              :  in    STD_ULOGIC;
6571 
                D1              :  in    STD_ULOGIC;
6572 
                S1              :  in    STD_ULOGIC;
6573 
                D2              :  in    STD_ULOGIC;
6574 
                D3              :  in    STD_ULOGIC;
6575 
                G               :  in    STD_ULOGIC;
6576 
                Q               :  out    STD_ULOGIC);
6577 
 
6578 
 end component;
6579 
 
6580 
 
6581 
------ Component DLM4 ------
6582 
 component DLM4
6583 
--pragma translate_off
6584 
    generic(
6585 
                TimingChecksOn: Boolean := True;
6586 
                InstancePath: STRING := "*";
6587 
                Xon: Boolean := False;
6588 
                MsgOn: Boolean := True;
6589 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6590 
                tpd_S10_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6591 
                tpd_S11_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6592 
                tpd_S0_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6593 
                tpd_D0_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6594 
                tpd_D1_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6595 
                tpd_D2_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6596 
                tpd_D3_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6597 
                tsetup_S10_G_posedge_negedge            :   VitalDelayType := 0.000 ns;
6598 
                thold_S10_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6599 
                tsetup_S10_G_negedge_negedge            :   VitalDelayType := 0.000 ns;
6600 
                thold_S10_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6601 
                tsetup_S11_G_posedge_negedge            :   VitalDelayType := 0.000 ns;
6602 
                thold_S11_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6603 
                tsetup_S11_G_negedge_negedge            :   VitalDelayType := 0.000 ns;
6604 
                thold_S11_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6605 
                tsetup_S0_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6606 
                thold_S0_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6607 
                tsetup_S0_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6608 
                thold_S0_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6609 
                tsetup_D0_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6610 
                thold_D0_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6611 
                tsetup_D0_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6612 
                thold_D0_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6613 
                tsetup_D1_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6614 
                thold_D1_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6615 
                tsetup_D1_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6616 
                thold_D1_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6617 
                tsetup_D2_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6618 
                thold_D2_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6619 
                tsetup_D2_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6620 
                thold_D2_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6621 
                tsetup_D3_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6622 
                thold_D3_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6623 
                tsetup_D3_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6624 
                thold_D3_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6625 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
6626 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
6627 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6628 
                tipd_S10                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6629 
                tipd_S11                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6630 
                tipd_S0         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6631 
                tipd_D0         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6632 
                tipd_D1         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6633 
                tipd_D2         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6634 
                tipd_D3         :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6635 
 
6636 
 
6637 
 --pragma translate_on
6638 
    port(
6639 
                S10             :  in    STD_ULOGIC;
6640 
                S11             :  in    STD_ULOGIC;
6641 
                S0              :  in    STD_ULOGIC;
6642 
                D0              :  in    STD_ULOGIC;
6643 
                D1              :  in    STD_ULOGIC;
6644 
                D2              :  in    STD_ULOGIC;
6645 
                D3              :  in    STD_ULOGIC;
6646 
                G               :  in    STD_ULOGIC;
6647 
                Q               :  out    STD_ULOGIC);
6648 
 
6649 
 end component;
6650 
 
6651 
 
6652 
------ Component DLM4A ------
6653 
 component DLM4A
6654 
--pragma translate_off
6655 
    generic(
6656 
                TimingChecksOn: Boolean := True;
6657 
                InstancePath: STRING := "*";
6658 
                Xon: Boolean := False;
6659 
                MsgOn: Boolean := True;
6660 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6661 
                tpd_S10_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6662 
                tpd_S11_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6663 
                tpd_S0_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6664 
                tpd_D0_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6665 
                tpd_D1_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6666 
                tpd_D2_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6667 
                tpd_D3_Q                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6668 
                tsetup_S10_G_posedge_posedge            :   VitalDelayType := 0.000 ns;
6669 
                thold_S10_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6670 
                tsetup_S10_G_negedge_posedge            :   VitalDelayType := 0.000 ns;
6671 
                thold_S10_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6672 
                tsetup_S11_G_posedge_posedge            :   VitalDelayType := 0.000 ns;
6673 
                thold_S11_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6674 
                tsetup_S11_G_negedge_posedge            :   VitalDelayType := 0.000 ns;
6675 
                thold_S11_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6676 
                tsetup_S0_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6677 
                thold_S0_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6678 
                tsetup_S0_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6679 
                thold_S0_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6680 
                tsetup_D0_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6681 
                thold_D0_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6682 
                tsetup_D0_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6683 
                thold_D0_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6684 
                tsetup_D1_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6685 
                thold_D1_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6686 
                tsetup_D1_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6687 
                thold_D1_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6688 
                tsetup_D2_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6689 
                thold_D2_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6690 
                tsetup_D2_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6691 
                thold_D2_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6692 
                tsetup_D3_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6693 
                thold_D3_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6694 
                tsetup_D3_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6695 
                thold_D3_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6696 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6697 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6698 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6699 
                tipd_S10                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6700 
                tipd_S11                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6701 
                tipd_S0         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6702 
                tipd_D0         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6703 
                tipd_D1         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6704 
                tipd_D2         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6705 
                tipd_D3         :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6706 
 
6707 
 
6708 
 --pragma translate_on
6709 
    port(
6710 
                S10             :  in    STD_ULOGIC;
6711 
                S11             :  in    STD_ULOGIC;
6712 
                S0              :  in    STD_ULOGIC;
6713 
                D0              :  in    STD_ULOGIC;
6714 
                D1              :  in    STD_ULOGIC;
6715 
                D2              :  in    STD_ULOGIC;
6716 
                D3              :  in    STD_ULOGIC;
6717 
                G               :  in    STD_ULOGIC;
6718 
                Q               :  out    STD_ULOGIC);
6719 
 
6720 
 end component;
6721 
 
6722 
 
6723 
------ Component DLMA ------
6724 
 component DLMA
6725 
--pragma translate_off
6726 
    generic(
6727 
                TimingChecksOn: Boolean := True;
6728 
                InstancePath: STRING := "*";
6729 
                Xon: Boolean := False;
6730 
                MsgOn: Boolean := True;
6731 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6732 
                tpd_A_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6733 
                tpd_S_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6734 
                tpd_B_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6735 
                tsetup_A_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6736 
                thold_A_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6737 
                tsetup_A_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6738 
                thold_A_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6739 
                tsetup_S_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6740 
                thold_S_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6741 
                tsetup_S_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6742 
                thold_S_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6743 
                tsetup_B_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6744 
                thold_B_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6745 
                tsetup_B_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6746 
                thold_B_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6747 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6748 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6749 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6750 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6751 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6752 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6753 
 
6754 
 
6755 
 --pragma translate_on
6756 
    port(
6757 
                A               :  in    STD_ULOGIC;
6758 
                S               :  in    STD_ULOGIC;
6759 
                B               :  in    STD_ULOGIC;
6760 
                G               :  in    STD_ULOGIC;
6761 
                Q               :  out    STD_ULOGIC);
6762 
 
6763 
 end component;
6764 
 
6765 
 
6766 
------ Component DLME1A ------
6767 
 component DLME1A
6768 
--pragma translate_off
6769 
    generic(
6770 
                TimingChecksOn: Boolean := True;
6771 
                InstancePath: STRING := "*";
6772 
                Xon: Boolean := False;
6773 
                MsgOn: Boolean := True;
6774 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6775 
                tpd_E_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6776 
                tpd_A_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6777 
                tpd_S_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6778 
                tpd_B_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6779 
                tsetup_A_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6780 
                thold_A_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6781 
                tsetup_A_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6782 
                thold_A_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6783 
                tsetup_S_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6784 
                thold_S_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6785 
                tsetup_S_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6786 
                thold_S_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6787 
                tsetup_B_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6788 
                thold_B_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6789 
                tsetup_B_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6790 
                thold_B_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6791 
                tsetup_A_E_posedge_posedge              :   VitalDelayType := 0.000 ns;
6792 
                thold_A_E_posedge_posedge               :   VitalDelayType := 0.000 ns;
6793 
                tsetup_A_E_negedge_posedge              :   VitalDelayType := 0.000 ns;
6794 
                thold_A_E_negedge_posedge               :   VitalDelayType := 0.000 ns;
6795 
                tsetup_S_E_posedge_posedge              :   VitalDelayType := 0.000 ns;
6796 
                thold_S_E_posedge_posedge               :   VitalDelayType := 0.000 ns;
6797 
                tsetup_S_E_negedge_posedge              :   VitalDelayType := 0.000 ns;
6798 
                thold_S_E_negedge_posedge               :   VitalDelayType := 0.000 ns;
6799 
                tsetup_B_E_posedge_posedge              :   VitalDelayType := 0.000 ns;
6800 
                thold_B_E_posedge_posedge               :   VitalDelayType := 0.000 ns;
6801 
                tsetup_B_E_negedge_posedge              :   VitalDelayType := 0.000 ns;
6802 
                thold_B_E_negedge_posedge               :   VitalDelayType := 0.000 ns;
6803 
                tsetup_E_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6804 
                thold_E_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6805 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6806 
                tpw_E_negedge           :  VitalDelayType := 0.000 ns;
6807 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6808 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6809 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6810 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6811 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6812 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6813 
 
6814 
 
6815 
 --pragma translate_on
6816 
    port(
6817 
                A               :  in    STD_ULOGIC;
6818 
                S               :  in    STD_ULOGIC;
6819 
                B               :  in    STD_ULOGIC;
6820 
                E               :  in    STD_ULOGIC;
6821 
                G               :  in    STD_ULOGIC;
6822 
                Q               :  out    STD_ULOGIC);
6823 
 
6824 
 end component;
6825 
 
6826 
 
6827 
------ Component DLP1 ------
6828 
 component DLP1
6829 
--pragma translate_off
6830 
    generic(
6831 
                TimingChecksOn: Boolean := True;
6832 
                InstancePath: STRING := "*";
6833 
                Xon: Boolean := False;
6834 
                MsgOn: Boolean := True;
6835 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6836 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6837 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6838 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6839 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6840 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6841 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6842 
                thold_PRE_G_negedge_negedge             :   VitalDelayType := 0.000 ns;
6843 
                trecovery_PRE_G_negedge_negedge         :   VitalDelayType := 0.000 ns;
6844 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
6845 
                tpw_PRE_posedge         :  VitalDelayType := 0.000 ns;
6846 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
6847 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6848 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6849 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6850 
 
6851 
 
6852 
 --pragma translate_on
6853 
    port(
6854 
                D               :  in    STD_ULOGIC;
6855 
                PRE             :  in    STD_ULOGIC;
6856 
                G               :  in    STD_ULOGIC;
6857 
                Q               :  out    STD_ULOGIC);
6858 
 
6859 
 end component;
6860 
 
6861 
 
6862 
------ Component DLP1A ------
6863 
 component DLP1A
6864 
--pragma translate_off
6865 
    generic(
6866 
                TimingChecksOn: Boolean := True;
6867 
                InstancePath: STRING := "*";
6868 
                Xon: Boolean := False;
6869 
                MsgOn: Boolean := True;
6870 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6871 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6872 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6873 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6874 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6875 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6876 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6877 
                thold_PRE_G_negedge_posedge             :   VitalDelayType := 0.000 ns;
6878 
                trecovery_PRE_G_negedge_posedge         :   VitalDelayType := 0.000 ns;
6879 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6880 
                tpw_PRE_posedge         :  VitalDelayType := 0.000 ns;
6881 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6882 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6883 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6884 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6885 
 
6886 
 
6887 
 --pragma translate_on
6888 
    port(
6889 
                D               :  in    STD_ULOGIC;
6890 
                PRE             :  in    STD_ULOGIC;
6891 
                G               :  in    STD_ULOGIC;
6892 
                Q               :  out    STD_ULOGIC);
6893 
 
6894 
 end component;
6895 
 
6896 
 
6897 
------ Component DLP1B ------
6898 
 component DLP1B
6899 
--pragma translate_off
6900 
    generic(
6901 
                TimingChecksOn: Boolean := True;
6902 
                InstancePath: STRING := "*";
6903 
                Xon: Boolean := False;
6904 
                MsgOn: Boolean := True;
6905 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6906 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6907 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6908 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6909 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6910 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6911 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6912 
                thold_PRE_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6913 
                trecovery_PRE_G_posedge_negedge         :   VitalDelayType := 0.000 ns;
6914 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
6915 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
6916 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
6917 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6918 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6919 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6920 
 
6921 
 
6922 
 --pragma translate_on
6923 
    port(
6924 
                D               :  in    STD_ULOGIC;
6925 
                PRE             :  in    STD_ULOGIC;
6926 
                G               :  in    STD_ULOGIC;
6927 
                Q               :  out    STD_ULOGIC);
6928 
 
6929 
 end component;
6930 
 
6931 
 
6932 
------ Component DLP1C ------
6933 
 component DLP1C
6934 
--pragma translate_off
6935 
    generic(
6936 
                TimingChecksOn: Boolean := True;
6937 
                InstancePath: STRING := "*";
6938 
                Xon: Boolean := False;
6939 
                MsgOn: Boolean := True;
6940 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6941 
                tpd_G_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6942 
                tpd_D_Q         :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6943 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
6944 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
6945 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
6946 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
6947 
                thold_PRE_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
6948 
                trecovery_PRE_G_posedge_posedge         :   VitalDelayType := 0.000 ns;
6949 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
6950 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
6951 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
6952 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6953 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6954 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6955 
 
6956 
 
6957 
 --pragma translate_on
6958 
    port(
6959 
                D               :  in    STD_ULOGIC;
6960 
                PRE             :  in    STD_ULOGIC;
6961 
                G               :  in    STD_ULOGIC;
6962 
                Q               :  out    STD_ULOGIC);
6963 
 
6964 
 end component;
6965 
 
6966 
 
6967 
------ Component DLP1D ------
6968 
 component DLP1D
6969 
--pragma translate_off
6970 
    generic(
6971 
                TimingChecksOn: Boolean := True;
6972 
                InstancePath: STRING := "*";
6973 
                Xon: Boolean := False;
6974 
                MsgOn: Boolean := True;
6975 
                tpd_PRE_QN              :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6976 
                tpd_G_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6977 
                tpd_D_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
6978 
                tsetup_D_G_posedge_negedge              :   VitalDelayType := 0.000 ns;
6979 
                thold_D_G_posedge_negedge               :   VitalDelayType := 0.000 ns;
6980 
                tsetup_D_G_negedge_negedge              :   VitalDelayType := 0.000 ns;
6981 
                thold_D_G_negedge_negedge               :   VitalDelayType := 0.000 ns;
6982 
                thold_PRE_G_posedge_negedge             :   VitalDelayType := 0.000 ns;
6983 
                trecovery_PRE_G_posedge_negedge         :   VitalDelayType := 0.000 ns;
6984 
                tperiod_G_negedge               :VitalDelayType := 0.000 ns;
6985 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
6986 
                tpw_G_posedge           :  VitalDelayType := 0.000 ns;
6987 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6988 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
6989 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
6990 
 
6991 
 
6992 
 --pragma translate_on
6993 
    port(
6994 
                D               :  in    STD_ULOGIC;
6995 
                PRE             :  in    STD_ULOGIC;
6996 
                G               :  in    STD_ULOGIC;
6997 
                QN              :  out    STD_ULOGIC);
6998 
 
6999 
 end component;
7000 
 
7001 
 
7002 
------ Component DLP1E ------
7003 
 component DLP1E
7004 
--pragma translate_off
7005 
    generic(
7006 
                TimingChecksOn: Boolean := True;
7007 
                InstancePath: STRING := "*";
7008 
                Xon: Boolean := False;
7009 
                MsgOn: Boolean := True;
7010 
                tpd_PRE_QN              :  VitalDelayType01 := (0.100 ns, 0.100 ns);
7011 
                tpd_G_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
7012 
                tpd_D_QN                :  VitalDelayType01 := (0.100 ns, 0.100 ns);
7013 
                tsetup_D_G_posedge_posedge              :   VitalDelayType := 0.000 ns;
7014 
                thold_D_G_posedge_posedge               :   VitalDelayType := 0.000 ns;
7015 
                tsetup_D_G_negedge_posedge              :   VitalDelayType := 0.000 ns;
7016 
                thold_D_G_negedge_posedge               :   VitalDelayType := 0.000 ns;
7017 
                thold_PRE_G_posedge_posedge             :   VitalDelayType := 0.000 ns;
7018 
                trecovery_PRE_G_posedge_posedge         :   VitalDelayType := 0.000 ns;
7019 
                tperiod_G_posedge               :  VitalDelayType := 0.000 ns;
7020 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
7021 
                tpw_G_negedge           :  VitalDelayType := 0.000 ns;
7022 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
7023 
                tipd_G          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
7024 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns));
7025 
 
7026 
 
7027 
 --pragma translate_on
7028 
    port(
7029 
                D               :  in    STD_ULOGIC;
7030 
                PRE             :  in    STD_ULOGIC;
7031 
                G               :  in    STD_ULOGIC;
7032 
                QN              :  out    STD_ULOGIC);
7033 
 
7034 
 end component;
7035 
 
7036 
 
7037 
------ Component FA1 ------
7038 
 component FA1
7039 
--pragma translate_off
7040 
    generic(
7041 
                TimingChecksOn:Boolean := True;
7042 
                Xon: Boolean := False;
7043 
                InstancePath: STRING :="*";
7044 
                MsgOn: Boolean := True;
7045 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7046 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7047 
                tpd_CI_S                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7048 
                tpd_A_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7049 
                tpd_B_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7050 
                tpd_CI_CO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7051 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7052 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7053 
                tipd_CI         : VitalDelayType01 := (0.000 ns, 0.000 ns));
7054 
 
7055 
 
7056 
--pragma translate_on
7057 
    port(
7058 
                A               : in    STD_ULOGIC;
7059 
                B               : in    STD_ULOGIC;
7060 
                CI              : in    STD_ULOGIC;
7061 
                S               : out    STD_ULOGIC;
7062 
                CO              : out    STD_ULOGIC);
7063 
 end component;
7064 
 
7065 
 
7066 
------ Component FCEND_BUFF ------
7067 
 component FCEND_BUFF
7068 
--pragma translate_off
7069 
    generic(
7070 
                TimingChecksOn:Boolean := True;
7071 
                Xon: Boolean := False;
7072 
                InstancePath: STRING :="*";
7073 
                MsgOn: Boolean := True;
7074 
                tpd_FCI_CO              : VitalDelayType01 := (0.100 ns, 0.100 ns);
7075 
                tipd_FCI                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7076 
 
7077 
 
7078 
--pragma translate_on
7079 
    port(
7080 
                FCI             : in    STD_ULOGIC;
7081 
                CO              : out    STD_ULOGIC);
7082 
 end component;
7083 
 
7084 
 
7085 
------ Component FCEND_INV ------
7086 
 component FCEND_INV
7087 
--pragma translate_off
7088 
    generic(
7089 
                TimingChecksOn:Boolean := True;
7090 
                Xon: Boolean := False;
7091 
                InstancePath: STRING :="*";
7092 
                MsgOn: Boolean := True;
7093 
                tpd_FCI_CO              : VitalDelayType01 := (0.100 ns, 0.100 ns);
7094 
                tipd_FCI                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7095 
 
7096 
 
7097 
--pragma translate_on
7098 
    port(
7099 
                FCI             : in    STD_ULOGIC;
7100 
                CO              : out    STD_ULOGIC);
7101 
 end component;
7102 
 
7103 
 
7104 
------ Component FCINIT_BUFF ------
7105 
 component FCINIT_BUFF
7106 
--pragma translate_off
7107 
    generic(
7108 
                TimingChecksOn:Boolean := True;
7109 
                Xon: Boolean := False;
7110 
                InstancePath: STRING :="*";
7111 
                MsgOn: Boolean := True;
7112 
                tpd_A_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7113 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7114 
 
7115 
 
7116 
--pragma translate_on
7117 
    port(
7118 
                A               : in    STD_ULOGIC;
7119 
                FCO             : out    STD_ULOGIC);
7120 
 end component;
7121 
 
7122 
 
7123 
------ Component FCINIT_GND ------
7124 
 component FCINIT_GND
7125 
--pragma translate_off
7126 
    generic(
7127 
                TimingChecksOn:Boolean := True;
7128 
                Xon: Boolean := False;
7129 
                InstancePath: STRING :="*";
7130 
                MsgOn: Boolean := True          );
7131 
--pragma translate_on
7132 
    port(
7133 
                FCO             : out    STD_ULOGIC);
7134 
 end component;
7135 
 
7136 
 
7137 
------ Component FCINIT_INV ------
7138 
 component FCINIT_INV
7139 
--pragma translate_off
7140 
    generic(
7141 
                TimingChecksOn:Boolean := True;
7142 
                Xon: Boolean := False;
7143 
                InstancePath: STRING :="*";
7144 
                MsgOn: Boolean := True;
7145 
                tpd_A_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7146 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7147 
 
7148 
 
7149 
--pragma translate_on
7150 
    port(
7151 
                A               : in    STD_ULOGIC;
7152 
                FCO             : out    STD_ULOGIC);
7153 
 end component;
7154 
 
7155 
 
7156 
------ Component FCINIT_VCC ------
7157 
 component FCINIT_VCC
7158 
--pragma translate_off
7159 
    generic(
7160 
                TimingChecksOn:Boolean := True;
7161 
                Xon: Boolean := False;
7162 
                InstancePath: STRING :="*";
7163 
                MsgOn: Boolean := True          );
7164 
--pragma translate_on
7165 
    port(
7166 
                FCO             : out    STD_ULOGIC);
7167 
 end component;
7168 
 
7169 
 
7170 
------ Component GAND2 ------
7171 
 component GAND2
7172 
--pragma translate_off
7173 
    generic(
7174 
                TimingChecksOn:Boolean := True;
7175 
                Xon: Boolean := False;
7176 
                InstancePath: STRING :="*";
7177 
                MsgOn: Boolean := True;
7178 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7179 
                tpd_G_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7180 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7181 
                tipd_G          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7182 
 
7183 
 
7184 
--pragma translate_on
7185 
    port(
7186 
                A               : in    STD_ULOGIC;
7187 
                G               : in    STD_ULOGIC;
7188 
                Y               : out    STD_ULOGIC);
7189 
 end component;
7190 
 
7191 
 
7192 
------ Component GMX4 ------
7193 
 component GMX4
7194 
--pragma translate_off
7195 
    generic(
7196 
                TimingChecksOn:Boolean := True;
7197 
                Xon: Boolean := False;
7198 
                InstancePath: STRING :="*";
7199 
                MsgOn: Boolean := True;
7200 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7201 
                tpd_S0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7202 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7203 
                tpd_G_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7204 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7205 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7206 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
7207 
                tipd_S0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
7208 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
7209 
                tipd_G          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7210 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
7211 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
7212 
 
7213 
 
7214 
--pragma translate_on
7215 
    port(
7216 
                D0              : in    STD_ULOGIC;
7217 
                S0              : in    STD_ULOGIC;
7218 
                D1              : in    STD_ULOGIC;
7219 
                G               : in    STD_ULOGIC;
7220 
                D2              : in    STD_ULOGIC;
7221 
                D3              : in    STD_ULOGIC;
7222 
                Y               : out    STD_ULOGIC);
7223 
 end component;
7224 
 
7225 
 
7226 
------ Component GNAND2 ------
7227 
 component GNAND2
7228 
--pragma translate_off
7229 
    generic(
7230 
                TimingChecksOn:Boolean := True;
7231 
                Xon: Boolean := False;
7232 
                InstancePath: STRING :="*";
7233 
                MsgOn: Boolean := True;
7234 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7235 
                tpd_G_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7236 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7237 
                tipd_G          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7238 
 
7239 
 
7240 
--pragma translate_on
7241 
    port(
7242 
                A               : in    STD_ULOGIC;
7243 
                G               : in    STD_ULOGIC;
7244 
                Y               : out    STD_ULOGIC);
7245 
 end component;
7246 
 
7247 
 
7248 
------ Component GND ------
7249 
 component GND
7250 
--pragma translate_off
7251 
    generic(
7252 
                TimingChecksOn:Boolean := True;
7253 
                Xon: Boolean := False;
7254 
                InstancePath: STRING :="*";
7255 
                MsgOn: Boolean := True          );
7256 
--pragma translate_on
7257 
    port(
7258 
                Y               : out    STD_ULOGIC);
7259 
 end component;
7260 
 
7261 
 
7262 
------ Component GNOR2 ------
7263 
 component GNOR2
7264 
--pragma translate_off
7265 
    generic(
7266 
                TimingChecksOn:Boolean := True;
7267 
                Xon: Boolean := False;
7268 
                InstancePath: STRING :="*";
7269 
                MsgOn: Boolean := True;
7270 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7271 
                tpd_G_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7272 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7273 
                tipd_G          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7274 
 
7275 
 
7276 
--pragma translate_on
7277 
    port(
7278 
                A               : in    STD_ULOGIC;
7279 
                G               : in    STD_ULOGIC;
7280 
                Y               : out    STD_ULOGIC);
7281 
 end component;
7282 
 
7283 
 
7284 
------ Component GOR2 ------
7285 
 component GOR2
7286 
--pragma translate_off
7287 
    generic(
7288 
                TimingChecksOn:Boolean := True;
7289 
                Xon: Boolean := False;
7290 
                InstancePath: STRING :="*";
7291 
                MsgOn: Boolean := True;
7292 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7293 
                tpd_G_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7294 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7295 
                tipd_G          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7296 
 
7297 
 
7298 
--pragma translate_on
7299 
    port(
7300 
                A               : in    STD_ULOGIC;
7301 
                G               : in    STD_ULOGIC;
7302 
                Y               : out    STD_ULOGIC);
7303 
 end component;
7304 
 
7305 
 
7306 
------ Component GXOR2 ------
7307 
 component GXOR2
7308 
--pragma translate_off
7309 
    generic(
7310 
                TimingChecksOn:Boolean := True;
7311 
                Xon: Boolean := False;
7312 
                InstancePath: STRING :="*";
7313 
                MsgOn: Boolean := True;
7314 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7315 
                tpd_G_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7316 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7317 
                tipd_G          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7318 
 
7319 
 
7320 
--pragma translate_on
7321 
    port(
7322 
                A               : in    STD_ULOGIC;
7323 
                G               : in    STD_ULOGIC;
7324 
                Y               : out    STD_ULOGIC);
7325 
 end component;
7326 
 
7327 
 
7328 
------ Component HA1 ------
7329 
 component HA1
7330 
--pragma translate_off
7331 
    generic(
7332 
                TimingChecksOn:Boolean := True;
7333 
                Xon: Boolean := False;
7334 
                InstancePath: STRING :="*";
7335 
                MsgOn: Boolean := True;
7336 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7337 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7338 
                tpd_A_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7339 
                tpd_B_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7340 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7341 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7342 
 
7343 
 
7344 
--pragma translate_on
7345 
    port(
7346 
                A               : in    STD_ULOGIC;
7347 
                B               : in    STD_ULOGIC;
7348 
                S               : out    STD_ULOGIC;
7349 
                CO              : out    STD_ULOGIC);
7350 
 end component;
7351 
 
7352 
 
7353 
------ Component HA1A ------
7354 
 component HA1A
7355 
--pragma translate_off
7356 
    generic(
7357 
                TimingChecksOn:Boolean := True;
7358 
                Xon: Boolean := False;
7359 
                InstancePath: STRING :="*";
7360 
                MsgOn: Boolean := True;
7361 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7362 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7363 
                tpd_A_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7364 
                tpd_B_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7365 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7366 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7367 
 
7368 
 
7369 
--pragma translate_on
7370 
    port(
7371 
                A               : in    STD_ULOGIC;
7372 
                B               : in    STD_ULOGIC;
7373 
                S               : out    STD_ULOGIC;
7374 
                CO              : out    STD_ULOGIC);
7375 
 end component;
7376 
 
7377 
 
7378 
------ Component HA1B ------
7379 
 component HA1B
7380 
--pragma translate_off
7381 
    generic(
7382 
                TimingChecksOn:Boolean := True;
7383 
                Xon: Boolean := False;
7384 
                InstancePath: STRING :="*";
7385 
                MsgOn: Boolean := True;
7386 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7387 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7388 
                tpd_A_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7389 
                tpd_B_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7390 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7391 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7392 
 
7393 
 
7394 
--pragma translate_on
7395 
    port(
7396 
                A               : in    STD_ULOGIC;
7397 
                B               : in    STD_ULOGIC;
7398 
                S               : out    STD_ULOGIC;
7399 
                CO              : out    STD_ULOGIC);
7400 
 end component;
7401 
 
7402 
 
7403 
------ Component HA1C ------
7404 
 component HA1C
7405 
--pragma translate_off
7406 
    generic(
7407 
                TimingChecksOn:Boolean := True;
7408 
                Xon: Boolean := False;
7409 
                InstancePath: STRING :="*";
7410 
                MsgOn: Boolean := True;
7411 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7412 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7413 
                tpd_A_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7414 
                tpd_B_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
7415 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
7416 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7417 
 
7418 
 
7419 
--pragma translate_on
7420 
    port(
7421 
                A               : in    STD_ULOGIC;
7422 
                B               : in    STD_ULOGIC;
7423 
                S               : out    STD_ULOGIC;
7424 
                CO              : out    STD_ULOGIC);
7425 
 end component;
7426 
 
7427 
 
7428 
------ Component HCLKBIBUF ------
7429 
 component HCLKBIBUF
7430 
--pragma translate_off
7431 
    generic(
7432 
                TimingChecksOn:Boolean := True;
7433 
                Xon: Boolean := False;
7434 
                InstancePath: STRING :="*";
7435 
                MsgOn: Boolean := True;
7436 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7437 
               tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
7438 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7439 
                tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
7440 
                tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
7441 
                tipd_D                  : VitalDelayType01 := (0.000 ns, 0.000 ns);
7442 
                tipd_E                  : VitalDelayType01 := (0.000 ns, 0.000 ns);
7443 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7444 
 
7445 
 
7446 
--pragma translate_on
7447 
    port(
7448 
                PAD             : inout  STD_ULOGIC;
7449 
                D               : in     STD_ULOGIC;
7450 
                E               : in     STD_ULOGIC;
7451 
                Y               : out    STD_ULOGIC);
7452 
 end component;
7453 
 
7454 
 
7455 
------ Component HCLKBUF ------
7456 
 component HCLKBUF
7457 
--pragma translate_off
7458 
    generic(
7459 
                TimingChecksOn:Boolean := True;
7460 
                Xon: Boolean := False;
7461 
                InstancePath: STRING :="*";
7462 
                MsgOn: Boolean := True;
7463 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7464 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7465 
 
7466 
 
7467 
--pragma translate_on
7468 
    port(
7469 
                PAD             : in    STD_ULOGIC;
7470 
                Y               : out    STD_ULOGIC);
7471 
 end component;
7472 
 
7473 
 
7474 
------ Component HCLKBUF_LVCMOS25 ------
7475 
 component HCLKBUF_LVCMOS25
7476 
--pragma translate_off
7477 
    generic(
7478 
                TimingChecksOn:Boolean := True;
7479 
                Xon: Boolean := False;
7480 
                InstancePath: STRING :="*";
7481 
                MsgOn: Boolean := True;
7482 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7483 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7484 
 
7485 
 
7486 
--pragma translate_on
7487 
    port(
7488 
                PAD             : in    STD_ULOGIC;
7489 
                Y               : out    STD_ULOGIC);
7490 
 end component;
7491 
 
7492 
 
7493 
------ Component HCLKBUF_LVCMOS18 ------
7494 
 component HCLKBUF_LVCMOS18
7495 
--pragma translate_off
7496 
    generic(
7497 
                TimingChecksOn:Boolean := True;
7498 
                Xon: Boolean := False;
7499 
                InstancePath: STRING :="*";
7500 
                MsgOn: Boolean := True;
7501 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7502 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7503 
 
7504 
 
7505 
--pragma translate_on
7506 
    port(
7507 
                PAD             : in    STD_ULOGIC;
7508 
                Y               : out    STD_ULOGIC);
7509 
 end component;
7510 
 
7511 
 
7512 
------ Component HCLKBUF_LVCMOS15 ------
7513 
 component HCLKBUF_LVCMOS15
7514 
--pragma translate_off
7515 
    generic(
7516 
                TimingChecksOn:Boolean := True;
7517 
                Xon: Boolean := False;
7518 
                InstancePath: STRING :="*";
7519 
                MsgOn: Boolean := True;
7520 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7521 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7522 
 
7523 
 
7524 
--pragma translate_on
7525 
    port(
7526 
                PAD             : in    STD_ULOGIC;
7527 
                Y               : out    STD_ULOGIC);
7528 
 end component;
7529 
 
7530 
 
7531 
------ Component HCLKBUF_PCI ------
7532 
 component HCLKBUF_PCI
7533 
--pragma translate_off
7534 
    generic(
7535 
                TimingChecksOn:Boolean := True;
7536 
                Xon: Boolean := False;
7537 
                InstancePath: STRING :="*";
7538 
                MsgOn: Boolean := True;
7539 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7540 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7541 
 
7542 
 
7543 
--pragma translate_on
7544 
    port(
7545 
                PAD             : in    STD_ULOGIC;
7546 
                Y               : out    STD_ULOGIC);
7547 
 end component;
7548 
 
7549 
 
7550 
------ Component HCLKBUF_PCIX ------
7551 
 component HCLKBUF_PCIX
7552 
--pragma translate_off
7553 
    generic(
7554 
                TimingChecksOn:Boolean := True;
7555 
                Xon: Boolean := False;
7556 
                InstancePath: STRING :="*";
7557 
                MsgOn: Boolean := True;
7558 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7559 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7560 
 
7561 
 
7562 
--pragma translate_on
7563 
    port(
7564 
                PAD             : in    STD_ULOGIC;
7565 
                Y               : out    STD_ULOGIC);
7566 
 end component;
7567 
 
7568 
 
7569 
------ Component HCLKBUF_GTLP33 ------
7570 
 component HCLKBUF_GTLP33
7571 
--pragma translate_off
7572 
    generic(
7573 
                TimingChecksOn:Boolean := True;
7574 
                Xon: Boolean := False;
7575 
                InstancePath: STRING :="*";
7576 
                MsgOn: Boolean := True;
7577 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7578 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7579 
 
7580 
 
7581 
--pragma translate_on
7582 
    port(
7583 
                PAD             : in    STD_ULOGIC;
7584 
                Y               : out    STD_ULOGIC);
7585 
 end component;
7586 
 
7587 
 
7588 
------ Component HCLKBUF_GTLP25 ------
7589 
 component HCLKBUF_GTLP25
7590 
--pragma translate_off
7591 
    generic(
7592 
                TimingChecksOn:Boolean := True;
7593 
                Xon: Boolean := False;
7594 
                InstancePath: STRING :="*";
7595 
                MsgOn: Boolean := True;
7596 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7597 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7598 
 
7599 
 
7600 
--pragma translate_on
7601 
    port(
7602 
                PAD             : in    STD_ULOGIC;
7603 
                Y               : out    STD_ULOGIC);
7604 
 end component;
7605 
 
7606 
 
7607 
------ Component HCLKBUF_HSTL_I ------
7608 
 component HCLKBUF_HSTL_I
7609 
--pragma translate_off
7610 
    generic(
7611 
                TimingChecksOn:Boolean := True;
7612 
                Xon: Boolean := False;
7613 
                InstancePath: STRING :="*";
7614 
                MsgOn: Boolean := True;
7615 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7616 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7617 
 
7618 
 
7619 
--pragma translate_on
7620 
    port(
7621 
                PAD             : in    STD_ULOGIC;
7622 
                Y               : out    STD_ULOGIC);
7623 
 end component;
7624 
 
7625 
 
7626 
------ Component HCLKBUF_SSTL3_I ------
7627 
 component HCLKBUF_SSTL3_I
7628 
--pragma translate_off
7629 
    generic(
7630 
                TimingChecksOn:Boolean := True;
7631 
                Xon: Boolean := False;
7632 
                InstancePath: STRING :="*";
7633 
                MsgOn: Boolean := True;
7634 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7635 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7636 
 
7637 
 
7638 
--pragma translate_on
7639 
    port(
7640 
                PAD             : in    STD_ULOGIC;
7641 
                Y               : out    STD_ULOGIC);
7642 
 end component;
7643 
 
7644 
 
7645 
------ Component HCLKBUF_SSTL3_II ------
7646 
 component HCLKBUF_SSTL3_II
7647 
--pragma translate_off
7648 
    generic(
7649 
                TimingChecksOn:Boolean := True;
7650 
                Xon: Boolean := False;
7651 
                InstancePath: STRING :="*";
7652 
                MsgOn: Boolean := True;
7653 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7654 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7655 
 
7656 
 
7657 
--pragma translate_on
7658 
    port(
7659 
                PAD             : in    STD_ULOGIC;
7660 
                Y               : out    STD_ULOGIC);
7661 
 end component;
7662 
 
7663 
 
7664 
------ Component HCLKBUF_SSTL2_I ------
7665 
 component HCLKBUF_SSTL2_I
7666 
--pragma translate_off
7667 
    generic(
7668 
                TimingChecksOn:Boolean := True;
7669 
                Xon: Boolean := False;
7670 
                InstancePath: STRING :="*";
7671 
                MsgOn: Boolean := True;
7672 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7673 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7674 
 
7675 
 
7676 
--pragma translate_on
7677 
    port(
7678 
                PAD             : in    STD_ULOGIC;
7679 
                Y               : out    STD_ULOGIC);
7680 
 end component;
7681 
 
7682 
 
7683 
------ Component HCLKBUF_SSTL2_II ------
7684 
 component HCLKBUF_SSTL2_II
7685 
--pragma translate_off
7686 
    generic(
7687 
                TimingChecksOn:Boolean := True;
7688 
                Xon: Boolean := False;
7689 
                InstancePath: STRING :="*";
7690 
                MsgOn: Boolean := True;
7691 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7692 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7693 
 
7694 
 
7695 
--pragma translate_on
7696 
    port(
7697 
                PAD             : in    STD_ULOGIC;
7698 
                Y               : out    STD_ULOGIC);
7699 
 end component;
7700 
 
7701 
 
7702 
------ Component HCLKINT ------
7703 
 component HCLKINT
7704 
--pragma translate_off
7705 
    generic(
7706 
                TimingChecksOn:Boolean := True;
7707 
                Xon: Boolean := False;
7708 
                InstancePath: STRING :="*";
7709 
                MsgOn: Boolean := True;
7710 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
7711 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
7712 
 
7713 
 
7714 
--pragma translate_on
7715 
    port(
7716 
                A               : in    STD_ULOGIC;
7717 
                Y               : out    STD_ULOGIC);
7718 
 end component;
7719 
 
7720 
 
7721 
------ Component INBUF ------
7722 
 component INBUF
7723 
--pragma translate_off
7724 
    generic(
7725 
                TimingChecksOn:Boolean := True;
7726 
                Xon: Boolean := False;
7727 
                InstancePath: STRING :="*";
7728 
                MsgOn: Boolean := True;
7729 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7730 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7731 
 
7732 
 
7733 
--pragma translate_on
7734 
    port(
7735 
                PAD             : in    STD_ULOGIC;
7736 
                Y               : out    STD_ULOGIC);
7737 
 end component;
7738 
 
7739 
 
7740 
------ Component INBUF_LVCMOS25 ------
7741 
 component INBUF_LVCMOS25
7742 
--pragma translate_off
7743 
    generic(
7744 
                TimingChecksOn:Boolean := True;
7745 
                Xon: Boolean := False;
7746 
                InstancePath: STRING :="*";
7747 
                MsgOn: Boolean := True;
7748 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7749 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7750 
 
7751 
 
7752 
--pragma translate_on
7753 
    port(
7754 
                PAD             : in    STD_ULOGIC;
7755 
                Y               : out    STD_ULOGIC);
7756 
 end component;
7757 
 
7758 
 
7759 
------ Component INBUF_LVCMOS25D ------
7760 
 component INBUF_LVCMOS25D
7761 
--pragma translate_off
7762 
    generic(
7763 
                TimingChecksOn:Boolean := True;
7764 
                Xon: Boolean := False;
7765 
                InstancePath: STRING :="*";
7766 
                MsgOn: Boolean := True;
7767 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7768 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7769 
 
7770 
 
7771 
--pragma translate_on
7772 
    port(
7773 
                PAD             : in    STD_ULOGIC;
7774 
                Y               : out    STD_ULOGIC);
7775 
 end component;
7776 
 
7777 
 
7778 
------ Component INBUF_LVCMOS25U ------
7779 
 component INBUF_LVCMOS25U
7780 
--pragma translate_off
7781 
    generic(
7782 
                TimingChecksOn:Boolean := True;
7783 
                Xon: Boolean := False;
7784 
                InstancePath: STRING :="*";
7785 
                MsgOn: Boolean := True;
7786 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7787 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7788 
 
7789 
 
7790 
--pragma translate_on
7791 
    port(
7792 
                PAD             : in    STD_ULOGIC;
7793 
                Y               : out    STD_ULOGIC);
7794 
 end component;
7795 
 
7796 
 
7797 
------ Component INBUF_LVCMOS18 ------
7798 
 component INBUF_LVCMOS18
7799 
--pragma translate_off
7800 
    generic(
7801 
                TimingChecksOn:Boolean := True;
7802 
                Xon: Boolean := False;
7803 
                InstancePath: STRING :="*";
7804 
                MsgOn: Boolean := True;
7805 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7806 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7807 
 
7808 
 
7809 
--pragma translate_on
7810 
    port(
7811 
                PAD             : in    STD_ULOGIC;
7812 
                Y               : out    STD_ULOGIC);
7813 
 end component;
7814 
 
7815 
 
7816 
------ Component INBUF_LVCMOS18D ------
7817 
 component INBUF_LVCMOS18D
7818 
--pragma translate_off
7819 
    generic(
7820 
                TimingChecksOn:Boolean := True;
7821 
                Xon: Boolean := False;
7822 
                InstancePath: STRING :="*";
7823 
                MsgOn: Boolean := True;
7824 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7825 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7826 
 
7827 
 
7828 
--pragma translate_on
7829 
    port(
7830 
                PAD             : in    STD_ULOGIC;
7831 
                Y               : out    STD_ULOGIC);
7832 
 end component;
7833 
 
7834 
 
7835 
------ Component INBUF_LVCMOS18U ------
7836 
 component INBUF_LVCMOS18U
7837 
--pragma translate_off
7838 
    generic(
7839 
                TimingChecksOn:Boolean := True;
7840 
                Xon: Boolean := False;
7841 
                InstancePath: STRING :="*";
7842 
                MsgOn: Boolean := True;
7843 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7844 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7845 
 
7846 
 
7847 
--pragma translate_on
7848 
    port(
7849 
                PAD             : in    STD_ULOGIC;
7850 
                Y               : out    STD_ULOGIC);
7851 
 end component;
7852 
 
7853 
 
7854 
------ Component INBUF_LVCMOS15 ------
7855 
 component INBUF_LVCMOS15
7856 
--pragma translate_off
7857 
    generic(
7858 
                TimingChecksOn:Boolean := True;
7859 
                Xon: Boolean := False;
7860 
                InstancePath: STRING :="*";
7861 
                MsgOn: Boolean := True;
7862 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7863 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7864 
 
7865 
 
7866 
--pragma translate_on
7867 
    port(
7868 
                PAD             : in    STD_ULOGIC;
7869 
                Y               : out    STD_ULOGIC);
7870 
 end component;
7871 
 
7872 
 
7873 
------ Component INBUF_LVCMOS15D ------
7874 
 component INBUF_LVCMOS15D
7875 
--pragma translate_off
7876 
    generic(
7877 
                TimingChecksOn:Boolean := True;
7878 
                Xon: Boolean := False;
7879 
                InstancePath: STRING :="*";
7880 
                MsgOn: Boolean := True;
7881 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7882 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7883 
 
7884 
 
7885 
--pragma translate_on
7886 
    port(
7887 
                PAD             : in    STD_ULOGIC;
7888 
                Y               : out    STD_ULOGIC);
7889 
 end component;
7890 
 
7891 
 
7892 
------ Component INBUF_LVCMOS15U ------
7893 
 component INBUF_LVCMOS15U
7894 
--pragma translate_off
7895 
    generic(
7896 
                TimingChecksOn:Boolean := True;
7897 
                Xon: Boolean := False;
7898 
                InstancePath: STRING :="*";
7899 
                MsgOn: Boolean := True;
7900 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7901 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7902 
 
7903 
 
7904 
--pragma translate_on
7905 
    port(
7906 
                PAD             : in    STD_ULOGIC;
7907 
                Y               : out    STD_ULOGIC);
7908 
 end component;
7909 
 
7910 
 
7911 
------ Component INBUF_PCI ------
7912 
 component INBUF_PCI
7913 
--pragma translate_off
7914 
    generic(
7915 
                TimingChecksOn:Boolean := True;
7916 
                Xon: Boolean := False;
7917 
                InstancePath: STRING :="*";
7918 
                MsgOn: Boolean := True;
7919 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7920 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7921 
 
7922 
 
7923 
--pragma translate_on
7924 
    port(
7925 
                PAD             : in    STD_ULOGIC;
7926 
                Y               : out    STD_ULOGIC);
7927 
 end component;
7928 
 
7929 
 
7930 
------ Component INBUF_PCIX ------
7931 
 component INBUF_PCIX
7932 
--pragma translate_off
7933 
    generic(
7934 
                TimingChecksOn:Boolean := True;
7935 
                Xon: Boolean := False;
7936 
                InstancePath: STRING :="*";
7937 
                MsgOn: Boolean := True;
7938 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7939 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7940 
 
7941 
 
7942 
--pragma translate_on
7943 
    port(
7944 
                PAD             : in    STD_ULOGIC;
7945 
                Y               : out    STD_ULOGIC);
7946 
 end component;
7947 
 
7948 
 
7949 
------ Component INBUF_GTLP33 ------
7950 
 component INBUF_GTLP33
7951 
--pragma translate_off
7952 
    generic(
7953 
                TimingChecksOn:Boolean := True;
7954 
                Xon: Boolean := False;
7955 
                InstancePath: STRING :="*";
7956 
                MsgOn: Boolean := True;
7957 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7958 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7959 
 
7960 
 
7961 
--pragma translate_on
7962 
    port(
7963 
                PAD             : in    STD_ULOGIC;
7964 
                Y               : out    STD_ULOGIC);
7965 
 end component;
7966 
 
7967 
 
7968 
------ Component INBUF_GTLP25 ------
7969 
 component INBUF_GTLP25
7970 
--pragma translate_off
7971 
    generic(
7972 
                TimingChecksOn:Boolean := True;
7973 
                Xon: Boolean := False;
7974 
                InstancePath: STRING :="*";
7975 
                MsgOn: Boolean := True;
7976 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7977 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7978 
 
7979 
 
7980 
--pragma translate_on
7981 
    port(
7982 
                PAD             : in    STD_ULOGIC;
7983 
                Y               : out    STD_ULOGIC);
7984 
 end component;
7985 
 
7986 
 
7987 
------ Component INBUF_HSTL_I ------
7988 
 component INBUF_HSTL_I
7989 
--pragma translate_off
7990 
    generic(
7991 
                TimingChecksOn:Boolean := True;
7992 
                Xon: Boolean := False;
7993 
                InstancePath: STRING :="*";
7994 
                MsgOn: Boolean := True;
7995 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
7996 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
7997 
 
7998 
 
7999 
--pragma translate_on
8000 
    port(
8001 
                PAD             : in    STD_ULOGIC;
8002 
                Y               : out    STD_ULOGIC);
8003 
 end component;
8004 
 
8005 
 
8006 
------ Component INBUF_SSTL3_I ------
8007 
 component INBUF_SSTL3_I
8008 
--pragma translate_off
8009 
    generic(
8010 
                TimingChecksOn:Boolean := True;
8011 
                Xon: Boolean := False;
8012 
                InstancePath: STRING :="*";
8013 
                MsgOn: Boolean := True;
8014 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8015 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
8016 
 
8017 
 
8018 
--pragma translate_on
8019 
    port(
8020 
                PAD             : in    STD_ULOGIC;
8021 
                Y               : out    STD_ULOGIC);
8022 
 end component;
8023 
 
8024 
 
8025 
------ Component INBUF_SSTL3_II ------
8026 
 component INBUF_SSTL3_II
8027 
--pragma translate_off
8028 
    generic(
8029 
                TimingChecksOn:Boolean := True;
8030 
                Xon: Boolean := False;
8031 
                InstancePath: STRING :="*";
8032 
                MsgOn: Boolean := True;
8033 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8034 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
8035 
 
8036 
 
8037 
--pragma translate_on
8038 
    port(
8039 
                PAD             : in    STD_ULOGIC;
8040 
                Y               : out    STD_ULOGIC);
8041 
 end component;
8042 
 
8043 
 
8044 
------ Component INBUF_SSTL2_I ------
8045 
 component INBUF_SSTL2_I
8046 
--pragma translate_off
8047 
    generic(
8048 
                TimingChecksOn:Boolean := True;
8049 
                Xon: Boolean := False;
8050 
                InstancePath: STRING :="*";
8051 
                MsgOn: Boolean := True;
8052 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8053 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
8054 
 
8055 
 
8056 
--pragma translate_on
8057 
    port(
8058 
                PAD             : in    STD_ULOGIC;
8059 
                Y               : out    STD_ULOGIC);
8060 
 end component;
8061 
 
8062 
 
8063 
------ Component INBUF_SSTL2_II ------
8064 
 component INBUF_SSTL2_II
8065 
--pragma translate_off
8066 
    generic(
8067 
                TimingChecksOn:Boolean := True;
8068 
                Xon: Boolean := False;
8069 
                InstancePath: STRING :="*";
8070 
                MsgOn: Boolean := True;
8071 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8072 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
8073 
 
8074 
 
8075 
--pragma translate_on
8076 
    port(
8077 
                PAD             : in    STD_ULOGIC;
8078 
                Y               : out    STD_ULOGIC);
8079 
 end component;
8080 
 
8081 
 
8082 
------ Component INV ------
8083 
 component INV
8084 
--pragma translate_off
8085 
    generic(
8086 
                TimingChecksOn:Boolean := True;
8087 
                Xon: Boolean := False;
8088 
                InstancePath: STRING :="*";
8089 
                MsgOn: Boolean := True;
8090 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8091 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8092 
 
8093 
 
8094 
--pragma translate_on
8095 
    port(
8096 
                A               : in    STD_ULOGIC;
8097 
                Y               : out    STD_ULOGIC);
8098 
 end component;
8099 
 
8100 
 
8101 
------ Component INVA ------
8102 
 component INVA
8103 
--pragma translate_off
8104 
    generic(
8105 
                TimingChecksOn:Boolean := True;
8106 
                Xon: Boolean := False;
8107 
                InstancePath: STRING :="*";
8108 
                MsgOn: Boolean := True;
8109 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8110 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8111 
 
8112 
 
8113 
--pragma translate_on
8114 
    port(
8115 
                A               : in    STD_ULOGIC;
8116 
                Y               : out    STD_ULOGIC);
8117 
 end component;
8118 
 
8119 
 
8120 
------ Component INVD ------
8121 
 component INVD
8122 
--pragma translate_off
8123 
    generic(
8124 
                TimingChecksOn:Boolean := True;
8125 
                Xon: Boolean := False;
8126 
                InstancePath: STRING :="*";
8127 
                MsgOn: Boolean := True;
8128 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8129 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8130 
 
8131 
 
8132 
--pragma translate_on
8133 
    port(
8134 
                A               : in    STD_ULOGIC;
8135 
                Y               : out    STD_ULOGIC);
8136 
 end component;
8137 
 
8138 
 
8139 
------ Component IOI_DFEG ------
8140 
 component IOI_DFEG
8141 
--pragma translate_off
8142 
    generic(
8143 
                TimingChecksOn: Boolean := True;
8144 
                InstancePath: STRING := "*";
8145 
                Xon: Boolean := False;
8146 
                MsgOn: Boolean := True;
8147 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8148 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8149 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8150 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
8151 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
8152 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
8153 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
8154 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
8155 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
8156 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
8157 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
8158 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
8159 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
8160 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
8161 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
8162 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
8163 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
8164 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
8165 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
8166 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8167 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8168 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8169 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8170 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
8171 
 
8172 
 
8173 
--pragma translate_on
8174 
    port(
8175 
                CLR             :   in    STD_ULOGIC;
8176 
                PRE             :   in    STD_ULOGIC;
8177 
                E               :   in    STD_ULOGIC;
8178 
                CLK             :   in    STD_ULOGIC;
8179 
                D               :  in    STD_ULOGIC;
8180 
                Q               :  out    STD_ULOGIC);
8181 
 
8182 
 end component;
8183 
 
8184 
 
8185 
------ Component IOI_DFEH ------
8186 
 component IOI_DFEH
8187 
--pragma translate_off
8188 
    generic(
8189 
                TimingChecksOn: Boolean := True;
8190 
                InstancePath: STRING := "*";
8191 
                Xon: Boolean := False;
8192 
                MsgOn: Boolean := True;
8193 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8194 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8195 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8196 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
8197 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
8198 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
8199 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
8200 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
8201 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
8202 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
8203 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
8204 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
8205 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
8206 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
8207 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
8208 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
8209 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
8210 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
8211 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
8212 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8213 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8214 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8215 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8216 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
8217 
 
8218 
 
8219 
--pragma translate_on
8220 
    port(
8221 
                CLR             :   in    STD_ULOGIC;
8222 
                PRE             :   in    STD_ULOGIC;
8223 
                E               :   in    STD_ULOGIC;
8224 
                CLK             :   in    STD_ULOGIC;
8225 
                D               :  in    STD_ULOGIC;
8226 
                Q               :  out    STD_ULOGIC);
8227 
 
8228 
 end component;
8229 
 
8230 
 
8231 
------ Component IOI_BUFF ------
8232 
 component IOI_BUFF
8233 
--pragma translate_off
8234 
    generic(
8235 
                TimingChecksOn:Boolean := True;
8236 
                Xon: Boolean := False;
8237 
                InstancePath: STRING :="*";
8238 
                MsgOn: Boolean := True;
8239 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8240 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8241 
 
8242 
 
8243 
--pragma translate_on
8244 
    port(
8245 
                A               : in    STD_ULOGIC;
8246 
                Y               : out    STD_ULOGIC);
8247 
 end component;
8248 
 
8249 
 
8250 
------ Component IOOE_BUFF ------
8251 
 component IOOE_BUFF
8252 
--pragma translate_off
8253 
    generic(
8254 
                TimingChecksOn:Boolean := True;
8255 
                Xon: Boolean := False;
8256 
                InstancePath: STRING :="*";
8257 
                MsgOn: Boolean := True;
8258 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8259 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8260 
 
8261 
 
8262 
--pragma translate_on
8263 
    port(
8264 
                A               : in    STD_ULOGIC;
8265 
                Y               : out    STD_ULOGIC);
8266 
 end component;
8267 
 
8268 
 
8269 
------ Component IOOE_DFEG ------
8270 
 component IOOE_DFEG
8271 
        generic(
8272 
                TimingChecksOn: Boolean := True;
8273 
                InstancePath: STRING := "*";
8274 
                Xon: Boolean := False;
8275 
                MsgOn: Boolean := True;
8276 
                tpd_CLK_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8277 
                tpd_PRE_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8278 
                tpd_CLR_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8279 
                tpd_CLK_YOUT    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8280 
                tpd_PRE_YOUT    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8281 
                tpd_CLR_YOUT    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8282 
                tsetup_D_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
8283 
                tsetup_D_CLK_negedge_posedge   :   VitalDelayType := 0.000 ns;
8284 
                thold_D_CLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
8285 
                thold_D_CLK_negedge_posedge       :   VitalDelayType := 0.000 ns;
8286 
                tperiod_CLK_negedge        :  VitalDelayType := 0.000 ns;
8287 
                tpw_CLK_posedge        :  VitalDelayType := 0.000 ns;
8288 
                tpw_CLK_negedge        :  VitalDelayType := 0.000 ns;
8289 
                trecovery_CLR_CLK_posedge_posedge       :   VitalDelayType := 0.000 ns;
8290 
                thold_CLR_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
8291 
                tpw_CLR_negedge :  VitalDelayType := 0.000 ns;
8292 
                tsetup_E_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
8293 
                tsetup_E_CLK_negedge_posedge   :   VitalDelayType := 0.000 ns;
8294 
                thold_E_CLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
8295 
                thold_E_CLK_negedge_posedge       :   VitalDelayType := 0.000 ns;
8296 
                trecovery_PRE_CLK_posedge_posedge       :   VitalDelayType := 0.000 ns;
8297 
                thold_PRE_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
8298 
                tpw_PRE_negedge :  VitalDelayType := 0.000 ns;
8299 
                tipd_D :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8300 
                tipd_CLK :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8301 
                tipd_CLR :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8302 
                tipd_E :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8303 
                tipd_PRE :   VitalDelayType01 := (0.000 ns, 0.000 ns));
8304 
--pragma translate_on
8305 
    port(
8306 
                D         : in    STD_ULOGIC;
8307 
                CLK         : in    STD_ULOGIC;
8308 
                CLR         : in    STD_ULOGIC;
8309 
                E         : in    STD_ULOGIC;
8310 
                PRE         : in    STD_ULOGIC;
8311 
                Q                : out    STD_ULOGIC;
8312 
                YOUT                : out    STD_ULOGIC);
8313 
 end component;
8314 
 
8315 
 
8316 
------ Component IOOE_DFEH ------
8317 
 component IOOE_DFEH
8318 
        generic(
8319 
                TimingChecksOn: Boolean := True;
8320 
                InstancePath: STRING := "*";
8321 
                Xon: Boolean := False;
8322 
                MsgOn: Boolean := True;
8323 
                tpd_CLK_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8324 
                tpd_PRE_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8325 
                tpd_CLR_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8326 
                tpd_CLK_YOUT    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8327 
                tpd_PRE_YOUT    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8328 
                tpd_CLR_YOUT    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8329 
                tsetup_D_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
8330 
                tsetup_D_CLK_negedge_negedge   :   VitalDelayType := 0.000 ns;
8331 
                thold_D_CLK_posedge_negedge     :   VitalDelayType := 0.000 ns;
8332 
                thold_D_CLK_negedge_negedge       :   VitalDelayType := 0.000 ns;
8333 
                tperiod_CLK_negedge        :  VitalDelayType := 0.000 ns;
8334 
                tpw_CLK_posedge        :  VitalDelayType := 0.000 ns;
8335 
                tpw_CLK_negedge        :  VitalDelayType := 0.000 ns;
8336 
                trecovery_CLR_CLK_posedge_negedge       :   VitalDelayType := 0.000 ns;
8337 
                thold_CLR_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
8338 
                tpw_CLR_negedge :  VitalDelayType := 0.000 ns;
8339 
                tsetup_E_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
8340 
                tsetup_E_CLK_negedge_negedge   :   VitalDelayType := 0.000 ns;
8341 
                thold_E_CLK_posedge_negedge     :   VitalDelayType := 0.000 ns;
8342 
                thold_E_CLK_negedge_negedge       :   VitalDelayType := 0.000 ns;
8343 
                trecovery_PRE_CLK_posedge_negedge       :   VitalDelayType := 0.000 ns;
8344 
                thold_PRE_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
8345 
                tpw_PRE_negedge :  VitalDelayType := 0.000 ns;
8346 
                tipd_D :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8347 
                tipd_CLK :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8348 
                tipd_CLR :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8349 
                tipd_E :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8350 
                tipd_PRE :   VitalDelayType01 := (0.000 ns, 0.000 ns));
8351 
--pragma translate_on
8352 
    port(
8353 
                D         : in    STD_ULOGIC;
8354 
                CLK         : in    STD_ULOGIC;
8355 
                CLR         : in    STD_ULOGIC;
8356 
                E         : in    STD_ULOGIC;
8357 
                PRE         : in    STD_ULOGIC;
8358 
                Q                : out    STD_ULOGIC;
8359 
                YOUT                : out    STD_ULOGIC);
8360 
 end component;
8361 
 
8362 
 
8363 
------ Component IOPAD_IN ------
8364 
 component IOPAD_IN
8365 
--pragma translate_off
8366 
    generic(
8367 
                TimingChecksOn:Boolean := True;
8368 
                Xon: Boolean := False;
8369 
                InstancePath: STRING :="*";
8370 
                MsgOn: Boolean := True;
8371 
-- DNW: Add the following 2 lines
8372 
                tpw_PAD_posedge         : VitalDelayType := 0.000 ns;
8373 
                tpw_PAD_negedge         : VitalDelayType := 0.000 ns;
8374 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8375 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
8376 
 
8377 
 
8378 
--pragma translate_on
8379 
    port(
8380 
                PAD             : in    STD_ULOGIC;
8381 
                Y               : out    STD_ULOGIC);
8382 
 end component;
8383 
 
8384 
 
8385 
------ Component IOPAD_TRI ------
8386 
 component IOPAD_TRI
8387 
--pragma translate_off
8388 
    generic(
8389 
                TimingChecksOn:Boolean := True;
8390 
                Xon: Boolean := False;
8391 
                InstancePath: STRING :="*";
8392 
                MsgOn: Boolean := True;
8393 
                tpw_D_posedge   : VitalDelayType := 0.000 ns;
8394 
                tpw_D_negedge   : VitalDelayType := 0.000 ns;
8395 
                tpw_E_posedge   : VitalDelayType := 0.000 ns;
8396 
                tpw_E_negedge   : VitalDelayType := 0.000 ns;
8397 
 
8398 
                tpd_D_PAD       : VitalDelayType01 := (0.100 ns, 0.100 ns);
8399 
                tpd_E_PAD       : VitalDelayType01Z := (0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns);
8400 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8401 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8402 
 
8403 
 
8404 
--pragma translate_on
8405 
    port(
8406 
                D               : in    STD_ULOGIC;
8407 
                E               : in    STD_ULOGIC;
8408 
                PAD             : out    STD_ULOGIC);
8409 
 end component;
8410 
 
8411 
 
8412 
------ Component IOPAD_BI ------
8413 
 component IOPAD_BI
8414 
--pragma translate_off
8415 
    generic(
8416 
                TimingChecksOn:Boolean := True;
8417 
                Xon: Boolean := False;
8418 
                InstancePath: STRING :="*";
8419 
                MsgOn: Boolean := True;
8420 
 
8421 
                tpw_D_posedge           : VitalDelayType := 0.000 ns;
8422 
                tpw_D_negedge           : VitalDelayType := 0.000 ns;
8423 
                tpw_E_posedge           : VitalDelayType := 0.000 ns;
8424 
                tpw_E_negedge           : VitalDelayType := 0.000 ns;
8425 
                tpw_PAD_negedge         : VitalDelayType := 0.000 ns;
8426 
                tpw_PAD_posedge         : VitalDelayType := 0.000 ns;
8427 
 
8428 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8429 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
8430 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8431 
                tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
8432 
                tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
8433 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8434 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8435 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
8436 
 
8437 
 
8438 
--pragma translate_on
8439 
    port(
8440 
                D               : in    STD_ULOGIC;
8441 
                E               : in    STD_ULOGIC;
8442 
                PAD             : inout STD_ULOGIC;
8443 
                Y               : out    STD_ULOGIC);
8444 
 end component;
8445 
 
8446 
 
8447 
------ Component JKF ------
8448 
 component JKF
8449 
--pragma translate_off
8450 
    generic(
8451 
                TimingChecksOn: Boolean := True;
8452 
                InstancePath: STRING := "*";
8453 
                Xon: Boolean := False;
8454 
                MsgOn: Boolean := True;
8455 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8456 
                tsetup_J_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
8457 
                thold_J_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
8458 
                tsetup_J_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
8459 
                thold_J_CLK_negedge_posedge   :   VitalDelayType := 0.000 ns;
8460 
                tsetup_K_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
8461 
                thold_K_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
8462 
                tsetup_K_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
8463 
                thold_K_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
8464 
                tpw_CLK_posedge         :  VitalDelayType := 0.000 ns;
8465 
                tpw_CLK_negedge         :  VitalDelayType := 0.000 ns;
8466 
                tipd_J      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8467 
                tipd_K      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8468 
                tipd_CLK        :   VitalDelayType01 := (0.000 ns, 0.000 ns));
8469 
 
8470 
 
8471 
--pragma translate_on
8472 
    port(
8473 
                J       :  in    STD_ULOGIC;
8474 
                K       :  in    STD_ULOGIC;
8475 
                CLK     :  in    STD_ULOGIC;
8476 
                Q       :  out    STD_ULOGIC);
8477 
 
8478 
 end component;
8479 
 
8480 
 
8481 
------ Component JKF1B ------
8482 
 component JKF1B
8483 
--pragma translate_off
8484 
    generic(
8485 
                TimingChecksOn: Boolean := True;
8486 
                InstancePath: STRING := "*";
8487 
                Xon: Boolean := False;
8488 
                MsgOn: Boolean := True;
8489 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8490 
                tsetup_J_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
8491 
                thold_J_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
8492 
                tsetup_J_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
8493 
                thold_J_CLK_negedge_negedge   :   VitalDelayType := 0.000 ns;
8494 
                tsetup_K_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
8495 
                thold_K_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
8496 
                tsetup_K_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
8497 
                thold_K_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
8498 
                tpw_CLK_posedge         :  VitalDelayType := 0.000 ns;
8499 
                tpw_CLK_negedge         :  VitalDelayType := 0.000 ns;
8500 
                tipd_J      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8501 
                tipd_K      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8502 
                tipd_CLK        :   VitalDelayType01 := (0.000 ns, 0.000 ns));
8503 
 
8504 
 
8505 
--pragma translate_on
8506 
    port(
8507 
                J       :  in    STD_ULOGIC;
8508 
                K       :  in    STD_ULOGIC;
8509 
                CLK     :  in    STD_ULOGIC;
8510 
                Q       :  out    STD_ULOGIC);
8511 
 
8512 
 end component;
8513 
 
8514 
 
8515 
------ Component JKF2A ------
8516 
 component JKF2A
8517 
--pragma translate_off
8518 
    generic(
8519 
                TimingChecksOn: Boolean := True;
8520 
                InstancePath: STRING := "*";
8521 
                Xon: Boolean := False;
8522 
                MsgOn: Boolean := True;
8523 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8524 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8525 
                tsetup_J_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
8526 
                thold_J_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
8527 
                tsetup_J_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
8528 
                thold_J_CLK_negedge_posedge   :   VitalDelayType := 0.000 ns;
8529 
                tsetup_K_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
8530 
                thold_K_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
8531 
                tsetup_K_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
8532 
                thold_K_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
8533 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
8534 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
8535 
                tpw_CLK_posedge         :  VitalDelayType := 0.000 ns;
8536 
                tpw_CLK_negedge         :  VitalDelayType := 0.000 ns;
8537 
                tpw_CLR_negedge :  VitalDelayType := 0.000 ns;
8538 
                tipd_CLR        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8539 
                tipd_J      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8540 
                tipd_K      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8541 
                tipd_CLK        :   VitalDelayType01 := (0.000 ns, 0.000 ns));
8542 
 
8543 
 
8544 
--pragma translate_on
8545 
    port(
8546 
                J       :  in    STD_ULOGIC;
8547 
                K       :  in    STD_ULOGIC;
8548 
                CLR     :  in    STD_ULOGIC;
8549 
                CLK     :  in    STD_ULOGIC;
8550 
                Q       :  out    STD_ULOGIC);
8551 
 
8552 
 end component;
8553 
 
8554 
 
8555 
------ Component JKF2B ------
8556 
 component JKF2B
8557 
--pragma translate_off
8558 
    generic(
8559 
                TimingChecksOn: Boolean := True;
8560 
                InstancePath: STRING := "*";
8561 
                Xon: Boolean := False;
8562 
                MsgOn: Boolean := True;
8563 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8564 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8565 
                tsetup_J_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
8566 
                thold_J_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
8567 
                tsetup_J_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
8568 
                thold_J_CLK_negedge_negedge   :   VitalDelayType := 0.000 ns;
8569 
                tsetup_K_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
8570 
                thold_K_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
8571 
                tsetup_K_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
8572 
                thold_K_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
8573 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
8574 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
8575 
                tpw_CLK_posedge         :  VitalDelayType := 0.000 ns;
8576 
                tpw_CLK_negedge         :  VitalDelayType := 0.000 ns;
8577 
                tpw_CLR_negedge :  VitalDelayType := 0.000 ns;
8578 
                tipd_CLR        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8579 
                tipd_J      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8580 
                tipd_K      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8581 
                tipd_CLK        :   VitalDelayType01 := (0.000 ns, 0.000 ns));
8582 
 
8583 
 
8584 
--pragma translate_on
8585 
    port(
8586 
                J       :  in    STD_ULOGIC;
8587 
                K       :  in    STD_ULOGIC;
8588 
                CLR     :  in    STD_ULOGIC;
8589 
                CLK     :  in    STD_ULOGIC;
8590 
                Q       :  out    STD_ULOGIC);
8591 
 
8592 
 end component;
8593 
 
8594 
 
8595 
------ Component JKF3A ------
8596 
 component JKF3A
8597 
--pragma translate_off
8598 
    generic(
8599 
                TimingChecksOn: Boolean := True;
8600 
                InstancePath: STRING := "*";
8601 
                Xon: Boolean := False;
8602 
                MsgOn: Boolean := True;
8603 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8604 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8605 
                tsetup_J_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
8606 
                thold_J_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
8607 
                tsetup_J_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
8608 
                thold_J_CLK_negedge_posedge   :   VitalDelayType := 0.000 ns;
8609 
                tsetup_K_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
8610 
                thold_K_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
8611 
                tsetup_K_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
8612 
                thold_K_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
8613 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
8614 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
8615 
                tpw_CLK_posedge         :  VitalDelayType := 0.000 ns;
8616 
                tpw_CLK_negedge         :  VitalDelayType := 0.000 ns;
8617 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
8618 
                tipd_PRE        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8619 
                tipd_J      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8620 
                tipd_K      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8621 
                tipd_CLK        :   VitalDelayType01 := (0.000 ns, 0.000 ns));
8622 
 
8623 
 
8624 
--pragma translate_on
8625 
    port(
8626 
                J       :  in    STD_ULOGIC;
8627 
                K       :  in    STD_ULOGIC;
8628 
                PRE     :  in    STD_ULOGIC;
8629 
                CLK     :  in    STD_ULOGIC;
8630 
                Q       :  out    STD_ULOGIC);
8631 
 
8632 
 end component;
8633 
 
8634 
 
8635 
------ Component JKF3B ------
8636 
 component JKF3B
8637 
--pragma translate_off
8638 
    generic(
8639 
                TimingChecksOn: Boolean := True;
8640 
                InstancePath: STRING := "*";
8641 
                Xon: Boolean := False;
8642 
                MsgOn: Boolean := True;
8643 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8644 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
8645 
                tsetup_J_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
8646 
                thold_J_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
8647 
                tsetup_J_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
8648 
                thold_J_CLK_negedge_negedge   :   VitalDelayType := 0.000 ns;
8649 
                tsetup_K_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
8650 
                thold_K_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
8651 
                tsetup_K_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
8652 
                thold_K_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
8653 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
8654 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
8655 
                tpw_CLK_posedge         :  VitalDelayType := 0.000 ns;
8656 
                tpw_CLK_negedge         :  VitalDelayType := 0.000 ns;
8657 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
8658 
                tipd_PRE        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8659 
                tipd_J      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8660 
                tipd_K      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
8661 
                tipd_CLK        :   VitalDelayType01 := (0.000 ns, 0.000 ns));
8662 
 
8663 
 
8664 
--pragma translate_on
8665 
    port(
8666 
                J       :  in    STD_ULOGIC;
8667 
                K       :  in    STD_ULOGIC;
8668 
                PRE     :  in    STD_ULOGIC;
8669 
                CLK     :  in    STD_ULOGIC;
8670 
                Q       :  out    STD_ULOGIC);
8671 
 
8672 
 end component;
8673 
 
8674 
 
8675 
------ Component MAJ3 ------
8676 
 component MAJ3
8677 
--pragma translate_off
8678 
    generic(
8679 
                TimingChecksOn:Boolean := True;
8680 
                Xon: Boolean := False;
8681 
                InstancePath: STRING :="*";
8682 
                MsgOn: Boolean := True;
8683 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8684 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8685 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8686 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8687 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8688 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8689 
 
8690 
 
8691 
--pragma translate_on
8692 
    port(
8693 
                A               : in    STD_ULOGIC;
8694 
                B               : in    STD_ULOGIC;
8695 
                C               : in    STD_ULOGIC;
8696 
                Y               : out    STD_ULOGIC);
8697 
 end component;
8698 
 
8699 
 
8700 
------ Component MAJ3X ------
8701 
 component MAJ3X
8702 
--pragma translate_off
8703 
    generic(
8704 
                TimingChecksOn:Boolean := True;
8705 
                Xon: Boolean := False;
8706 
                InstancePath: STRING :="*";
8707 
                MsgOn: Boolean := True;
8708 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8709 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8710 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8711 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8712 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8713 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8714 
 
8715 
 
8716 
--pragma translate_on
8717 
    port(
8718 
                A               : in    STD_ULOGIC;
8719 
                B               : in    STD_ULOGIC;
8720 
                C               : in    STD_ULOGIC;
8721 
                Y               : out    STD_ULOGIC);
8722 
 end component;
8723 
 
8724 
 
8725 
------ Component MAJ3XI ------
8726 
 component MAJ3XI
8727 
--pragma translate_off
8728 
    generic(
8729 
                TimingChecksOn:Boolean := True;
8730 
                Xon: Boolean := False;
8731 
                InstancePath: STRING :="*";
8732 
                MsgOn: Boolean := True;
8733 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8734 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8735 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8736 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8737 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8738 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8739 
 
8740 
 
8741 
--pragma translate_on
8742 
    port(
8743 
                A               : in    STD_ULOGIC;
8744 
                B               : in    STD_ULOGIC;
8745 
                C               : in    STD_ULOGIC;
8746 
                Y               : out    STD_ULOGIC);
8747 
 end component;
8748 
 
8749 
 
8750 
------ Component MIN3 ------
8751 
 component MIN3
8752 
--pragma translate_off
8753 
    generic(
8754 
                TimingChecksOn:Boolean := True;
8755 
                Xon: Boolean := False;
8756 
                InstancePath: STRING :="*";
8757 
                MsgOn: Boolean := True;
8758 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8759 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8760 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8761 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8762 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8763 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8764 
 
8765 
 
8766 
--pragma translate_on
8767 
    port(
8768 
                A               : in    STD_ULOGIC;
8769 
                B               : in    STD_ULOGIC;
8770 
                C               : in    STD_ULOGIC;
8771 
                Y               : out    STD_ULOGIC);
8772 
 end component;
8773 
 
8774 
 
8775 
------ Component MIN3X ------
8776 
 component MIN3X
8777 
--pragma translate_off
8778 
    generic(
8779 
                TimingChecksOn:Boolean := True;
8780 
                Xon: Boolean := False;
8781 
                InstancePath: STRING :="*";
8782 
                MsgOn: Boolean := True;
8783 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8784 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8785 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8786 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8787 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8788 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8789 
 
8790 
 
8791 
--pragma translate_on
8792 
    port(
8793 
                A               : in    STD_ULOGIC;
8794 
                B               : in    STD_ULOGIC;
8795 
                C               : in    STD_ULOGIC;
8796 
                Y               : out    STD_ULOGIC);
8797 
 end component;
8798 
 
8799 
 
8800 
------ Component MIN3XI ------
8801 
 component MIN3XI
8802 
--pragma translate_off
8803 
    generic(
8804 
                TimingChecksOn:Boolean := True;
8805 
                Xon: Boolean := False;
8806 
                InstancePath: STRING :="*";
8807 
                MsgOn: Boolean := True;
8808 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8809 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8810 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8811 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8812 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8813 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8814 
 
8815 
 
8816 
--pragma translate_on
8817 
    port(
8818 
                A               : in    STD_ULOGIC;
8819 
                B               : in    STD_ULOGIC;
8820 
                C               : in    STD_ULOGIC;
8821 
                Y               : out    STD_ULOGIC);
8822 
 end component;
8823 
 
8824 
 
8825 
------ Component MULT1 ------
8826 
 component MULT1
8827 
--pragma translate_off
8828 
    generic(
8829 
                TimingChecksOn:Boolean := True;
8830 
                Xon: Boolean := False;
8831 
                InstancePath: STRING :="*";
8832 
                MsgOn: Boolean := True;
8833 
                tpd_A_PO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
8834 
                tpd_B_PO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
8835 
                tpd_PI_PO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8836 
                tpd_FCI_PO              : VitalDelayType01 := (0.100 ns, 0.100 ns);
8837 
                tpd_A_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8838 
                tpd_B_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
8839 
                tpd_PI_FCO              : VitalDelayType01 := (0.100 ns, 0.100 ns);
8840 
                tpd_FCI_FCO             : VitalDelayType01 := (0.100 ns, 0.100 ns);
8841 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8842 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8843 
                tipd_PI         : VitalDelayType01 := (0.000 ns, 0.000 ns);
8844 
                tipd_FCI                : VitalDelayType01 := (0.000 ns, 0.000 ns));
8845 
 
8846 
 
8847 
--pragma translate_on
8848 
    port(
8849 
                A               : in    STD_ULOGIC;
8850 
                B               : in    STD_ULOGIC;
8851 
                PI              : in    STD_ULOGIC;
8852 
                FCI             : in    STD_ULOGIC;
8853 
                PO              : out    STD_ULOGIC;
8854 
                FCO             : out    STD_ULOGIC);
8855 
 end component;
8856 
 
8857 
 
8858 
------ Component MX2 ------
8859 
 component MX2
8860 
--pragma translate_off
8861 
    generic(
8862 
                TimingChecksOn:Boolean := True;
8863 
                Xon: Boolean := False;
8864 
                InstancePath: STRING :="*";
8865 
                MsgOn: Boolean := True;
8866 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8867 
                tpd_S_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8868 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8869 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8870 
                tipd_S          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8871 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8872 
 
8873 
 
8874 
--pragma translate_on
8875 
    port(
8876 
                A               : in    STD_ULOGIC;
8877 
                S               : in    STD_ULOGIC;
8878 
                B               : in    STD_ULOGIC;
8879 
                Y               : out    STD_ULOGIC);
8880 
 end component;
8881 
 
8882 
 
8883 
------ Component MX2A ------
8884 
 component MX2A
8885 
--pragma translate_off
8886 
    generic(
8887 
                TimingChecksOn:Boolean := True;
8888 
                Xon: Boolean := False;
8889 
                InstancePath: STRING :="*";
8890 
                MsgOn: Boolean := True;
8891 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8892 
                tpd_S_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8893 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8894 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8895 
                tipd_S          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8896 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8897 
 
8898 
 
8899 
--pragma translate_on
8900 
    port(
8901 
                A               : in    STD_ULOGIC;
8902 
                S               : in    STD_ULOGIC;
8903 
                B               : in    STD_ULOGIC;
8904 
                Y               : out    STD_ULOGIC);
8905 
 end component;
8906 
 
8907 
 
8908 
------ Component MX2B ------
8909 
 component MX2B
8910 
--pragma translate_off
8911 
    generic(
8912 
                TimingChecksOn:Boolean := True;
8913 
                Xon: Boolean := False;
8914 
                InstancePath: STRING :="*";
8915 
                MsgOn: Boolean := True;
8916 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8917 
                tpd_S_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8918 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8919 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8920 
                tipd_S          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8921 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8922 
 
8923 
 
8924 
--pragma translate_on
8925 
    port(
8926 
                A               : in    STD_ULOGIC;
8927 
                S               : in    STD_ULOGIC;
8928 
                B               : in    STD_ULOGIC;
8929 
                Y               : out    STD_ULOGIC);
8930 
 end component;
8931 
 
8932 
 
8933 
------ Component MX2C ------
8934 
 component MX2C
8935 
--pragma translate_off
8936 
    generic(
8937 
                TimingChecksOn:Boolean := True;
8938 
                Xon: Boolean := False;
8939 
                InstancePath: STRING :="*";
8940 
                MsgOn: Boolean := True;
8941 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8942 
                tpd_S_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8943 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
8944 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8945 
                tipd_S          : VitalDelayType01 := (0.000 ns, 0.000 ns);
8946 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
8947 
 
8948 
 
8949 
--pragma translate_on
8950 
    port(
8951 
                A               : in    STD_ULOGIC;
8952 
                S               : in    STD_ULOGIC;
8953 
                B               : in    STD_ULOGIC;
8954 
                Y               : out    STD_ULOGIC);
8955 
 end component;
8956 
 
8957 
 
8958 
------ Component MX4 ------
8959 
 component MX4
8960 
--pragma translate_off
8961 
    generic(
8962 
                TimingChecksOn:Boolean := True;
8963 
                Xon: Boolean := False;
8964 
                InstancePath: STRING :="*";
8965 
                MsgOn: Boolean := True;
8966 
                tpd_D0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
8967 
                tpd_S0_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
8968 
                tpd_D1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
8969 
                tpd_S1_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
8970 
                tpd_D2_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
8971 
                tpd_D3_Y                : VitalDelayType01 := (0.100 ns, 0.100 ns);
8972 
                tipd_D0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
8973 
                tipd_S0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
8974 
                tipd_D1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
8975 
                tipd_S1         : VitalDelayType01 := (0.000 ns, 0.000 ns);
8976 
                tipd_D2         : VitalDelayType01 := (0.000 ns, 0.000 ns);
8977 
                tipd_D3         : VitalDelayType01 := (0.000 ns, 0.000 ns));
8978 
 
8979 
 
8980 
--pragma translate_on
8981 
    port(
8982 
                D0              : in    STD_ULOGIC;
8983 
                S0              : in    STD_ULOGIC;
8984 
                D1              : in    STD_ULOGIC;
8985 
                S1              : in    STD_ULOGIC;
8986 
                D2              : in    STD_ULOGIC;
8987 
                D3              : in    STD_ULOGIC;
8988 
                Y               : out    STD_ULOGIC);
8989 
 end component;
8990 
 
8991 
 
8992 
------ Component NAND2 ------
8993 
 component NAND2
8994 
--pragma translate_off
8995 
    generic(
8996 
                TimingChecksOn:Boolean := True;
8997 
                Xon: Boolean := False;
8998 
                InstancePath: STRING :="*";
8999 
                MsgOn: Boolean := True;
9000 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9001 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9002 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9003 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9004 
 
9005 
 
9006 
--pragma translate_on
9007 
    port(
9008 
                A               : in    STD_ULOGIC;
9009 
                B               : in    STD_ULOGIC;
9010 
                Y               : out    STD_ULOGIC);
9011 
 end component;
9012 
 
9013 
 
9014 
------ Component NAND2A ------
9015 
 component NAND2A
9016 
--pragma translate_off
9017 
    generic(
9018 
                TimingChecksOn:Boolean := True;
9019 
                Xon: Boolean := False;
9020 
                InstancePath: STRING :="*";
9021 
                MsgOn: Boolean := True;
9022 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9023 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9024 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9025 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9026 
 
9027 
 
9028 
--pragma translate_on
9029 
    port(
9030 
                A               : in    STD_ULOGIC;
9031 
                B               : in    STD_ULOGIC;
9032 
                Y               : out    STD_ULOGIC);
9033 
 end component;
9034 
 
9035 
 
9036 
------ Component NAND2B ------
9037 
 component NAND2B
9038 
--pragma translate_off
9039 
    generic(
9040 
                TimingChecksOn:Boolean := True;
9041 
                Xon: Boolean := False;
9042 
                InstancePath: STRING :="*";
9043 
                MsgOn: Boolean := True;
9044 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9045 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9046 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9047 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9048 
 
9049 
 
9050 
--pragma translate_on
9051 
    port(
9052 
                A               : in    STD_ULOGIC;
9053 
                B               : in    STD_ULOGIC;
9054 
                Y               : out    STD_ULOGIC);
9055 
 end component;
9056 
 
9057 
 
9058 
------ Component NAND3 ------
9059 
 component NAND3
9060 
--pragma translate_off
9061 
    generic(
9062 
                TimingChecksOn:Boolean := True;
9063 
                Xon: Boolean := False;
9064 
                InstancePath: STRING :="*";
9065 
                MsgOn: Boolean := True;
9066 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9067 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9068 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9069 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9070 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9071 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9072 
 
9073 
 
9074 
--pragma translate_on
9075 
    port(
9076 
                A               : in    STD_ULOGIC;
9077 
                B               : in    STD_ULOGIC;
9078 
                C               : in    STD_ULOGIC;
9079 
                Y               : out    STD_ULOGIC);
9080 
 end component;
9081 
 
9082 
 
9083 
------ Component NAND3A ------
9084 
 component NAND3A
9085 
--pragma translate_off
9086 
    generic(
9087 
                TimingChecksOn:Boolean := True;
9088 
                Xon: Boolean := False;
9089 
                InstancePath: STRING :="*";
9090 
                MsgOn: Boolean := True;
9091 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9092 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9093 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9094 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9095 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9096 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9097 
 
9098 
 
9099 
--pragma translate_on
9100 
    port(
9101 
                A               : in    STD_ULOGIC;
9102 
                B               : in    STD_ULOGIC;
9103 
                C               : in    STD_ULOGIC;
9104 
                Y               : out    STD_ULOGIC);
9105 
 end component;
9106 
 
9107 
 
9108 
------ Component NAND3B ------
9109 
 component NAND3B
9110 
--pragma translate_off
9111 
    generic(
9112 
                TimingChecksOn:Boolean := True;
9113 
                Xon: Boolean := False;
9114 
                InstancePath: STRING :="*";
9115 
                MsgOn: Boolean := True;
9116 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9117 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9118 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9119 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9120 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9121 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9122 
 
9123 
 
9124 
--pragma translate_on
9125 
    port(
9126 
                A               : in    STD_ULOGIC;
9127 
                B               : in    STD_ULOGIC;
9128 
                C               : in    STD_ULOGIC;
9129 
                Y               : out    STD_ULOGIC);
9130 
 end component;
9131 
 
9132 
 
9133 
------ Component NAND3C ------
9134 
 component NAND3C
9135 
--pragma translate_off
9136 
    generic(
9137 
                TimingChecksOn:Boolean := True;
9138 
                Xon: Boolean := False;
9139 
                InstancePath: STRING :="*";
9140 
                MsgOn: Boolean := True;
9141 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9142 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9143 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9144 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9145 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9146 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9147 
 
9148 
 
9149 
--pragma translate_on
9150 
    port(
9151 
                A               : in    STD_ULOGIC;
9152 
                B               : in    STD_ULOGIC;
9153 
                C               : in    STD_ULOGIC;
9154 
                Y               : out    STD_ULOGIC);
9155 
 end component;
9156 
 
9157 
 
9158 
------ Component NAND4 ------
9159 
 component NAND4
9160 
--pragma translate_off
9161 
    generic(
9162 
                TimingChecksOn:Boolean := True;
9163 
                Xon: Boolean := False;
9164 
                InstancePath: STRING :="*";
9165 
                MsgOn: Boolean := True;
9166 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9167 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9168 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9169 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9170 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9171 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9172 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9173 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9174 
 
9175 
 
9176 
--pragma translate_on
9177 
    port(
9178 
                A               : in    STD_ULOGIC;
9179 
                B               : in    STD_ULOGIC;
9180 
                C               : in    STD_ULOGIC;
9181 
                D               : in    STD_ULOGIC;
9182 
                Y               : out    STD_ULOGIC);
9183 
 end component;
9184 
 
9185 
 
9186 
------ Component NAND4A ------
9187 
 component NAND4A
9188 
--pragma translate_off
9189 
    generic(
9190 
                TimingChecksOn:Boolean := True;
9191 
                Xon: Boolean := False;
9192 
                InstancePath: STRING :="*";
9193 
                MsgOn: Boolean := True;
9194 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9195 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9196 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9197 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9198 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9199 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9200 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9201 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9202 
 
9203 
 
9204 
--pragma translate_on
9205 
    port(
9206 
                A               : in    STD_ULOGIC;
9207 
                B               : in    STD_ULOGIC;
9208 
                C               : in    STD_ULOGIC;
9209 
                D               : in    STD_ULOGIC;
9210 
                Y               : out    STD_ULOGIC);
9211 
 end component;
9212 
 
9213 
 
9214 
------ Component NAND4B ------
9215 
 component NAND4B
9216 
--pragma translate_off
9217 
    generic(
9218 
                TimingChecksOn:Boolean := True;
9219 
                Xon: Boolean := False;
9220 
                InstancePath: STRING :="*";
9221 
                MsgOn: Boolean := True;
9222 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9223 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9224 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9225 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9226 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9227 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9228 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9229 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9230 
 
9231 
 
9232 
--pragma translate_on
9233 
    port(
9234 
                A               : in    STD_ULOGIC;
9235 
                B               : in    STD_ULOGIC;
9236 
                C               : in    STD_ULOGIC;
9237 
                D               : in    STD_ULOGIC;
9238 
                Y               : out    STD_ULOGIC);
9239 
 end component;
9240 
 
9241 
 
9242 
------ Component NAND4C ------
9243 
 component NAND4C
9244 
--pragma translate_off
9245 
    generic(
9246 
                TimingChecksOn:Boolean := True;
9247 
                Xon: Boolean := False;
9248 
                InstancePath: STRING :="*";
9249 
                MsgOn: Boolean := True;
9250 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9251 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9252 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9253 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9254 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9255 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9256 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9257 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9258 
 
9259 
 
9260 
--pragma translate_on
9261 
    port(
9262 
                A               : in    STD_ULOGIC;
9263 
                B               : in    STD_ULOGIC;
9264 
                C               : in    STD_ULOGIC;
9265 
                D               : in    STD_ULOGIC;
9266 
                Y               : out    STD_ULOGIC);
9267 
 end component;
9268 
 
9269 
 
9270 
------ Component NAND4D ------
9271 
 component NAND4D
9272 
--pragma translate_off
9273 
    generic(
9274 
                TimingChecksOn:Boolean := True;
9275 
                Xon: Boolean := False;
9276 
                InstancePath: STRING :="*";
9277 
                MsgOn: Boolean := True;
9278 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9279 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9280 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9281 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9282 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9283 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9284 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9285 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9286 
 
9287 
 
9288 
--pragma translate_on
9289 
    port(
9290 
                A               : in    STD_ULOGIC;
9291 
                B               : in    STD_ULOGIC;
9292 
                C               : in    STD_ULOGIC;
9293 
                D               : in    STD_ULOGIC;
9294 
                Y               : out    STD_ULOGIC);
9295 
 end component;
9296 
 
9297 
 
9298 
------ Component NAND5B ------
9299 
 component NAND5B
9300 
--pragma translate_off
9301 
    generic(
9302 
                TimingChecksOn:Boolean := True;
9303 
                Xon: Boolean := False;
9304 
                InstancePath: STRING :="*";
9305 
                MsgOn: Boolean := True;
9306 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9307 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9308 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9309 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9310 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9311 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9312 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9313 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9314 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9315 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9316 
 
9317 
 
9318 
--pragma translate_on
9319 
    port(
9320 
                A               : in    STD_ULOGIC;
9321 
                B               : in    STD_ULOGIC;
9322 
                C               : in    STD_ULOGIC;
9323 
                D               : in    STD_ULOGIC;
9324 
                E               : in    STD_ULOGIC;
9325 
                Y               : out    STD_ULOGIC);
9326 
 end component;
9327 
 
9328 
 
9329 
------ Component NAND5C ------
9330 
 component NAND5C
9331 
--pragma translate_off
9332 
    generic(
9333 
                TimingChecksOn:Boolean := True;
9334 
                Xon: Boolean := False;
9335 
                InstancePath: STRING :="*";
9336 
                MsgOn: Boolean := True;
9337 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9338 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9339 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9340 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9341 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9342 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9343 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9344 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9345 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9346 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9347 
 
9348 
 
9349 
--pragma translate_on
9350 
    port(
9351 
                A               : in    STD_ULOGIC;
9352 
                B               : in    STD_ULOGIC;
9353 
                C               : in    STD_ULOGIC;
9354 
                D               : in    STD_ULOGIC;
9355 
                E               : in    STD_ULOGIC;
9356 
                Y               : out    STD_ULOGIC);
9357 
 end component;
9358 
 
9359 
 
9360 
------ Component NOR2 ------
9361 
 component NOR2
9362 
--pragma translate_off
9363 
    generic(
9364 
                TimingChecksOn:Boolean := True;
9365 
                Xon: Boolean := False;
9366 
                InstancePath: STRING :="*";
9367 
                MsgOn: Boolean := True;
9368 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9369 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9370 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9371 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9372 
 
9373 
 
9374 
--pragma translate_on
9375 
    port(
9376 
                A               : in    STD_ULOGIC;
9377 
                B               : in    STD_ULOGIC;
9378 
                Y               : out    STD_ULOGIC);
9379 
 end component;
9380 
 
9381 
 
9382 
------ Component NOR2A ------
9383 
 component NOR2A
9384 
--pragma translate_off
9385 
    generic(
9386 
                TimingChecksOn:Boolean := True;
9387 
                Xon: Boolean := False;
9388 
                InstancePath: STRING :="*";
9389 
                MsgOn: Boolean := True;
9390 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9391 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9392 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9393 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9394 
 
9395 
 
9396 
--pragma translate_on
9397 
    port(
9398 
                A               : in    STD_ULOGIC;
9399 
                B               : in    STD_ULOGIC;
9400 
                Y               : out    STD_ULOGIC);
9401 
 end component;
9402 
 
9403 
 
9404 
------ Component NOR2B ------
9405 
 component NOR2B
9406 
--pragma translate_off
9407 
    generic(
9408 
                TimingChecksOn:Boolean := True;
9409 
                Xon: Boolean := False;
9410 
                InstancePath: STRING :="*";
9411 
                MsgOn: Boolean := True;
9412 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9413 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9414 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9415 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9416 
 
9417 
 
9418 
--pragma translate_on
9419 
    port(
9420 
                A               : in    STD_ULOGIC;
9421 
                B               : in    STD_ULOGIC;
9422 
                Y               : out    STD_ULOGIC);
9423 
 end component;
9424 
 
9425 
 
9426 
------ Component NOR3 ------
9427 
 component NOR3
9428 
--pragma translate_off
9429 
    generic(
9430 
                TimingChecksOn:Boolean := True;
9431 
                Xon: Boolean := False;
9432 
                InstancePath: STRING :="*";
9433 
                MsgOn: Boolean := True;
9434 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9435 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9436 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9437 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9438 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9439 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9440 
 
9441 
 
9442 
--pragma translate_on
9443 
    port(
9444 
                A               : in    STD_ULOGIC;
9445 
                B               : in    STD_ULOGIC;
9446 
                C               : in    STD_ULOGIC;
9447 
                Y               : out    STD_ULOGIC);
9448 
 end component;
9449 
 
9450 
 
9451 
------ Component NOR3A ------
9452 
 component NOR3A
9453 
--pragma translate_off
9454 
    generic(
9455 
                TimingChecksOn:Boolean := True;
9456 
                Xon: Boolean := False;
9457 
                InstancePath: STRING :="*";
9458 
                MsgOn: Boolean := True;
9459 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9460 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9461 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9462 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9463 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9464 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9465 
 
9466 
 
9467 
--pragma translate_on
9468 
    port(
9469 
                A               : in    STD_ULOGIC;
9470 
                B               : in    STD_ULOGIC;
9471 
                C               : in    STD_ULOGIC;
9472 
                Y               : out    STD_ULOGIC);
9473 
 end component;
9474 
 
9475 
 
9476 
------ Component NOR3B ------
9477 
 component NOR3B
9478 
--pragma translate_off
9479 
    generic(
9480 
                TimingChecksOn:Boolean := True;
9481 
                Xon: Boolean := False;
9482 
                InstancePath: STRING :="*";
9483 
                MsgOn: Boolean := True;
9484 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9485 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9486 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9487 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9488 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9489 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9490 
 
9491 
 
9492 
--pragma translate_on
9493 
    port(
9494 
                A               : in    STD_ULOGIC;
9495 
                B               : in    STD_ULOGIC;
9496 
                C               : in    STD_ULOGIC;
9497 
                Y               : out    STD_ULOGIC);
9498 
 end component;
9499 
 
9500 
 
9501 
------ Component NOR3C ------
9502 
 component NOR3C
9503 
--pragma translate_off
9504 
    generic(
9505 
                TimingChecksOn:Boolean := True;
9506 
                Xon: Boolean := False;
9507 
                InstancePath: STRING :="*";
9508 
                MsgOn: Boolean := True;
9509 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9510 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9511 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9512 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9513 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9514 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9515 
 
9516 
 
9517 
--pragma translate_on
9518 
    port(
9519 
                A               : in    STD_ULOGIC;
9520 
                B               : in    STD_ULOGIC;
9521 
                C               : in    STD_ULOGIC;
9522 
                Y               : out    STD_ULOGIC);
9523 
 end component;
9524 
 
9525 
 
9526 
------ Component NOR4 ------
9527 
 component NOR4
9528 
--pragma translate_off
9529 
    generic(
9530 
                TimingChecksOn:Boolean := True;
9531 
                Xon: Boolean := False;
9532 
                InstancePath: STRING :="*";
9533 
                MsgOn: Boolean := True;
9534 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9535 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9536 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9537 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9538 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9539 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9540 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9541 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9542 
 
9543 
 
9544 
--pragma translate_on
9545 
    port(
9546 
                A               : in    STD_ULOGIC;
9547 
                B               : in    STD_ULOGIC;
9548 
                C               : in    STD_ULOGIC;
9549 
                D               : in    STD_ULOGIC;
9550 
                Y               : out    STD_ULOGIC);
9551 
 end component;
9552 
 
9553 
 
9554 
------ Component NOR4A ------
9555 
 component NOR4A
9556 
--pragma translate_off
9557 
    generic(
9558 
                TimingChecksOn:Boolean := True;
9559 
                Xon: Boolean := False;
9560 
                InstancePath: STRING :="*";
9561 
                MsgOn: Boolean := True;
9562 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9563 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9564 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9565 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9566 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9567 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9568 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9569 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9570 
 
9571 
 
9572 
--pragma translate_on
9573 
    port(
9574 
                A               : in    STD_ULOGIC;
9575 
                B               : in    STD_ULOGIC;
9576 
                C               : in    STD_ULOGIC;
9577 
                D               : in    STD_ULOGIC;
9578 
                Y               : out    STD_ULOGIC);
9579 
 end component;
9580 
 
9581 
 
9582 
------ Component NOR4B ------
9583 
 component NOR4B
9584 
--pragma translate_off
9585 
    generic(
9586 
                TimingChecksOn:Boolean := True;
9587 
                Xon: Boolean := False;
9588 
                InstancePath: STRING :="*";
9589 
                MsgOn: Boolean := True;
9590 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9591 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9592 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9593 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9594 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9595 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9596 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9597 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9598 
 
9599 
 
9600 
--pragma translate_on
9601 
    port(
9602 
                A               : in    STD_ULOGIC;
9603 
                B               : in    STD_ULOGIC;
9604 
                C               : in    STD_ULOGIC;
9605 
                D               : in    STD_ULOGIC;
9606 
                Y               : out    STD_ULOGIC);
9607 
 end component;
9608 
 
9609 
 
9610 
------ Component NOR4C ------
9611 
 component NOR4C
9612 
--pragma translate_off
9613 
    generic(
9614 
                TimingChecksOn:Boolean := True;
9615 
                Xon: Boolean := False;
9616 
                InstancePath: STRING :="*";
9617 
                MsgOn: Boolean := True;
9618 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9619 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9620 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9621 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9622 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9623 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9624 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9625 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9626 
 
9627 
 
9628 
--pragma translate_on
9629 
    port(
9630 
                A               : in    STD_ULOGIC;
9631 
                B               : in    STD_ULOGIC;
9632 
                C               : in    STD_ULOGIC;
9633 
                D               : in    STD_ULOGIC;
9634 
                Y               : out    STD_ULOGIC);
9635 
 end component;
9636 
 
9637 
 
9638 
------ Component NOR4D ------
9639 
 component NOR4D
9640 
--pragma translate_off
9641 
    generic(
9642 
                TimingChecksOn:Boolean := True;
9643 
                Xon: Boolean := False;
9644 
                InstancePath: STRING :="*";
9645 
                MsgOn: Boolean := True;
9646 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9647 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9648 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9649 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9650 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9651 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9652 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9653 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9654 
 
9655 
 
9656 
--pragma translate_on
9657 
    port(
9658 
                A               : in    STD_ULOGIC;
9659 
                B               : in    STD_ULOGIC;
9660 
                C               : in    STD_ULOGIC;
9661 
                D               : in    STD_ULOGIC;
9662 
                Y               : out    STD_ULOGIC);
9663 
 end component;
9664 
 
9665 
 
9666 
------ Component NOR5B ------
9667 
 component NOR5B
9668 
--pragma translate_off
9669 
    generic(
9670 
                TimingChecksOn:Boolean := True;
9671 
                Xon: Boolean := False;
9672 
                InstancePath: STRING :="*";
9673 
                MsgOn: Boolean := True;
9674 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9675 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9676 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9677 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9678 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9679 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9680 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9681 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9682 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9683 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9684 
 
9685 
 
9686 
--pragma translate_on
9687 
    port(
9688 
                A               : in    STD_ULOGIC;
9689 
                B               : in    STD_ULOGIC;
9690 
                C               : in    STD_ULOGIC;
9691 
                D               : in    STD_ULOGIC;
9692 
                E               : in    STD_ULOGIC;
9693 
                Y               : out    STD_ULOGIC);
9694 
 end component;
9695 
 
9696 
 
9697 
------ Component NOR5C ------
9698 
 component NOR5C
9699 
--pragma translate_off
9700 
    generic(
9701 
                TimingChecksOn:Boolean := True;
9702 
                Xon: Boolean := False;
9703 
                InstancePath: STRING :="*";
9704 
                MsgOn: Boolean := True;
9705 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9706 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9707 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9708 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9709 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9710 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9711 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9712 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9713 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9714 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9715 
 
9716 
 
9717 
--pragma translate_on
9718 
    port(
9719 
                A               : in    STD_ULOGIC;
9720 
                B               : in    STD_ULOGIC;
9721 
                C               : in    STD_ULOGIC;
9722 
                D               : in    STD_ULOGIC;
9723 
                E               : in    STD_ULOGIC;
9724 
                Y               : out    STD_ULOGIC);
9725 
 end component;
9726 
 
9727 
 
9728 
------ Component OA1 ------
9729 
 component OA1
9730 
--pragma translate_off
9731 
    generic(
9732 
                TimingChecksOn:Boolean := True;
9733 
                Xon: Boolean := False;
9734 
                InstancePath: STRING :="*";
9735 
                MsgOn: Boolean := True;
9736 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9737 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9738 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9739 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9740 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9741 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9742 
 
9743 
 
9744 
--pragma translate_on
9745 
    port(
9746 
                A               : in    STD_ULOGIC;
9747 
                B               : in    STD_ULOGIC;
9748 
                C               : in    STD_ULOGIC;
9749 
                Y               : out    STD_ULOGIC);
9750 
 end component;
9751 
 
9752 
 
9753 
------ Component OA1A ------
9754 
 component OA1A
9755 
--pragma translate_off
9756 
    generic(
9757 
                TimingChecksOn:Boolean := True;
9758 
                Xon: Boolean := False;
9759 
                InstancePath: STRING :="*";
9760 
                MsgOn: Boolean := True;
9761 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9762 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9763 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9764 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9765 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9766 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9767 
 
9768 
 
9769 
--pragma translate_on
9770 
    port(
9771 
                A               : in    STD_ULOGIC;
9772 
                B               : in    STD_ULOGIC;
9773 
                C               : in    STD_ULOGIC;
9774 
                Y               : out    STD_ULOGIC);
9775 
 end component;
9776 
 
9777 
 
9778 
------ Component OA1B ------
9779 
 component OA1B
9780 
--pragma translate_off
9781 
    generic(
9782 
                TimingChecksOn:Boolean := True;
9783 
                Xon: Boolean := False;
9784 
                InstancePath: STRING :="*";
9785 
                MsgOn: Boolean := True;
9786 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9787 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9788 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9789 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9790 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9791 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9792 
 
9793 
 
9794 
--pragma translate_on
9795 
    port(
9796 
                C               : in    STD_ULOGIC;
9797 
                A               : in    STD_ULOGIC;
9798 
                B               : in    STD_ULOGIC;
9799 
                Y               : out    STD_ULOGIC);
9800 
 end component;
9801 
 
9802 
 
9803 
------ Component OA1C ------
9804 
 component OA1C
9805 
--pragma translate_off
9806 
    generic(
9807 
                TimingChecksOn:Boolean := True;
9808 
                Xon: Boolean := False;
9809 
                InstancePath: STRING :="*";
9810 
                MsgOn: Boolean := True;
9811 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9812 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9813 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9814 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9815 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9816 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9817 
 
9818 
 
9819 
--pragma translate_on
9820 
    port(
9821 
                C               : in    STD_ULOGIC;
9822 
                A               : in    STD_ULOGIC;
9823 
                B               : in    STD_ULOGIC;
9824 
                Y               : out    STD_ULOGIC);
9825 
 end component;
9826 
 
9827 
 
9828 
------ Component OA2 ------
9829 
 component OA2
9830 
--pragma translate_off
9831 
    generic(
9832 
                TimingChecksOn:Boolean := True;
9833 
                Xon: Boolean := False;
9834 
                InstancePath: STRING :="*";
9835 
                MsgOn: Boolean := True;
9836 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9837 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9838 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9839 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9840 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9841 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9842 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9843 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9844 
 
9845 
 
9846 
--pragma translate_on
9847 
    port(
9848 
                A               : in    STD_ULOGIC;
9849 
                B               : in    STD_ULOGIC;
9850 
                C               : in    STD_ULOGIC;
9851 
                D               : in    STD_ULOGIC;
9852 
                Y               : out    STD_ULOGIC);
9853 
 end component;
9854 
 
9855 
 
9856 
------ Component OA2A ------
9857 
 component OA2A
9858 
--pragma translate_off
9859 
    generic(
9860 
                TimingChecksOn:Boolean := True;
9861 
                Xon: Boolean := False;
9862 
                InstancePath: STRING :="*";
9863 
                MsgOn: Boolean := True;
9864 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9865 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9866 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9867 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9868 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9869 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9870 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9871 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9872 
 
9873 
 
9874 
--pragma translate_on
9875 
    port(
9876 
                A               : in    STD_ULOGIC;
9877 
                B               : in    STD_ULOGIC;
9878 
                C               : in    STD_ULOGIC;
9879 
                D               : in    STD_ULOGIC;
9880 
                Y               : out    STD_ULOGIC);
9881 
 end component;
9882 
 
9883 
 
9884 
------ Component OA3 ------
9885 
 component OA3
9886 
--pragma translate_off
9887 
    generic(
9888 
                TimingChecksOn:Boolean := True;
9889 
                Xon: Boolean := False;
9890 
                InstancePath: STRING :="*";
9891 
                MsgOn: Boolean := True;
9892 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9893 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9894 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9895 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9896 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9897 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9898 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9899 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9900 
 
9901 
 
9902 
--pragma translate_on
9903 
    port(
9904 
                A               : in    STD_ULOGIC;
9905 
                B               : in    STD_ULOGIC;
9906 
                C               : in    STD_ULOGIC;
9907 
                D               : in    STD_ULOGIC;
9908 
                Y               : out    STD_ULOGIC);
9909 
 end component;
9910 
 
9911 
 
9912 
------ Component OA3A ------
9913 
 component OA3A
9914 
--pragma translate_off
9915 
    generic(
9916 
                TimingChecksOn:Boolean := True;
9917 
                Xon: Boolean := False;
9918 
                InstancePath: STRING :="*";
9919 
                MsgOn: Boolean := True;
9920 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9921 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9922 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9923 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9924 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9925 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9926 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9927 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9928 
 
9929 
 
9930 
--pragma translate_on
9931 
    port(
9932 
                A               : in    STD_ULOGIC;
9933 
                B               : in    STD_ULOGIC;
9934 
                C               : in    STD_ULOGIC;
9935 
                D               : in    STD_ULOGIC;
9936 
                Y               : out    STD_ULOGIC);
9937 
 end component;
9938 
 
9939 
 
9940 
------ Component OA3B ------
9941 
 component OA3B
9942 
--pragma translate_off
9943 
    generic(
9944 
                TimingChecksOn:Boolean := True;
9945 
                Xon: Boolean := False;
9946 
                InstancePath: STRING :="*";
9947 
                MsgOn: Boolean := True;
9948 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9949 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9950 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9951 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9952 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9953 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9954 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9955 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9956 
 
9957 
 
9958 
--pragma translate_on
9959 
    port(
9960 
                A               : in    STD_ULOGIC;
9961 
                B               : in    STD_ULOGIC;
9962 
                C               : in    STD_ULOGIC;
9963 
                D               : in    STD_ULOGIC;
9964 
                Y               : out    STD_ULOGIC);
9965 
 end component;
9966 
 
9967 
 
9968 
------ Component OA4 ------
9969 
 component OA4
9970 
--pragma translate_off
9971 
    generic(
9972 
                TimingChecksOn:Boolean := True;
9973 
                Xon: Boolean := False;
9974 
                InstancePath: STRING :="*";
9975 
                MsgOn: Boolean := True;
9976 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9977 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9978 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9979 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
9980 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9981 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9982 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
9983 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
9984 
 
9985 
 
9986 
--pragma translate_on
9987 
    port(
9988 
                A               : in    STD_ULOGIC;
9989 
                B               : in    STD_ULOGIC;
9990 
                C               : in    STD_ULOGIC;
9991 
                D               : in    STD_ULOGIC;
9992 
                Y               : out    STD_ULOGIC);
9993 
 end component;
9994 
 
9995 
 
9996 
------ Component OA4A ------
9997 
 component OA4A
9998 
--pragma translate_off
9999 
    generic(
10000 
                TimingChecksOn:Boolean := True;
10001 
                Xon: Boolean := False;
10002 
                InstancePath: STRING :="*";
10003 
                MsgOn: Boolean := True;
10004 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10005 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10006 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10007 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10008 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10009 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10010 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10011 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10012 
 
10013 
 
10014 
--pragma translate_on
10015 
    port(
10016 
                A               : in    STD_ULOGIC;
10017 
                B               : in    STD_ULOGIC;
10018 
                C               : in    STD_ULOGIC;
10019 
                D               : in    STD_ULOGIC;
10020 
                Y               : out    STD_ULOGIC);
10021 
 end component;
10022 
 
10023 
 
10024 
------ Component OA5 ------
10025 
 component OA5
10026 
--pragma translate_off
10027 
    generic(
10028 
                TimingChecksOn:Boolean := True;
10029 
                Xon: Boolean := False;
10030 
                InstancePath: STRING :="*";
10031 
                MsgOn: Boolean := True;
10032 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10033 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10034 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10035 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10036 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10037 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10038 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10039 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10040 
 
10041 
 
10042 
--pragma translate_on
10043 
    port(
10044 
                A               : in    STD_ULOGIC;
10045 
                B               : in    STD_ULOGIC;
10046 
                C               : in    STD_ULOGIC;
10047 
                D               : in    STD_ULOGIC;
10048 
                Y               : out    STD_ULOGIC);
10049 
 end component;
10050 
 
10051 
 
10052 
------ Component OAI1 ------
10053 
 component OAI1
10054 
--pragma translate_off
10055 
    generic(
10056 
                TimingChecksOn:Boolean := True;
10057 
                Xon: Boolean := False;
10058 
                InstancePath: STRING :="*";
10059 
                MsgOn: Boolean := True;
10060 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10061 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10062 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10063 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10064 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10065 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10066 
 
10067 
 
10068 
--pragma translate_on
10069 
    port(
10070 
                A               : in    STD_ULOGIC;
10071 
                B               : in    STD_ULOGIC;
10072 
                C               : in    STD_ULOGIC;
10073 
                Y               : out    STD_ULOGIC);
10074 
 end component;
10075 
 
10076 
 
10077 
------ Component OAI2A ------
10078 
 component OAI2A
10079 
--pragma translate_off
10080 
    generic(
10081 
                TimingChecksOn:Boolean := True;
10082 
                Xon: Boolean := False;
10083 
                InstancePath: STRING :="*";
10084 
                MsgOn: Boolean := True;
10085 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10086 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10087 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10088 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10089 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10090 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10091 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10092 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10093 
 
10094 
 
10095 
--pragma translate_on
10096 
    port(
10097 
                A               : in    STD_ULOGIC;
10098 
                B               : in    STD_ULOGIC;
10099 
                C               : in    STD_ULOGIC;
10100 
                D               : in    STD_ULOGIC;
10101 
                Y               : out    STD_ULOGIC);
10102 
 end component;
10103 
 
10104 
 
10105 
------ Component OAI3 ------
10106 
 component OAI3
10107 
--pragma translate_off
10108 
    generic(
10109 
                TimingChecksOn:Boolean := True;
10110 
                Xon: Boolean := False;
10111 
                InstancePath: STRING :="*";
10112 
                MsgOn: Boolean := True;
10113 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10114 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10115 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10116 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10117 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10118 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10119 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10120 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10121 
 
10122 
 
10123 
--pragma translate_on
10124 
    port(
10125 
                A               : in    STD_ULOGIC;
10126 
                B               : in    STD_ULOGIC;
10127 
                C               : in    STD_ULOGIC;
10128 
                D               : in    STD_ULOGIC;
10129 
                Y               : out    STD_ULOGIC);
10130 
 end component;
10131 
 
10132 
 
10133 
------ Component OAI3A ------
10134 
 component OAI3A
10135 
--pragma translate_off
10136 
    generic(
10137 
                TimingChecksOn:Boolean := True;
10138 
                Xon: Boolean := False;
10139 
                InstancePath: STRING :="*";
10140 
                MsgOn: Boolean := True;
10141 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10142 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10143 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10144 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10145 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10146 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10147 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10148 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10149 
 
10150 
 
10151 
--pragma translate_on
10152 
    port(
10153 
                A               : in    STD_ULOGIC;
10154 
                B               : in    STD_ULOGIC;
10155 
                C               : in    STD_ULOGIC;
10156 
                D               : in    STD_ULOGIC;
10157 
                Y               : out    STD_ULOGIC);
10158 
 end component;
10159 
 
10160 
 
10161 
------ Component OR2 ------
10162 
 component OR2
10163 
--pragma translate_off
10164 
    generic(
10165 
                TimingChecksOn:Boolean := True;
10166 
                Xon: Boolean := False;
10167 
                InstancePath: STRING :="*";
10168 
                MsgOn: Boolean := True;
10169 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10170 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10171 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10172 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10173 
 
10174 
 
10175 
--pragma translate_on
10176 
    port(
10177 
                A               : in    STD_ULOGIC;
10178 
                B               : in    STD_ULOGIC;
10179 
                Y               : out    STD_ULOGIC);
10180 
 end component;
10181 
 
10182 
 
10183 
------ Component OR2A ------
10184 
 component OR2A
10185 
--pragma translate_off
10186 
    generic(
10187 
                TimingChecksOn:Boolean := True;
10188 
                Xon: Boolean := False;
10189 
                InstancePath: STRING :="*";
10190 
                MsgOn: Boolean := True;
10191 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10192 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10193 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10194 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10195 
 
10196 
 
10197 
--pragma translate_on
10198 
    port(
10199 
                A               : in    STD_ULOGIC;
10200 
                B               : in    STD_ULOGIC;
10201 
                Y               : out    STD_ULOGIC);
10202 
 end component;
10203 
 
10204 
 
10205 
------ Component OR2B ------
10206 
 component OR2B
10207 
--pragma translate_off
10208 
    generic(
10209 
                TimingChecksOn:Boolean := True;
10210 
                Xon: Boolean := False;
10211 
                InstancePath: STRING :="*";
10212 
                MsgOn: Boolean := True;
10213 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10214 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10215 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10216 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10217 
 
10218 
 
10219 
--pragma translate_on
10220 
    port(
10221 
                A               : in    STD_ULOGIC;
10222 
                B               : in    STD_ULOGIC;
10223 
                Y               : out    STD_ULOGIC);
10224 
 end component;
10225 
 
10226 
 
10227 
------ Component OR3 ------
10228 
 component OR3
10229 
--pragma translate_off
10230 
    generic(
10231 
                TimingChecksOn:Boolean := True;
10232 
                Xon: Boolean := False;
10233 
                InstancePath: STRING :="*";
10234 
                MsgOn: Boolean := True;
10235 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10236 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10237 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10238 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10239 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10240 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10241 
 
10242 
 
10243 
--pragma translate_on
10244 
    port(
10245 
                A               : in    STD_ULOGIC;
10246 
                B               : in    STD_ULOGIC;
10247 
                C               : in    STD_ULOGIC;
10248 
                Y               : out    STD_ULOGIC);
10249 
 end component;
10250 
 
10251 
 
10252 
------ Component OR3A ------
10253 
 component OR3A
10254 
--pragma translate_off
10255 
    generic(
10256 
                TimingChecksOn:Boolean := True;
10257 
                Xon: Boolean := False;
10258 
                InstancePath: STRING :="*";
10259 
                MsgOn: Boolean := True;
10260 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10261 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10262 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10263 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10264 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10265 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10266 
 
10267 
 
10268 
--pragma translate_on
10269 
    port(
10270 
                A               : in    STD_ULOGIC;
10271 
                B               : in    STD_ULOGIC;
10272 
                C               : in    STD_ULOGIC;
10273 
                Y               : out    STD_ULOGIC);
10274 
 end component;
10275 
 
10276 
 
10277 
------ Component OR3B ------
10278 
 component OR3B
10279 
--pragma translate_off
10280 
    generic(
10281 
                TimingChecksOn:Boolean := True;
10282 
                Xon: Boolean := False;
10283 
                InstancePath: STRING :="*";
10284 
                MsgOn: Boolean := True;
10285 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10286 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10287 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10288 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10289 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10290 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10291 
 
10292 
 
10293 
--pragma translate_on
10294 
    port(
10295 
                A               : in    STD_ULOGIC;
10296 
                B               : in    STD_ULOGIC;
10297 
                C               : in    STD_ULOGIC;
10298 
                Y               : out    STD_ULOGIC);
10299 
 end component;
10300 
 
10301 
 
10302 
------ Component OR3C ------
10303 
 component OR3C
10304 
--pragma translate_off
10305 
    generic(
10306 
                TimingChecksOn:Boolean := True;
10307 
                Xon: Boolean := False;
10308 
                InstancePath: STRING :="*";
10309 
                MsgOn: Boolean := True;
10310 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10311 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10312 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10313 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10314 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10315 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10316 
 
10317 
 
10318 
--pragma translate_on
10319 
    port(
10320 
                A               : in    STD_ULOGIC;
10321 
                B               : in    STD_ULOGIC;
10322 
                C               : in    STD_ULOGIC;
10323 
                Y               : out    STD_ULOGIC);
10324 
 end component;
10325 
 
10326 
 
10327 
------ Component OR4 ------
10328 
 component OR4
10329 
--pragma translate_off
10330 
    generic(
10331 
                TimingChecksOn:Boolean := True;
10332 
                Xon: Boolean := False;
10333 
                InstancePath: STRING :="*";
10334 
                MsgOn: Boolean := True;
10335 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10336 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10337 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10338 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10339 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10340 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10341 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10342 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10343 
 
10344 
 
10345 
--pragma translate_on
10346 
    port(
10347 
                A               : in    STD_ULOGIC;
10348 
                B               : in    STD_ULOGIC;
10349 
                C               : in    STD_ULOGIC;
10350 
                D               : in    STD_ULOGIC;
10351 
                Y               : out    STD_ULOGIC);
10352 
 end component;
10353 
 
10354 
 
10355 
------ Component OR4A ------
10356 
 component OR4A
10357 
--pragma translate_off
10358 
    generic(
10359 
                TimingChecksOn:Boolean := True;
10360 
                Xon: Boolean := False;
10361 
                InstancePath: STRING :="*";
10362 
                MsgOn: Boolean := True;
10363 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10364 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10365 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10366 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10367 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10368 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10369 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10370 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10371 
 
10372 
 
10373 
--pragma translate_on
10374 
    port(
10375 
                A               : in    STD_ULOGIC;
10376 
                B               : in    STD_ULOGIC;
10377 
                C               : in    STD_ULOGIC;
10378 
                D               : in    STD_ULOGIC;
10379 
                Y               : out    STD_ULOGIC);
10380 
 end component;
10381 
 
10382 
 
10383 
------ Component OR4B ------
10384 
 component OR4B
10385 
--pragma translate_off
10386 
    generic(
10387 
                TimingChecksOn:Boolean := True;
10388 
                Xon: Boolean := False;
10389 
                InstancePath: STRING :="*";
10390 
                MsgOn: Boolean := True;
10391 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10392 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10393 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10394 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10395 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10396 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10397 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10398 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10399 
 
10400 
 
10401 
--pragma translate_on
10402 
    port(
10403 
                A               : in    STD_ULOGIC;
10404 
                B               : in    STD_ULOGIC;
10405 
                C               : in    STD_ULOGIC;
10406 
                D               : in    STD_ULOGIC;
10407 
                Y               : out    STD_ULOGIC);
10408 
 end component;
10409 
 
10410 
 
10411 
------ Component OR4C ------
10412 
 component OR4C
10413 
--pragma translate_off
10414 
    generic(
10415 
                TimingChecksOn:Boolean := True;
10416 
                Xon: Boolean := False;
10417 
                InstancePath: STRING :="*";
10418 
                MsgOn: Boolean := True;
10419 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10420 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10421 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10422 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10423 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10424 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10425 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10426 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10427 
 
10428 
 
10429 
--pragma translate_on
10430 
    port(
10431 
                A               : in    STD_ULOGIC;
10432 
                B               : in    STD_ULOGIC;
10433 
                C               : in    STD_ULOGIC;
10434 
                D               : in    STD_ULOGIC;
10435 
                Y               : out    STD_ULOGIC);
10436 
 end component;
10437 
 
10438 
 
10439 
------ Component OR4D ------
10440 
 component OR4D
10441 
--pragma translate_off
10442 
    generic(
10443 
                TimingChecksOn:Boolean := True;
10444 
                Xon: Boolean := False;
10445 
                InstancePath: STRING :="*";
10446 
                MsgOn: Boolean := True;
10447 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10448 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10449 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10450 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10451 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10452 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10453 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10454 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10455 
 
10456 
 
10457 
--pragma translate_on
10458 
    port(
10459 
                A               : in    STD_ULOGIC;
10460 
                B               : in    STD_ULOGIC;
10461 
                C               : in    STD_ULOGIC;
10462 
                D               : in    STD_ULOGIC;
10463 
                Y               : out    STD_ULOGIC);
10464 
 end component;
10465 
 
10466 
 
10467 
------ Component OR5A ------
10468 
 component OR5A
10469 
--pragma translate_off
10470 
    generic(
10471 
                TimingChecksOn:Boolean := True;
10472 
                Xon: Boolean := False;
10473 
                InstancePath: STRING :="*";
10474 
                MsgOn: Boolean := True;
10475 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10476 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10477 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10478 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10479 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10480 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10481 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10482 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10483 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10484 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10485 
 
10486 
 
10487 
--pragma translate_on
10488 
    port(
10489 
                A               : in    STD_ULOGIC;
10490 
                B               : in    STD_ULOGIC;
10491 
                C               : in    STD_ULOGIC;
10492 
                D               : in    STD_ULOGIC;
10493 
                E               : in    STD_ULOGIC;
10494 
                Y               : out    STD_ULOGIC);
10495 
 end component;
10496 
 
10497 
 
10498 
------ Component OR5B ------
10499 
 component OR5B
10500 
--pragma translate_off
10501 
    generic(
10502 
                TimingChecksOn:Boolean := True;
10503 
                Xon: Boolean := False;
10504 
                InstancePath: STRING :="*";
10505 
                MsgOn: Boolean := True;
10506 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10507 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10508 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10509 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10510 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10511 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10512 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10513 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10514 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10515 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10516 
 
10517 
 
10518 
--pragma translate_on
10519 
    port(
10520 
                A               : in    STD_ULOGIC;
10521 
                B               : in    STD_ULOGIC;
10522 
                C               : in    STD_ULOGIC;
10523 
                D               : in    STD_ULOGIC;
10524 
                E               : in    STD_ULOGIC;
10525 
                Y               : out    STD_ULOGIC);
10526 
 end component;
10527 
 
10528 
 
10529 
------ Component OR5C ------
10530 
 component OR5C
10531 
--pragma translate_off
10532 
    generic(
10533 
                TimingChecksOn:Boolean := True;
10534 
                Xon: Boolean := False;
10535 
                InstancePath: STRING :="*";
10536 
                MsgOn: Boolean := True;
10537 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10538 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10539 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10540 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10541 
                tpd_E_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10542 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10543 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10544 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10545 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
10546 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10547 
 
10548 
 
10549 
--pragma translate_on
10550 
    port(
10551 
                A               : in    STD_ULOGIC;
10552 
                B               : in    STD_ULOGIC;
10553 
                C               : in    STD_ULOGIC;
10554 
                D               : in    STD_ULOGIC;
10555 
                E               : in    STD_ULOGIC;
10556 
                Y               : out    STD_ULOGIC);
10557 
 end component;
10558 
 
10559 
 
10560 
------ Component OUTBUF ------
10561 
 component OUTBUF
10562 
--pragma translate_off
10563 
    generic(
10564 
                TimingChecksOn:Boolean := True;
10565 
                Xon: Boolean := False;
10566 
                InstancePath: STRING :="*";
10567 
                MsgOn: Boolean := True;
10568 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10569 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10570 
 
10571 
 
10572 
--pragma translate_on
10573 
    port(
10574 
                D               : in    STD_ULOGIC;
10575 
                PAD             : out    STD_ULOGIC);
10576 
 end component;
10577 
 
10578 
 
10579 
------ Component OUTBUF_S_8 ------
10580 
 component OUTBUF_S_8
10581 
--pragma translate_off
10582 
    generic(
10583 
                TimingChecksOn:Boolean := True;
10584 
                Xon: Boolean := False;
10585 
                InstancePath: STRING :="*";
10586 
                MsgOn: Boolean := True;
10587 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10588 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10589 
 
10590 
 
10591 
--pragma translate_on
10592 
    port(
10593 
                D               : in    STD_ULOGIC;
10594 
                PAD             : out    STD_ULOGIC);
10595 
 end component;
10596 
 
10597 
 
10598 
------ Component OUTBUF_S_12 ------
10599 
 component OUTBUF_S_12
10600 
--pragma translate_off
10601 
    generic(
10602 
                TimingChecksOn:Boolean := True;
10603 
                Xon: Boolean := False;
10604 
                InstancePath: STRING :="*";
10605 
                MsgOn: Boolean := True;
10606 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10607 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10608 
 
10609 
 
10610 
--pragma translate_on
10611 
    port(
10612 
                D               : in    STD_ULOGIC;
10613 
                PAD             : out    STD_ULOGIC);
10614 
 end component;
10615 
 
10616 
 
10617 
------ Component OUTBUF_S_16 ------
10618 
 component OUTBUF_S_16
10619 
--pragma translate_off
10620 
    generic(
10621 
                TimingChecksOn:Boolean := True;
10622 
                Xon: Boolean := False;
10623 
                InstancePath: STRING :="*";
10624 
                MsgOn: Boolean := True;
10625 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10626 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10627 
 
10628 
 
10629 
--pragma translate_on
10630 
    port(
10631 
                D               : in    STD_ULOGIC;
10632 
                PAD             : out    STD_ULOGIC);
10633 
 end component;
10634 
 
10635 
 
10636 
------ Component OUTBUF_S_24 ------
10637 
 component OUTBUF_S_24
10638 
--pragma translate_off
10639 
    generic(
10640 
                TimingChecksOn:Boolean := True;
10641 
                Xon: Boolean := False;
10642 
                InstancePath: STRING :="*";
10643 
                MsgOn: Boolean := True;
10644 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10645 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10646 
 
10647 
 
10648 
--pragma translate_on
10649 
    port(
10650 
                D               : in    STD_ULOGIC;
10651 
                PAD             : out    STD_ULOGIC);
10652 
 end component;
10653 
 
10654 
 
10655 
------ Component OUTBUF_F_8 ------
10656 
 component OUTBUF_F_8
10657 
--pragma translate_off
10658 
    generic(
10659 
                TimingChecksOn:Boolean := True;
10660 
                Xon: Boolean := False;
10661 
                InstancePath: STRING :="*";
10662 
                MsgOn: Boolean := True;
10663 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10664 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10665 
 
10666 
 
10667 
--pragma translate_on
10668 
    port(
10669 
                D               : in    STD_ULOGIC;
10670 
                PAD             : out    STD_ULOGIC);
10671 
 end component;
10672 
 
10673 
 
10674 
------ Component OUTBUF_F_12 ------
10675 
 component OUTBUF_F_12
10676 
--pragma translate_off
10677 
    generic(
10678 
                TimingChecksOn:Boolean := True;
10679 
                Xon: Boolean := False;
10680 
                InstancePath: STRING :="*";
10681 
                MsgOn: Boolean := True;
10682 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10683 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10684 
 
10685 
 
10686 
--pragma translate_on
10687 
    port(
10688 
                D               : in    STD_ULOGIC;
10689 
                PAD             : out    STD_ULOGIC);
10690 
 end component;
10691 
 
10692 
 
10693 
------ Component OUTBUF_F_16 ------
10694 
 component OUTBUF_F_16
10695 
--pragma translate_off
10696 
    generic(
10697 
                TimingChecksOn:Boolean := True;
10698 
                Xon: Boolean := False;
10699 
                InstancePath: STRING :="*";
10700 
                MsgOn: Boolean := True;
10701 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10702 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10703 
 
10704 
 
10705 
--pragma translate_on
10706 
    port(
10707 
                D               : in    STD_ULOGIC;
10708 
                PAD             : out    STD_ULOGIC);
10709 
 end component;
10710 
 
10711 
 
10712 
------ Component OUTBUF_F_24 ------
10713 
 component OUTBUF_F_24
10714 
--pragma translate_off
10715 
    generic(
10716 
                TimingChecksOn:Boolean := True;
10717 
                Xon: Boolean := False;
10718 
                InstancePath: STRING :="*";
10719 
                MsgOn: Boolean := True;
10720 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10721 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10722 
 
10723 
 
10724 
--pragma translate_on
10725 
    port(
10726 
                D               : in    STD_ULOGIC;
10727 
                PAD             : out    STD_ULOGIC);
10728 
 end component;
10729 
 
10730 
 
10731 
------ Component OUTBUF_LVCMOS25 ------
10732 
 component OUTBUF_LVCMOS25
10733 
--pragma translate_off
10734 
    generic(
10735 
                TimingChecksOn:Boolean := True;
10736 
                Xon: Boolean := False;
10737 
                InstancePath: STRING :="*";
10738 
                MsgOn: Boolean := True;
10739 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10740 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10741 
 
10742 
 
10743 
--pragma translate_on
10744 
    port(
10745 
                D               : in    STD_ULOGIC;
10746 
                PAD             : out    STD_ULOGIC);
10747 
 end component;
10748 
 
10749 
 
10750 
------ Component OUTBUF_LVCMOS18 ------
10751 
 component OUTBUF_LVCMOS18
10752 
--pragma translate_off
10753 
    generic(
10754 
                TimingChecksOn:Boolean := True;
10755 
                Xon: Boolean := False;
10756 
                InstancePath: STRING :="*";
10757 
                MsgOn: Boolean := True;
10758 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10759 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10760 
 
10761 
 
10762 
--pragma translate_on
10763 
    port(
10764 
                D               : in    STD_ULOGIC;
10765 
                PAD             : out    STD_ULOGIC);
10766 
 end component;
10767 
 
10768 
 
10769 
------ Component OUTBUF_LVCMOS15 ------
10770 
 component OUTBUF_LVCMOS15
10771 
--pragma translate_off
10772 
    generic(
10773 
                TimingChecksOn:Boolean := True;
10774 
                Xon: Boolean := False;
10775 
                InstancePath: STRING :="*";
10776 
                MsgOn: Boolean := True;
10777 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10778 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10779 
 
10780 
 
10781 
--pragma translate_on
10782 
    port(
10783 
                D               : in    STD_ULOGIC;
10784 
                PAD             : out    STD_ULOGIC);
10785 
 end component;
10786 
 
10787 
 
10788 
------ Component OUTBUF_PCI ------
10789 
 component OUTBUF_PCI
10790 
--pragma translate_off
10791 
    generic(
10792 
                TimingChecksOn:Boolean := True;
10793 
                Xon: Boolean := False;
10794 
                InstancePath: STRING :="*";
10795 
                MsgOn: Boolean := True;
10796 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10797 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10798 
 
10799 
 
10800 
--pragma translate_on
10801 
    port(
10802 
                D               : in    STD_ULOGIC;
10803 
                PAD             : out    STD_ULOGIC);
10804 
 end component;
10805 
 
10806 
 
10807 
------ Component OUTBUF_PCIX ------
10808 
 component OUTBUF_PCIX
10809 
--pragma translate_off
10810 
    generic(
10811 
                TimingChecksOn:Boolean := True;
10812 
                Xon: Boolean := False;
10813 
                InstancePath: STRING :="*";
10814 
                MsgOn: Boolean := True;
10815 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10816 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10817 
 
10818 
 
10819 
--pragma translate_on
10820 
    port(
10821 
                D               : in    STD_ULOGIC;
10822 
                PAD             : out    STD_ULOGIC);
10823 
 end component;
10824 
 
10825 
 
10826 
------ Component OUTBUF_GTLP33 ------
10827 
 component OUTBUF_GTLP33
10828 
--pragma translate_off
10829 
    generic(
10830 
                TimingChecksOn:Boolean := True;
10831 
                Xon: Boolean := False;
10832 
                InstancePath: STRING :="*";
10833 
                MsgOn: Boolean := True;
10834 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10835 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10836 
 
10837 
 
10838 
--pragma translate_on
10839 
    port(
10840 
                D               : in    STD_ULOGIC;
10841 
                PAD             : out    STD_ULOGIC);
10842 
 end component;
10843 
 
10844 
 
10845 
------ Component OUTBUF_GTLP25 ------
10846 
 component OUTBUF_GTLP25
10847 
--pragma translate_off
10848 
    generic(
10849 
                TimingChecksOn:Boolean := True;
10850 
                Xon: Boolean := False;
10851 
                InstancePath: STRING :="*";
10852 
                MsgOn: Boolean := True;
10853 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10854 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10855 
 
10856 
 
10857 
--pragma translate_on
10858 
    port(
10859 
                D               : in    STD_ULOGIC;
10860 
                PAD             : out    STD_ULOGIC);
10861 
 end component;
10862 
 
10863 
 
10864 
------ Component OUTBUF_HSTL_I ------
10865 
 component OUTBUF_HSTL_I
10866 
--pragma translate_off
10867 
    generic(
10868 
                TimingChecksOn:Boolean := True;
10869 
                Xon: Boolean := False;
10870 
                InstancePath: STRING :="*";
10871 
                MsgOn: Boolean := True;
10872 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10873 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10874 
 
10875 
 
10876 
--pragma translate_on
10877 
    port(
10878 
                D               : in    STD_ULOGIC;
10879 
                PAD             : out    STD_ULOGIC);
10880 
 end component;
10881 
 
10882 
 
10883 
------ Component OUTBUF_SSTL3_I ------
10884 
 component OUTBUF_SSTL3_I
10885 
--pragma translate_off
10886 
    generic(
10887 
                TimingChecksOn:Boolean := True;
10888 
                Xon: Boolean := False;
10889 
                InstancePath: STRING :="*";
10890 
                MsgOn: Boolean := True;
10891 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10892 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10893 
 
10894 
 
10895 
--pragma translate_on
10896 
    port(
10897 
                D               : in    STD_ULOGIC;
10898 
                PAD             : out    STD_ULOGIC);
10899 
 end component;
10900 
 
10901 
 
10902 
------ Component OUTBUF_SSTL3_II ------
10903 
 component OUTBUF_SSTL3_II
10904 
--pragma translate_off
10905 
    generic(
10906 
                TimingChecksOn:Boolean := True;
10907 
                Xon: Boolean := False;
10908 
                InstancePath: STRING :="*";
10909 
                MsgOn: Boolean := True;
10910 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10911 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10912 
 
10913 
 
10914 
--pragma translate_on
10915 
    port(
10916 
                D               : in    STD_ULOGIC;
10917 
                PAD             : out    STD_ULOGIC);
10918 
 end component;
10919 
 
10920 
 
10921 
------ Component OUTBUF_SSTL2_I ------
10922 
 component OUTBUF_SSTL2_I
10923 
--pragma translate_off
10924 
    generic(
10925 
                TimingChecksOn:Boolean := True;
10926 
                Xon: Boolean := False;
10927 
                InstancePath: STRING :="*";
10928 
                MsgOn: Boolean := True;
10929 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10930 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10931 
 
10932 
 
10933 
--pragma translate_on
10934 
    port(
10935 
                D               : in    STD_ULOGIC;
10936 
                PAD             : out    STD_ULOGIC);
10937 
 end component;
10938 
 
10939 
 
10940 
------ Component OUTBUF_SSTL2_II ------
10941 
 component OUTBUF_SSTL2_II
10942 
--pragma translate_off
10943 
    generic(
10944 
                TimingChecksOn:Boolean := True;
10945 
                Xon: Boolean := False;
10946 
                InstancePath: STRING :="*";
10947 
                MsgOn: Boolean := True;
10948 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
10949 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10950 
 
10951 
 
10952 
--pragma translate_on
10953 
    port(
10954 
                D               : in    STD_ULOGIC;
10955 
                PAD             : out    STD_ULOGIC);
10956 
 end component;
10957 
 
10958 
 
10959 
------ Component PLLHCLK ------
10960 
 component PLLHCLK
10961 
--pragma translate_off
10962 
    generic(
10963 
                TimingChecksOn:Boolean := True;
10964 
                Xon: Boolean := False;
10965 
                InstancePath: STRING :="*";
10966 
                MsgOn: Boolean := True;
10967 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10968 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10969 
 
10970 
 
10971 
--pragma translate_on
10972 
    port(
10973 
                A               : in    STD_ULOGIC;
10974 
                Y               : out    STD_ULOGIC);
10975 
 end component;
10976 
 
10977 
 
10978 
------ Component PLLRCLK ------
10979 
 component PLLRCLK
10980 
--pragma translate_off
10981 
    generic(
10982 
                TimingChecksOn:Boolean := True;
10983 
                Xon: Boolean := False;
10984 
                InstancePath: STRING :="*";
10985 
                MsgOn: Boolean := True;
10986 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
10987 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
10988 
 
10989 
 
10990 
--pragma translate_on
10991 
    port(
10992 
                A               : in    STD_ULOGIC;
10993 
                Y               : out    STD_ULOGIC);
10994 
 end component;
10995 
 
10996 
 
10997 
------ Component SFCNTECP1 ------
10998 
 component SFCNTECP1
10999 
--pragma translate_off
11000 
    generic(
11001 
                TimingChecksOn: Boolean := True;
11002 
                InstancePath: STRING := "*";
11003 
                Xon: Boolean := False;
11004 
                MsgOn: Boolean := True;
11005 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11006 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11007 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11008 
                tpd_UD_FCO              :   VitalDelayType01 := (0.100 ns, 0.100 ns);
11009 
                tpd_FCI_FCO             :   VitalDelayType01 := (0.100 ns, 0.100 ns);
11010 
                tsetup_Q_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
11011 
                thold_Q_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
11012 
                tsetup_UD_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
11013 
                thold_UD_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
11014 
                tsetup_FCI_CLK_posedge_negedge          :   VitalDelayType := 0.000 ns;
11015 
                thold_FCI_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
11016 
                tsetup_Q_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
11017 
                thold_Q_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
11018 
                tsetup_UD_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
11019 
                thold_UD_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
11020 
                tsetup_FCI_CLK_negedge_negedge          :   VitalDelayType := 0.000 ns;
11021 
                thold_FCI_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
11022 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
11023 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
11024 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
11025 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
11026 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
11027 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
11028 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
11029 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
11030 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
11031 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
11032 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
11033 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
11034 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11035 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11036 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11037 
                tipd_UD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11038 
                tipd_FCI                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11039 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
11040 
 
11041 
 
11042 
--pragma translate_on
11043 
    port(
11044 
                CLR             :   in    STD_ULOGIC;
11045 
                PRE             :   in    STD_ULOGIC;
11046 
                E               :   in    STD_ULOGIC;
11047 
                CLK             :   in    STD_ULOGIC;
11048 
                Q               :  out STD_ULOGIC;
11049 
                UD              :  in    STD_ULOGIC;
11050 
                FCI             :  in    STD_ULOGIC;
11051 
                FCO             :  out    STD_ULOGIC);
11052 
 
11053 
 end component;
11054 
 
11055 
 
11056 
------ Component SRCNTECP1 ------
11057 
 component SRCNTECP1
11058 
--pragma translate_off
11059 
    generic(
11060 
                TimingChecksOn: Boolean := True;
11061 
                InstancePath: STRING := "*";
11062 
                Xon: Boolean := False;
11063 
                MsgOn: Boolean := True;
11064 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11065 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11066 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11067 
                tpd_UD_FCO              :   VitalDelayType01 := (0.100 ns, 0.100 ns);
11068 
                tpd_FCI_FCO             :   VitalDelayType01 := (0.100 ns, 0.100 ns);
11069 
                tsetup_Q_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
11070 
                thold_Q_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
11071 
                tsetup_UD_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
11072 
                thold_UD_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
11073 
                tsetup_FCI_CLK_posedge_posedge          :   VitalDelayType := 0.000 ns;
11074 
                thold_FCI_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
11075 
                tsetup_Q_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
11076 
                thold_Q_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
11077 
                tsetup_UD_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
11078 
                thold_UD_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
11079 
                tsetup_FCI_CLK_negedge_posedge          :   VitalDelayType := 0.000 ns;
11080 
                thold_FCI_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
11081 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
11082 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
11083 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
11084 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
11085 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
11086 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
11087 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
11088 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
11089 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
11090 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
11091 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
11092 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
11093 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11094 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11095 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11096 
                tipd_UD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11097 
                tipd_FCI                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11098 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
11099 
 
11100 
 
11101 
--pragma translate_on
11102 
    port(
11103 
                CLR             :   in    STD_ULOGIC;
11104 
                PRE             :   in    STD_ULOGIC;
11105 
                E               :   in    STD_ULOGIC;
11106 
                CLK             :   in    STD_ULOGIC;
11107 
                Q               :  out STD_ULOGIC;
11108 
                UD              :  in    STD_ULOGIC;
11109 
                FCI             :  in    STD_ULOGIC;
11110 
                FCO             :  out    STD_ULOGIC);
11111 
 
11112 
 end component;
11113 
 
11114 
 
11115 
------ Component SFCNTELDCP1 ------
11116 
 component SFCNTELDCP1
11117 
--pragma translate_off
11118 
    generic(
11119 
                TimingChecksOn: Boolean := True;
11120 
                InstancePath: STRING := "*";
11121 
                Xon: Boolean := False;
11122 
                MsgOn: Boolean := True;
11123 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11124 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11125 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11126 
                tpd_UD_FCO              :   VitalDelayType01 := (0.100 ns, 0.100 ns);
11127 
                tpd_FCI_FCO             :   VitalDelayType01 := (0.100 ns, 0.100 ns);
11128 
                tsetup_Q_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
11129 
                thold_Q_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
11130 
                tsetup_UD_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
11131 
                thold_UD_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
11132 
                tsetup_FCI_CLK_posedge_negedge          :   VitalDelayType := 0.000 ns;
11133 
                thold_FCI_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
11134 
                tsetup_LD_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
11135 
                thold_LD_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
11136 
                tsetup_D_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
11137 
                thold_D_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
11138 
                tsetup_Q_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
11139 
                thold_Q_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
11140 
                tsetup_UD_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
11141 
                thold_UD_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
11142 
                tsetup_FCI_CLK_negedge_negedge          :   VitalDelayType := 0.000 ns;
11143 
                thold_FCI_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
11144 
                tsetup_LD_CLK_negedge_negedge           :   VitalDelayType := 0.000 ns;
11145 
                thold_LD_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
11146 
                tsetup_D_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
11147 
                thold_D_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
11148 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
11149 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
11150 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
11151 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
11152 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
11153 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
11154 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
11155 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
11156 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
11157 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
11158 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
11159 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
11160 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11161 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11162 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11163 
                tipd_UD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11164 
                tipd_FCI                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11165 
                tipd_LD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11166 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11167 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
11168 
 
11169 
 
11170 
--pragma translate_on
11171 
    port(
11172 
                CLR             :   in    STD_ULOGIC;
11173 
                PRE             :   in    STD_ULOGIC;
11174 
                E               :   in    STD_ULOGIC;
11175 
                CLK             :   in    STD_ULOGIC;
11176 
                Q               :  out STD_ULOGIC;
11177 
                UD              :  in    STD_ULOGIC;
11178 
                FCI             :  in    STD_ULOGIC;
11179 
                LD              :  in    STD_ULOGIC;
11180 
                D               :  in    STD_ULOGIC;
11181 
                FCO             :  out    STD_ULOGIC);
11182 
 
11183 
 end component;
11184 
 
11185 
 
11186 
------ Component SRCNTELDCP1 ------
11187 
 component SRCNTELDCP1
11188 
--pragma translate_off
11189 
    generic(
11190 
                TimingChecksOn: Boolean := True;
11191 
                InstancePath: STRING := "*";
11192 
                Xon: Boolean := False;
11193 
                MsgOn: Boolean := True;
11194 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11195 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11196 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11197 
                tpd_UD_FCO              :   VitalDelayType01 := (0.100 ns, 0.100 ns);
11198 
                tpd_FCI_FCO             :   VitalDelayType01 := (0.100 ns, 0.100 ns);
11199 
                tsetup_Q_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
11200 
                thold_Q_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
11201 
                tsetup_UD_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
11202 
                thold_UD_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
11203 
                tsetup_FCI_CLK_posedge_posedge          :   VitalDelayType := 0.000 ns;
11204 
                thold_FCI_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
11205 
                tsetup_LD_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
11206 
                thold_LD_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
11207 
                tsetup_D_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
11208 
                thold_D_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
11209 
                tsetup_Q_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
11210 
                thold_Q_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
11211 
                tsetup_UD_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
11212 
                thold_UD_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
11213 
                tsetup_FCI_CLK_negedge_posedge          :   VitalDelayType := 0.000 ns;
11214 
                thold_FCI_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
11215 
                tsetup_LD_CLK_negedge_posedge           :   VitalDelayType := 0.000 ns;
11216 
                thold_LD_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
11217 
                tsetup_D_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
11218 
                thold_D_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
11219 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
11220 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
11221 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
11222 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
11223 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
11224 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
11225 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
11226 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
11227 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
11228 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
11229 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
11230 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
11231 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11232 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11233 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11234 
                tipd_UD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11235 
                tipd_FCI                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11236 
                tipd_LD         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11237 
                tipd_D          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11238 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
11239 
 
11240 
 
11241 
--pragma translate_on
11242 
    port(
11243 
                CLR             :   in    STD_ULOGIC;
11244 
                PRE             :   in    STD_ULOGIC;
11245 
                E               :   in    STD_ULOGIC;
11246 
                CLK             :   in    STD_ULOGIC;
11247 
                Q               :  out STD_ULOGIC;
11248 
                UD              :  in    STD_ULOGIC;
11249 
                FCI             :  in    STD_ULOGIC;
11250 
                LD              :  in    STD_ULOGIC;
11251 
                D               :  in    STD_ULOGIC;
11252 
                FCO             :  out    STD_ULOGIC);
11253 
 
11254 
 end component;
11255 
 
11256 
 
11257 
------ Component SUB1 ------
11258 
 component SUB1
11259 
--pragma translate_off
11260 
    generic(
11261 
                TimingChecksOn:Boolean := True;
11262 
                Xon: Boolean := False;
11263 
                InstancePath: STRING :="*";
11264 
                MsgOn: Boolean := True;
11265 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
11266 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
11267 
                tpd_FCI_S               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11268 
                tpd_A_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11269 
                tpd_B_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11270 
                tpd_FCI_FCO             : VitalDelayType01 := (0.100 ns, 0.100 ns);
11271 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11272 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11273 
                tipd_FCI                : VitalDelayType01 := (0.000 ns, 0.000 ns));
11274 
 
11275 
 
11276 
--pragma translate_on
11277 
    port(
11278 
                A               : in    STD_ULOGIC;
11279 
                B               : in    STD_ULOGIC;
11280 
                FCI             : in    STD_ULOGIC;
11281 
                S               : out    STD_ULOGIC;
11282 
                FCO             : out    STD_ULOGIC);
11283 
 end component;
11284 
 
11285 
 
11286 
------ Component TF1A ------
11287 
 component TF1A
11288 
--pragma translate_off
11289 
    generic(
11290 
                TimingChecksOn: Boolean := True;
11291 
                InstancePath: STRING := "*";
11292 
                Xon: Boolean := False;
11293 
                MsgOn: Boolean := True;
11294 
                tpd_CLR_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11295 
                tpd_CLK_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11296 
                tsetup_T_CLK_negedge_posedge    :   VitalDelayType := 0.000 ns;
11297 
                thold_T_CLK_negedge_posedge     :   VitalDelayType := 0.000 ns;
11298 
                tsetup_T_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
11299 
                thold_T_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
11300 
                thold_CLR_CLK_posedge_posedge   :   VitalDelayType := 0.000 ns;
11301 
                trecovery_CLR_CLK_posedge_posedge       :   VitalDelayType := 0.000 ns;
11302 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
11303 
                tpw_CLK_negedge :  VitalDelayType := 0.000 ns;
11304 
                tpw_CLR_negedge :  VitalDelayType := 0.000 ns;
11305 
                tipd_CLK        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
11306 
                tipd_CLR        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11307 
                tipd_T  :   VitalDelayType01 := (0.000 ns, 0.000 ns));
11308 
 
11309 
 
11310 
 --pragma translate_on
11311 
    port(
11312 
                T       :  in    STD_ULOGIC;
11313 
                CLR     :  in    STD_ULOGIC;
11314 
                CLK     :  in    STD_ULOGIC;
11315 
                Q       :  out    STD_ULOGIC);
11316 
 
11317 
 end component;
11318 
 
11319 
 
11320 
------ Component TF1B ------
11321 
 component TF1B
11322 
--pragma translate_off
11323 
    generic(
11324 
                TimingChecksOn: Boolean := True;
11325 
                InstancePath: STRING := "*";
11326 
                Xon: Boolean := False;
11327 
                MsgOn: Boolean := True;
11328 
                tpd_CLR_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11329 
                tpd_CLK_Q       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
11330 
                tsetup_T_CLK_negedge_negedge    :   VitalDelayType := 0.000 ns;
11331 
                thold_T_CLK_negedge_negedge     :   VitalDelayType := 0.000 ns;
11332 
                tsetup_T_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
11333 
                thold_T_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
11334 
                thold_CLR_CLK_posedge_negedge   :   VitalDelayType := 0.000 ns;
11335 
                trecovery_CLR_CLK_posedge_negedge       :   VitalDelayType := 0.000 ns;
11336 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
11337 
                tpw_CLK_negedge :  VitalDelayType := 0.000 ns;
11338 
                tpw_CLR_negedge :  VitalDelayType := 0.000 ns;
11339 
                tipd_CLK        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
11340 
                tipd_CLR        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
11341 
                tipd_T  :   VitalDelayType01 := (0.000 ns, 0.000 ns));
11342 
 
11343 
 
11344 
 --pragma translate_on
11345 
    port(
11346 
                T       :  in    STD_ULOGIC;
11347 
                CLR     :  in    STD_ULOGIC;
11348 
                CLK     :  in    STD_ULOGIC;
11349 
                Q       :  out    STD_ULOGIC);
11350 
 
11351 
 end component;
11352 
 
11353 
 
11354 
------ Component TRIBUFF ------
11355 
 component TRIBUFF
11356 
--pragma translate_off
11357 
    generic(
11358 
                TimingChecksOn:Boolean := True;
11359 
                Xon: Boolean := False;
11360 
                InstancePath: STRING :="*";
11361 
                MsgOn: Boolean := True;
11362 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11363 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11364 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11365 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11366 
 
11367 
 
11368 
--pragma translate_on
11369 
    port(
11370 
                D               : in    STD_ULOGIC;
11371 
                E               : in    STD_ULOGIC;
11372 
                PAD             : out    STD_ULOGIC);
11373 
 end component;
11374 
 
11375 
 
11376 
------ Component TRIBUFF_S_8 ------
11377 
 component TRIBUFF_S_8
11378 
--pragma translate_off
11379 
    generic(
11380 
                TimingChecksOn:Boolean := True;
11381 
                Xon: Boolean := False;
11382 
                InstancePath: STRING :="*";
11383 
                MsgOn: Boolean := True;
11384 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11385 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11386 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11387 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11388 
 
11389 
 
11390 
--pragma translate_on
11391 
    port(
11392 
                D               : in    STD_ULOGIC;
11393 
                E               : in    STD_ULOGIC;
11394 
                PAD             : out    STD_ULOGIC);
11395 
 end component;
11396 
 
11397 
 
11398 
------ Component TRIBUFF_S_8D ------
11399 
 component TRIBUFF_S_8D
11400 
--pragma translate_off
11401 
    generic(
11402 
                TimingChecksOn:Boolean := True;
11403 
                Xon: Boolean := False;
11404 
                InstancePath: STRING :="*";
11405 
                MsgOn: Boolean := True;
11406 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11407 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11408 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11409 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11410 
 
11411 
 
11412 
--pragma translate_on
11413 
    port(
11414 
                D               : in    STD_ULOGIC;
11415 
                E               : in    STD_ULOGIC;
11416 
                PAD             : out    STD_ULOGIC);
11417 
 end component;
11418 
 
11419 
 
11420 
------ Component TRIBUFF_S_8U ------
11421 
 component TRIBUFF_S_8U
11422 
--pragma translate_off
11423 
    generic(
11424 
                TimingChecksOn:Boolean := True;
11425 
                Xon: Boolean := False;
11426 
                InstancePath: STRING :="*";
11427 
                MsgOn: Boolean := True;
11428 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11429 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11430 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11431 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11432 
 
11433 
 
11434 
--pragma translate_on
11435 
    port(
11436 
                D               : in    STD_ULOGIC;
11437 
                E               : in    STD_ULOGIC;
11438 
                PAD             : out    STD_ULOGIC);
11439 
 end component;
11440 
 
11441 
 
11442 
------ Component TRIBUFF_S_12 ------
11443 
 component TRIBUFF_S_12
11444 
--pragma translate_off
11445 
    generic(
11446 
                TimingChecksOn:Boolean := True;
11447 
                Xon: Boolean := False;
11448 
                InstancePath: STRING :="*";
11449 
                MsgOn: Boolean := True;
11450 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11451 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11452 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11453 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11454 
 
11455 
 
11456 
--pragma translate_on
11457 
    port(
11458 
                D               : in    STD_ULOGIC;
11459 
                E               : in    STD_ULOGIC;
11460 
                PAD             : out    STD_ULOGIC);
11461 
 end component;
11462 
 
11463 
 
11464 
------ Component TRIBUFF_S_12D ------
11465 
 component TRIBUFF_S_12D
11466 
--pragma translate_off
11467 
    generic(
11468 
                TimingChecksOn:Boolean := True;
11469 
                Xon: Boolean := False;
11470 
                InstancePath: STRING :="*";
11471 
                MsgOn: Boolean := True;
11472 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11473 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11474 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11475 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11476 
 
11477 
 
11478 
--pragma translate_on
11479 
    port(
11480 
                D               : in    STD_ULOGIC;
11481 
                E               : in    STD_ULOGIC;
11482 
                PAD             : out    STD_ULOGIC);
11483 
 end component;
11484 
 
11485 
 
11486 
------ Component TRIBUFF_S_12U ------
11487 
 component TRIBUFF_S_12U
11488 
--pragma translate_off
11489 
    generic(
11490 
                TimingChecksOn:Boolean := True;
11491 
                Xon: Boolean := False;
11492 
                InstancePath: STRING :="*";
11493 
                MsgOn: Boolean := True;
11494 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11495 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11496 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11497 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11498 
 
11499 
 
11500 
--pragma translate_on
11501 
    port(
11502 
                D               : in    STD_ULOGIC;
11503 
                E               : in    STD_ULOGIC;
11504 
                PAD             : out    STD_ULOGIC);
11505 
 end component;
11506 
 
11507 
 
11508 
------ Component TRIBUFF_S_16 ------
11509 
 component TRIBUFF_S_16
11510 
--pragma translate_off
11511 
    generic(
11512 
                TimingChecksOn:Boolean := True;
11513 
                Xon: Boolean := False;
11514 
                InstancePath: STRING :="*";
11515 
                MsgOn: Boolean := True;
11516 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11517 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11518 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11519 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11520 
 
11521 
 
11522 
--pragma translate_on
11523 
    port(
11524 
                D               : in    STD_ULOGIC;
11525 
                E               : in    STD_ULOGIC;
11526 
                PAD             : out    STD_ULOGIC);
11527 
 end component;
11528 
 
11529 
 
11530 
------ Component TRIBUFF_S_16D ------
11531 
 component TRIBUFF_S_16D
11532 
--pragma translate_off
11533 
    generic(
11534 
                TimingChecksOn:Boolean := True;
11535 
                Xon: Boolean := False;
11536 
                InstancePath: STRING :="*";
11537 
                MsgOn: Boolean := True;
11538 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11539 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11540 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11541 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11542 
 
11543 
 
11544 
--pragma translate_on
11545 
    port(
11546 
                D               : in    STD_ULOGIC;
11547 
                E               : in    STD_ULOGIC;
11548 
                PAD             : out    STD_ULOGIC);
11549 
 end component;
11550 
 
11551 
 
11552 
------ Component TRIBUFF_S_16U ------
11553 
 component TRIBUFF_S_16U
11554 
--pragma translate_off
11555 
    generic(
11556 
                TimingChecksOn:Boolean := True;
11557 
                Xon: Boolean := False;
11558 
                InstancePath: STRING :="*";
11559 
                MsgOn: Boolean := True;
11560 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11561 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11562 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11563 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11564 
 
11565 
 
11566 
--pragma translate_on
11567 
    port(
11568 
                D               : in    STD_ULOGIC;
11569 
                E               : in    STD_ULOGIC;
11570 
                PAD             : out    STD_ULOGIC);
11571 
 end component;
11572 
 
11573 
 
11574 
------ Component TRIBUFF_S_24 ------
11575 
 component TRIBUFF_S_24
11576 
--pragma translate_off
11577 
    generic(
11578 
                TimingChecksOn:Boolean := True;
11579 
                Xon: Boolean := False;
11580 
                InstancePath: STRING :="*";
11581 
                MsgOn: Boolean := True;
11582 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11583 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11584 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11585 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11586 
 
11587 
 
11588 
--pragma translate_on
11589 
    port(
11590 
                D               : in    STD_ULOGIC;
11591 
                E               : in    STD_ULOGIC;
11592 
                PAD             : out    STD_ULOGIC);
11593 
 end component;
11594 
 
11595 
 
11596 
------ Component TRIBUFF_S_24D ------
11597 
 component TRIBUFF_S_24D
11598 
--pragma translate_off
11599 
    generic(
11600 
                TimingChecksOn:Boolean := True;
11601 
                Xon: Boolean := False;
11602 
                InstancePath: STRING :="*";
11603 
                MsgOn: Boolean := True;
11604 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11605 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11606 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11607 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11608 
 
11609 
 
11610 
--pragma translate_on
11611 
    port(
11612 
                D               : in    STD_ULOGIC;
11613 
                E               : in    STD_ULOGIC;
11614 
                PAD             : out    STD_ULOGIC);
11615 
 end component;
11616 
 
11617 
 
11618 
------ Component TRIBUFF_S_24U ------
11619 
 component TRIBUFF_S_24U
11620 
--pragma translate_off
11621 
    generic(
11622 
                TimingChecksOn:Boolean := True;
11623 
                Xon: Boolean := False;
11624 
                InstancePath: STRING :="*";
11625 
                MsgOn: Boolean := True;
11626 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11627 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11628 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11629 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11630 
 
11631 
 
11632 
--pragma translate_on
11633 
    port(
11634 
                D               : in    STD_ULOGIC;
11635 
                E               : in    STD_ULOGIC;
11636 
                PAD             : out    STD_ULOGIC);
11637 
 end component;
11638 
 
11639 
 
11640 
------ Component TRIBUFF_F_8 ------
11641 
 component TRIBUFF_F_8
11642 
--pragma translate_off
11643 
    generic(
11644 
                TimingChecksOn:Boolean := True;
11645 
                Xon: Boolean := False;
11646 
                InstancePath: STRING :="*";
11647 
                MsgOn: Boolean := True;
11648 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11649 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11650 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11651 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11652 
 
11653 
 
11654 
--pragma translate_on
11655 
    port(
11656 
                D               : in    STD_ULOGIC;
11657 
                E               : in    STD_ULOGIC;
11658 
                PAD             : out    STD_ULOGIC);
11659 
 end component;
11660 
 
11661 
 
11662 
------ Component TRIBUFF_F_8D ------
11663 
 component TRIBUFF_F_8D
11664 
--pragma translate_off
11665 
    generic(
11666 
                TimingChecksOn:Boolean := True;
11667 
                Xon: Boolean := False;
11668 
                InstancePath: STRING :="*";
11669 
                MsgOn: Boolean := True;
11670 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11671 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11672 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11673 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11674 
 
11675 
 
11676 
--pragma translate_on
11677 
    port(
11678 
                D               : in    STD_ULOGIC;
11679 
                E               : in    STD_ULOGIC;
11680 
                PAD             : out    STD_ULOGIC);
11681 
 end component;
11682 
 
11683 
 
11684 
------ Component TRIBUFF_F_8U ------
11685 
 component TRIBUFF_F_8U
11686 
--pragma translate_off
11687 
    generic(
11688 
                TimingChecksOn:Boolean := True;
11689 
                Xon: Boolean := False;
11690 
                InstancePath: STRING :="*";
11691 
                MsgOn: Boolean := True;
11692 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11693 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11694 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11695 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11696 
 
11697 
 
11698 
--pragma translate_on
11699 
    port(
11700 
                D               : in    STD_ULOGIC;
11701 
                E               : in    STD_ULOGIC;
11702 
                PAD             : out    STD_ULOGIC);
11703 
 end component;
11704 
 
11705 
 
11706 
------ Component TRIBUFF_F_12 ------
11707 
 component TRIBUFF_F_12
11708 
--pragma translate_off
11709 
    generic(
11710 
                TimingChecksOn:Boolean := True;
11711 
                Xon: Boolean := False;
11712 
                InstancePath: STRING :="*";
11713 
                MsgOn: Boolean := True;
11714 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11715 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11716 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11717 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11718 
 
11719 
 
11720 
--pragma translate_on
11721 
    port(
11722 
                D               : in    STD_ULOGIC;
11723 
                E               : in    STD_ULOGIC;
11724 
                PAD             : out    STD_ULOGIC);
11725 
 end component;
11726 
 
11727 
 
11728 
------ Component TRIBUFF_F_12D ------
11729 
 component TRIBUFF_F_12D
11730 
--pragma translate_off
11731 
    generic(
11732 
                TimingChecksOn:Boolean := True;
11733 
                Xon: Boolean := False;
11734 
                InstancePath: STRING :="*";
11735 
                MsgOn: Boolean := True;
11736 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11737 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11738 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11739 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11740 
 
11741 
 
11742 
--pragma translate_on
11743 
    port(
11744 
                D               : in    STD_ULOGIC;
11745 
                E               : in    STD_ULOGIC;
11746 
                PAD             : out    STD_ULOGIC);
11747 
 end component;
11748 
 
11749 
 
11750 
------ Component TRIBUFF_F_12U ------
11751 
 component TRIBUFF_F_12U
11752 
--pragma translate_off
11753 
    generic(
11754 
                TimingChecksOn:Boolean := True;
11755 
                Xon: Boolean := False;
11756 
                InstancePath: STRING :="*";
11757 
                MsgOn: Boolean := True;
11758 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11759 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11760 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11761 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11762 
 
11763 
 
11764 
--pragma translate_on
11765 
    port(
11766 
                D               : in    STD_ULOGIC;
11767 
                E               : in    STD_ULOGIC;
11768 
                PAD             : out    STD_ULOGIC);
11769 
 end component;
11770 
 
11771 
 
11772 
------ Component TRIBUFF_F_16 ------
11773 
 component TRIBUFF_F_16
11774 
--pragma translate_off
11775 
    generic(
11776 
                TimingChecksOn:Boolean := True;
11777 
                Xon: Boolean := False;
11778 
                InstancePath: STRING :="*";
11779 
                MsgOn: Boolean := True;
11780 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11781 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11782 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11783 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11784 
 
11785 
 
11786 
--pragma translate_on
11787 
    port(
11788 
                D               : in    STD_ULOGIC;
11789 
                E               : in    STD_ULOGIC;
11790 
                PAD             : out    STD_ULOGIC);
11791 
 end component;
11792 
 
11793 
 
11794 
------ Component TRIBUFF_F_16D ------
11795 
 component TRIBUFF_F_16D
11796 
--pragma translate_off
11797 
    generic(
11798 
                TimingChecksOn:Boolean := True;
11799 
                Xon: Boolean := False;
11800 
                InstancePath: STRING :="*";
11801 
                MsgOn: Boolean := True;
11802 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11803 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11804 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11805 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11806 
 
11807 
 
11808 
--pragma translate_on
11809 
    port(
11810 
                D               : in    STD_ULOGIC;
11811 
                E               : in    STD_ULOGIC;
11812 
                PAD             : out    STD_ULOGIC);
11813 
 end component;
11814 
 
11815 
 
11816 
------ Component TRIBUFF_F_16U ------
11817 
 component TRIBUFF_F_16U
11818 
--pragma translate_off
11819 
    generic(
11820 
                TimingChecksOn:Boolean := True;
11821 
                Xon: Boolean := False;
11822 
                InstancePath: STRING :="*";
11823 
                MsgOn: Boolean := True;
11824 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11825 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11826 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11827 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11828 
 
11829 
 
11830 
--pragma translate_on
11831 
    port(
11832 
                D               : in    STD_ULOGIC;
11833 
                E               : in    STD_ULOGIC;
11834 
                PAD             : out    STD_ULOGIC);
11835 
 end component;
11836 
 
11837 
 
11838 
------ Component TRIBUFF_F_24 ------
11839 
 component TRIBUFF_F_24
11840 
--pragma translate_off
11841 
    generic(
11842 
                TimingChecksOn:Boolean := True;
11843 
                Xon: Boolean := False;
11844 
                InstancePath: STRING :="*";
11845 
                MsgOn: Boolean := True;
11846 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11847 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11848 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11849 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11850 
 
11851 
 
11852 
--pragma translate_on
11853 
    port(
11854 
                D               : in    STD_ULOGIC;
11855 
                E               : in    STD_ULOGIC;
11856 
                PAD             : out    STD_ULOGIC);
11857 
 end component;
11858 
 
11859 
 
11860 
------ Component TRIBUFF_F_24D ------
11861 
 component TRIBUFF_F_24D
11862 
--pragma translate_off
11863 
    generic(
11864 
                TimingChecksOn:Boolean := True;
11865 
                Xon: Boolean := False;
11866 
                InstancePath: STRING :="*";
11867 
                MsgOn: Boolean := True;
11868 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11869 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11870 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11871 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11872 
 
11873 
 
11874 
--pragma translate_on
11875 
    port(
11876 
                D               : in    STD_ULOGIC;
11877 
                E               : in    STD_ULOGIC;
11878 
                PAD             : out    STD_ULOGIC);
11879 
 end component;
11880 
 
11881 
 
11882 
------ Component TRIBUFF_F_24U ------
11883 
 component TRIBUFF_F_24U
11884 
--pragma translate_off
11885 
    generic(
11886 
                TimingChecksOn:Boolean := True;
11887 
                Xon: Boolean := False;
11888 
                InstancePath: STRING :="*";
11889 
                MsgOn: Boolean := True;
11890 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11891 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11892 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11893 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11894 
 
11895 
 
11896 
--pragma translate_on
11897 
    port(
11898 
                D               : in    STD_ULOGIC;
11899 
                E               : in    STD_ULOGIC;
11900 
                PAD             : out    STD_ULOGIC);
11901 
 end component;
11902 
 
11903 
 
11904 
------ Component TRIBUFF_LVCMOS25 ------
11905 
 component TRIBUFF_LVCMOS25
11906 
--pragma translate_off
11907 
    generic(
11908 
                TimingChecksOn:Boolean := True;
11909 
                Xon: Boolean := False;
11910 
                InstancePath: STRING :="*";
11911 
                MsgOn: Boolean := True;
11912 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11913 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11914 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11915 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11916 
 
11917 
 
11918 
--pragma translate_on
11919 
    port(
11920 
                D               : in    STD_ULOGIC;
11921 
                E               : in    STD_ULOGIC;
11922 
                PAD             : out    STD_ULOGIC);
11923 
 end component;
11924 
 
11925 
 
11926 
------ Component TRIBUFF_LVCMOS25D ------
11927 
 component TRIBUFF_LVCMOS25D
11928 
--pragma translate_off
11929 
    generic(
11930 
                TimingChecksOn:Boolean := True;
11931 
                Xon: Boolean := False;
11932 
                InstancePath: STRING :="*";
11933 
                MsgOn: Boolean := True;
11934 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11935 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11936 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11937 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11938 
 
11939 
 
11940 
--pragma translate_on
11941 
    port(
11942 
                D               : in    STD_ULOGIC;
11943 
                E               : in    STD_ULOGIC;
11944 
                PAD             : out    STD_ULOGIC);
11945 
 end component;
11946 
 
11947 
 
11948 
------ Component TRIBUFF_LVCMOS25U ------
11949 
 component TRIBUFF_LVCMOS25U
11950 
--pragma translate_off
11951 
    generic(
11952 
                TimingChecksOn:Boolean := True;
11953 
                Xon: Boolean := False;
11954 
                InstancePath: STRING :="*";
11955 
                MsgOn: Boolean := True;
11956 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11957 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11958 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11959 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11960 
 
11961 
 
11962 
--pragma translate_on
11963 
    port(
11964 
                D               : in    STD_ULOGIC;
11965 
                E               : in    STD_ULOGIC;
11966 
                PAD             : out    STD_ULOGIC);
11967 
 end component;
11968 
 
11969 
 
11970 
------ Component TRIBUFF_LVCMOS18 ------
11971 
 component TRIBUFF_LVCMOS18
11972 
--pragma translate_off
11973 
    generic(
11974 
                TimingChecksOn:Boolean := True;
11975 
                Xon: Boolean := False;
11976 
                InstancePath: STRING :="*";
11977 
                MsgOn: Boolean := True;
11978 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
11979 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
11980 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
11981 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
11982 
 
11983 
 
11984 
--pragma translate_on
11985 
    port(
11986 
                D               : in    STD_ULOGIC;
11987 
                E               : in    STD_ULOGIC;
11988 
                PAD             : out    STD_ULOGIC);
11989 
 end component;
11990 
 
11991 
 
11992 
------ Component TRIBUFF_LVCMOS18D ------
11993 
 component TRIBUFF_LVCMOS18D
11994 
--pragma translate_off
11995 
    generic(
11996 
                TimingChecksOn:Boolean := True;
11997 
                Xon: Boolean := False;
11998 
                InstancePath: STRING :="*";
11999 
                MsgOn: Boolean := True;
12000 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12001 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12002 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12003 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12004 
 
12005 
 
12006 
--pragma translate_on
12007 
    port(
12008 
                D               : in    STD_ULOGIC;
12009 
                E               : in    STD_ULOGIC;
12010 
                PAD             : out    STD_ULOGIC);
12011 
 end component;
12012 
 
12013 
 
12014 
------ Component TRIBUFF_LVCMOS18U ------
12015 
 component TRIBUFF_LVCMOS18U
12016 
--pragma translate_off
12017 
    generic(
12018 
                TimingChecksOn:Boolean := True;
12019 
                Xon: Boolean := False;
12020 
                InstancePath: STRING :="*";
12021 
                MsgOn: Boolean := True;
12022 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12023 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12024 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12025 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12026 
 
12027 
 
12028 
--pragma translate_on
12029 
    port(
12030 
                D               : in    STD_ULOGIC;
12031 
                E               : in    STD_ULOGIC;
12032 
                PAD             : out    STD_ULOGIC);
12033 
 end component;
12034 
 
12035 
 
12036 
------ Component TRIBUFF_LVCMOS15 ------
12037 
 component TRIBUFF_LVCMOS15
12038 
--pragma translate_off
12039 
    generic(
12040 
                TimingChecksOn:Boolean := True;
12041 
                Xon: Boolean := False;
12042 
                InstancePath: STRING :="*";
12043 
                MsgOn: Boolean := True;
12044 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12045 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12046 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12047 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12048 
 
12049 
 
12050 
--pragma translate_on
12051 
    port(
12052 
                D               : in    STD_ULOGIC;
12053 
                E               : in    STD_ULOGIC;
12054 
                PAD             : out    STD_ULOGIC);
12055 
 end component;
12056 
 
12057 
 
12058 
------ Component TRIBUFF_LVCMOS15D ------
12059 
 component TRIBUFF_LVCMOS15D
12060 
--pragma translate_off
12061 
    generic(
12062 
                TimingChecksOn:Boolean := True;
12063 
                Xon: Boolean := False;
12064 
                InstancePath: STRING :="*";
12065 
                MsgOn: Boolean := True;
12066 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12067 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12068 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12069 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12070 
 
12071 
 
12072 
--pragma translate_on
12073 
    port(
12074 
                D               : in    STD_ULOGIC;
12075 
                E               : in    STD_ULOGIC;
12076 
                PAD             : out    STD_ULOGIC);
12077 
 end component;
12078 
 
12079 
 
12080 
------ Component TRIBUFF_LVCMOS15U ------
12081 
 component TRIBUFF_LVCMOS15U
12082 
--pragma translate_off
12083 
    generic(
12084 
                TimingChecksOn:Boolean := True;
12085 
                Xon: Boolean := False;
12086 
                InstancePath: STRING :="*";
12087 
                MsgOn: Boolean := True;
12088 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12089 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12090 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12091 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12092 
 
12093 
 
12094 
--pragma translate_on
12095 
    port(
12096 
                D               : in    STD_ULOGIC;
12097 
                E               : in    STD_ULOGIC;
12098 
                PAD             : out    STD_ULOGIC);
12099 
 end component;
12100 
 
12101 
 
12102 
------ Component TRIBUFF_PCI ------
12103 
 component TRIBUFF_PCI
12104 
--pragma translate_off
12105 
    generic(
12106 
                TimingChecksOn:Boolean := True;
12107 
                Xon: Boolean := False;
12108 
                InstancePath: STRING :="*";
12109 
                MsgOn: Boolean := True;
12110 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12111 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12112 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12113 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12114 
 
12115 
 
12116 
--pragma translate_on
12117 
    port(
12118 
                D               : in    STD_ULOGIC;
12119 
                E               : in    STD_ULOGIC;
12120 
                PAD             : out    STD_ULOGIC);
12121 
 end component;
12122 
 
12123 
 
12124 
------ Component TRIBUFF_PCIX ------
12125 
 component TRIBUFF_PCIX
12126 
--pragma translate_off
12127 
    generic(
12128 
                TimingChecksOn:Boolean := True;
12129 
                Xon: Boolean := False;
12130 
                InstancePath: STRING :="*";
12131 
                MsgOn: Boolean := True;
12132 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12133 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12134 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12135 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12136 
 
12137 
 
12138 
--pragma translate_on
12139 
    port(
12140 
                D               : in    STD_ULOGIC;
12141 
                E               : in    STD_ULOGIC;
12142 
                PAD             : out    STD_ULOGIC);
12143 
 end component;
12144 
 
12145 
 
12146 
------ Component TRIBUFF_GTLP33 ------
12147 
 component TRIBUFF_GTLP33
12148 
--pragma translate_off
12149 
    generic(
12150 
                TimingChecksOn:Boolean := True;
12151 
                Xon: Boolean := False;
12152 
                InstancePath: STRING :="*";
12153 
                MsgOn: Boolean := True;
12154 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12155 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12156 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12157 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12158 
 
12159 
 
12160 
--pragma translate_on
12161 
    port(
12162 
                D               : in    STD_ULOGIC;
12163 
                E               : in    STD_ULOGIC;
12164 
                PAD             : out    STD_ULOGIC);
12165 
 end component;
12166 
 
12167 
 
12168 
------ Component TRIBUFF_GTLP25 ------
12169 
 component TRIBUFF_GTLP25
12170 
--pragma translate_off
12171 
    generic(
12172 
                TimingChecksOn:Boolean := True;
12173 
                Xon: Boolean := False;
12174 
                InstancePath: STRING :="*";
12175 
                MsgOn: Boolean := True;
12176 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12177 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12178 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12179 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12180 
 
12181 
 
12182 
--pragma translate_on
12183 
    port(
12184 
                D               : in    STD_ULOGIC;
12185 
                E               : in    STD_ULOGIC;
12186 
                PAD             : out    STD_ULOGIC);
12187 
 end component;
12188 
 
12189 
 
12190 
------ Component VCC ------
12191 
 component VCC
12192 
--pragma translate_off
12193 
    generic(
12194 
                TimingChecksOn:Boolean := True;
12195 
                Xon: Boolean := False;
12196 
                InstancePath: STRING :="*";
12197 
                MsgOn: Boolean := True          );
12198 
--pragma translate_on
12199 
    port(
12200 
                Y               : out    STD_ULOGIC);
12201 
 end component;
12202 
 
12203 
 
12204 
------ Component XA1 ------
12205 
 component XA1
12206 
--pragma translate_off
12207 
    generic(
12208 
                TimingChecksOn:Boolean := True;
12209 
                Xon: Boolean := False;
12210 
                InstancePath: STRING :="*";
12211 
                MsgOn: Boolean := True;
12212 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12213 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12214 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12215 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12216 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12217 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12218 
 
12219 
 
12220 
--pragma translate_on
12221 
    port(
12222 
                A               : in    STD_ULOGIC;
12223 
                B               : in    STD_ULOGIC;
12224 
                C               : in    STD_ULOGIC;
12225 
                Y               : out    STD_ULOGIC);
12226 
 end component;
12227 
 
12228 
 
12229 
------ Component XA1A ------
12230 
 component XA1A
12231 
--pragma translate_off
12232 
    generic(
12233 
                TimingChecksOn:Boolean := True;
12234 
                Xon: Boolean := False;
12235 
                InstancePath: STRING :="*";
12236 
                MsgOn: Boolean := True;
12237 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12238 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12239 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12240 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12241 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12242 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12243 
 
12244 
 
12245 
--pragma translate_on
12246 
    port(
12247 
                A               : in    STD_ULOGIC;
12248 
                B               : in    STD_ULOGIC;
12249 
                C               : in    STD_ULOGIC;
12250 
                Y               : out    STD_ULOGIC);
12251 
 end component;
12252 
 
12253 
 
12254 
------ Component XA1B ------
12255 
 component XA1B
12256 
--pragma translate_off
12257 
    generic(
12258 
                TimingChecksOn:Boolean := True;
12259 
                Xon: Boolean := False;
12260 
                InstancePath: STRING :="*";
12261 
                MsgOn: Boolean := True;
12262 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12263 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12264 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12265 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12266 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12267 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12268 
 
12269 
 
12270 
--pragma translate_on
12271 
    port(
12272 
                A               : in    STD_ULOGIC;
12273 
                B               : in    STD_ULOGIC;
12274 
                C               : in    STD_ULOGIC;
12275 
                Y               : out    STD_ULOGIC);
12276 
 end component;
12277 
 
12278 
 
12279 
------ Component XA1C ------
12280 
 component XA1C
12281 
--pragma translate_off
12282 
    generic(
12283 
                TimingChecksOn:Boolean := True;
12284 
                Xon: Boolean := False;
12285 
                InstancePath: STRING :="*";
12286 
                MsgOn: Boolean := True;
12287 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12288 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12289 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12290 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12291 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12292 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12293 
 
12294 
 
12295 
--pragma translate_on
12296 
    port(
12297 
                A               : in    STD_ULOGIC;
12298 
                B               : in    STD_ULOGIC;
12299 
                C               : in    STD_ULOGIC;
12300 
                Y               : out    STD_ULOGIC);
12301 
 end component;
12302 
 
12303 
 
12304 
------ Component XAI1 ------
12305 
 component XAI1
12306 
--pragma translate_off
12307 
    generic(
12308 
                TimingChecksOn:Boolean := True;
12309 
                Xon: Boolean := False;
12310 
                InstancePath: STRING :="*";
12311 
                MsgOn: Boolean := True;
12312 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12313 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12314 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12315 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12316 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12317 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12318 
 
12319 
 
12320 
--pragma translate_on
12321 
    port(
12322 
                A               : in    STD_ULOGIC;
12323 
                B               : in    STD_ULOGIC;
12324 
                C               : in    STD_ULOGIC;
12325 
                Y               : out    STD_ULOGIC);
12326 
 end component;
12327 
 
12328 
 
12329 
------ Component XAI1A ------
12330 
 component XAI1A
12331 
--pragma translate_off
12332 
    generic(
12333 
                TimingChecksOn:Boolean := True;
12334 
                Xon: Boolean := False;
12335 
                InstancePath: STRING :="*";
12336 
                MsgOn: Boolean := True;
12337 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12338 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12339 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12340 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12341 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12342 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12343 
 
12344 
 
12345 
--pragma translate_on
12346 
    port(
12347 
                A               : in    STD_ULOGIC;
12348 
                B               : in    STD_ULOGIC;
12349 
                C               : in    STD_ULOGIC;
12350 
                Y               : out    STD_ULOGIC);
12351 
 end component;
12352 
 
12353 
 
12354 
------ Component XNOR2 ------
12355 
 component XNOR2
12356 
--pragma translate_off
12357 
    generic(
12358 
                TimingChecksOn:Boolean := True;
12359 
                Xon: Boolean := False;
12360 
                InstancePath: STRING :="*";
12361 
                MsgOn: Boolean := True;
12362 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12363 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12364 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12365 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12366 
 
12367 
 
12368 
--pragma translate_on
12369 
    port(
12370 
                A               : in    STD_ULOGIC;
12371 
                B               : in    STD_ULOGIC;
12372 
                Y               : out    STD_ULOGIC);
12373 
 end component;
12374 
 
12375 
 
12376 
------ Component XNOR3 ------
12377 
 component XNOR3
12378 
--pragma translate_off
12379 
    generic(
12380 
                TimingChecksOn:Boolean := True;
12381 
                Xon: Boolean := False;
12382 
                InstancePath: STRING :="*";
12383 
                MsgOn: Boolean := True;
12384 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12385 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12386 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12387 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12388 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12389 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12390 
 
12391 
 
12392 
--pragma translate_on
12393 
    port(
12394 
                A               : in    STD_ULOGIC;
12395 
                B               : in    STD_ULOGIC;
12396 
                C               : in    STD_ULOGIC;
12397 
                Y               : out    STD_ULOGIC);
12398 
 end component;
12399 
 
12400 
 
12401 
------ Component XNOR4 ------
12402 
 component XNOR4
12403 
--pragma translate_off
12404 
    generic(
12405 
                TimingChecksOn:Boolean := True;
12406 
                Xon: Boolean := False;
12407 
                InstancePath: STRING :="*";
12408 
                MsgOn: Boolean := True;
12409 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12410 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12411 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12412 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12413 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12414 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12415 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12416 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12417 
 
12418 
 
12419 
--pragma translate_on
12420 
    port(
12421 
                A               : in    STD_ULOGIC;
12422 
                B               : in    STD_ULOGIC;
12423 
                C               : in    STD_ULOGIC;
12424 
                D               : in    STD_ULOGIC;
12425 
                Y               : out    STD_ULOGIC);
12426 
 end component;
12427 
 
12428 
 
12429 
------ Component XO1 ------
12430 
 component XO1
12431 
--pragma translate_off
12432 
    generic(
12433 
                TimingChecksOn:Boolean := True;
12434 
                Xon: Boolean := False;
12435 
                InstancePath: STRING :="*";
12436 
                MsgOn: Boolean := True;
12437 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12438 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12439 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12440 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12441 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12442 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12443 
 
12444 
 
12445 
--pragma translate_on
12446 
    port(
12447 
                A               : in    STD_ULOGIC;
12448 
                B               : in    STD_ULOGIC;
12449 
                C               : in    STD_ULOGIC;
12450 
                Y               : out    STD_ULOGIC);
12451 
 end component;
12452 
 
12453 
 
12454 
------ Component XO1A ------
12455 
 component XO1A
12456 
--pragma translate_off
12457 
    generic(
12458 
                TimingChecksOn:Boolean := True;
12459 
                Xon: Boolean := False;
12460 
                InstancePath: STRING :="*";
12461 
                MsgOn: Boolean := True;
12462 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12463 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12464 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12465 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12466 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12467 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12468 
 
12469 
 
12470 
--pragma translate_on
12471 
    port(
12472 
                A               : in    STD_ULOGIC;
12473 
                B               : in    STD_ULOGIC;
12474 
                C               : in    STD_ULOGIC;
12475 
                Y               : out    STD_ULOGIC);
12476 
 end component;
12477 
 
12478 
 
12479 
------ Component XOR2 ------
12480 
 component XOR2
12481 
--pragma translate_off
12482 
    generic(
12483 
                TimingChecksOn:Boolean := True;
12484 
                Xon: Boolean := False;
12485 
                InstancePath: STRING :="*";
12486 
                MsgOn: Boolean := True;
12487 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12488 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12489 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12490 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12491 
 
12492 
 
12493 
--pragma translate_on
12494 
    port(
12495 
                A               : in    STD_ULOGIC;
12496 
                B               : in    STD_ULOGIC;
12497 
                Y               : out    STD_ULOGIC);
12498 
 end component;
12499 
 
12500 
 
12501 
------ Component XOR3 ------
12502 
 component XOR3
12503 
--pragma translate_off
12504 
    generic(
12505 
                TimingChecksOn:Boolean := True;
12506 
                Xon: Boolean := False;
12507 
                InstancePath: STRING :="*";
12508 
                MsgOn: Boolean := True;
12509 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12510 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12511 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12512 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12513 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12514 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12515 
 
12516 
 
12517 
--pragma translate_on
12518 
    port(
12519 
                A               : in    STD_ULOGIC;
12520 
                B               : in    STD_ULOGIC;
12521 
                C               : in    STD_ULOGIC;
12522 
                Y               : out    STD_ULOGIC);
12523 
 end component;
12524 
 
12525 
 
12526 
------ Component XOR4 ------
12527 
 component XOR4
12528 
--pragma translate_off
12529 
    generic(
12530 
                TimingChecksOn:Boolean := True;
12531 
                Xon: Boolean := False;
12532 
                InstancePath: STRING :="*";
12533 
                MsgOn: Boolean := True;
12534 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12535 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12536 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12537 
                tpd_D_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12538 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12539 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12540 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12541 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12542 
 
12543 
 
12544 
--pragma translate_on
12545 
    port(
12546 
                A               : in    STD_ULOGIC;
12547 
                B               : in    STD_ULOGIC;
12548 
                C               : in    STD_ULOGIC;
12549 
                D               : in    STD_ULOGIC;
12550 
                Y               : out    STD_ULOGIC);
12551 
 end component;
12552 
 
12553 
 
12554 
------ Component XOR4_FCI ------
12555 
 component XOR4_FCI
12556 
--pragma translate_off
12557 
    generic(
12558 
                TimingChecksOn:Boolean := True;
12559 
                Xon: Boolean := False;
12560 
                InstancePath: STRING :="*";
12561 
                MsgOn: Boolean := True;
12562 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12563 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12564 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12565 
                tpd_FCI_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12566 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12567 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12568 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12569 
                tipd_FCI                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12570 
 
12571 
 
12572 
--pragma translate_on
12573 
    port(
12574 
                A               : in    STD_ULOGIC;
12575 
                B               : in    STD_ULOGIC;
12576 
                C               : in    STD_ULOGIC;
12577 
                FCI             : in    STD_ULOGIC;
12578 
                Y               : out    STD_ULOGIC);
12579 
 end component;
12580 
 
12581 
 
12582 
------ Component ZOR3 ------
12583 
 component ZOR3
12584 
--pragma translate_off
12585 
    generic(
12586 
                TimingChecksOn:Boolean := True;
12587 
                Xon: Boolean := False;
12588 
                InstancePath: STRING :="*";
12589 
                MsgOn: Boolean := True;
12590 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12591 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12592 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12593 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12594 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12595 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12596 
 
12597 
 
12598 
--pragma translate_on
12599 
    port(
12600 
                A               : in    STD_ULOGIC;
12601 
                B               : in    STD_ULOGIC;
12602 
                C               : in    STD_ULOGIC;
12603 
                Y               : out    STD_ULOGIC);
12604 
 end component;
12605 
 
12606 
 
12607 
------ Component ZOR3I ------
12608 
 component ZOR3I
12609 
--pragma translate_off
12610 
    generic(
12611 
                TimingChecksOn:Boolean := True;
12612 
                Xon: Boolean := False;
12613 
                InstancePath: STRING :="*";
12614 
                MsgOn: Boolean := True;
12615 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12616 
                tpd_B_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12617 
                tpd_C_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12618 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12619 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12620 
                tipd_C          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12621 
 
12622 
 
12623 
--pragma translate_on
12624 
    port(
12625 
                A               : in    STD_ULOGIC;
12626 
                B               : in    STD_ULOGIC;
12627 
                C               : in    STD_ULOGIC;
12628 
                Y               : out    STD_ULOGIC);
12629 
 end component;
12630 
 
12631 
 
12632 
------ Component IOFIFO_BIBUF ------
12633 
 component IOFIFO_BIBUF
12634 
--pragma translate_off
12635 
    generic(
12636 
                TimingChecksOn:Boolean := True;
12637 
                Xon: Boolean := False;
12638 
                InstancePath: STRING :="*";
12639 
                MsgOn: Boolean := True;
12640 
                tpd_AIN_YIN             : VitalDelayType01 := (0.100 ns, 0.100 ns);
12641 
                tpd_AOUT_YOUT           : VitalDelayType01 := (0.100 ns, 0.100 ns);
12642 
                tipd_AIN                : VitalDelayType01 := (0.000 ns, 0.000 ns);
12643 
                tipd_AOUT               : VitalDelayType01 := (0.000 ns, 0.000 ns));
12644 
 
12645 
 
12646 
--pragma translate_on
12647 
    port(
12648 
                AIN             : in    STD_ULOGIC;
12649 
                AOUT            : in    STD_ULOGIC;
12650 
                YIN             : out    STD_ULOGIC;
12651 
                YOUT            : out    STD_ULOGIC);
12652 
 end component;
12653 
 
12654 
 
12655 
------ Component IOI_FCLK_EN_BUFF ------
12656 
 component IOI_FCLK_EN_BUFF
12657 
--pragma translate_off
12658 
    generic(
12659 
                TimingChecksOn:Boolean := True;
12660 
                Xon: Boolean := False;
12661 
                InstancePath: STRING :="*";
12662 
                MsgOn: Boolean := True;
12663 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12664 
                tpd_EN_ENOUT            : VitalDelayType01 := (0.100 ns, 0.100 ns);
12665 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12666 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12667 
                tipd_EN         : VitalDelayType01 := (0.000 ns, 0.000 ns);
12668 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12669 
 
12670 
 
12671 
--pragma translate_on
12672 
    port(
12673 
                A               : in    STD_ULOGIC;
12674 
                EN              : in    STD_ULOGIC;
12675 
                CLK             : in    STD_ULOGIC;
12676 
                Y               : out    STD_ULOGIC;
12677 
                ENOUT           : out    STD_ULOGIC;
12678 
                CLKOUT          : out    STD_ULOGIC);
12679 
 end component;
12680 
 
12681 
 
12682 
------ Component IOI_FCLK_BUFF ------
12683 
 component IOI_FCLK_BUFF
12684 
--pragma translate_off
12685 
    generic(
12686 
                TimingChecksOn:Boolean := True;
12687 
                Xon: Boolean := False;
12688 
                InstancePath: STRING :="*";
12689 
                MsgOn: Boolean := True;
12690 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12691 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12692 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12693 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12694 
 
12695 
 
12696 
--pragma translate_on
12697 
    port(
12698 
                A               : in    STD_ULOGIC;
12699 
                CLK             : in    STD_ULOGIC;
12700 
                Y               : out    STD_ULOGIC;
12701 
                CLKOUT          : out    STD_ULOGIC);
12702 
 end component;
12703 
 
12704 
 
12705 
------ Component IOI_RCLK_EN_BUFF ------
12706 
 component IOI_RCLK_EN_BUFF
12707 
--pragma translate_off
12708 
    generic(
12709 
                TimingChecksOn:Boolean := True;
12710 
                Xon: Boolean := False;
12711 
                InstancePath: STRING :="*";
12712 
                MsgOn: Boolean := True;
12713 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12714 
                tpd_EN_ENOUT            : VitalDelayType01 := (0.100 ns, 0.100 ns);
12715 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12716 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12717 
                tipd_EN         : VitalDelayType01 := (0.000 ns, 0.000 ns);
12718 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12719 
 
12720 
 
12721 
--pragma translate_on
12722 
    port(
12723 
                A               : in    STD_ULOGIC;
12724 
                EN              : in    STD_ULOGIC;
12725 
                CLK             : in    STD_ULOGIC;
12726 
                Y               : out    STD_ULOGIC;
12727 
                ENOUT           : out    STD_ULOGIC;
12728 
                CLKOUT          : out    STD_ULOGIC);
12729 
 end component;
12730 
 
12731 
 
12732 
------ Component IOI_RCLK_BUFF ------
12733 
 component IOI_RCLK_BUFF
12734 
--pragma translate_off
12735 
    generic(
12736 
                TimingChecksOn:Boolean := True;
12737 
                Xon: Boolean := False;
12738 
                InstancePath: STRING :="*";
12739 
                MsgOn: Boolean := True;
12740 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12741 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12742 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12743 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12744 
 
12745 
 
12746 
--pragma translate_on
12747 
    port(
12748 
                A               : in    STD_ULOGIC;
12749 
                CLK             : in    STD_ULOGIC;
12750 
                Y               : out    STD_ULOGIC;
12751 
                CLKOUT          : out    STD_ULOGIC);
12752 
 end component;
12753 
 
12754 
 
12755 
------ Component IOOE_FCLK_EN_BUFF ------
12756 
 component IOOE_FCLK_EN_BUFF
12757 
--pragma translate_off
12758 
    generic(
12759 
                TimingChecksOn:Boolean := True;
12760 
                Xon: Boolean := False;
12761 
                InstancePath: STRING :="*";
12762 
                MsgOn: Boolean := True;
12763 
                tpd_A_YOUT              : VitalDelayType01 := (0.100 ns, 0.100 ns);
12764 
                tpd_EN_ENOUT            : VitalDelayType01 := (0.100 ns, 0.100 ns);
12765 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12766 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12767 
                tipd_EN         : VitalDelayType01 := (0.000 ns, 0.000 ns);
12768 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12769 
 
12770 
 
12771 
--pragma translate_on
12772 
    port(
12773 
                A               : in    STD_ULOGIC;
12774 
                EN              : in    STD_ULOGIC;
12775 
                CLK             : in    STD_ULOGIC;
12776 
                YOUT            : out    STD_ULOGIC;
12777 
                ENOUT           : out    STD_ULOGIC;
12778 
                CLKOUT          : out    STD_ULOGIC);
12779 
 end component;
12780 
 
12781 
 
12782 
------ Component IOOE_FCLK ------
12783 
 component IOOE_FCLK
12784 
--pragma translate_off
12785 
    generic(
12786 
                TimingChecksOn:Boolean := True;
12787 
                Xon: Boolean := False;
12788 
                InstancePath: STRING :="*";
12789 
                MsgOn: Boolean := True;
12790 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12791 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12792 
 
12793 
 
12794 
--pragma translate_on
12795 
    port(
12796 
                CLK             : in    STD_ULOGIC;
12797 
                CLKOUT          : out    STD_ULOGIC);
12798 
 end component;
12799 
 
12800 
 
12801 
------ Component IOOE_RCLK_EN_BUFF ------
12802 
 component IOOE_RCLK_EN_BUFF
12803 
--pragma translate_off
12804 
    generic(
12805 
                TimingChecksOn:Boolean := True;
12806 
                Xon: Boolean := False;
12807 
                InstancePath: STRING :="*";
12808 
                MsgOn: Boolean := True;
12809 
                tpd_A_YOUT              : VitalDelayType01 := (0.100 ns, 0.100 ns);
12810 
                tpd_EN_ENOUT            : VitalDelayType01 := (0.100 ns, 0.100 ns);
12811 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12812 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12813 
                tipd_EN         : VitalDelayType01 := (0.000 ns, 0.000 ns);
12814 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12815 
 
12816 
 
12817 
--pragma translate_on
12818 
    port(
12819 
                A               : in    STD_ULOGIC;
12820 
                EN              : in    STD_ULOGIC;
12821 
                CLK             : in    STD_ULOGIC;
12822 
                YOUT            : out    STD_ULOGIC;
12823 
                ENOUT           : out    STD_ULOGIC;
12824 
                CLKOUT          : out    STD_ULOGIC);
12825 
 end component;
12826 
 
12827 
 
12828 
------ Component IOOE_RCLK_CLR_EN ------
12829 
 component IOOE_RCLK_CLR_EN
12830 
--pragma translate_off
12831 
    generic(
12832 
                TimingChecksOn:Boolean := True;
12833 
                Xon: Boolean := False;
12834 
                InstancePath: STRING :="*";
12835 
                MsgOn: Boolean := True;
12836 
                tpd_CLR_CLROUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12837 
                tpd_EN_ENOUT            : VitalDelayType01 := (0.100 ns, 0.100 ns);
12838 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12839 
                tipd_CLR                : VitalDelayType01 := (0.000 ns, 0.000 ns);
12840 
                tipd_EN         : VitalDelayType01 := (0.000 ns, 0.000 ns);
12841 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12842 
 
12843 
 
12844 
--pragma translate_on
12845 
    port(
12846 
                CLR             : in    STD_ULOGIC;
12847 
                EN              : in    STD_ULOGIC;
12848 
                CLK             : in    STD_ULOGIC;
12849 
                CLROUT          : out    STD_ULOGIC;
12850 
                ENOUT           : out    STD_ULOGIC;
12851 
                CLKOUT          : out    STD_ULOGIC);
12852 
 end component;
12853 
 
12854 
 
12855 
------ Component IOOE_RCLK_BUFF ------
12856 
 component IOOE_RCLK_BUFF
12857 
--pragma translate_off
12858 
    generic(
12859 
                TimingChecksOn:Boolean := True;
12860 
                Xon: Boolean := False;
12861 
                InstancePath: STRING :="*";
12862 
                MsgOn: Boolean := True;
12863 
                tpd_A_YOUT              : VitalDelayType01 := (0.100 ns, 0.100 ns);
12864 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12865 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12866 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12867 
 
12868 
 
12869 
--pragma translate_on
12870 
    port(
12871 
                A               : in    STD_ULOGIC;
12872 
                CLK             : in    STD_ULOGIC;
12873 
                YOUT            : out    STD_ULOGIC;
12874 
                CLKOUT          : out    STD_ULOGIC);
12875 
 end component;
12876 
 
12877 
 
12878 
------ Component IOOE_RCLK ------
12879 
 component IOOE_RCLK
12880 
--pragma translate_off
12881 
    generic(
12882 
                TimingChecksOn:Boolean := True;
12883 
                Xon: Boolean := False;
12884 
                InstancePath: STRING :="*";
12885 
                MsgOn: Boolean := True;
12886 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
12887 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12888 
 
12889 
 
12890 
--pragma translate_on
12891 
    port(
12892 
                CLK             : in    STD_ULOGIC;
12893 
                CLKOUT          : out    STD_ULOGIC);
12894 
 end component;
12895 
 
12896 
 
12897 
------ Component PLLINT ------
12898 
 component PLLINT
12899 
--pragma translate_off
12900 
    generic(
12901 
                TimingChecksOn:Boolean := True;
12902 
                Xon: Boolean := False;
12903 
                InstancePath: STRING :="*";
12904 
                MsgOn: Boolean := True;
12905 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12906 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12907 
 
12908 
 
12909 
--pragma translate_on
12910 
    port(
12911 
                A               : in    STD_ULOGIC;
12912 
                Y               : out    STD_ULOGIC);
12913 
 end component;
12914 
 
12915 
 
12916 
------ Component PLLOUT ------
12917 
 component PLLOUT
12918 
--pragma translate_off
12919 
    generic(
12920 
                TimingChecksOn:Boolean := True;
12921 
                Xon: Boolean := False;
12922 
                InstancePath: STRING :="*";
12923 
                MsgOn: Boolean := True;
12924 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
12925 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
12926 
 
12927 
 
12928 
--pragma translate_on
12929 
    port(
12930 
                A               : in    STD_ULOGIC;
12931 
                Y               : out    STD_ULOGIC);
12932 
 end component;
12933 
 
12934 
 
12935 
------ Component BIBUF_HSTL_I ------
12936 
 component BIBUF_HSTL_I
12937 
--pragma translate_off
12938 
    generic(
12939 
                TimingChecksOn:Boolean := True;
12940 
                Xon: Boolean := False;
12941 
                InstancePath: STRING :="*";
12942 
                MsgOn: Boolean := True;
12943 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12944 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12945 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12946 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
12947 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
12948 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12949 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12950 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12951 
 
12952 
 
12953 
--pragma translate_on
12954 
    port(
12955 
                D               : in    STD_ULOGIC;
12956 
                E               : in    STD_ULOGIC;
12957 
                PAD             : inout STD_ULOGIC;
12958 
                Y               : out    STD_ULOGIC);
12959 
 end component;
12960 
 
12961 
 
12962 
------ Component BIBUF_SSTL3_I ------
12963 
 component BIBUF_SSTL3_I
12964 
--pragma translate_off
12965 
    generic(
12966 
                TimingChecksOn:Boolean := True;
12967 
                Xon: Boolean := False;
12968 
                InstancePath: STRING :="*";
12969 
                MsgOn: Boolean := True;
12970 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12971 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12972 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12973 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
12974 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
12975 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12976 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
12977 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
12978 
 
12979 
 
12980 
--pragma translate_on
12981 
    port(
12982 
                D               : in    STD_ULOGIC;
12983 
                E               : in    STD_ULOGIC;
12984 
                PAD             : inout STD_ULOGIC;
12985 
                Y               : out    STD_ULOGIC);
12986 
 end component;
12987 
 
12988 
 
12989 
------ Component BIBUF_SSTL3_II ------
12990 
 component BIBUF_SSTL3_II
12991 
--pragma translate_off
12992 
    generic(
12993 
                TimingChecksOn:Boolean := True;
12994 
                Xon: Boolean := False;
12995 
                InstancePath: STRING :="*";
12996 
                MsgOn: Boolean := True;
12997 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
12998 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
12999 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
13000 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
13001 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
13002 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
13003 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
13004 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
13005 
 
13006 
 
13007 
--pragma translate_on
13008 
    port(
13009 
                D               : in    STD_ULOGIC;
13010 
                E               : in    STD_ULOGIC;
13011 
                PAD             : inout STD_ULOGIC;
13012 
                Y               : out    STD_ULOGIC);
13013 
 end component;
13014 
 
13015 
 
13016 
------ Component BIBUF_SSTL2_I ------
13017 
 component BIBUF_SSTL2_I
13018 
--pragma translate_off
13019 
    generic(
13020 
                TimingChecksOn:Boolean := True;
13021 
                Xon: Boolean := False;
13022 
                InstancePath: STRING :="*";
13023 
                MsgOn: Boolean := True;
13024 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
13025 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
13026 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
13027 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
13028 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
13029 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
13030 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
13031 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
13032 
 
13033 
 
13034 
--pragma translate_on
13035 
    port(
13036 
                D               : in    STD_ULOGIC;
13037 
                E               : in    STD_ULOGIC;
13038 
                PAD             : inout STD_ULOGIC;
13039 
                Y               : out    STD_ULOGIC);
13040 
 end component;
13041 
 
13042 
 
13043 
------ Component BIBUF_SSTL2_II ------
13044 
 component BIBUF_SSTL2_II
13045 
--pragma translate_off
13046 
    generic(
13047 
                TimingChecksOn:Boolean := True;
13048 
                Xon: Boolean := False;
13049 
                InstancePath: STRING :="*";
13050 
                MsgOn: Boolean := True;
13051 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
13052 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
13053 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
13054 
                        tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
13055 
                        tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
13056 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
13057 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
13058 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
13059 
 
13060 
 
13061 
--pragma translate_on
13062 
    port(
13063 
                D               : in    STD_ULOGIC;
13064 
                E               : in    STD_ULOGIC;
13065 
                PAD             : inout STD_ULOGIC;
13066 
                Y               : out    STD_ULOGIC);
13067 
 end component;
13068 
 
13069 
 
13070 
------ Component BUFF ------
13071 
 component BUFF
13072 
--pragma translate_off
13073 
    generic(
13074 
                TimingChecksOn:Boolean := True;
13075 
                Xon: Boolean := False;
13076 
                InstancePath: STRING :="*";
13077 
                MsgOn: Boolean := True;
13078 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
13079 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
13080 
 
13081 
 
13082 
--pragma translate_on
13083 
    port(
13084 
                A               : in    STD_ULOGIC;
13085 
                Y               : out    STD_ULOGIC);
13086 
 end component;
13087 
 
13088 
 
13089 
------ Component CLKINT ------
13090 
 component CLKINT
13091 
--pragma translate_off
13092 
    generic(
13093 
                TimingChecksOn:Boolean := True;
13094 
                Xon: Boolean := False;
13095 
                InstancePath: STRING :="*";
13096 
                MsgOn: Boolean := True;
13097 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
13098 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
13099 
 
13100 
 
13101 
--pragma translate_on
13102 
    port(
13103 
                A               : in    STD_ULOGIC;
13104 
                Y               : out    STD_ULOGIC);
13105 
 end component;
13106 
 
13107 
 
13108 
------ Component CLKINT_W ------
13109 
 component CLKINT_W
13110 
--pragma translate_off
13111 
    generic(
13112 
                TimingChecksOn:Boolean := True;
13113 
                Xon: Boolean := False;
13114 
                InstancePath: STRING :="*";
13115 
                MsgOn: Boolean := True;
13116 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
13117 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
13118 
 
13119 
 
13120 
--pragma translate_on
13121 
    port(
13122 
                A               : in    STD_ULOGIC;
13123 
                Y               : out    STD_ULOGIC);
13124 
 end component;
13125 
 
13126 
 
13127 
------ Component CLKOUT_E ------
13128 
 component CLKOUT_E
13129 
--pragma translate_off
13130 
    generic(
13131 
                TimingChecksOn:Boolean := True;
13132 
                Xon: Boolean := False;
13133 
                InstancePath: STRING :="*";
13134 
                MsgOn: Boolean := True;
13135 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
13136 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
13137 
 
13138 
 
13139 
--pragma translate_on
13140 
    port(
13141 
                A               : in    STD_ULOGIC;
13142 
                Y               : out    STD_ULOGIC);
13143 
 end component;
13144 
 
13145 
 
13146 
------ Component CLKOUT_W ------
13147 
 component CLKOUT_W
13148 
--pragma translate_off
13149 
    generic(
13150 
                TimingChecksOn:Boolean := True;
13151 
                Xon: Boolean := False;
13152 
                InstancePath: STRING :="*";
13153 
                MsgOn: Boolean := True;
13154 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
13155 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
13156 
 
13157 
 
13158 
--pragma translate_on
13159 
    port(
13160 
                A               : in    STD_ULOGIC;
13161 
                Y               : out    STD_ULOGIC);
13162 
 end component;
13163 
 
13164 
 
13165 
------ Component DFM ------
13166 
 component DFM
13167 
--pragma translate_off
13168 
    generic(
13169 
                TimingChecksOn: Boolean := True;
13170 
                InstancePath: STRING := "*";
13171 
                Xon: Boolean := False;
13172 
                MsgOn: Boolean := True;
13173 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13174 
                tsetup_S_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13175 
                thold_S_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13176 
                tsetup_A_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13177 
                thold_A_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13178 
                tsetup_B_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13179 
                thold_B_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13180 
                tsetup_S_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13181 
                thold_S_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13182 
                tsetup_A_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13183 
                thold_A_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13184 
                tsetup_B_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13185 
                thold_B_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13186 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13187 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13188 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13189 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13190 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13191 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13192 
 
13193 
 
13194 
--pragma translate_on
13195 
    port(
13196 
                CLK             :   in    STD_ULOGIC;
13197 
                S               :  in    STD_ULOGIC;
13198 
                A               :  in    STD_ULOGIC;
13199 
                B               :  in    STD_ULOGIC;
13200 
                Q               :  out    STD_ULOGIC);
13201 
 
13202 
 end component;
13203 
 
13204 
 
13205 
------ Component DFM3B ------
13206 
 component DFM3B
13207 
--pragma translate_off
13208 
    generic(
13209 
                TimingChecksOn: Boolean := True;
13210 
                InstancePath: STRING := "*";
13211 
                Xon: Boolean := False;
13212 
                MsgOn: Boolean := True;
13213 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13214 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13215 
                tsetup_S_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13216 
                thold_S_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13217 
                tsetup_A_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13218 
                thold_A_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13219 
                tsetup_B_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13220 
                thold_B_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13221 
                tsetup_S_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13222 
                thold_S_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13223 
                tsetup_A_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13224 
                thold_A_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13225 
                tsetup_B_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13226 
                thold_B_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13227 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
13228 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
13229 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13230 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13231 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
13232 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13233 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13234 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13235 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13236 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13237 
 
13238 
 
13239 
--pragma translate_on
13240 
    port(
13241 
                CLR             :   in    STD_ULOGIC;
13242 
                CLK             :   in    STD_ULOGIC;
13243 
                S               :  in    STD_ULOGIC;
13244 
                A               :  in    STD_ULOGIC;
13245 
                B               :  in    STD_ULOGIC;
13246 
                Q               :  out    STD_ULOGIC);
13247 
 
13248 
 end component;
13249 
 
13250 
 
13251 
------ Component DFM4A ------
13252 
 component DFM4A
13253 
--pragma translate_off
13254 
    generic(
13255 
                TimingChecksOn: Boolean := True;
13256 
                InstancePath: STRING := "*";
13257 
                Xon: Boolean := False;
13258 
                MsgOn: Boolean := True;
13259 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13260 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13261 
                tsetup_S_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13262 
                thold_S_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13263 
                tsetup_A_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13264 
                thold_A_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13265 
                tsetup_B_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13266 
                thold_B_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13267 
                tsetup_S_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13268 
                thold_S_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13269 
                tsetup_A_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13270 
                thold_A_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13271 
                tsetup_B_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13272 
                thold_B_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13273 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
13274 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
13275 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13276 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13277 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
13278 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13279 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13280 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13281 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13282 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13283 
 
13284 
 
13285 
--pragma translate_on
13286 
    port(
13287 
                PRE             :   in    STD_ULOGIC;
13288 
                CLK             :   in    STD_ULOGIC;
13289 
                S               :  in    STD_ULOGIC;
13290 
                A               :  in    STD_ULOGIC;
13291 
                B               :  in    STD_ULOGIC;
13292 
                Q               :  out    STD_ULOGIC);
13293 
 
13294 
 end component;
13295 
 
13296 
 
13297 
------ Component DFM4B ------
13298 
 component DFM4B
13299 
--pragma translate_off
13300 
    generic(
13301 
                TimingChecksOn: Boolean := True;
13302 
                InstancePath: STRING := "*";
13303 
                Xon: Boolean := False;
13304 
                MsgOn: Boolean := True;
13305 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13306 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13307 
                tsetup_S_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13308 
                thold_S_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13309 
                tsetup_A_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13310 
                thold_A_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13311 
                tsetup_B_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13312 
                thold_B_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13313 
                tsetup_S_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13314 
                thold_S_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13315 
                tsetup_A_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13316 
                thold_A_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13317 
                tsetup_B_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13318 
                thold_B_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13319 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
13320 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
13321 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13322 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13323 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
13324 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13325 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13326 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13327 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13328 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13329 
 
13330 
 
13331 
--pragma translate_on
13332 
    port(
13333 
                PRE             :   in    STD_ULOGIC;
13334 
                CLK             :   in    STD_ULOGIC;
13335 
                S               :  in    STD_ULOGIC;
13336 
                A               :  in    STD_ULOGIC;
13337 
                B               :  in    STD_ULOGIC;
13338 
                Q               :  out    STD_ULOGIC);
13339 
 
13340 
 end component;
13341 
 
13342 
 
13343 
------ Component DFMA ------
13344 
 component DFMA
13345 
--pragma translate_off
13346 
    generic(
13347 
                TimingChecksOn: Boolean := True;
13348 
                InstancePath: STRING := "*";
13349 
                Xon: Boolean := False;
13350 
                MsgOn: Boolean := True;
13351 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13352 
                tsetup_S_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13353 
                thold_S_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13354 
                tsetup_A_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13355 
                thold_A_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13356 
                tsetup_B_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13357 
                thold_B_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13358 
                tsetup_S_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13359 
                thold_S_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13360 
                tsetup_A_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13361 
                thold_A_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13362 
                tsetup_B_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13363 
                thold_B_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13364 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13365 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13366 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13367 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13368 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13369 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13370 
 
13371 
 
13372 
--pragma translate_on
13373 
    port(
13374 
                CLK             :   in    STD_ULOGIC;
13375 
                S               :  in    STD_ULOGIC;
13376 
                A               :  in    STD_ULOGIC;
13377 
                B               :  in    STD_ULOGIC;
13378 
                Q               :  out    STD_ULOGIC);
13379 
 
13380 
 end component;
13381 
 
13382 
 
13383 
------ Component DFMB ------
13384 
 component DFMB
13385 
--pragma translate_off
13386 
    generic(
13387 
                TimingChecksOn: Boolean := True;
13388 
                InstancePath: STRING := "*";
13389 
                Xon: Boolean := False;
13390 
                MsgOn: Boolean := True;
13391 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13392 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13393 
                tsetup_S_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13394 
                thold_S_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13395 
                tsetup_A_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13396 
                thold_A_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13397 
                tsetup_B_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13398 
                thold_B_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13399 
                tsetup_S_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13400 
                thold_S_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13401 
                tsetup_A_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13402 
                thold_A_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13403 
                tsetup_B_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13404 
                thold_B_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13405 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
13406 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
13407 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13408 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13409 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
13410 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13411 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13412 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13413 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13414 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13415 
 
13416 
 
13417 
--pragma translate_on
13418 
    port(
13419 
                CLR             :   in    STD_ULOGIC;
13420 
                CLK             :   in    STD_ULOGIC;
13421 
                S               :  in    STD_ULOGIC;
13422 
                A               :  in    STD_ULOGIC;
13423 
                B               :  in    STD_ULOGIC;
13424 
                Q               :  out    STD_ULOGIC);
13425 
 
13426 
 end component;
13427 
 
13428 
 
13429 
------ Component DFME1A ------
13430 
 component DFME1A
13431 
--pragma translate_off
13432 
    generic(
13433 
                TimingChecksOn: Boolean := True;
13434 
                InstancePath: STRING := "*";
13435 
                Xon: Boolean := False;
13436 
                MsgOn: Boolean := True;
13437 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13438 
                tsetup_S_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13439 
                thold_S_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13440 
                tsetup_A_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13441 
                thold_A_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13442 
                tsetup_B_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13443 
                thold_B_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13444 
                tsetup_S_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13445 
                thold_S_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13446 
                tsetup_A_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13447 
                thold_A_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13448 
                tsetup_B_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13449 
                thold_B_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13450 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13451 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13452 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13453 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13454 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13455 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13456 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13457 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13458 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13459 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13460 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13461 
 
13462 
 
13463 
--pragma translate_on
13464 
    port(
13465 
                E               :   in    STD_ULOGIC;
13466 
                CLK             :   in    STD_ULOGIC;
13467 
                S               :  in    STD_ULOGIC;
13468 
                A               :  in    STD_ULOGIC;
13469 
                B               :  in    STD_ULOGIC;
13470 
                Q               :  out    STD_ULOGIC);
13471 
 
13472 
 end component;
13473 
 
13474 
 
13475 
------ Component DFME1B ------
13476 
 component DFME1B
13477 
--pragma translate_off
13478 
    generic(
13479 
                TimingChecksOn: Boolean := True;
13480 
                InstancePath: STRING := "*";
13481 
                Xon: Boolean := False;
13482 
                MsgOn: Boolean := True;
13483 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13484 
                tsetup_S_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13485 
                thold_S_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13486 
                tsetup_A_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13487 
                thold_A_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13488 
                tsetup_B_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13489 
                thold_B_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13490 
                tsetup_S_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13491 
                thold_S_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13492 
                tsetup_A_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13493 
                thold_A_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13494 
                tsetup_B_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13495 
                thold_B_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13496 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13497 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13498 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13499 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13500 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13501 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13502 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13503 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13504 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13505 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13506 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13507 
 
13508 
 
13509 
--pragma translate_on
13510 
    port(
13511 
                E               :   in    STD_ULOGIC;
13512 
                CLK             :   in    STD_ULOGIC;
13513 
                S               :  in    STD_ULOGIC;
13514 
                A               :  in    STD_ULOGIC;
13515 
                B               :  in    STD_ULOGIC;
13516 
                Q               :  out    STD_ULOGIC);
13517 
 
13518 
 end component;
13519 
 
13520 
 
13521 
------ Component DFME2A ------
13522 
 component DFME2A
13523 
--pragma translate_off
13524 
    generic(
13525 
                TimingChecksOn: Boolean := True;
13526 
                InstancePath: STRING := "*";
13527 
                Xon: Boolean := False;
13528 
                MsgOn: Boolean := True;
13529 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13530 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13531 
                tsetup_S_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13532 
                thold_S_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13533 
                tsetup_A_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13534 
                thold_A_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13535 
                tsetup_B_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13536 
                thold_B_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13537 
                tsetup_S_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13538 
                thold_S_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13539 
                tsetup_A_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13540 
                thold_A_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13541 
                tsetup_B_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13542 
                thold_B_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13543 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13544 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13545 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13546 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13547 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
13548 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
13549 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13550 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13551 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
13552 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13553 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13554 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13555 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13556 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13557 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13558 
 
13559 
 
13560 
--pragma translate_on
13561 
    port(
13562 
                PRE             :   in    STD_ULOGIC;
13563 
                E               :   in    STD_ULOGIC;
13564 
                CLK             :   in    STD_ULOGIC;
13565 
                S               :  in    STD_ULOGIC;
13566 
                A               :  in    STD_ULOGIC;
13567 
                B               :  in    STD_ULOGIC;
13568 
                Q               :  out    STD_ULOGIC);
13569 
 
13570 
 end component;
13571 
 
13572 
 
13573 
------ Component DFME2B ------
13574 
 component DFME2B
13575 
--pragma translate_off
13576 
    generic(
13577 
                TimingChecksOn: Boolean := True;
13578 
                InstancePath: STRING := "*";
13579 
                Xon: Boolean := False;
13580 
                MsgOn: Boolean := True;
13581 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13582 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13583 
                tsetup_S_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13584 
                thold_S_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13585 
                tsetup_A_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13586 
                thold_A_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13587 
                tsetup_B_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13588 
                thold_B_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13589 
                tsetup_S_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13590 
                thold_S_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13591 
                tsetup_A_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13592 
                thold_A_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13593 
                tsetup_B_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13594 
                thold_B_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13595 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13596 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13597 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13598 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13599 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
13600 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
13601 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13602 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13603 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
13604 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13605 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13606 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13607 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13608 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13609 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13610 
 
13611 
 
13612 
--pragma translate_on
13613 
    port(
13614 
                PRE             :   in    STD_ULOGIC;
13615 
                E               :   in    STD_ULOGIC;
13616 
                CLK             :   in    STD_ULOGIC;
13617 
                S               :  in    STD_ULOGIC;
13618 
                A               :  in    STD_ULOGIC;
13619 
                B               :  in    STD_ULOGIC;
13620 
                Q               :  out    STD_ULOGIC);
13621 
 
13622 
 end component;
13623 
 
13624 
 
13625 
------ Component DFME3A ------
13626 
 component DFME3A
13627 
--pragma translate_off
13628 
    generic(
13629 
                TimingChecksOn: Boolean := True;
13630 
                InstancePath: STRING := "*";
13631 
                Xon: Boolean := False;
13632 
                MsgOn: Boolean := True;
13633 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13634 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13635 
                tsetup_S_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13636 
                thold_S_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13637 
                tsetup_A_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13638 
                thold_A_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13639 
                tsetup_B_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13640 
                thold_B_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13641 
                tsetup_S_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13642 
                thold_S_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13643 
                tsetup_A_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13644 
                thold_A_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13645 
                tsetup_B_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13646 
                thold_B_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13647 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13648 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13649 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13650 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13651 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
13652 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
13653 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13654 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13655 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
13656 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13657 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13658 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13659 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13660 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13661 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13662 
 
13663 
 
13664 
--pragma translate_on
13665 
    port(
13666 
                CLR             :   in    STD_ULOGIC;
13667 
                E               :   in    STD_ULOGIC;
13668 
                CLK             :   in    STD_ULOGIC;
13669 
                S               :  in    STD_ULOGIC;
13670 
                A               :  in    STD_ULOGIC;
13671 
                B               :  in    STD_ULOGIC;
13672 
                Q               :  out    STD_ULOGIC);
13673 
 
13674 
 end component;
13675 
 
13676 
 
13677 
------ Component DFME3B ------
13678 
 component DFME3B
13679 
--pragma translate_off
13680 
    generic(
13681 
                TimingChecksOn: Boolean := True;
13682 
                InstancePath: STRING := "*";
13683 
                Xon: Boolean := False;
13684 
                MsgOn: Boolean := True;
13685 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13686 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13687 
                tsetup_S_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13688 
                thold_S_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13689 
                tsetup_A_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13690 
                thold_A_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13691 
                tsetup_B_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13692 
                thold_B_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13693 
                tsetup_S_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13694 
                thold_S_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13695 
                tsetup_A_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13696 
                thold_A_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13697 
                tsetup_B_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13698 
                thold_B_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13699 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13700 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13701 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13702 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13703 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
13704 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
13705 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13706 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13707 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
13708 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13709 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13710 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13711 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13712 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13713 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13714 
 
13715 
 
13716 
--pragma translate_on
13717 
    port(
13718 
                CLR             :   in    STD_ULOGIC;
13719 
                E               :   in    STD_ULOGIC;
13720 
                CLK             :   in    STD_ULOGIC;
13721 
                S               :  in    STD_ULOGIC;
13722 
                A               :  in    STD_ULOGIC;
13723 
                B               :  in    STD_ULOGIC;
13724 
                Q               :  out    STD_ULOGIC);
13725 
 
13726 
 end component;
13727 
 
13728 
 
13729 
------ Component DFMEG ------
13730 
 component DFMEG
13731 
--pragma translate_off
13732 
    generic(
13733 
                TimingChecksOn: Boolean := True;
13734 
                InstancePath: STRING := "*";
13735 
                Xon: Boolean := False;
13736 
                MsgOn: Boolean := True;
13737 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13738 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13739 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13740 
                tsetup_S_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13741 
                thold_S_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13742 
                tsetup_A_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13743 
                thold_A_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13744 
                tsetup_B_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13745 
                thold_B_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13746 
                tsetup_S_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13747 
                thold_S_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13748 
                tsetup_A_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13749 
                thold_A_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13750 
                tsetup_B_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13751 
                thold_B_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13752 
                tsetup_E_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13753 
                thold_E_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13754 
                tsetup_E_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13755 
                thold_E_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13756 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
13757 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
13758 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
13759 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
13760 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13761 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13762 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
13763 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
13764 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13765 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13766 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13767 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13768 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13769 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13770 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13771 
 
13772 
 
13773 
--pragma translate_on
13774 
    port(
13775 
                CLR             :   in    STD_ULOGIC;
13776 
                PRE             :   in    STD_ULOGIC;
13777 
                E               :   in    STD_ULOGIC;
13778 
                CLK             :   in    STD_ULOGIC;
13779 
                S               :  in    STD_ULOGIC;
13780 
                A               :  in    STD_ULOGIC;
13781 
                B               :  in    STD_ULOGIC;
13782 
                Q               :  out    STD_ULOGIC);
13783 
 
13784 
 end component;
13785 
 
13786 
 
13787 
------ Component DFMEH ------
13788 
 component DFMEH
13789 
--pragma translate_off
13790 
    generic(
13791 
                TimingChecksOn: Boolean := True;
13792 
                InstancePath: STRING := "*";
13793 
                Xon: Boolean := False;
13794 
                MsgOn: Boolean := True;
13795 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13796 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13797 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13798 
                tsetup_S_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13799 
                thold_S_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13800 
                tsetup_A_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13801 
                thold_A_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13802 
                tsetup_B_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13803 
                thold_B_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13804 
                tsetup_S_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13805 
                thold_S_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13806 
                tsetup_A_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13807 
                thold_A_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13808 
                tsetup_B_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13809 
                thold_B_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13810 
                tsetup_E_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13811 
                thold_E_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13812 
                tsetup_E_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13813 
                thold_E_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13814 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
13815 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
13816 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
13817 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
13818 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13819 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13820 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
13821 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
13822 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13823 
                tipd_E          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13824 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13825 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13826 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13827 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13828 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13829 
 
13830 
 
13831 
--pragma translate_on
13832 
    port(
13833 
                CLR             :   in    STD_ULOGIC;
13834 
                PRE             :   in    STD_ULOGIC;
13835 
                E               :   in    STD_ULOGIC;
13836 
                CLK             :   in    STD_ULOGIC;
13837 
                S               :  in    STD_ULOGIC;
13838 
                A               :  in    STD_ULOGIC;
13839 
                B               :  in    STD_ULOGIC;
13840 
                Q               :  out    STD_ULOGIC);
13841 
 
13842 
 end component;
13843 
 
13844 
 
13845 
------ Component DFMPCA ------
13846 
 component DFMPCA
13847 
--pragma translate_off
13848 
    generic(
13849 
                TimingChecksOn: Boolean := True;
13850 
                InstancePath: STRING := "*";
13851 
                Xon: Boolean := False;
13852 
                MsgOn: Boolean := True;
13853 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13854 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13855 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13856 
                tsetup_S_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13857 
                thold_S_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13858 
                tsetup_A_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13859 
                thold_A_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13860 
                tsetup_B_CLK_posedge_posedge            :   VitalDelayType := 0.000 ns;
13861 
                thold_B_CLK_posedge_posedge             :   VitalDelayType := 0.000 ns;
13862 
                tsetup_S_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13863 
                thold_S_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13864 
                tsetup_A_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13865 
                thold_A_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13866 
                tsetup_B_CLK_negedge_posedge            :   VitalDelayType := 0.000 ns;
13867 
                thold_B_CLK_negedge_posedge             :   VitalDelayType := 0.000 ns;
13868 
                thold_PRE_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
13869 
                trecovery_PRE_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
13870 
                thold_CLR_CLK_posedge_posedge           :   VitalDelayType := 0.000 ns;
13871 
                trecovery_CLR_CLK_posedge_posedge               :   VitalDelayType := 0.000 ns;
13872 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13873 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13874 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
13875 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
13876 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13877 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13878 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13879 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13880 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13881 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13882 
 
13883 
 
13884 
--pragma translate_on
13885 
    port(
13886 
                CLR             :   in    STD_ULOGIC;
13887 
                PRE             :   in    STD_ULOGIC;
13888 
                CLK             :   in    STD_ULOGIC;
13889 
                S               :  in    STD_ULOGIC;
13890 
                A               :  in    STD_ULOGIC;
13891 
                B               :  in    STD_ULOGIC;
13892 
                Q               :  out    STD_ULOGIC);
13893 
 
13894 
 end component;
13895 
 
13896 
 
13897 
------ Component DFMPCB ------
13898 
 component DFMPCB
13899 
--pragma translate_off
13900 
    generic(
13901 
                TimingChecksOn: Boolean := True;
13902 
                InstancePath: STRING := "*";
13903 
                Xon: Boolean := False;
13904 
                MsgOn: Boolean := True;
13905 
                tpd_PRE_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13906 
                tpd_CLR_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13907 
                tpd_CLK_Q               :  VitalDelayType01 := (0.100 ns, 0.100 ns);
13908 
                tsetup_S_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13909 
                thold_S_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13910 
                tsetup_A_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13911 
                thold_A_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13912 
                tsetup_B_CLK_posedge_negedge            :   VitalDelayType := 0.000 ns;
13913 
                thold_B_CLK_posedge_negedge             :   VitalDelayType := 0.000 ns;
13914 
                tsetup_S_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13915 
                thold_S_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13916 
                tsetup_A_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13917 
                thold_A_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13918 
                tsetup_B_CLK_negedge_negedge            :   VitalDelayType := 0.000 ns;
13919 
                thold_B_CLK_negedge_negedge             :   VitalDelayType := 0.000 ns;
13920 
                thold_PRE_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
13921 
                trecovery_PRE_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
13922 
                thold_CLR_CLK_posedge_negedge           :   VitalDelayType := 0.000 ns;
13923 
                trecovery_CLR_CLK_posedge_negedge               :   VitalDelayType := 0.000 ns;
13924 
                tpw_CLK_posedge :  VitalDelayType := 0.000 ns;
13925 
                tpw_CLK_negedge  :  VitalDelayType := 0.000 ns;
13926 
                tpw_PRE_negedge         :  VitalDelayType := 0.000 ns;
13927 
                tpw_CLR_negedge         :  VitalDelayType := 0.000 ns;
13928 
                tipd_PRE                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13929 
                tipd_CLR                :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13930 
                tipd_S          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13931 
                tipd_A          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13932 
                tipd_B          :   VitalDelayType01 := (0.000 ns, 0.000 ns);
13933 
                tipd_CLK                :    VitalDelayType01 := (0.000 ns, 0.000 ns));
13934 
 
13935 
 
13936 
--pragma translate_on
13937 
    port(
13938 
                CLR             :   in    STD_ULOGIC;
13939 
                PRE             :   in    STD_ULOGIC;
13940 
                CLK             :   in    STD_ULOGIC;
13941 
                S               :  in    STD_ULOGIC;
13942 
                A               :  in    STD_ULOGIC;
13943 
                B               :  in    STD_ULOGIC;
13944 
                Q               :  out    STD_ULOGIC);
13945 
 
13946 
 end component;
13947 
 
13948 
 
13949 
------ Component HCLKMUX ------
13950 
 component HCLKMUX
13951 
--pragma translate_off
13952 
    generic(
13953 
                TimingChecksOn:Boolean := True;
13954 
                Xon: Boolean := False;
13955 
                InstancePath: STRING :="*";
13956 
                MsgOn: Boolean := True;
13957 
 
13958 
                tpw_A_posedge   : VitalDelayType := 0.000 ns;
13959 
                tpw_A_negedge   : VitalDelayType := 0.000 ns;
13960 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
13961 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
13962 
 
13963 
 
13964 
--pragma translate_on
13965 
    port(
13966 
                A               : in    STD_ULOGIC;
13967 
                Y               : out    STD_ULOGIC);
13968 
 end component;
13969 
 
13970 
 
13971 
------ Component IOFIFO_INBUF ------
13972 
 component IOFIFO_INBUF
13973 
--pragma translate_off
13974 
    generic(
13975 
                TimingChecksOn:Boolean := True;
13976 
                Xon: Boolean := False;
13977 
                InstancePath: STRING :="*";
13978 
                MsgOn: Boolean := True;
13979 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
13980 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
13981 
 
13982 
 
13983 
--pragma translate_on
13984 
    port(
13985 
                A               : in    STD_ULOGIC;
13986 
                Y               : out    STD_ULOGIC);
13987 
 end component;
13988 
 
13989 
 
13990 
------ Component IOFIFO_OUTBUF ------
13991 
 component IOFIFO_OUTBUF
13992 
--pragma translate_off
13993 
    generic(
13994 
                TimingChecksOn:Boolean := True;
13995 
                Xon: Boolean := False;
13996 
                InstancePath: STRING :="*";
13997 
                MsgOn: Boolean := True;
13998 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
13999 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
14000 
 
14001 
 
14002 
--pragma translate_on
14003 
    port(
14004 
                A               : in    STD_ULOGIC;
14005 
                Y               : out    STD_ULOGIC);
14006 
 end component;
14007 
 
14008 
 
14009 
------ Component IOOE_FCLK_BUFF ------
14010 
 component IOOE_FCLK_BUFF
14011 
--pragma translate_off
14012 
    generic(
14013 
                TimingChecksOn:Boolean := True;
14014 
                Xon: Boolean := False;
14015 
                InstancePath: STRING :="*";
14016 
                MsgOn: Boolean := True;
14017 
                tpd_A_YOUT              : VitalDelayType01 := (0.100 ns, 0.100 ns);
14018 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
14019 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14020 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
14021 
 
14022 
 
14023 
--pragma translate_on
14024 
    port(
14025 
                A               : in    STD_ULOGIC;
14026 
                CLK             : in    STD_ULOGIC;
14027 
                YOUT            : out    STD_ULOGIC;
14028 
                CLKOUT          : out    STD_ULOGIC);
14029 
 end component;
14030 
 
14031 
 
14032 
------ Component IOOE_OUT_FCLK ------
14033 
 component IOOE_OUT_FCLK
14034 
--pragma translate_off
14035 
    generic(
14036 
                TimingChecksOn:Boolean := True;
14037 
                Xon: Boolean := False;
14038 
                InstancePath: STRING :="*";
14039 
                MsgOn: Boolean := True;
14040 
                tpd_A_YOUT              : VitalDelayType01 := (0.100 ns, 0.100 ns);
14041 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
14042 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14043 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
14044 
 
14045 
 
14046 
--pragma translate_on
14047 
    port(
14048 
                A               : in    STD_ULOGIC;
14049 
                CLK             : in    STD_ULOGIC;
14050 
                YOUT            : out    STD_ULOGIC;
14051 
                CLKOUT          : out    STD_ULOGIC);
14052 
 end component;
14053 
 
14054 
 
14055 
------ Component IOOE_OUT_FCLK_CLR_EN ------
14056 
 component IOOE_OUT_FCLK_CLR_EN
14057 
--pragma translate_off
14058 
    generic(
14059 
                TimingChecksOn:Boolean := True;
14060 
                Xon: Boolean := False;
14061 
                InstancePath: STRING :="*";
14062 
                MsgOn: Boolean := True;
14063 
                tpd_A_YOUT              : VitalDelayType01 := (0.100 ns, 0.100 ns);
14064 
                tpd_EN_ENOUT            : VitalDelayType01 := (0.100 ns, 0.100 ns);
14065 
                tpd_CLR_CLROUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
14066 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
14067 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14068 
                tipd_EN         : VitalDelayType01 := (0.000 ns, 0.000 ns);
14069 
                tipd_CLR                : VitalDelayType01 := (0.000 ns, 0.000 ns);
14070 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
14071 
 
14072 
 
14073 
--pragma translate_on
14074 
    port(
14075 
                A               : in    STD_ULOGIC;
14076 
                EN              : in    STD_ULOGIC;
14077 
                CLR             : in    STD_ULOGIC;
14078 
                CLK             : in    STD_ULOGIC;
14079 
                YOUT            : out    STD_ULOGIC;
14080 
                ENOUT           : out    STD_ULOGIC;
14081 
                CLROUT          : out    STD_ULOGIC;
14082 
                CLKOUT          : out    STD_ULOGIC);
14083 
 end component;
14084 
 
14085 
 
14086 
------ Component IOOE_OUT_RCLK ------
14087 
 component IOOE_OUT_RCLK
14088 
--pragma translate_off
14089 
    generic(
14090 
                TimingChecksOn:Boolean := True;
14091 
                Xon: Boolean := False;
14092 
                InstancePath: STRING :="*";
14093 
                MsgOn: Boolean := True;
14094 
                tpd_A_YOUT              : VitalDelayType01 := (0.100 ns, 0.100 ns);
14095 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
14096 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14097 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
14098 
 
14099 
 
14100 
--pragma translate_on
14101 
    port(
14102 
                A               : in    STD_ULOGIC;
14103 
                CLK             : in    STD_ULOGIC;
14104 
                YOUT            : out    STD_ULOGIC;
14105 
                CLKOUT          : out    STD_ULOGIC);
14106 
 end component;
14107 
 
14108 
 
14109 
------ Component IOOE_OUT_RCLK_CLR_EN ------
14110 
 component IOOE_OUT_RCLK_CLR_EN
14111 
--pragma translate_off
14112 
    generic(
14113 
                TimingChecksOn:Boolean := True;
14114 
                Xon: Boolean := False;
14115 
                InstancePath: STRING :="*";
14116 
                MsgOn: Boolean := True;
14117 
                tpd_A_YOUT              : VitalDelayType01 := (0.100 ns, 0.100 ns);
14118 
                tpd_EN_ENOUT            : VitalDelayType01 := (0.100 ns, 0.100 ns);
14119 
                tpd_CLR_CLROUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
14120 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
14121 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14122 
                tipd_EN         : VitalDelayType01 := (0.000 ns, 0.000 ns);
14123 
                tipd_CLR                : VitalDelayType01 := (0.000 ns, 0.000 ns);
14124 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
14125 
 
14126 
 
14127 
--pragma translate_on
14128 
    port(
14129 
                A               : in    STD_ULOGIC;
14130 
                EN              : in    STD_ULOGIC;
14131 
                CLR             : in    STD_ULOGIC;
14132 
                CLK             : in    STD_ULOGIC;
14133 
                YOUT            : out    STD_ULOGIC;
14134 
                ENOUT           : out    STD_ULOGIC;
14135 
                CLROUT          : out    STD_ULOGIC;
14136 
                CLKOUT          : out    STD_ULOGIC);
14137 
 end component;
14138 
 
14139 
 
14140 
------ Component IOOE_FCLK_CLR_EN ------
14141 
 component IOOE_FCLK_CLR_EN
14142 
--pragma translate_off
14143 
    generic(
14144 
                TimingChecksOn:Boolean := True;
14145 
                Xon: Boolean := False;
14146 
                InstancePath: STRING :="*";
14147 
                MsgOn: Boolean := True;
14148 
                tpd_EN_ENOUT            : VitalDelayType01 := (0.100 ns, 0.100 ns);
14149 
                tpd_CLR_CLROUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
14150 
                tpd_CLK_CLKOUT          : VitalDelayType01 := (0.100 ns, 0.100 ns);
14151 
                tipd_EN         : VitalDelayType01 := (0.000 ns, 0.000 ns);
14152 
                tipd_CLR                : VitalDelayType01 := (0.000 ns, 0.000 ns);
14153 
                tipd_CLK                : VitalDelayType01 := (0.000 ns, 0.000 ns));
14154 
 
14155 
 
14156 
--pragma translate_on
14157 
    port(
14158 
                EN              : in    STD_ULOGIC;
14159 
                CLR             : in    STD_ULOGIC;
14160 
                CLK             : in    STD_ULOGIC;
14161 
                ENOUT           : out    STD_ULOGIC;
14162 
                CLROUT          : out    STD_ULOGIC;
14163 
                CLKOUT          : out    STD_ULOGIC);
14164 
 end component;
14165 
 
14166 
 
14167 
------ Component IOPAD_IN_U ------
14168 
 component IOPAD_IN_U
14169 
--pragma translate_off
14170 
    generic(
14171 
                TimingChecksOn:Boolean := True;
14172 
                Xon: Boolean := False;
14173 
                InstancePath: STRING :="*";
14174 
                MsgOn: Boolean := True;
14175 
                tpw_PAD_posedge         : VitalDelayType := 0.000 ns;
14176 
                tpw_PAD_negedge         : VitalDelayType := 0.000 ns;
14177 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14178 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
14179 
 
14180 
 
14181 
--pragma translate_on
14182 
    port(
14183 
                PAD             : in    STD_ULOGIC;
14184 
                Y               : out    STD_ULOGIC);
14185 
 end component;
14186 
 
14187 
 
14188 
------ Component IOPAD_IN_D ------
14189 
 component IOPAD_IN_D
14190 
--pragma translate_off
14191 
    generic(
14192 
                TimingChecksOn:Boolean := True;
14193 
                Xon: Boolean := False;
14194 
                InstancePath: STRING :="*";
14195 
                MsgOn: Boolean := True;
14196 
                tpw_PAD_posedge         : VitalDelayType := 0.000 ns;
14197 
                tpw_PAD_negedge         : VitalDelayType := 0.000 ns;
14198 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14199 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
14200 
 
14201 
 
14202 
--pragma translate_on
14203 
    port(
14204 
                PAD             : in    STD_ULOGIC;
14205 
                Y               : out    STD_ULOGIC);
14206 
 end component;
14207 
 
14208 
 
14209 
------ Component IOPAD_TRI_U ------
14210 
 component IOPAD_TRI_U
14211 
--pragma translate_off
14212 
    generic(
14213 
                TimingChecksOn:Boolean := True;
14214 
                Xon: Boolean := False;
14215 
                InstancePath: STRING :="*";
14216 
                MsgOn: Boolean := True;
14217 
                tpw_D_posedge   : VitalDelayType := 0.000 ns;
14218 
                tpw_D_negedge   : VitalDelayType := 0.000 ns;
14219 
                tpw_E_posedge   : VitalDelayType := 0.000 ns;
14220 
                tpw_E_negedge       : VitalDelayType := 0.000 ns;
14221 
 
14222 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14223 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
14224 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14225 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
14226 
 
14227 
 
14228 
--pragma translate_on
14229 
    port(
14230 
                D               : in    STD_ULOGIC;
14231 
                E               : in    STD_ULOGIC;
14232 
                PAD             : out    STD_ULOGIC);
14233 
 end component;
14234 
 
14235 
 
14236 
------ Component IOPAD_TRI_D ------
14237 
 component IOPAD_TRI_D
14238 
--pragma translate_off
14239 
    generic(
14240 
                TimingChecksOn:Boolean := True;
14241 
                Xon: Boolean := False;
14242 
                InstancePath: STRING :="*";
14243 
                MsgOn: Boolean := True;
14244 
                tpw_D_posedge   : VitalDelayType := 0.000 ns;
14245 
                tpw_D_negedge   : VitalDelayType := 0.000 ns;
14246 
                tpw_E_posedge   : VitalDelayType := 0.000 ns;
14247 
                tpw_E_negedge   : VitalDelayType := 0.000 ns;
14248 
 
14249 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14250 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
14251 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14252 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
14253 
 
14254 
 
14255 
--pragma translate_on
14256 
    port(
14257 
                D               : in    STD_ULOGIC;
14258 
                E               : in    STD_ULOGIC;
14259 
                PAD             : out    STD_ULOGIC);
14260 
 end component;
14261 
 
14262 
 
14263 
------ Component IOPAD_BI_U ------
14264 
 component IOPAD_BI_U
14265 
--pragma translate_off
14266 
    generic(
14267 
                TimingChecksOn:Boolean := True;
14268 
                Xon: Boolean := False;
14269 
                InstancePath: STRING :="*";
14270 
                MsgOn: Boolean := True;
14271 
 
14272 
                tpw_D_posedge       : VitalDelayType := 0.000 ns;
14273 
                tpw_D_negedge       : VitalDelayType := 0.000 ns;
14274 
                tpw_E_posedge       : VitalDelayType := 0.000 ns;
14275 
                tpw_E_negedge       : VitalDelayType := 0.000 ns;
14276 
                tpw_PAD_posedge     : VitalDelayType := 0.000 ns;
14277 
                tpw_PAD_negedge     : VitalDelayType := 0.000 ns;
14278 
 
14279 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14280 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
14281 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14282 
                tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
14283 
                tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
14284 
 
14285 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14286 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14287 
                tipd_PAD        : VitalDelayType01 := (0.000 ns, 0.000 ns));
14288 
 
14289 
 
14290 
--pragma translate_on
14291 
    port(
14292 
                D               : in    STD_ULOGIC;
14293 
                E               : in    STD_ULOGIC;
14294 
                PAD             : inout STD_ULOGIC;
14295 
                Y               : out    STD_ULOGIC);
14296 
 end component;
14297 
 
14298 
 
14299 
------ Component IOPAD_BI_D ------
14300 
 component IOPAD_BI_D
14301 
--pragma translate_off
14302 
    generic(
14303 
                TimingChecksOn:Boolean := True;
14304 
                Xon: Boolean := False;
14305 
                InstancePath: STRING :="*";
14306 
                MsgOn: Boolean := True;
14307 
 
14308 
                tpw_E_posedge       : VitalDelayType := 0.000 ns;
14309 
                tpw_E_negedge       : VitalDelayType := 0.000 ns;
14310 
                tpw_D_posedge       : VitalDelayType := 0.000 ns;
14311 
                tpw_D_negedge       : VitalDelayType := 0.000 ns;
14312 
                tpw_PAD_posedge     : VitalDelayType := 0.000 ns;
14313 
                tpw_PAD_negedge     : VitalDelayType := 0.000 ns;
14314 
 
14315 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14316 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
14317 
                tpd_PAD_Y               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14318 
                tpd_D_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
14319 
                tpd_E_Y                 : VitalDelayType01 := (0.100 ns, 0.100 ns);
14320 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14321 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14322 
                tipd_PAD                : VitalDelayType01 := (0.000 ns, 0.000 ns));
14323 
 
14324 
 
14325 
--pragma translate_on
14326 
    port(
14327 
                D               : in    STD_ULOGIC;
14328 
                E               : in    STD_ULOGIC;
14329 
                PAD             : inout STD_ULOGIC;
14330 
                Y               : out    STD_ULOGIC);
14331 
 end component;
14332 
 
14333 
 
14334 
------ Component RCLKMUX ------
14335 
 component RCLKMUX
14336 
--pragma translate_off
14337 
    generic(
14338 
                TimingChecksOn:Boolean := True;
14339 
                Xon: Boolean := False;
14340 
                InstancePath: STRING :="*";
14341 
                MsgOn: Boolean := True;
14342 
 
14343 
                tpw_A_posedge   : VitalDelayType := 0.000 ns;
14344 
                tpw_A_negedge   : VitalDelayType := 0.000 ns;
14345 
                tpd_A_Y         : VitalDelayType01 := (0.100 ns, 0.100 ns);
14346 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
14347 
 
14348 
 
14349 
--pragma translate_on
14350 
    port(
14351 
                A               : in    STD_ULOGIC;
14352 
                Y               : out    STD_ULOGIC);
14353 
 end component;
14354 
 
14355 
 
14356 
------ Component TRIBUFF_HSTL_I ------
14357 
 component TRIBUFF_HSTL_I
14358 
--pragma translate_off
14359 
    generic(
14360 
                TimingChecksOn:Boolean := True;
14361 
                Xon: Boolean := False;
14362 
                InstancePath: STRING :="*";
14363 
                MsgOn: Boolean := True;
14364 
 
14365 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14366 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
14367 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14368 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
14369 
 
14370 
 
14371 
--pragma translate_on
14372 
    port(
14373 
                D               : in    STD_ULOGIC;
14374 
                E               : in    STD_ULOGIC;
14375 
                PAD             : out    STD_ULOGIC);
14376 
 end component;
14377 
 
14378 
 
14379 
------ Component TRIBUFF_SSTL3_I ------
14380 
 component TRIBUFF_SSTL3_I
14381 
--pragma translate_off
14382 
    generic(
14383 
                TimingChecksOn:Boolean := True;
14384 
                Xon: Boolean := False;
14385 
                InstancePath: STRING :="*";
14386 
                MsgOn: Boolean := True;
14387 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14388 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
14389 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14390 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
14391 
 
14392 
 
14393 
--pragma translate_on
14394 
    port(
14395 
                D               : in    STD_ULOGIC;
14396 
                E               : in    STD_ULOGIC;
14397 
                PAD             : out    STD_ULOGIC);
14398 
 end component;
14399 
 
14400 
 
14401 
------ Component TRIBUFF_SSTL3_II ------
14402 
 component TRIBUFF_SSTL3_II
14403 
--pragma translate_off
14404 
    generic(
14405 
                TimingChecksOn:Boolean := True;
14406 
                Xon: Boolean := False;
14407 
                InstancePath: STRING :="*";
14408 
                MsgOn: Boolean := True;
14409 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14410 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
14411 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14412 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
14413 
 
14414 
 
14415 
--pragma translate_on
14416 
    port(
14417 
                D               : in    STD_ULOGIC;
14418 
                E               : in    STD_ULOGIC;
14419 
                PAD             : out    STD_ULOGIC);
14420 
 end component;
14421 
 
14422 
 
14423 
------ Component TRIBUFF_SSTL2_I ------
14424 
 component TRIBUFF_SSTL2_I
14425 
--pragma translate_off
14426 
    generic(
14427 
                TimingChecksOn:Boolean := True;
14428 
                Xon: Boolean := False;
14429 
                InstancePath: STRING :="*";
14430 
                MsgOn: Boolean := True;
14431 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14432 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
14433 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14434 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
14435 
 
14436 
 
14437 
--pragma translate_on
14438 
    port(
14439 
                D               : in    STD_ULOGIC;
14440 
                E               : in    STD_ULOGIC;
14441 
                PAD             : out    STD_ULOGIC);
14442 
 end component;
14443 
 
14444 
 
14445 
------ Component TRIBUFF_SSTL2_II ------
14446 
 component TRIBUFF_SSTL2_II
14447 
--pragma translate_off
14448 
    generic(
14449 
                TimingChecksOn:Boolean := True;
14450 
                Xon: Boolean := False;
14451 
                InstancePath: STRING :="*";
14452 
                MsgOn: Boolean := True;
14453 
                tpd_D_PAD               : VitalDelayType01 := (0.100 ns, 0.100 ns);
14454 
                tpd_E_PAD               : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
14455 
                tipd_D          : VitalDelayType01 := (0.000 ns, 0.000 ns);
14456 
                tipd_E          : VitalDelayType01 := (0.000 ns, 0.000 ns));
14457 
 
14458 
 
14459 
--pragma translate_on
14460 
    port(
14461 
                D               : in    STD_ULOGIC;
14462 
                E               : in    STD_ULOGIC;
14463 
                PAD             : out    STD_ULOGIC);
14464 
 end component;
14465 
 
14466 
component BIOFIFO_BIDIRINFIFO
14467 
--pragma translate_off
14468 
  GENERIC (
14469 
        tipd_A       : VitalDelayType01 := (0.00 ns, 0.00 ns);
14470 
        tipd_D       : VitalDelayType01 := (0.00 ns, 0.00 ns);
14471 
        tipd_WENB       : VitalDelayType01 := (0.00 ns, 0.00 ns);
14472 
        tipd_WCLK     : VitalDelayType01 := (0.00 ns, 0.00 ns);
14473 
        tipd_RENB       : VitalDelayType01 := (0.00 ns, 0.00 ns);
14474 
        tipd_RCLK     : VitalDelayType01 := (0.00 ns, 0.00 ns);
14475 
        tipd_CLRB      : VitalDelayType01 := (0.00 ns, 0.00 ns);
14476 
        tpd_A_Y   : VitalDelayType01 := (0.1000 ns, 0.1000 ns);
14477 
        tpd_RCLK_Q   : VitalDelayType01 := (0.1000 ns, 0.1000 ns);
14478 
        tpd_CLRB_Q    : VitalDelayType01 := (0.1000 ns, 0.1000 ns);
14479 
        tsetup_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14480 
        tsetup_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14481 
        thold_D_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14482 
        thold_D_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14483 
        tsetup_RENB_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14484 
        tsetup_RENB_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14485 
        tsetup_WENB_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14486 
        tsetup_WENB_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14487 
        thold_RENB_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14488 
        thold_RENB_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14489 
        thold_WENB_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14490 
        thold_WENB_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14491 
        thold_CLRB_RCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14492 
        thold_CLRB_RCLK_negedge_posedge     :   VitalDelayType := 0.000 ns;
14493 
        trecovery_CLRB_RCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14494 
        thold_CLRB_WCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14495 
        trecovery_CLRB_WCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14496 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
14497 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
14498 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
14499 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns;
14500 
        tpw_CLRB_negedge     : VitalDelayType := 0.000 ns;
14501 
        TimingCheckOn : BOOLEAN := TRUE;
14502 
        InstancePath  : STRING := "*";
14503 
        Xon: Boolean := False;
14504 
        MsgOn: Boolean := True
14505 
        );
14506 
--pragma translate_on
14507 
  PORT (
14508 
        A     : IN STD_ULOGIC ;
14509 
        D     : IN STD_ULOGIC ;
14510 
        WENB     : IN STD_ULOGIC ;
14511 
        WCLK   : IN STD_ULOGIC ;
14512 
        RENB     : IN STD_ULOGIC ;
14513 
        RCLK   : IN STD_ULOGIC ;
14514 
        CLRB    : IN STD_ULOGIC ;
14515 
        Q     : OUT STD_ULOGIC ;
14516 
        Y     : OUT STD_ULOGIC
14517 
        );
14518 
 
14519 
 
14520 
end component;
14521 
 
14522 
 
14523 
component BIOFIFO_BIDIROUTFIFO
14524 
--pragma translate_off
14525 
  GENERIC (
14526 
        tipd_A       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14527 
        tipd_D       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14528 
        tipd_WENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14529 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14530 
        tipd_RENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14531 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14532 
        tipd_CLRB      : VitalDelayType01 := (0.000 ns, 0.000 ns);
14533 
        tpd_A_Y   : VitalDelayType01 := (0.100 ns, 0.100 ns);
14534 
        tpd_RCLK_Q   : VitalDelayType01 := (0.100 ns, 0.100 ns);
14535 
        tpd_CLRB_Q    : VitalDelayType01 := (0.100 ns, 0.100 ns);
14536 
        tsetup_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14537 
        tsetup_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14538 
        thold_D_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14539 
        thold_D_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14540 
        tsetup_RENB_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14541 
        tsetup_RENB_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14542 
        tsetup_WENB_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14543 
        tsetup_WENB_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14544 
        thold_RENB_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14545 
        thold_RENB_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14546 
        thold_WENB_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14547 
        thold_WENB_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14548 
        thold_CLRB_RCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14549 
        thold_CLRB_RCLK_negedge_posedge     :   VitalDelayType := 0.000 ns;
14550 
        trecovery_CLRB_RCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14551 
        thold_CLRB_WCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14552 
        trecovery_CLRB_WCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14553 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
14554 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
14555 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
14556 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns;
14557 
        tpw_CLRB_negedge     : VitalDelayType := 0.000 ns;
14558 
        TimingCheckOn : BOOLEAN := TRUE;
14559 
        InstancePath  : STRING := "*";
14560 
        Xon: Boolean := False;
14561 
        MsgOn: Boolean := True
14562 
        );
14563 
--pragma translate_on
14564 
  PORT (
14565 
        A     : IN STD_ULOGIC ;
14566 
        D     : IN STD_ULOGIC ;
14567 
        WENB     : IN STD_ULOGIC ;
14568 
        WCLK   : IN STD_ULOGIC ;
14569 
        RENB     : IN STD_ULOGIC ;
14570 
        RCLK   : IN STD_ULOGIC ;
14571 
        CLRB    : IN STD_ULOGIC ;
14572 
        Q     : OUT STD_ULOGIC ;
14573 
        Y     : OUT STD_ULOGIC
14574 
        );
14575 
 
14576 
 
14577 
end component;
14578 
 
14579 
 
14580 
component BIOFIFO_INFIFO
14581 
--pragma translate_off
14582 
  GENERIC (
14583 
        tipd_D       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14584 
        tipd_WENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14585 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14586 
        tipd_RENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14587 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14588 
        tipd_CLRB      : VitalDelayType01 := (0.000 ns, 0.000 ns);
14589 
        tpd_RCLK_Q   : VitalDelayType01 := (0.100 ns, 0.100 ns);
14590 
        tpd_CLRB_Q    : VitalDelayType01 := (0.100 ns, 0.100 ns);
14591 
        tsetup_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14592 
        tsetup_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14593 
        thold_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14594 
        thold_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14595 
        tsetup_RENB_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14596 
        tsetup_RENB_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14597 
        tsetup_WENB_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14598 
        tsetup_WENB_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14599 
        thold_RENB_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14600 
        thold_RENB_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14601 
        thold_WENB_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14602 
        thold_WENB_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14603 
        thold_CLRB_RCLK_negedge_posedge     :   VitalDelayType := 0.000 ns;
14604 
        thold_CLRB_RCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14605 
        trecovery_CLRB_RCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14606 
        thold_CLRB_WCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14607 
        trecovery_CLRB_WCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14608 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
14609 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
14610 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
14611 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns;
14612 
        tpw_CLRB_negedge     : VitalDelayType := 0.000 ns;
14613 
        TimingCheckOn : BOOLEAN := TRUE;
14614 
        InstancePath  : STRING := "*";
14615 
        Xon: Boolean := False;
14616 
        MsgOn: Boolean := True
14617 
        );
14618 
--pragma translate_on
14619 
  PORT (
14620 
        D     : IN STD_ULOGIC ;
14621 
        WENB     : IN STD_ULOGIC ;
14622 
        WCLK   : IN STD_ULOGIC ;
14623 
        RENB     : IN STD_ULOGIC ;
14624 
        RCLK   : IN STD_ULOGIC ;
14625 
        CLRB    : IN STD_ULOGIC ;
14626 
        Q     : OUT STD_ULOGIC
14627 
        );
14628 
 
14629 
 
14630 
end component;
14631 
 
14632 
component BIOFIFO_OUTFIFO
14633 
--pragma translate_off
14634 
  GENERIC (
14635 
        tipd_D       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14636 
        tipd_WENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14637 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14638 
        tipd_RENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14639 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14640 
        tipd_CLRB      : VitalDelayType01 := (0.000 ns, 0.000 ns);
14641 
        tpd_RCLK_Q   : VitalDelayType01 := (0.100 ns, 0.100 ns);
14642 
        tpd_CLRB_Q    : VitalDelayType01 := (0.100 ns, 0.100 ns);
14643 
        tsetup_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14644 
        tsetup_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14645 
        thold_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14646 
        thold_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14647 
        tsetup_RENB_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14648 
        tsetup_RENB_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14649 
        tsetup_WENB_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14650 
        tsetup_WENB_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14651 
        thold_RENB_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14652 
        thold_RENB_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14653 
        thold_WENB_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14654 
        thold_WENB_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14655 
        thold_CLRB_RCLK_negedge_posedge     :   VitalDelayType := 0.000 ns;
14656 
        thold_CLRB_RCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14657 
        trecovery_CLRB_RCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14658 
        thold_CLRB_WCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14659 
        trecovery_CLRB_WCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14660 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
14661 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
14662 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
14663 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns;
14664 
        tpw_CLRB_negedge     : VitalDelayType := 0.000 ns;
14665 
        TimingCheckOn : BOOLEAN := TRUE;
14666 
        InstancePath  : STRING := "*";
14667 
        Xon: Boolean := False;
14668 
        MsgOn: Boolean := True
14669 
        );
14670 
--pragma translate_on
14671 
  PORT (
14672 
        D     : IN STD_ULOGIC ;
14673 
        WENB     : IN STD_ULOGIC ;
14674 
        WCLK   : IN STD_ULOGIC ;
14675 
        RENB     : IN STD_ULOGIC ;
14676 
        RCLK   : IN STD_ULOGIC ;
14677 
        CLRB    : IN STD_ULOGIC ;
14678 
        Q     : OUT STD_ULOGIC
14679 
        );
14680 
 
14681 
 
14682 
end component;
14683 
 
14684 
 
14685 
component IOFIFO_BIDIRINFIFO
14686 
--pragma translate_off
14687 
  GENERIC (
14688 
        tipd_A       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14689 
        tipd_D       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14690 
        tipd_WENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14691 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14692 
        tipd_RENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14693 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14694 
        tipd_CLRB      : VitalDelayType01 := (0.000 ns, 0.000 ns);
14695 
        tpd_A_Y   : VitalDelayType01 := (0.100 ns, 0.100 ns);
14696 
        tpd_RCLK_Q   : VitalDelayType01 := (0.100 ns, 0.100 ns);
14697 
        tpd_CLRB_Q    : VitalDelayType01 := (0.100 ns, 0.100 ns);
14698 
        tsetup_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14699 
        tsetup_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14700 
        thold_D_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14701 
        thold_D_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14702 
        tsetup_RENB_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14703 
        tsetup_RENB_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14704 
        tsetup_WENB_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14705 
        tsetup_WENB_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14706 
        thold_RENB_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14707 
        thold_RENB_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14708 
        thold_WENB_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14709 
        thold_WENB_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14710 
        thold_CLRB_RCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14711 
        thold_CLRB_RCLK_negedge_posedge     :   VitalDelayType := 0.000 ns;
14712 
        trecovery_CLRB_RCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14713 
        thold_CLRB_WCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14714 
        trecovery_CLRB_WCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14715 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
14716 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
14717 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
14718 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns;
14719 
        tpw_CLRB_negedge     : VitalDelayType := 0.000 ns;
14720 
        TimingCheckOn : BOOLEAN := TRUE;
14721 
        InstancePath  : STRING := "*";
14722 
        Xon: Boolean := False;
14723 
        MsgOn: Boolean := True
14724 
        );
14725 
--pragma translate_on
14726 
  PORT (
14727 
        A     : IN STD_ULOGIC ;
14728 
        D     : IN STD_ULOGIC ;
14729 
        WENB     : IN STD_ULOGIC ;
14730 
        WCLK   : IN STD_ULOGIC ;
14731 
        RENB     : IN STD_ULOGIC ;
14732 
        RCLK   : IN STD_ULOGIC ;
14733 
        CLRB    : IN STD_ULOGIC ;
14734 
        Q     : OUT STD_ULOGIC ;
14735 
        Y     : OUT STD_ULOGIC
14736 
        );
14737 
 
14738 
 
14739 
 
14740 
end component;
14741 
 
14742 
 
14743 
component IOFIFO_BIDIROUTFIFO
14744 
--pragma translate_off
14745 
  GENERIC (
14746 
        tipd_A       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14747 
        tipd_D       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14748 
        tipd_WENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14749 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14750 
        tipd_RENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14751 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14752 
        tipd_CLRB      : VitalDelayType01 := (0.000 ns, 0.000 ns);
14753 
        tpd_A_Y   : VitalDelayType01 := (0.100 ns, 0.100 ns);
14754 
        tpd_RCLK_Q   : VitalDelayType01 := (0.100 ns, 0.100 ns);
14755 
        tpd_CLRB_Q    : VitalDelayType01 := (0.100 ns, 0.100 ns);
14756 
        tsetup_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14757 
        tsetup_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14758 
        thold_D_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14759 
        thold_D_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14760 
        tsetup_RENB_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14761 
        tsetup_RENB_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14762 
        tsetup_WENB_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14763 
        tsetup_WENB_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14764 
        thold_RENB_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14765 
        thold_RENB_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14766 
        thold_WENB_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14767 
        thold_WENB_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14768 
        thold_CLRB_RCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14769 
        thold_CLRB_RCLK_negedge_posedge     :   VitalDelayType := 0.000 ns;
14770 
        trecovery_CLRB_RCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14771 
        thold_CLRB_WCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14772 
        trecovery_CLRB_WCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14773 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
14774 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
14775 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
14776 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns;
14777 
        tpw_CLRB_negedge     : VitalDelayType := 0.000 ns;
14778 
        TimingCheckOn : BOOLEAN := TRUE;
14779 
        InstancePath  : STRING := "*";
14780 
        Xon: Boolean := False;
14781 
        MsgOn: Boolean := True
14782 
        );
14783 
--pragma translate_on
14784 
  PORT (
14785 
        A     : IN STD_ULOGIC ;
14786 
        D     : IN STD_ULOGIC ;
14787 
        WENB     : IN STD_ULOGIC ;
14788 
        WCLK   : IN STD_ULOGIC ;
14789 
        RENB     : IN STD_ULOGIC ;
14790 
        RCLK   : IN STD_ULOGIC ;
14791 
        CLRB    : IN STD_ULOGIC ;
14792 
        Q     : OUT STD_ULOGIC ;
14793 
        Y     : OUT STD_ULOGIC
14794 
        );
14795 
 
14796 
 
14797 
end component;
14798 
 
14799 
 
14800 
component IOFIFO_INFIFO
14801 
--pragma translate_off
14802 
  GENERIC (
14803 
        tipd_D       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14804 
        tipd_WENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14805 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14806 
        tipd_RENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14807 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14808 
        tipd_CLRB      : VitalDelayType01 := (0.000 ns, 0.000 ns);
14809 
        tpd_RCLK_Q   : VitalDelayType01 := (0.100 ns, 0.100 ns);
14810 
        tpd_CLRB_Q    : VitalDelayType01 := (0.100 ns, 0.100 ns);
14811 
        tsetup_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14812 
        tsetup_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14813 
        thold_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14814 
        thold_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14815 
        tsetup_RENB_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14816 
        tsetup_RENB_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14817 
        tsetup_WENB_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14818 
        tsetup_WENB_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14819 
        thold_RENB_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14820 
        thold_RENB_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14821 
        thold_WENB_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14822 
        thold_WENB_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14823 
        thold_CLRB_RCLK_negedge_posedge     :   VitalDelayType := 0.000 ns;
14824 
        thold_CLRB_RCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14825 
        trecovery_CLRB_RCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14826 
        thold_CLRB_WCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14827 
        trecovery_CLRB_WCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14828 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
14829 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
14830 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
14831 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns;
14832 
        tpw_CLRB_negedge     : VitalDelayType := 0.000 ns;
14833 
        TimingCheckOn : BOOLEAN := TRUE;
14834 
        InstancePath  : STRING := "*";
14835 
        Xon: Boolean := False;
14836 
        MsgOn: Boolean := True
14837 
        );
14838 
--pragma translate_on
14839 
  PORT (
14840 
        D     : IN STD_ULOGIC ;
14841 
        WENB     : IN STD_ULOGIC ;
14842 
        WCLK   : IN STD_ULOGIC ;
14843 
        RENB     : IN STD_ULOGIC ;
14844 
        RCLK   : IN STD_ULOGIC ;
14845 
        CLRB    : IN STD_ULOGIC ;
14846 
        Q     : OUT STD_ULOGIC
14847 
        );
14848 
 
14849 
 
14850 
end component;
14851 
 
14852 
component IOFIFO_OUTFIFO
14853 
--pragma translate_off
14854 
  GENERIC (
14855 
        tipd_D       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14856 
        tipd_WENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14857 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14858 
        tipd_RENB       : VitalDelayType01 := (0.000 ns, 0.000 ns);
14859 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
14860 
        tipd_CLRB      : VitalDelayType01 := (0.000 ns, 0.000 ns);
14861 
        tpd_RCLK_Q   : VitalDelayType01 := (0.1000 ns, 0.100 ns);
14862 
        tpd_CLRB_Q    : VitalDelayType01 := (0.1000 ns, 0.1000 ns);
14863 
        tsetup_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14864 
        tsetup_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14865 
        thold_D_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14866 
        thold_D_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14867 
        tsetup_RENB_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14868 
        tsetup_RENB_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14869 
        tsetup_WENB_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
14870 
        tsetup_WENB_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
14871 
        thold_RENB_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14872 
        thold_RENB_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14873 
        thold_WENB_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
14874 
        thold_WENB_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
14875 
        thold_CLRB_RCLK_negedge_posedge     :   VitalDelayType := 0.000 ns;
14876 
        thold_CLRB_RCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14877 
        trecovery_CLRB_RCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14878 
        thold_CLRB_WCLK_posedge_posedge     :   VitalDelayType := 0.000 ns;
14879 
        trecovery_CLRB_WCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
14880 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
14881 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
14882 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
14883 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns;
14884 
        tpw_CLRB_negedge     : VitalDelayType := 0.000 ns;
14885 
        TimingCheckOn : BOOLEAN := TRUE;
14886 
        InstancePath  : STRING := "*";
14887 
        Xon: Boolean := False;
14888 
        MsgOn: Boolean := True
14889 
        );
14890 
--pragma translate_on
14891 
  PORT (
14892 
        D     : IN STD_ULOGIC ;
14893 
        WENB     : IN STD_ULOGIC ;
14894 
        WCLK   : IN STD_ULOGIC ;
14895 
        RENB     : IN STD_ULOGIC ;
14896 
        RCLK   : IN STD_ULOGIC ;
14897 
        CLRB    : IN STD_ULOGIC ;
14898 
        Q     : OUT STD_ULOGIC
14899 
        );
14900 
 
14901 
 
14902 
end component;
14903 
 
14904 
component IOPADP_IN
14905 
--pragma translate_off
14906 
   generic(
14907 
      TimingChecksOn: Boolean := True;
14908 
      InstancePath: STRING := "*";
14909 
      Xon: Boolean := False;
14910 
      MsgOn: Boolean := True;
14911 
 
14912 
      tpw_PAD_posedge           : VitalDelayType := 0.000 ns;
14913 
      tpw_PAD_negedge           : VitalDelayType := 0.000 ns;
14914 
      tpw_N2PIN_posedge         : VitalDelayType := 0.000 ns;
14915 
      tpw_N2PIN_negedge         : VitalDelayType := 0.000 ns;
14916 
 
14917 
      tpd_PAD_Y                 :        VitalDelayType01 := (0.100 ns, 0.100 ns);
14918 
      tpd_N2PIN_Y               :        VitalDelayType01 := (0.100 ns, 0.100 ns);
14919 
      tipd_PAD               :        VitalDelayType01 := (0.000 ns, 0.000 ns);
14920 
      tipd_N2PIN             :        VitalDelayType01 := (0.000 ns, 0.000 ns));
14921 
 
14922 
--pragma translate_on
14923 
   port(
14924 
      PAD                            :        in    STD_ULOGIC;
14925 
      N2PIN                          :        in    STD_ULOGIC;
14926 
      Y                              :        out   STD_ULOGIC);
14927 
 
14928 
end component;
14929 
 
14930 
 
14931 
component IOPADN_IN
14932 
--pragma translate_off
14933 
   generic(
14934 
      TimingChecksOn: Boolean := True;
14935 
      InstancePath: STRING := "*";
14936 
      Xon: Boolean := False;
14937 
      MsgOn: Boolean := True;
14938 
 
14939 
      tpw_PAD_posedge           : VitalDelayType := 0.000 ns;
14940 
      tpw_PAD_negedge           : VitalDelayType := 0.000 ns;
14941 
 
14942 
      tpd_PAD_N2POUT                 :  VitalDelayType01 := (0.100 ns, 0.100 ns);
14943 
      tipd_PAD                               :  VitalDelayType01 := (0.000 ns, 0.000 ns));
14944 
 
14945 
--pragma translate_on
14946 
   port(
14947 
      PAD                            :  in    STD_ULOGIC;
14948 
      N2POUT                         :  out   STD_ULOGIC);
14949 
 
14950 
end component;
14951 
 
14952 
component IOPADP_TRI
14953 
--pragma translate_off
14954 
   generic(
14955 
      TimingChecksOn: Boolean := True;
14956 
      InstancePath: STRING := "*";
14957 
      Xon: Boolean := False;
14958 
      MsgOn: Boolean := True;
14959 
      tpw_E_posedge           : VitalDelayType := 0.000 ns;
14960 
      tpw_E_negedge           : VitalDelayType := 0.000 ns;
14961 
      tpw_D_posedge           : VitalDelayType := 0.000 ns;
14962 
      tpw_D_negedge           : VitalDelayType := 0.000 ns;
14963 
 
14964 
      tpd_E_PAD                      :  VitalDelayType01Z :=
14965 
               (0.100 ns, 0.100 ns, 0.100 ns, 0.000 ns, 0.100 ns, 0.100 ns);
14966 
      tpd_D_PAD                      :  VitalDelayType01 := (0.100 ns, 0.100 ns);
14967 
      tipd_D                         :  VitalDelayType01 := (0.000 ns, 0.000 ns);
14968 
      tipd_E                         :  VitalDelayType01 := (0.000 ns, 0.000 ns));
14969 
 
14970 
--pragma translate_on
14971 
   port(
14972 
      D                              :  in    STD_ULOGIC;
14973 
      E                              :  in    STD_ULOGIC;
14974 
      PAD                            :  out   STD_ULOGIC);
14975 
 
14976 
end component;
14977 
 
14978 
component IOPADN_TRI
14979 
--pragma translate_off
14980 
   generic(
14981 
      TimingChecksOn: Boolean := True;
14982 
      InstancePath: STRING := "*";
14983 
      Xon: Boolean := False;
14984 
      MsgOn: Boolean := True;
14985 
 
14986 
      tpw_DB_posedge        :   VitalDelayType := 0.000 ns;
14987 
      tpw_DB_negedge            :   VitalDelayType := 0.000 ns;
14988 
      tpw_E_posedge             : VitalDelayType := 0.000 ns;
14989 
      tpw_E_negedge           : VitalDelayType := 0.000 ns;
14990 
 
14991 
      tpd_E_PAD                     :   VitalDelayType01Z :=
14992 
               (0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns);
14993 
      tpd_DB_PAD                      : VitalDelayType01 := (0.100 ns, 0.100 ns);
14994 
      tipd_DB                        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
14995 
      tipd_E                         :  VitalDelayType01 := (0.000 ns, 0.000 ns));
14996 
 
14997 
--pragma translate_on
14998 
   port(
14999 
      DB                             :  in    STD_ULOGIC;
15000 
      E                              :  in    STD_ULOGIC;
15001 
      PAD                            :  out   STD_ULOGIC);
15002 
 
15003 
end component;
15004 
 
15005 
 
15006 
component CLKBUF_LVDS
15007 
--pragma translate_off
15008 
   generic(
15009 
      TimingChecksOn: Boolean := True;
15010 
      InstancePath: STRING := "*";
15011 
      Xon: Boolean := False;
15012 
      MsgOn: Boolean := True;
15013 
      tpd_PADP_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15014 
      tpd_PADN_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15015 
      tipd_PADP                             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15016 
      tipd_PADN                             :  VitalDelayType01 := (0.000 ns, 0.000 ns));
15017 
 
15018 
--pragma translate_on
15019 
   port(
15020 
      PADP                           :  in    STD_ULOGIC;
15021 
      PADN                           :  in    STD_ULOGIC;
15022 
      Y                              :  out   STD_ULOGIC);
15023 
 
15024 
end component;
15025 
 
15026 
component CLKBUF_LVPECL
15027 
--pragma translate_off
15028 
   generic(
15029 
      TimingChecksOn: Boolean := True;
15030 
      InstancePath: STRING := "*";
15031 
      Xon: Boolean := False;
15032 
      MsgOn: Boolean := True;
15033 
      tpd_PADP_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15034 
      tpd_PADN_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15035 
      tipd_PADP                             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15036 
      tipd_PADN                             :  VitalDelayType01 := (0.000 ns, 0.000 ns));
15037 
 
15038 
--pragma translate_on
15039 
   port(
15040 
      PADP                           :  in    STD_ULOGIC;
15041 
      PADN                           :  in    STD_ULOGIC;
15042 
      Y                              :  out   STD_ULOGIC);
15043 
 
15044 
end component;
15045 
 
15046 
component HCLKBUF_LVDS
15047 
--pragma translate_off
15048 
   generic(
15049 
      TimingChecksOn: Boolean := True;
15050 
      InstancePath: STRING := "*";
15051 
      Xon: Boolean := False;
15052 
      MsgOn: Boolean := True;
15053 
      tpd_PADP_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15054 
      tpd_PADN_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15055 
      tipd_PADP                             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15056 
      tipd_PADN                             :  VitalDelayType01 := (0.000 ns, 0.000 ns));
15057 
 
15058 
--pragma translate_on
15059 
   port(
15060 
      PADP                           :  in    STD_ULOGIC;
15061 
      PADN                           :  in    STD_ULOGIC;
15062 
      Y                              :  out   STD_ULOGIC);
15063 
 
15064 
end component;
15065 
 
15066 
component HCLKBUF_LVPECL
15067 
--pragma translate_off
15068 
   generic(
15069 
      TimingChecksOn: Boolean := True;
15070 
      InstancePath: STRING := "*";
15071 
      Xon: Boolean := False;
15072 
      MsgOn: Boolean := True;
15073 
      tpd_PADP_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15074 
      tpd_PADN_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15075 
      tipd_PADP                             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15076 
      tipd_PADN                             :  VitalDelayType01 := (0.000 ns, 0.000 ns));
15077 
 
15078 
--pragma translate_on
15079 
   port(
15080 
      PADP                           :  in    STD_ULOGIC;
15081 
      PADN                           :  in    STD_ULOGIC;
15082 
      Y                              :  out   STD_ULOGIC);
15083 
 
15084 
end component;
15085 
 
15086 
component INBUF_LVDS
15087 
--pragma translate_off
15088 
   generic(
15089 
      TimingChecksOn: Boolean := True;
15090 
      InstancePath: STRING := "*";
15091 
      Xon: Boolean := False;
15092 
      MsgOn: Boolean := True;
15093 
      tpd_PADP_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15094 
      tpd_PADN_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15095 
      tipd_PADP                             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15096 
      tipd_PADN                             :  VitalDelayType01 := (0.000 ns, 0.000 ns));
15097 
 
15098 
--pragma translate_on
15099 
   port(
15100 
      PADP                           :  in    STD_ULOGIC;
15101 
      PADN                           :  in    STD_ULOGIC;
15102 
      Y                              :  out   STD_ULOGIC);
15103 
 
15104 
end component;
15105 
 
15106 
component INBUF_LVPECL
15107 
--pragma translate_off
15108 
   generic(
15109 
      TimingChecksOn: Boolean := True;
15110 
      InstancePath: STRING := "*";
15111 
      Xon: Boolean := False;
15112 
      MsgOn: Boolean := True;
15113 
      tpd_PADP_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15114 
      tpd_PADN_Y                    :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15115 
      tipd_PADP                             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15116 
      tipd_PADN                             :  VitalDelayType01 := (0.000 ns, 0.000 ns));
15117 
 
15118 
--pragma translate_on
15119 
   port(
15120 
      PADP                           :  in    STD_ULOGIC;
15121 
      PADN                           :  in    STD_ULOGIC;
15122 
      Y                              :  out   STD_ULOGIC);
15123 
 
15124 
end component;
15125 
 
15126 
component OUTBUF_LVDS
15127 
--pragma translate_off
15128 
   generic(
15129 
      TimingChecksOn: Boolean := True;
15130 
      InstancePath: STRING := "*";
15131 
      Xon: Boolean := False;
15132 
      MsgOn: Boolean := True;
15133 
      tpd_D_PADP                     :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15134 
      tpd_D_PADN                     :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15135 
      tipd_D                                 :  VitalDelayType01 := (0.000 ns, 0.000 ns));
15136 
 
15137 
--pragma translate_on
15138 
   port(
15139 
      D                              :  in    STD_ULOGIC;
15140 
      PADP                           :  out   STD_ULOGIC;
15141 
      PADN                           :  out   STD_ULOGIC);
15142 
 
15143 
end component;
15144 
 
15145 
component OUTBUF_LVPECL
15146 
--pragma translate_off
15147 
   generic(
15148 
      TimingChecksOn: Boolean := True;
15149 
      InstancePath: STRING := "*";
15150 
      Xon: Boolean := False;
15151 
      MsgOn: Boolean := True;
15152 
      tpd_D_PADP                     :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15153 
      tpd_D_PADN                     :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15154 
      tipd_D                         :  VitalDelayType01 := (0.000 ns, 0.000 ns));
15155 
 
15156 
--pragma translate_on
15157 
   port(
15158 
      D                              :  in    STD_ULOGIC;
15159 
      PADP                           :  out   STD_ULOGIC;
15160 
      PADN                           :  out   STD_ULOGIC);
15161 
 
15162 
end component;
15163 
 
15164 
 
15165 
component CM8F
15166 
--pragma translate_off
15167 
   generic(
15168 
      TimingChecksOn: Boolean := True;
15169 
      InstancePath: STRING := "*";
15170 
      Xon: Boolean := False;
15171 
      MsgOn: Boolean := True;
15172 
      tpd_S11_Y                      :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15173 
      tpd_S10_Y                      :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15174 
      tpd_S01_Y                      :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15175 
      tpd_S00_Y                      :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15176 
      tpd_D3_Y                       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15177 
      tpd_D2_Y                       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15178 
      tpd_D1_Y                       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15179 
      tpd_D0_Y                       :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15180 
      tpd_S11_FY                     :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15181 
      tpd_S10_FY                     :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15182 
      tpd_S01_FY                     :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15183 
      tpd_S00_FY                     :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15184 
      tpd_D3_FY                      :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15185 
      tpd_D2_FY                      :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15186 
      tpd_D1_FY                      :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15187 
      tpd_D0_FY                      :  VitalDelayType01 := (0.100 ns, 0.100 ns);
15188 
      tipd_D0                        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15189 
      tipd_D1                        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15190 
      tipd_D2                        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15191 
      tipd_D3                        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15192 
      tipd_S00                       :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15193 
      tipd_S01                       :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15194 
      tipd_S10                       :  VitalDelayType01 := (0.000 ns, 0.000 ns);
15195 
      tipd_S11                       :  VitalDelayType01 := (0.000 ns, 0.000 ns));
15196 
 
15197 
--pragma translate_on
15198 
   port(
15199 
      D0                             :  in    STD_ULOGIC;
15200 
      D1                             :  in    STD_ULOGIC;
15201 
      D2                             :  in    STD_ULOGIC;
15202 
      D3                             :  in    STD_ULOGIC;
15203 
      S00                            :  in    STD_ULOGIC;
15204 
      S01                            :  in    STD_ULOGIC;
15205 
      S10                            :  in    STD_ULOGIC;
15206 
      S11                            :  in    STD_ULOGIC;
15207 
      FY                             :  out   STD_ULOGIC;
15208 
      Y                              :  out   STD_ULOGIC);
15209 
end component;
15210 
 
15211 
component FIFO64K36
15212 
--pragma translate_off
15213 
  GENERIC (
15214 
        tipd_DEPTH3   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15215 
        tipd_DEPTH2   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15216 
        tipd_DEPTH1   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15217 
        tipd_DEPTH0   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15218 
        tipd_WIDTH2   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15219 
        tipd_WIDTH1   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15220 
        tipd_WIDTH0   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15221 
        tipd_AEVAL7   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15222 
        tipd_AEVAL6   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15223 
        tipd_AEVAL5   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15224 
        tipd_AEVAL4   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15225 
        tipd_AEVAL3   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15226 
        tipd_AEVAL2   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15227 
        tipd_AEVAL1   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15228 
        tipd_AEVAL0   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15229 
        tipd_AFVAL7   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15230 
        tipd_AFVAL6   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15231 
        tipd_AFVAL5   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15232 
        tipd_AFVAL4   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15233 
        tipd_AFVAL3   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15234 
        tipd_AFVAL2   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15235 
        tipd_AFVAL1   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15236 
        tipd_AFVAL0   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15237 
        tipd_REN      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15238 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15239 
        tipd_WD35     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15240 
        tipd_WD34     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15241 
        tipd_WD33     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15242 
        tipd_WD32     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15243 
        tipd_WD31     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15244 
        tipd_WD30     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15245 
        tipd_WD29     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15246 
        tipd_WD28     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15247 
        tipd_WD27     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15248 
        tipd_WD26     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15249 
        tipd_WD25     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15250 
        tipd_WD24     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15251 
        tipd_WD23     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15252 
        tipd_WD22     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15253 
        tipd_WD21     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15254 
        tipd_WD20     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15255 
        tipd_WD19     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15256 
        tipd_WD18     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15257 
        tipd_WD17     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15258 
        tipd_WD16     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15259 
        tipd_WD15     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15260 
        tipd_WD14     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15261 
        tipd_WD13     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15262 
        tipd_WD12     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15263 
        tipd_WD11     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15264 
        tipd_WD10     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15265 
        tipd_WD9      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15266 
        tipd_WD8      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15267 
        tipd_WD7      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15268 
        tipd_WD6      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15269 
        tipd_WD5      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15270 
        tipd_WD4      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15271 
        tipd_WD3      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15272 
        tipd_WD2      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15273 
        tipd_WD1      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15274 
        tipd_WD0      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15275 
        tipd_WEN      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15276 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15277 
        tipd_CLR      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15278 
        tpd_RCLK_RD0  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15279 
        tpd_RCLK_RD1  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15280 
        tpd_RCLK_RD2  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15281 
        tpd_RCLK_RD3  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15282 
        tpd_RCLK_RD4  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15283 
        tpd_RCLK_RD5  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15284 
        tpd_RCLK_RD6  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15285 
        tpd_RCLK_RD7  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15286 
        tpd_RCLK_RD8  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15287 
        tpd_RCLK_RD9  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15288 
        tpd_RCLK_RD10 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15289 
        tpd_RCLK_RD11 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15290 
        tpd_RCLK_RD12 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15291 
        tpd_RCLK_RD13 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15292 
        tpd_RCLK_RD14 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15293 
        tpd_RCLK_RD15 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15294 
        tpd_RCLK_RD16 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15295 
        tpd_RCLK_RD17 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15296 
        tpd_RCLK_RD18 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15297 
        tpd_RCLK_RD19 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15298 
        tpd_RCLK_RD20 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15299 
        tpd_RCLK_RD21 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15300 
        tpd_RCLK_RD22 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15301 
        tpd_RCLK_RD23 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15302 
        tpd_RCLK_RD24 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15303 
        tpd_RCLK_RD25 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15304 
        tpd_RCLK_RD26 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15305 
        tpd_RCLK_RD27 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15306 
        tpd_RCLK_RD28 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15307 
        tpd_RCLK_RD29 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15308 
        tpd_RCLK_RD30 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15309 
        tpd_RCLK_RD31 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15310 
        tpd_RCLK_RD32 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15311 
        tpd_RCLK_RD33 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15312 
        tpd_RCLK_RD34 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15313 
        tpd_RCLK_RD35 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15314 
        tpd_RCLK_FULL   : VitalDelayType01 := (0.100 ns, 0.100 ns);
15315 
        tpd_RCLK_AFULL  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15316 
        tpd_RCLK_EMPTY  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15317 
        tpd_RCLK_AEMPTY : VitalDelayType01 := (0.100 ns, 0.100 ns);
15318 
        tpd_CLR_RD0  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15319 
        tpd_CLR_RD1  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15320 
        tpd_CLR_RD2  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15321 
        tpd_CLR_RD3  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15322 
        tpd_CLR_RD4  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15323 
        tpd_CLR_RD5  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15324 
        tpd_CLR_RD6  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15325 
        tpd_CLR_RD7  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15326 
        tpd_CLR_RD8  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15327 
        tpd_CLR_RD9  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15328 
        tpd_CLR_RD10 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15329 
        tpd_CLR_RD11 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15330 
        tpd_CLR_RD12 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15331 
        tpd_CLR_RD13 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15332 
        tpd_CLR_RD14 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15333 
        tpd_CLR_RD15 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15334 
        tpd_CLR_RD16 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15335 
        tpd_CLR_RD17 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15336 
        tpd_CLR_RD18 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15337 
        tpd_CLR_RD19 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15338 
        tpd_CLR_RD20 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15339 
        tpd_CLR_RD21 : VitalDelayType01 := (0.100 ns, 0.10 ns);
15340 
        tpd_CLR_RD22 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15341 
        tpd_CLR_RD23 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15342 
        tpd_CLR_RD24 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15343 
        tpd_CLR_RD25 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15344 
        tpd_CLR_RD26 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15345 
        tpd_CLR_RD27 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15346 
        tpd_CLR_RD28 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15347 
        tpd_CLR_RD29 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15348 
        tpd_CLR_RD30 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15349 
        tpd_CLR_RD31 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15350 
        tpd_CLR_RD32 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15351 
        tpd_CLR_RD33 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15352 
        tpd_CLR_RD34 : VitalDelayType01 := (0.1000 ns, 0.100 ns);
15353 
        tpd_CLR_RD35 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15354 
        tpd_CLR_FULL   : VitalDelayType01 := (0.100 ns, 0.100 ns);
15355 
        tpd_CLR_AFULL  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15356 
        tpd_CLR_EMPTY  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15357 
        tpd_CLR_AEMPTY : VitalDelayType01 := (0.100 ns, 0.100 ns);
15358 
 
15359 
 
15360 
        tsetup_WD35_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15361 
        tsetup_WD34_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15362 
        tsetup_WD33_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15363 
        tsetup_WD32_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15364 
        tsetup_WD31_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15365 
        tsetup_WD30_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15366 
        tsetup_WD29_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15367 
        tsetup_WD28_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15368 
        tsetup_WD27_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15369 
        tsetup_WD26_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15370 
        tsetup_WD25_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15371 
        tsetup_WD24_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15372 
        tsetup_WD23_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15373 
        tsetup_WD22_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15374 
        tsetup_WD21_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15375 
        tsetup_WD20_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15376 
        tsetup_WD19_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15377 
        tsetup_WD18_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15378 
        tsetup_WD17_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15379 
        tsetup_WD16_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15380 
        tsetup_WD15_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15381 
        tsetup_WD14_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15382 
        tsetup_WD13_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15383 
        tsetup_WD12_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15384 
        tsetup_WD11_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15385 
        tsetup_WD10_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15386 
        tsetup_WD9_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15387 
        tsetup_WD8_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15388 
        tsetup_WD7_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15389 
        tsetup_WD6_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15390 
        tsetup_WD5_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15391 
        tsetup_WD4_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15392 
        tsetup_WD3_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15393 
        tsetup_WD2_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15394 
        tsetup_WD1_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15395 
        tsetup_WD0_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15396 
        tsetup_WD35_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15397 
        tsetup_WD34_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15398 
        tsetup_WD33_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15399 
        tsetup_WD32_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15400 
        tsetup_WD31_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15401 
        tsetup_WD30_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15402 
        tsetup_WD29_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15403 
        tsetup_WD28_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15404 
        tsetup_WD27_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15405 
        tsetup_WD26_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15406 
        tsetup_WD25_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15407 
        tsetup_WD24_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15408 
        tsetup_WD23_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15409 
        tsetup_WD22_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15410 
        tsetup_WD21_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15411 
        tsetup_WD20_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15412 
        tsetup_WD19_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15413 
        tsetup_WD18_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15414 
        tsetup_WD17_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15415 
        tsetup_WD16_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15416 
        tsetup_WD15_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15417 
        tsetup_WD14_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15418 
        tsetup_WD13_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15419 
        tsetup_WD12_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15420 
        tsetup_WD11_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15421 
        tsetup_WD10_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15422 
        tsetup_WD9_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15423 
        tsetup_WD8_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15424 
        tsetup_WD7_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15425 
        tsetup_WD6_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15426 
        tsetup_WD5_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15427 
        tsetup_WD4_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15428 
        tsetup_WD3_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15429 
        tsetup_WD2_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15430 
        tsetup_WD1_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15431 
        tsetup_WD0_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15432 
 
15433 
        tsetup_WEN_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
15434 
        tsetup_WEN_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
15435 
 
15436 
        tsetup_DEPTH3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15437 
        tsetup_DEPTH2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15438 
        tsetup_DEPTH1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15439 
        tsetup_DEPTH0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15440 
        tsetup_DEPTH3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15441 
        tsetup_DEPTH2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15442 
        tsetup_DEPTH1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15443 
        tsetup_DEPTH0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15444 
 
15445 
 
15446 
        tsetup_WIDTH2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15447 
        tsetup_WIDTH1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15448 
        tsetup_WIDTH0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15449 
        tsetup_WIDTH2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15450 
        tsetup_WIDTH1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15451 
        tsetup_WIDTH0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15452 
 
15453 
        tsetup_AEVAL7_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15454 
        tsetup_AEVAL6_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15455 
        tsetup_AEVAL5_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15456 
        tsetup_AEVAL4_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15457 
        tsetup_AEVAL3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15458 
        tsetup_AEVAL2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15459 
        tsetup_AEVAL1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15460 
        tsetup_AEVAL0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15461 
        tsetup_AEVAL7_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15462 
        tsetup_AEVAL6_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15463 
        tsetup_AEVAL5_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15464 
        tsetup_AEVAL4_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15465 
        tsetup_AEVAL3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15466 
        tsetup_AEVAL2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15467 
        tsetup_AEVAL1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15468 
        tsetup_AEVAL0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15469 
 
15470 
        tsetup_AFVAL7_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15471 
        tsetup_AFVAL6_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15472 
        tsetup_AFVAL5_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15473 
        tsetup_AFVAL4_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15474 
        tsetup_AFVAL3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15475 
        tsetup_AFVAL2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15476 
        tsetup_AFVAL1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15477 
        tsetup_AFVAL0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15478 
        tsetup_AFVAL7_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15479 
        tsetup_AFVAL6_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15480 
        tsetup_AFVAL5_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15481 
        tsetup_AFVAL4_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15482 
        tsetup_AFVAL3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15483 
        tsetup_AFVAL2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15484 
        tsetup_AFVAL1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15485 
        tsetup_AFVAL0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15486 
 
15487 
        tsetup_DEPTH3_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15488 
        tsetup_DEPTH2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15489 
        tsetup_DEPTH1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15490 
        tsetup_DEPTH0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15491 
        tsetup_DEPTH3_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15492 
        tsetup_DEPTH2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15493 
        tsetup_DEPTH1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15494 
        tsetup_DEPTH0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15495 
 
15496 
 
15497 
        tsetup_WIDTH2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15498 
        tsetup_WIDTH1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15499 
        tsetup_WIDTH0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15500 
        tsetup_WIDTH2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15501 
        tsetup_WIDTH1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15502 
        tsetup_WIDTH0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15503 
 
15504 
 
15505 
        tsetup_AEVAL7_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15506 
        tsetup_AEVAL6_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15507 
        tsetup_AEVAL5_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15508 
        tsetup_AEVAL4_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15509 
        tsetup_AEVAL3_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15510 
        tsetup_AEVAL2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15511 
        tsetup_AEVAL1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15512 
        tsetup_AEVAL0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15513 
        tsetup_AEVAL7_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15514 
        tsetup_AEVAL6_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15515 
        tsetup_AEVAL5_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15516 
        tsetup_AEVAL4_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15517 
        tsetup_AEVAL3_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15518 
        tsetup_AEVAL2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15519 
        tsetup_AEVAL1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15520 
        tsetup_AEVAL0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15521 
 
15522 
        tsetup_AFVAL7_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15523 
        tsetup_AFVAL6_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15524 
        tsetup_AFVAL5_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15525 
        tsetup_AFVAL4_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15526 
        tsetup_AFVAL3_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15527 
        tsetup_AFVAL2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15528 
        tsetup_AFVAL1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15529 
        tsetup_AFVAL0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15530 
        tsetup_AFVAL7_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15531 
        tsetup_AFVAL6_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15532 
        tsetup_AFVAL5_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15533 
        tsetup_AFVAL4_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15534 
        tsetup_AFVAL3_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15535 
        tsetup_AFVAL2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15536 
        tsetup_AFVAL1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15537 
        tsetup_AFVAL0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15538 
 
15539 
        tsetup_REN_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
15540 
        tsetup_REN_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
15541 
 
15542 
        thold_WD35_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15543 
        thold_WD34_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15544 
        thold_WD33_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15545 
        thold_WD32_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15546 
        thold_WD31_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15547 
        thold_WD30_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15548 
        thold_WD29_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15549 
        thold_WD28_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15550 
        thold_WD27_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15551 
        thold_WD26_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15552 
        thold_WD25_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15553 
        thold_WD24_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15554 
        thold_WD23_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15555 
        thold_WD22_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15556 
        thold_WD21_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15557 
        thold_WD20_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15558 
        thold_WD19_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15559 
        thold_WD18_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15560 
        thold_WD17_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15561 
        thold_WD16_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15562 
        thold_WD15_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15563 
        thold_WD14_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15564 
        thold_WD13_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15565 
        thold_WD12_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15566 
        thold_WD11_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15567 
        thold_WD10_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
15568 
        thold_WD9_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15569 
        thold_WD8_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15570 
        thold_WD7_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15571 
        thold_WD6_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15572 
        thold_WD5_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15573 
        thold_WD4_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15574 
        thold_WD3_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15575 
        thold_WD2_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15576 
        thold_WD1_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15577 
        thold_WD0_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
15578 
        thold_WD35_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15579 
        thold_WD34_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15580 
        thold_WD33_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15581 
        thold_WD32_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15582 
        thold_WD31_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15583 
        thold_WD30_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15584 
        thold_WD29_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15585 
        thold_WD28_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15586 
        thold_WD27_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15587 
        thold_WD26_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15588 
        thold_WD25_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15589 
        thold_WD24_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15590 
        thold_WD23_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15591 
        thold_WD22_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15592 
        thold_WD21_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15593 
        thold_WD20_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15594 
        thold_WD19_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15595 
        thold_WD18_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15596 
        thold_WD17_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15597 
        thold_WD16_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15598 
        thold_WD15_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15599 
        thold_WD14_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15600 
        thold_WD13_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15601 
        thold_WD12_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15602 
        thold_WD11_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15603 
        thold_WD10_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
15604 
        thold_WD9_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15605 
        thold_WD8_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15606 
        thold_WD7_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15607 
        thold_WD6_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15608 
        thold_WD5_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15609 
        thold_WD4_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15610 
        thold_WD3_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15611 
        thold_WD2_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15612 
        thold_WD1_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15613 
        thold_WD0_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
15614 
 
15615 
 
15616 
        thold_WEN_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
15617 
        thold_WEN_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
15618 
 
15619 
        thold_DEPTH3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15620 
        thold_DEPTH2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15621 
        thold_DEPTH1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15622 
        thold_DEPTH0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15623 
        thold_DEPTH3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15624 
        thold_DEPTH2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15625 
        thold_DEPTH1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15626 
        thold_DEPTH0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15627 
 
15628 
 
15629 
        thold_WIDTH2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15630 
        thold_WIDTH1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15631 
        thold_WIDTH0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15632 
        thold_WIDTH2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15633 
        thold_WIDTH1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15634 
        thold_WIDTH0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15635 
 
15636 
        thold_AEVAL7_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15637 
        thold_AEVAL6_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15638 
        thold_AEVAL5_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15639 
        thold_AEVAL4_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15640 
        thold_AEVAL3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15641 
        thold_AEVAL2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15642 
        thold_AEVAL1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15643 
        thold_AEVAL0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15644 
        thold_AEVAL7_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15645 
        thold_AEVAL6_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15646 
        thold_AEVAL5_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15647 
        thold_AEVAL4_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15648 
        thold_AEVAL3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15649 
        thold_AEVAL2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15650 
        thold_AEVAL1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15651 
        thold_AEVAL0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15652 
 
15653 
        thold_AFVAL7_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15654 
        thold_AFVAL6_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15655 
        thold_AFVAL5_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15656 
        thold_AFVAL4_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15657 
        thold_AFVAL3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15658 
        thold_AFVAL2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15659 
        thold_AFVAL1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15660 
        thold_AFVAL0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15661 
        thold_AFVAL7_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15662 
        thold_AFVAL6_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15663 
        thold_AFVAL5_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15664 
        thold_AFVAL4_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15665 
        thold_AFVAL3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15666 
        thold_AFVAL2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15667 
        thold_AFVAL1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15668 
        thold_AFVAL0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15669 
 
15670 
 
15671 
 
15672 
        thold_DEPTH3_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15673 
        thold_DEPTH2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15674 
        thold_DEPTH1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15675 
        thold_DEPTH0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15676 
        thold_DEPTH3_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15677 
        thold_DEPTH2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15678 
        thold_DEPTH1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15679 
        thold_DEPTH0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15680 
 
15681 
 
15682 
        thold_WIDTH2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15683 
        thold_WIDTH1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15684 
        thold_WIDTH0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15685 
        thold_WIDTH2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15686 
        thold_WIDTH1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15687 
        thold_WIDTH0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15688 
 
15689 
 
15690 
        thold_AEVAL7_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15691 
        thold_AEVAL6_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15692 
        thold_AEVAL5_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15693 
        thold_AEVAL4_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15694 
        thold_AEVAL3_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15695 
        thold_AEVAL2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15696 
        thold_AEVAL1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15697 
        thold_AEVAL0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15698 
        thold_AEVAL7_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15699 
        thold_AEVAL6_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15700 
        thold_AEVAL5_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15701 
        thold_AEVAL4_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15702 
        thold_AEVAL3_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15703 
        thold_AEVAL2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15704 
        thold_AEVAL1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15705 
        thold_AEVAL0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15706 
 
15707 
        thold_AFVAL7_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15708 
        thold_AFVAL6_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15709 
        thold_AFVAL5_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15710 
        thold_AFVAL4_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15711 
        thold_AFVAL3_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15712 
        thold_AFVAL2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15713 
        thold_AFVAL1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15714 
        thold_AFVAL0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15715 
        thold_AFVAL7_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15716 
        thold_AFVAL6_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15717 
        thold_AFVAL5_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15718 
        thold_AFVAL4_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15719 
        thold_AFVAL3_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15720 
        thold_AFVAL2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15721 
        thold_AFVAL1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15722 
        thold_AFVAL0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
15723 
 
15724 
        thold_REN_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
15725 
        thold_REN_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
15726 
 
15727 
        trecovery_CLR_RCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
15728 
        thold_CLR_RCLK_posedge_posedge      :  VitalDelayType := 0.000 ns;
15729 
 
15730 
        trecovery_CLR_WCLK_posedge_posedge :  VitalDelayType := 0.000 ns;
15731 
        thold_CLR_WCLK_posedge_posedge      :  VitalDelayType := 0.000 ns;
15732 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
15733 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
15734 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
15735 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns;
15736 
        tpw_CLR_negedge     : VitalDelayType := 0.000 ns;
15737 
        TimingCheckOn : BOOLEAN := TRUE;
15738 
        InstancePath  : STRING := "*";
15739 
        Xon: Boolean := False;
15740 
        MsgOn: Boolean := True
15741 
        );
15742 
--pragma translate_on
15743 
  PORT (
15744 
        DEPTH3 : IN STD_ULOGIC ;
15745 
        DEPTH2 : IN STD_ULOGIC ;
15746 
        DEPTH1 : IN STD_ULOGIC ;
15747 
        DEPTH0 : IN STD_ULOGIC ;
15748 
        WIDTH2 : IN STD_ULOGIC ;
15749 
        WIDTH1 : IN STD_ULOGIC ;
15750 
        WIDTH0 : IN STD_ULOGIC ;
15751 
        AEVAL7 : IN STD_ULOGIC ;
15752 
        AEVAL6 : IN STD_ULOGIC ;
15753 
        AEVAL5 : IN STD_ULOGIC ;
15754 
        AEVAL4 : IN STD_ULOGIC ;
15755 
        AEVAL3 : IN STD_ULOGIC ;
15756 
        AEVAL2 : IN STD_ULOGIC ;
15757 
        AEVAL1 : IN STD_ULOGIC ;
15758 
        AEVAL0 : IN STD_ULOGIC ;
15759 
        AFVAL7 : IN STD_ULOGIC ;
15760 
        AFVAL6 : IN STD_ULOGIC ;
15761 
        AFVAL5 : IN STD_ULOGIC ;
15762 
        AFVAL4 : IN STD_ULOGIC ;
15763 
        AFVAL3 : IN STD_ULOGIC ;
15764 
        AFVAL2 : IN STD_ULOGIC ;
15765 
        AFVAL1 : IN STD_ULOGIC ;
15766 
        AFVAL0 : IN STD_ULOGIC ;
15767 
        REN    : IN STD_ULOGIC ;
15768 
        RCLK   : IN STD_ULOGIC ;
15769 
        WD35   : IN STD_ULOGIC ;
15770 
        WD34   : IN STD_ULOGIC ;
15771 
        WD33   : IN STD_ULOGIC ;
15772 
        WD32   : IN STD_ULOGIC ;
15773 
        WD31   : IN STD_ULOGIC ;
15774 
        WD30   : IN STD_ULOGIC ;
15775 
        WD29   : IN STD_ULOGIC ;
15776 
        WD28   : IN STD_ULOGIC ;
15777 
        WD27   : IN STD_ULOGIC ;
15778 
        WD26   : IN STD_ULOGIC ;
15779 
        WD25   : IN STD_ULOGIC ;
15780 
        WD24   : IN STD_ULOGIC ;
15781 
        WD23   : IN STD_ULOGIC ;
15782 
        WD22   : IN STD_ULOGIC ;
15783 
        WD21   : IN STD_ULOGIC ;
15784 
        WD20   : IN STD_ULOGIC ;
15785 
        WD19   : IN STD_ULOGIC ;
15786 
        WD18   : IN STD_ULOGIC ;
15787 
        WD17   : IN STD_ULOGIC ;
15788 
        WD16   : IN STD_ULOGIC ;
15789 
        WD15   : IN STD_ULOGIC ;
15790 
        WD14   : IN STD_ULOGIC ;
15791 
        WD13   : IN STD_ULOGIC ;
15792 
        WD12   : IN STD_ULOGIC ;
15793 
        WD11   : IN STD_ULOGIC ;
15794 
        WD10   : IN STD_ULOGIC ;
15795 
        WD9    : IN STD_ULOGIC ;
15796 
        WD8    : IN STD_ULOGIC ;
15797 
        WD7    : IN STD_ULOGIC ;
15798 
        WD6    : IN STD_ULOGIC ;
15799 
        WD5    : IN STD_ULOGIC ;
15800 
        WD4    : IN STD_ULOGIC ;
15801 
        WD3    : IN STD_ULOGIC ;
15802 
        WD2    : IN STD_ULOGIC ;
15803 
        WD1    : IN STD_ULOGIC ;
15804 
        WD0    : IN STD_ULOGIC ;
15805 
        WEN    : IN STD_ULOGIC ;
15806 
        WCLK   : IN STD_ULOGIC ;
15807 
        CLR    : IN STD_ULOGIC ;
15808 
        RD35   : OUT STD_ULOGIC ;
15809 
        RD34   : OUT STD_ULOGIC ;
15810 
        RD33   : OUT STD_ULOGIC ;
15811 
        RD32   : OUT STD_ULOGIC ;
15812 
        RD31   : OUT STD_ULOGIC ;
15813 
        RD30   : OUT STD_ULOGIC ;
15814 
        RD29   : OUT STD_ULOGIC ;
15815 
        RD28   : OUT STD_ULOGIC ;
15816 
        RD27   : OUT STD_ULOGIC ;
15817 
        RD26   : OUT STD_ULOGIC ;
15818 
        RD25   : OUT STD_ULOGIC ;
15819 
        RD24   : OUT STD_ULOGIC ;
15820 
        RD23   : OUT STD_ULOGIC ;
15821 
        RD22   : OUT STD_ULOGIC ;
15822 
        RD21   : OUT STD_ULOGIC ;
15823 
        RD20   : OUT STD_ULOGIC ;
15824 
        RD19   : OUT STD_ULOGIC ;
15825 
        RD18   : OUT STD_ULOGIC ;
15826 
        RD17   : OUT STD_ULOGIC ;
15827 
        RD16   : OUT STD_ULOGIC ;
15828 
        RD15   : OUT STD_ULOGIC ;
15829 
        RD14   : OUT STD_ULOGIC ;
15830 
        RD13   : OUT STD_ULOGIC ;
15831 
        RD12   : OUT STD_ULOGIC ;
15832 
        RD11   : OUT STD_ULOGIC ;
15833 
        RD10   : OUT STD_ULOGIC ;
15834 
        RD9    : OUT STD_ULOGIC ;
15835 
        RD8    : OUT STD_ULOGIC ;
15836 
        RD7    : OUT STD_ULOGIC ;
15837 
        RD6    : OUT STD_ULOGIC ;
15838 
        RD5    : OUT STD_ULOGIC ;
15839 
        RD4    : OUT STD_ULOGIC ;
15840 
        RD3    : OUT STD_ULOGIC ;
15841 
        RD2    : OUT STD_ULOGIC ;
15842 
        RD1    : OUT STD_ULOGIC ;
15843 
        RD0    : OUT STD_ULOGIC ;
15844 
        FULL   : OUT STD_ULOGIC ;
15845 
        AFULL  : OUT STD_ULOGIC ;
15846 
        EMPTY  : OUT STD_ULOGIC ;
15847 
        AEMPTY : OUT STD_ULOGIC
15848 
        );
15849 
 
15850 
 
15851 
 
15852 
end component;
15853 
 
15854 
 
15855 
component RAM64K36
15856 
--pragma translate_off
15857 
  GENERIC (
15858 
 
15859 
        TimingChecksOn  : Boolean := True;
15860 
        InstancePath    : String  := "*";
15861 
        Xon             : Boolean := False;
15862 
        MsgOn           : Boolean := True;
15863 
        MEMORYFILE      : String  := "";
15864 
 
15865 
        tipd_DEPTH3   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15866 
        tipd_DEPTH2   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15867 
        tipd_DEPTH1   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15868 
        tipd_DEPTH0   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15869 
        tipd_WRAD15   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15870 
        tipd_WRAD14   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15871 
        tipd_WRAD13   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15872 
        tipd_WRAD12   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15873 
        tipd_WRAD11   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15874 
        tipd_WRAD10   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15875 
        tipd_WRAD9    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15876 
        tipd_WRAD8    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15877 
        tipd_WRAD7    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15878 
        tipd_WRAD6    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15879 
        tipd_WRAD5    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15880 
        tipd_WRAD4    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15881 
        tipd_WRAD3    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15882 
        tipd_WRAD2    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15883 
        tipd_WRAD1    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15884 
        tipd_WRAD0    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15885 
        tipd_WD35     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15886 
        tipd_WD34     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15887 
        tipd_WD33     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15888 
        tipd_WD32     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15889 
        tipd_WD31     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15890 
        tipd_WD30     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15891 
        tipd_WD29     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15892 
        tipd_WD28     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15893 
        tipd_WD27     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15894 
        tipd_WD26     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15895 
        tipd_WD25     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15896 
        tipd_WD24     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15897 
        tipd_WD23     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15898 
        tipd_WD22     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15899 
        tipd_WD21     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15900 
        tipd_WD20     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15901 
        tipd_WD19     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15902 
        tipd_WD18     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15903 
        tipd_WD17     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15904 
        tipd_WD16     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15905 
        tipd_WD15     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15906 
        tipd_WD14     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15907 
        tipd_WD13     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15908 
        tipd_WD12     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15909 
        tipd_WD11     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15910 
        tipd_WD10     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15911 
        tipd_WD9      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15912 
        tipd_WD8      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15913 
        tipd_WD7      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15914 
        tipd_WD6      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15915 
        tipd_WD5      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15916 
        tipd_WD4      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15917 
        tipd_WD3      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15918 
        tipd_WD2      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15919 
        tipd_WD1      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15920 
        tipd_WD0      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15921 
        tipd_WW2      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15922 
        tipd_WW1      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15923 
        tipd_WW0      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15924 
        tipd_WEN      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15925 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15926 
        tipd_RDAD15   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15927 
        tipd_RDAD14   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15928 
        tipd_RDAD13   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15929 
        tipd_RDAD12   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15930 
        tipd_RDAD11   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15931 
        tipd_RDAD10   : VitalDelayType01 := (0.000 ns, 0.000 ns);
15932 
        tipd_RDAD9    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15933 
        tipd_RDAD8    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15934 
        tipd_RDAD7    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15935 
        tipd_RDAD6    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15936 
        tipd_RDAD5    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15937 
        tipd_RDAD4    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15938 
        tipd_RDAD3    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15939 
        tipd_RDAD2    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15940 
        tipd_RDAD1    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15941 
        tipd_RDAD0    : VitalDelayType01 := (0.000 ns, 0.000 ns);
15942 
        tipd_RW2      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15943 
        tipd_RW1      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15944 
        tipd_RW0      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15945 
        tipd_REN      : VitalDelayType01 := (0.000 ns, 0.000 ns);
15946 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
15947 
 
15948 
 
15949 
        tpd_RCLK_RD0  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15950 
        tpd_RCLK_RD1  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15951 
        tpd_RCLK_RD2  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15952 
        tpd_RCLK_RD3  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15953 
        tpd_RCLK_RD4  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15954 
        tpd_RCLK_RD5  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15955 
        tpd_RCLK_RD6  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15956 
        tpd_RCLK_RD7  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15957 
        tpd_RCLK_RD8  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15958 
        tpd_RCLK_RD9  : VitalDelayType01 := (0.100 ns, 0.100 ns);
15959 
        tpd_RCLK_RD10 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15960 
        tpd_RCLK_RD11 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15961 
        tpd_RCLK_RD12 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15962 
        tpd_RCLK_RD13 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15963 
        tpd_RCLK_RD14 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15964 
        tpd_RCLK_RD15 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15965 
        tpd_RCLK_RD16 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15966 
        tpd_RCLK_RD17 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15967 
        tpd_RCLK_RD18 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15968 
        tpd_RCLK_RD19 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15969 
        tpd_RCLK_RD20 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15970 
        tpd_RCLK_RD21 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15971 
        tpd_RCLK_RD22 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15972 
        tpd_RCLK_RD23 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15973 
        tpd_RCLK_RD24 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15974 
        tpd_RCLK_RD25 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15975 
        tpd_RCLK_RD26 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15976 
        tpd_RCLK_RD27 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15977 
        tpd_RCLK_RD28 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15978 
        tpd_RCLK_RD29 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15979 
        tpd_RCLK_RD30 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15980 
        tpd_RCLK_RD31 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15981 
        tpd_RCLK_RD32 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15982 
        tpd_RCLK_RD33 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15983 
        tpd_RCLK_RD34 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15984 
        tpd_RCLK_RD35 : VitalDelayType01 := (0.100 ns, 0.100 ns);
15985 
 
15986 
 
15987 
        tsetup_RDAD15_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
15988 
        tsetup_RDAD14_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
15989 
        tsetup_RDAD13_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
15990 
        tsetup_RDAD12_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
15991 
        tsetup_RDAD11_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
15992 
        tsetup_RDAD10_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
15993 
        tsetup_RDAD9_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15994 
        tsetup_RDAD8_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15995 
        tsetup_RDAD7_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15996 
        tsetup_RDAD6_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15997 
        tsetup_RDAD5_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15998 
        tsetup_RDAD4_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
15999 
        tsetup_RDAD3_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16000 
        tsetup_RDAD2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16001 
        tsetup_RDAD1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16002 
        tsetup_RDAD0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16003 
 
16004 
        tsetup_RDAD15_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16005 
        tsetup_RDAD14_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16006 
        tsetup_RDAD13_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16007 
        tsetup_RDAD12_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16008 
        tsetup_RDAD11_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16009 
        tsetup_RDAD10_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16010 
        tsetup_RDAD9_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16011 
        tsetup_RDAD8_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16012 
        tsetup_RDAD7_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16013 
        tsetup_RDAD6_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16014 
        tsetup_RDAD5_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16015 
        tsetup_RDAD4_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16016 
        tsetup_RDAD3_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16017 
        tsetup_RDAD2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16018 
        tsetup_RDAD1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16019 
        tsetup_RDAD0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16020 
 
16021 
 
16022 
        tsetup_RW2_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16023 
        tsetup_RW1_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16024 
        tsetup_RW0_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16025 
        tsetup_RW2_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16026 
        tsetup_RW1_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16027 
        tsetup_RW0_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16028 
 
16029 
 
16030 
        tsetup_DEPTH3_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16031 
        tsetup_DEPTH2_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16032 
        tsetup_DEPTH1_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16033 
        tsetup_DEPTH0_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16034 
        tsetup_DEPTH3_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16035 
        tsetup_DEPTH2_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16036 
        tsetup_DEPTH1_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16037 
        tsetup_DEPTH0_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16038 
 
16039 
 
16040 
 
16041 
        tsetup_WRAD15_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16042 
        tsetup_WRAD14_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16043 
        tsetup_WRAD13_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16044 
        tsetup_WRAD12_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16045 
        tsetup_WRAD11_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16046 
        tsetup_WRAD10_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16047 
        tsetup_WRAD9_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16048 
        tsetup_WRAD8_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16049 
        tsetup_WRAD7_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16050 
        tsetup_WRAD6_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16051 
        tsetup_WRAD5_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16052 
        tsetup_WRAD4_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16053 
        tsetup_WRAD3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16054 
        tsetup_WRAD2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16055 
        tsetup_WRAD1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16056 
        tsetup_WRAD0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16057 
 
16058 
        tsetup_WRAD15_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16059 
        tsetup_WRAD14_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16060 
        tsetup_WRAD13_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16061 
        tsetup_WRAD12_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16062 
        tsetup_WRAD11_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16063 
        tsetup_WRAD10_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16064 
        tsetup_WRAD9_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16065 
        tsetup_WRAD8_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16066 
        tsetup_WRAD7_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16067 
        tsetup_WRAD6_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16068 
        tsetup_WRAD5_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16069 
        tsetup_WRAD4_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16070 
        tsetup_WRAD3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16071 
        tsetup_WRAD2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16072 
        tsetup_WRAD1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16073 
        tsetup_WRAD0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16074 
 
16075 
        tsetup_WD35_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16076 
        tsetup_WD34_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16077 
        tsetup_WD33_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16078 
        tsetup_WD32_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16079 
        tsetup_WD31_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16080 
        tsetup_WD30_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16081 
        tsetup_WD29_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16082 
        tsetup_WD28_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16083 
        tsetup_WD27_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16084 
        tsetup_WD26_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16085 
        tsetup_WD25_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16086 
        tsetup_WD24_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16087 
        tsetup_WD23_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16088 
        tsetup_WD22_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16089 
        tsetup_WD21_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16090 
        tsetup_WD20_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16091 
        tsetup_WD19_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16092 
        tsetup_WD18_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16093 
        tsetup_WD17_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16094 
        tsetup_WD16_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16095 
        tsetup_WD15_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16096 
        tsetup_WD14_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16097 
        tsetup_WD13_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16098 
        tsetup_WD12_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16099 
        tsetup_WD11_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16100 
        tsetup_WD10_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16101 
        tsetup_WD9_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16102 
        tsetup_WD8_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16103 
        tsetup_WD7_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16104 
        tsetup_WD6_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16105 
        tsetup_WD5_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16106 
        tsetup_WD4_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16107 
        tsetup_WD3_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16108 
        tsetup_WD2_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16109 
        tsetup_WD1_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16110 
        tsetup_WD0_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16111 
        tsetup_WD35_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16112 
        tsetup_WD34_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16113 
        tsetup_WD33_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16114 
        tsetup_WD32_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16115 
        tsetup_WD31_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16116 
        tsetup_WD30_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16117 
        tsetup_WD29_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16118 
        tsetup_WD28_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16119 
        tsetup_WD27_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16120 
        tsetup_WD26_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16121 
        tsetup_WD25_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16122 
        tsetup_WD24_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16123 
        tsetup_WD23_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16124 
        tsetup_WD22_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16125 
        tsetup_WD21_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16126 
        tsetup_WD20_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16127 
        tsetup_WD19_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16128 
        tsetup_WD18_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16129 
        tsetup_WD17_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16130 
        tsetup_WD16_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16131 
        tsetup_WD15_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16132 
        tsetup_WD14_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16133 
        tsetup_WD13_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16134 
        tsetup_WD12_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16135 
        tsetup_WD11_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16136 
        tsetup_WD10_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16137 
        tsetup_WD9_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16138 
        tsetup_WD8_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16139 
        tsetup_WD7_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16140 
        tsetup_WD6_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16141 
        tsetup_WD5_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16142 
        tsetup_WD4_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16143 
        tsetup_WD3_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16144 
        tsetup_WD2_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16145 
        tsetup_WD1_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16146 
        tsetup_WD0_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16147 
 
16148 
 
16149 
        tsetup_WW2_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16150 
        tsetup_WW1_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16151 
        tsetup_WW0_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16152 
        tsetup_WW2_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16153 
        tsetup_WW1_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16154 
        tsetup_WW0_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16155 
 
16156 
 
16157 
        thold_RDAD15_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16158 
        thold_RDAD14_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16159 
        thold_RDAD13_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16160 
        thold_RDAD12_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16161 
        thold_RDAD11_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16162 
        thold_RDAD10_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16163 
        thold_RDAD9_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16164 
        thold_RDAD8_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16165 
        thold_RDAD7_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16166 
        thold_RDAD6_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16167 
        thold_RDAD5_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16168 
        thold_RDAD4_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16169 
        thold_RDAD3_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16170 
        thold_RDAD2_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16171 
        thold_RDAD1_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16172 
        thold_RDAD0_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16173 
 
16174 
        thold_RDAD15_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16175 
        thold_RDAD14_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16176 
        thold_RDAD13_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16177 
        thold_RDAD12_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16178 
        thold_RDAD11_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16179 
        thold_RDAD10_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16180 
        thold_RDAD9_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16181 
        thold_RDAD8_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16182 
        thold_RDAD7_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16183 
        thold_RDAD6_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16184 
        thold_RDAD5_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16185 
        thold_RDAD4_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16186 
        thold_RDAD3_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16187 
        thold_RDAD2_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16188 
        thold_RDAD1_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16189 
        thold_RDAD0_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16190 
 
16191 
 
16192 
 
16193 
        thold_RW2_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16194 
        thold_RW1_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16195 
        thold_RW0_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16196 
        thold_RW2_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16197 
        thold_RW1_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16198 
        thold_RW0_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16199 
 
16200 
        thold_DEPTH3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16201 
        thold_DEPTH2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16202 
        thold_DEPTH1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16203 
        thold_DEPTH0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16204 
        thold_DEPTH3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16205 
        thold_DEPTH2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16206 
        thold_DEPTH1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16207 
        thold_DEPTH0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16208 
 
16209 
        thold_WRAD15_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16210 
        thold_WRAD14_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16211 
        thold_WRAD13_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16212 
        thold_WRAD12_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16213 
        thold_WRAD11_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16214 
        thold_WRAD10_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16215 
        thold_WRAD9_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16216 
        thold_WRAD8_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16217 
        thold_WRAD7_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16218 
        thold_WRAD6_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16219 
        thold_WRAD5_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16220 
        thold_WRAD4_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16221 
        thold_WRAD3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16222 
        thold_WRAD2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16223 
        thold_WRAD1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16224 
        thold_WRAD0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16225 
 
16226 
        thold_WRAD15_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16227 
        thold_WRAD14_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16228 
        thold_WRAD13_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16229 
        thold_WRAD12_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16230 
        thold_WRAD11_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16231 
        thold_WRAD10_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16232 
        thold_WRAD9_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16233 
        thold_WRAD8_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16234 
        thold_WRAD7_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16235 
        thold_WRAD6_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16236 
        thold_WRAD5_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16237 
        thold_WRAD4_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16238 
        thold_WRAD3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16239 
        thold_WRAD2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16240 
        thold_WRAD1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16241 
        thold_WRAD0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16242 
 
16243 
 
16244 
        thold_WD35_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16245 
        thold_WD34_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16246 
        thold_WD33_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16247 
        thold_WD32_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16248 
        thold_WD31_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16249 
        thold_WD30_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16250 
        thold_WD29_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16251 
        thold_WD28_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16252 
        thold_WD27_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16253 
        thold_WD26_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16254 
        thold_WD25_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16255 
        thold_WD24_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16256 
        thold_WD23_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16257 
        thold_WD22_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16258 
        thold_WD21_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16259 
        thold_WD20_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16260 
        thold_WD19_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16261 
        thold_WD18_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16262 
        thold_WD17_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16263 
        thold_WD16_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16264 
        thold_WD15_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16265 
        thold_WD14_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16266 
        thold_WD13_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16267 
        thold_WD12_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16268 
        thold_WD11_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16269 
        thold_WD10_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16270 
        thold_WD9_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16271 
        thold_WD8_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16272 
        thold_WD7_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16273 
        thold_WD6_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16274 
        thold_WD5_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16275 
        thold_WD4_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16276 
        thold_WD3_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16277 
        thold_WD2_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16278 
        thold_WD1_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16279 
        thold_WD0_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16280 
        thold_WD35_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16281 
        thold_WD34_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16282 
        thold_WD33_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16283 
        thold_WD32_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16284 
        thold_WD31_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16285 
        thold_WD30_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16286 
        thold_WD29_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16287 
        thold_WD28_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16288 
        thold_WD27_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16289 
        thold_WD26_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16290 
        thold_WD25_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16291 
        thold_WD24_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16292 
        thold_WD23_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16293 
        thold_WD22_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16294 
        thold_WD21_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16295 
        thold_WD20_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16296 
        thold_WD19_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16297 
        thold_WD18_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16298 
        thold_WD17_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16299 
        thold_WD16_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16300 
        thold_WD15_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16301 
        thold_WD14_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16302 
        thold_WD13_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16303 
        thold_WD12_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16304 
        thold_WD11_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16305 
        thold_WD10_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16306 
        thold_WD9_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16307 
        thold_WD8_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16308 
        thold_WD7_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16309 
        thold_WD6_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16310 
        thold_WD5_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16311 
        thold_WD4_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16312 
        thold_WD3_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16313 
        thold_WD2_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16314 
        thold_WD1_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16315 
        thold_WD0_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16316 
 
16317 
 
16318 
        thold_WW2_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16319 
        thold_WW1_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16320 
        thold_WW0_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16321 
        thold_WW2_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16322 
        thold_WW1_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16323 
        thold_WW0_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16324 
 
16325 
        tsetup_REN_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16326 
        tsetup_WEN_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16327 
        thold_REN_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16328 
        thold_WEN_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16329 
        tsetup_REN_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16330 
        tsetup_WEN_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16331 
        thold_REN_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16332 
        thold_WEN_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16333 
 
16334 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
16335 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
16336 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
16337 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns
16338 
 
16339 
        );
16340 
--pragma translate_on
16341 
  PORT (
16342 
        DEPTH3 : IN STD_ULOGIC ;
16343 
        DEPTH2 : IN STD_ULOGIC ;
16344 
        DEPTH1 : IN STD_ULOGIC ;
16345 
        DEPTH0 : IN STD_ULOGIC ;
16346 
        WRAD15 : IN STD_ULOGIC ;
16347 
        WRAD14 : IN STD_ULOGIC ;
16348 
        WRAD13 : IN STD_ULOGIC ;
16349 
        WRAD12 : IN STD_ULOGIC ;
16350 
        WRAD11 : IN STD_ULOGIC ;
16351 
        WRAD10 : IN STD_ULOGIC ;
16352 
        WRAD9  : IN STD_ULOGIC ;
16353 
        WRAD8  : IN STD_ULOGIC ;
16354 
        WRAD7  : IN STD_ULOGIC ;
16355 
        WRAD6  : IN STD_ULOGIC ;
16356 
        WRAD5  : IN STD_ULOGIC ;
16357 
        WRAD4  : IN STD_ULOGIC ;
16358 
        WRAD3  : IN STD_ULOGIC ;
16359 
        WRAD2  : IN STD_ULOGIC ;
16360 
        WRAD1  : IN STD_ULOGIC ;
16361 
        WRAD0  : IN STD_ULOGIC ;
16362 
        WD35   : IN STD_ULOGIC ;
16363 
        WD34   : IN STD_ULOGIC ;
16364 
        WD33   : IN STD_ULOGIC ;
16365 
        WD32   : IN STD_ULOGIC ;
16366 
        WD31   : IN STD_ULOGIC ;
16367 
        WD30   : IN STD_ULOGIC ;
16368 
        WD29   : IN STD_ULOGIC ;
16369 
        WD28   : IN STD_ULOGIC ;
16370 
        WD27   : IN STD_ULOGIC ;
16371 
        WD26   : IN STD_ULOGIC ;
16372 
        WD25   : IN STD_ULOGIC ;
16373 
        WD24   : IN STD_ULOGIC ;
16374 
        WD23   : IN STD_ULOGIC ;
16375 
        WD22   : IN STD_ULOGIC ;
16376 
        WD21   : IN STD_ULOGIC ;
16377 
        WD20   : IN STD_ULOGIC ;
16378 
        WD19   : IN STD_ULOGIC ;
16379 
        WD18   : IN STD_ULOGIC ;
16380 
        WD17   : IN STD_ULOGIC ;
16381 
        WD16   : IN STD_ULOGIC ;
16382 
        WD15   : IN STD_ULOGIC ;
16383 
        WD14   : IN STD_ULOGIC ;
16384 
        WD13   : IN STD_ULOGIC ;
16385 
        WD12   : IN STD_ULOGIC ;
16386 
        WD11   : IN STD_ULOGIC ;
16387 
        WD10   : IN STD_ULOGIC ;
16388 
        WD9    : IN STD_ULOGIC ;
16389 
        WD8    : IN STD_ULOGIC ;
16390 
        WD7    : IN STD_ULOGIC ;
16391 
        WD6    : IN STD_ULOGIC ;
16392 
        WD5    : IN STD_ULOGIC ;
16393 
        WD4    : IN STD_ULOGIC ;
16394 
        WD3    : IN STD_ULOGIC ;
16395 
        WD2    : IN STD_ULOGIC ;
16396 
        WD1    : IN STD_ULOGIC ;
16397 
        WD0    : IN STD_ULOGIC ;
16398 
        WW2    : IN STD_ULOGIC ;
16399 
        WW1    : IN STD_ULOGIC ;
16400 
        WW0    : IN STD_ULOGIC ;
16401 
        WEN    : IN STD_ULOGIC ;
16402 
        WCLK   : IN STD_ULOGIC ;
16403 
        RDAD15 : IN STD_ULOGIC ;
16404 
        RDAD14 : IN STD_ULOGIC ;
16405 
        RDAD13 : IN STD_ULOGIC ;
16406 
        RDAD12 : IN STD_ULOGIC ;
16407 
        RDAD11 : IN STD_ULOGIC ;
16408 
        RDAD10 : IN STD_ULOGIC ;
16409 
        RDAD9  : IN STD_ULOGIC ;
16410 
        RDAD8  : IN STD_ULOGIC ;
16411 
        RDAD7  : IN STD_ULOGIC ;
16412 
        RDAD6  : IN STD_ULOGIC ;
16413 
        RDAD5  : IN STD_ULOGIC ;
16414 
        RDAD4  : IN STD_ULOGIC ;
16415 
        RDAD3  : IN STD_ULOGIC ;
16416 
        RDAD2  : IN STD_ULOGIC ;
16417 
        RDAD1  : IN STD_ULOGIC ;
16418 
        RDAD0  : IN STD_ULOGIC ;
16419 
        RW2    : IN STD_ULOGIC ;
16420 
        RW1    : IN STD_ULOGIC ;
16421 
        RW0    : IN STD_ULOGIC ;
16422 
        REN    : IN STD_ULOGIC ;
16423 
        RCLK   : IN STD_ULOGIC ;
16424 
        RD35   : OUT STD_ULOGIC ;
16425 
        RD34   : OUT STD_ULOGIC ;
16426 
        RD33   : OUT STD_ULOGIC ;
16427 
        RD32   : OUT STD_ULOGIC ;
16428 
        RD31   : OUT STD_ULOGIC ;
16429 
        RD30   : OUT STD_ULOGIC ;
16430 
        RD29   : OUT STD_ULOGIC ;
16431 
        RD28   : OUT STD_ULOGIC ;
16432 
        RD27   : OUT STD_ULOGIC ;
16433 
        RD26   : OUT STD_ULOGIC ;
16434 
        RD25   : OUT STD_ULOGIC ;
16435 
        RD24   : OUT STD_ULOGIC ;
16436 
        RD23   : OUT STD_ULOGIC ;
16437 
        RD22   : OUT STD_ULOGIC ;
16438 
        RD21   : OUT STD_ULOGIC ;
16439 
        RD20   : OUT STD_ULOGIC ;
16440 
        RD19   : OUT STD_ULOGIC ;
16441 
        RD18   : OUT STD_ULOGIC ;
16442 
        RD17   : OUT STD_ULOGIC ;
16443 
        RD16   : OUT STD_ULOGIC ;
16444 
        RD15   : OUT STD_ULOGIC ;
16445 
        RD14   : OUT STD_ULOGIC ;
16446 
        RD13   : OUT STD_ULOGIC ;
16447 
        RD12   : OUT STD_ULOGIC ;
16448 
        RD11   : OUT STD_ULOGIC ;
16449 
        RD10   : OUT STD_ULOGIC ;
16450 
        RD9    : OUT STD_ULOGIC ;
16451 
        RD8    : OUT STD_ULOGIC ;
16452 
        RD7    : OUT STD_ULOGIC ;
16453 
        RD6    : OUT STD_ULOGIC ;
16454 
        RD5    : OUT STD_ULOGIC ;
16455 
        RD4    : OUT STD_ULOGIC ;
16456 
        RD3    : OUT STD_ULOGIC ;
16457 
        RD2    : OUT STD_ULOGIC ;
16458 
        RD1    : OUT STD_ULOGIC ;
16459 
        RD0    : OUT STD_ULOGIC
16460 
        );
16461 
 
16462 
 
16463 
end component;
16464 
 
16465 
 
16466 
component RAM64K36P
16467 
--pragma translate_off
16468 
  GENERIC (
16469 
 
16470 
        TimingChecksOn  : Boolean := True;
16471 
        InstancePath    : String  := "*";
16472 
        Xon             : Boolean := False;
16473 
        MsgOn           : Boolean := True;
16474 
        MEMORYFILE      : String  := "";
16475 
 
16476 
        tipd_DEPTH3   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16477 
        tipd_DEPTH2   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16478 
        tipd_DEPTH1   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16479 
        tipd_DEPTH0   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16480 
        tipd_WRAD15   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16481 
        tipd_WRAD14   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16482 
        tipd_WRAD13   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16483 
        tipd_WRAD12   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16484 
        tipd_WRAD11   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16485 
        tipd_WRAD10   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16486 
        tipd_WRAD9    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16487 
        tipd_WRAD8    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16488 
        tipd_WRAD7    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16489 
        tipd_WRAD6    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16490 
        tipd_WRAD5    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16491 
        tipd_WRAD4    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16492 
        tipd_WRAD3    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16493 
        tipd_WRAD2    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16494 
        tipd_WRAD1    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16495 
        tipd_WRAD0    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16496 
        tipd_WD35     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16497 
        tipd_WD34     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16498 
        tipd_WD33     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16499 
        tipd_WD32     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16500 
        tipd_WD31     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16501 
        tipd_WD30     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16502 
        tipd_WD29     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16503 
        tipd_WD28     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16504 
        tipd_WD27     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16505 
        tipd_WD26     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16506 
        tipd_WD25     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16507 
        tipd_WD24     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16508 
        tipd_WD23     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16509 
        tipd_WD22     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16510 
        tipd_WD21     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16511 
        tipd_WD20     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16512 
        tipd_WD19     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16513 
        tipd_WD18     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16514 
        tipd_WD17     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16515 
        tipd_WD16     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16516 
        tipd_WD15     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16517 
        tipd_WD14     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16518 
        tipd_WD13     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16519 
        tipd_WD12     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16520 
        tipd_WD11     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16521 
        tipd_WD10     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16522 
        tipd_WD9      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16523 
        tipd_WD8      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16524 
        tipd_WD7      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16525 
        tipd_WD6      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16526 
        tipd_WD5      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16527 
        tipd_WD4      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16528 
        tipd_WD3      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16529 
        tipd_WD2      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16530 
        tipd_WD1      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16531 
        tipd_WD0      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16532 
        tipd_WW2      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16533 
        tipd_WW1      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16534 
        tipd_WW0      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16535 
        tipd_WEN      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16536 
        tipd_WCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16537 
        tipd_RDAD15   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16538 
        tipd_RDAD14   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16539 
        tipd_RDAD13   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16540 
        tipd_RDAD12   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16541 
        tipd_RDAD11   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16542 
        tipd_RDAD10   : VitalDelayType01 := (0.000 ns, 0.000 ns);
16543 
        tipd_RDAD9    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16544 
        tipd_RDAD8    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16545 
        tipd_RDAD7    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16546 
        tipd_RDAD6    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16547 
        tipd_RDAD5    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16548 
        tipd_RDAD4    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16549 
        tipd_RDAD3    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16550 
        tipd_RDAD2    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16551 
        tipd_RDAD1    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16552 
        tipd_RDAD0    : VitalDelayType01 := (0.000 ns, 0.000 ns);
16553 
        tipd_RW2      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16554 
        tipd_RW1      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16555 
        tipd_RW0      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16556 
        tipd_REN      : VitalDelayType01 := (0.000 ns, 0.000 ns);
16557 
        tipd_RCLK     : VitalDelayType01 := (0.000 ns, 0.000 ns);
16558 
 
16559 
 
16560 
        tpd_RCLK_RD0  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16561 
        tpd_RCLK_RD1  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16562 
        tpd_RCLK_RD2  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16563 
        tpd_RCLK_RD3  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16564 
        tpd_RCLK_RD4  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16565 
        tpd_RCLK_RD5  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16566 
        tpd_RCLK_RD6  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16567 
        tpd_RCLK_RD7  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16568 
        tpd_RCLK_RD8  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16569 
        tpd_RCLK_RD9  : VitalDelayType01 := (0.100 ns, 0.100 ns);
16570 
        tpd_RCLK_RD10 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16571 
        tpd_RCLK_RD11 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16572 
        tpd_RCLK_RD12 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16573 
        tpd_RCLK_RD13 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16574 
        tpd_RCLK_RD14 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16575 
        tpd_RCLK_RD15 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16576 
        tpd_RCLK_RD16 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16577 
        tpd_RCLK_RD17 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16578 
        tpd_RCLK_RD18 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16579 
        tpd_RCLK_RD19 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16580 
        tpd_RCLK_RD20 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16581 
        tpd_RCLK_RD21 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16582 
        tpd_RCLK_RD22 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16583 
        tpd_RCLK_RD23 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16584 
        tpd_RCLK_RD24 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16585 
        tpd_RCLK_RD25 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16586 
        tpd_RCLK_RD26 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16587 
        tpd_RCLK_RD27 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16588 
        tpd_RCLK_RD28 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16589 
        tpd_RCLK_RD29 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16590 
        tpd_RCLK_RD30 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16591 
        tpd_RCLK_RD31 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16592 
        tpd_RCLK_RD32 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16593 
        tpd_RCLK_RD33 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16594 
        tpd_RCLK_RD34 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16595 
        tpd_RCLK_RD35 : VitalDelayType01 := (0.100 ns, 0.100 ns);
16596 
 
16597 
 
16598 
        tsetup_RDAD15_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16599 
        tsetup_RDAD14_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16600 
        tsetup_RDAD13_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16601 
        tsetup_RDAD12_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16602 
        tsetup_RDAD11_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16603 
        tsetup_RDAD10_RCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16604 
        tsetup_RDAD9_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16605 
        tsetup_RDAD8_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16606 
        tsetup_RDAD7_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16607 
        tsetup_RDAD6_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16608 
        tsetup_RDAD5_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16609 
        tsetup_RDAD4_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16610 
        tsetup_RDAD3_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16611 
        tsetup_RDAD2_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16612 
        tsetup_RDAD1_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16613 
        tsetup_RDAD0_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16614 
 
16615 
        tsetup_RDAD15_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16616 
        tsetup_RDAD14_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16617 
        tsetup_RDAD13_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16618 
        tsetup_RDAD12_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16619 
        tsetup_RDAD11_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16620 
        tsetup_RDAD10_RCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16621 
        tsetup_RDAD9_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16622 
        tsetup_RDAD8_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16623 
        tsetup_RDAD7_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16624 
        tsetup_RDAD6_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16625 
        tsetup_RDAD5_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16626 
        tsetup_RDAD4_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16627 
        tsetup_RDAD3_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16628 
        tsetup_RDAD2_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16629 
        tsetup_RDAD1_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16630 
        tsetup_RDAD0_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16631 
 
16632 
 
16633 
 
16634 
        tsetup_RW2_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16635 
        tsetup_RW1_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16636 
        tsetup_RW0_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16637 
        tsetup_RW2_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16638 
        tsetup_RW1_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16639 
        tsetup_RW0_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16640 
 
16641 
 
16642 
        tsetup_DEPTH3_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16643 
        tsetup_DEPTH2_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16644 
        tsetup_DEPTH1_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16645 
        tsetup_DEPTH0_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16646 
        tsetup_DEPTH3_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16647 
        tsetup_DEPTH2_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16648 
        tsetup_DEPTH1_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16649 
        tsetup_DEPTH0_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16650 
 
16651 
 
16652 
 
16653 
        tsetup_WRAD15_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16654 
        tsetup_WRAD14_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16655 
        tsetup_WRAD13_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16656 
        tsetup_WRAD12_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16657 
        tsetup_WRAD11_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16658 
        tsetup_WRAD10_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16659 
        tsetup_WRAD9_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16660 
        tsetup_WRAD8_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16661 
        tsetup_WRAD7_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16662 
        tsetup_WRAD6_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16663 
        tsetup_WRAD5_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16664 
        tsetup_WRAD4_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16665 
        tsetup_WRAD3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16666 
        tsetup_WRAD2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16667 
        tsetup_WRAD1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16668 
        tsetup_WRAD0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16669 
 
16670 
        tsetup_WRAD15_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16671 
        tsetup_WRAD14_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16672 
        tsetup_WRAD13_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16673 
        tsetup_WRAD12_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16674 
        tsetup_WRAD11_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16675 
        tsetup_WRAD10_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16676 
        tsetup_WRAD9_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16677 
        tsetup_WRAD8_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16678 
        tsetup_WRAD7_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16679 
        tsetup_WRAD6_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16680 
        tsetup_WRAD5_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16681 
        tsetup_WRAD4_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16682 
        tsetup_WRAD3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16683 
        tsetup_WRAD2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16684 
        tsetup_WRAD1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16685 
        tsetup_WRAD0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16686 
 
16687 
 
16688 
        tsetup_WD35_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16689 
        tsetup_WD34_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16690 
        tsetup_WD33_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16691 
        tsetup_WD32_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16692 
        tsetup_WD31_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16693 
        tsetup_WD30_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16694 
        tsetup_WD29_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16695 
        tsetup_WD28_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16696 
        tsetup_WD27_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16697 
        tsetup_WD26_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16698 
        tsetup_WD25_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16699 
        tsetup_WD24_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16700 
        tsetup_WD23_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16701 
        tsetup_WD22_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16702 
        tsetup_WD21_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16703 
        tsetup_WD20_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16704 
        tsetup_WD19_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16705 
        tsetup_WD18_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16706 
        tsetup_WD17_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16707 
        tsetup_WD16_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16708 
        tsetup_WD15_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16709 
        tsetup_WD14_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16710 
        tsetup_WD13_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16711 
        tsetup_WD12_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16712 
        tsetup_WD11_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16713 
        tsetup_WD10_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16714 
        tsetup_WD9_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16715 
        tsetup_WD8_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16716 
        tsetup_WD7_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16717 
        tsetup_WD6_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16718 
        tsetup_WD5_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16719 
        tsetup_WD4_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16720 
        tsetup_WD3_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16721 
        tsetup_WD2_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16722 
        tsetup_WD1_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16723 
        tsetup_WD0_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16724 
        tsetup_WD35_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16725 
        tsetup_WD34_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16726 
        tsetup_WD33_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16727 
        tsetup_WD32_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16728 
        tsetup_WD31_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16729 
        tsetup_WD30_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16730 
        tsetup_WD29_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16731 
        tsetup_WD28_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16732 
        tsetup_WD27_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16733 
        tsetup_WD26_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16734 
        tsetup_WD25_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16735 
        tsetup_WD24_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16736 
        tsetup_WD23_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16737 
        tsetup_WD22_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16738 
        tsetup_WD21_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16739 
        tsetup_WD20_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16740 
        tsetup_WD19_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16741 
        tsetup_WD18_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16742 
        tsetup_WD17_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16743 
        tsetup_WD16_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16744 
        tsetup_WD15_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16745 
        tsetup_WD14_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16746 
        tsetup_WD13_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16747 
        tsetup_WD12_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16748 
        tsetup_WD11_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16749 
        tsetup_WD10_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16750 
        tsetup_WD9_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16751 
        tsetup_WD8_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16752 
        tsetup_WD7_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16753 
        tsetup_WD6_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16754 
        tsetup_WD5_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16755 
        tsetup_WD4_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16756 
        tsetup_WD3_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16757 
        tsetup_WD2_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16758 
        tsetup_WD1_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16759 
        tsetup_WD0_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16760 
 
16761 
 
16762 
 
16763 
        tsetup_WW2_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16764 
        tsetup_WW1_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16765 
        tsetup_WW0_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16766 
        tsetup_WW2_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16767 
        tsetup_WW1_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16768 
        tsetup_WW0_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16769 
 
16770 
 
16771 
        thold_RDAD15_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16772 
        thold_RDAD14_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16773 
        thold_RDAD13_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16774 
        thold_RDAD12_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16775 
        thold_RDAD11_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16776 
        thold_RDAD10_RCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16777 
        thold_RDAD9_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16778 
        thold_RDAD8_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16779 
        thold_RDAD7_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16780 
        thold_RDAD6_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16781 
        thold_RDAD5_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16782 
        thold_RDAD4_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16783 
        thold_RDAD3_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16784 
        thold_RDAD2_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16785 
        thold_RDAD1_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16786 
        thold_RDAD0_RCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16787 
 
16788 
        thold_RDAD15_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16789 
        thold_RDAD14_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16790 
        thold_RDAD13_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16791 
        thold_RDAD12_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16792 
        thold_RDAD11_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16793 
        thold_RDAD10_RCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16794 
        thold_RDAD9_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16795 
        thold_RDAD8_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16796 
        thold_RDAD7_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16797 
        thold_RDAD6_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16798 
        thold_RDAD5_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16799 
        thold_RDAD4_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16800 
        thold_RDAD3_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16801 
        thold_RDAD2_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16802 
        thold_RDAD1_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16803 
        thold_RDAD0_RCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16804 
 
16805 
        thold_RW2_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16806 
        thold_RW1_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16807 
        thold_RW0_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16808 
        thold_RW2_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16809 
        thold_RW1_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16810 
        thold_RW0_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16811 
 
16812 
        thold_DEPTH3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16813 
        thold_DEPTH2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16814 
        thold_DEPTH1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16815 
        thold_DEPTH0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16816 
        thold_DEPTH3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16817 
        thold_DEPTH2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16818 
        thold_DEPTH1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16819 
        thold_DEPTH0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16820 
 
16821 
 
16822 
        thold_WRAD15_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16823 
        thold_WRAD14_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16824 
        thold_WRAD13_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16825 
        thold_WRAD12_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16826 
        thold_WRAD11_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16827 
        thold_WRAD10_WCLK_posedge_posedge  : VitalDelayType := 0.000 ns;
16828 
        thold_WRAD9_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16829 
        thold_WRAD8_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16830 
        thold_WRAD7_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16831 
        thold_WRAD6_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16832 
        thold_WRAD5_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16833 
        thold_WRAD4_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16834 
        thold_WRAD3_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16835 
        thold_WRAD2_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16836 
        thold_WRAD1_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16837 
        thold_WRAD0_WCLK_posedge_posedge   : VitalDelayType := 0.000 ns;
16838 
 
16839 
        thold_WRAD15_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16840 
        thold_WRAD14_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16841 
        thold_WRAD13_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16842 
        thold_WRAD12_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16843 
        thold_WRAD11_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16844 
        thold_WRAD10_WCLK_negedge_posedge  : VitalDelayType := 0.000 ns;
16845 
        thold_WRAD9_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16846 
        thold_WRAD8_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16847 
        thold_WRAD7_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16848 
        thold_WRAD6_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16849 
        thold_WRAD5_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16850 
        thold_WRAD4_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16851 
        thold_WRAD3_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16852 
        thold_WRAD2_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16853 
        thold_WRAD1_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16854 
        thold_WRAD0_WCLK_negedge_posedge   : VitalDelayType := 0.000 ns;
16855 
 
16856 
 
16857 
        thold_WD35_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16858 
        thold_WD34_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16859 
        thold_WD33_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16860 
        thold_WD32_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16861 
        thold_WD31_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16862 
        thold_WD30_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16863 
        thold_WD29_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16864 
        thold_WD28_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16865 
        thold_WD27_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16866 
        thold_WD26_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16867 
        thold_WD25_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16868 
        thold_WD24_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16869 
        thold_WD23_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16870 
        thold_WD22_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16871 
        thold_WD21_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16872 
        thold_WD20_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16873 
        thold_WD19_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16874 
        thold_WD18_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16875 
        thold_WD17_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16876 
        thold_WD16_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16877 
        thold_WD15_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16878 
        thold_WD14_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16879 
        thold_WD13_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16880 
        thold_WD12_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16881 
        thold_WD11_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16882 
        thold_WD10_WCLK_posedge_posedge    : VitalDelayType := 0.000 ns;
16883 
        thold_WD9_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16884 
        thold_WD8_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16885 
        thold_WD7_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16886 
        thold_WD6_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16887 
        thold_WD5_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16888 
        thold_WD4_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16889 
        thold_WD3_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16890 
        thold_WD2_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16891 
        thold_WD1_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16892 
        thold_WD0_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16893 
        thold_WD35_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16894 
        thold_WD34_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16895 
        thold_WD33_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16896 
        thold_WD32_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16897 
        thold_WD31_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16898 
        thold_WD30_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16899 
        thold_WD29_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16900 
        thold_WD28_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16901 
        thold_WD27_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16902 
        thold_WD26_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16903 
        thold_WD25_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16904 
        thold_WD24_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16905 
        thold_WD23_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16906 
        thold_WD22_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16907 
        thold_WD21_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16908 
        thold_WD20_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16909 
        thold_WD19_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16910 
        thold_WD18_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16911 
        thold_WD17_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16912 
        thold_WD16_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16913 
        thold_WD15_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16914 
        thold_WD14_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16915 
        thold_WD13_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16916 
        thold_WD12_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16917 
        thold_WD11_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16918 
        thold_WD10_WCLK_negedge_posedge    : VitalDelayType := 0.000 ns;
16919 
        thold_WD9_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16920 
        thold_WD8_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16921 
        thold_WD7_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16922 
        thold_WD6_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16923 
        thold_WD5_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16924 
        thold_WD4_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16925 
        thold_WD3_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16926 
        thold_WD2_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16927 
        thold_WD1_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16928 
        thold_WD0_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16929 
 
16930 
 
16931 
        thold_WW2_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16932 
        thold_WW1_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16933 
        thold_WW0_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16934 
        thold_WW2_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16935 
        thold_WW1_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16936 
        thold_WW0_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16937 
 
16938 
        tsetup_REN_RCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16939 
        tsetup_WEN_WCLK_posedge_posedge     : VitalDelayType := 0.000 ns;
16940 
        thold_REN_RCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16941 
        thold_WEN_WCLK_posedge_posedge      : VitalDelayType := 0.000 ns;
16942 
        tsetup_REN_RCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16943 
        tsetup_WEN_WCLK_negedge_posedge     : VitalDelayType := 0.000 ns;
16944 
        thold_REN_RCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16945 
        thold_WEN_WCLK_negedge_posedge      : VitalDelayType := 0.000 ns;
16946 
 
16947 
 
16948 
 
16949 
        tpw_RCLK_posedge    : VitalDelayType := 0.000 ns;
16950 
        tpw_RCLK_negedge    : VitalDelayType := 0.000 ns;
16951 
        tpw_WCLK_posedge    : VitalDelayType := 0.000 ns;
16952 
        tpw_WCLK_negedge    : VitalDelayType := 0.000 ns
16953 
 
16954 
        );
16955 
--pragma translate_on
16956 
  PORT (
16957 
        DEPTH3 : IN STD_ULOGIC ;
16958 
        DEPTH2 : IN STD_ULOGIC ;
16959 
        DEPTH1 : IN STD_ULOGIC ;
16960 
        DEPTH0 : IN STD_ULOGIC ;
16961 
        WRAD15 : IN STD_ULOGIC ;
16962 
        WRAD14 : IN STD_ULOGIC ;
16963 
        WRAD13 : IN STD_ULOGIC ;
16964 
        WRAD12 : IN STD_ULOGIC ;
16965 
        WRAD11 : IN STD_ULOGIC ;
16966 
        WRAD10 : IN STD_ULOGIC ;
16967 
        WRAD9  : IN STD_ULOGIC ;
16968 
        WRAD8  : IN STD_ULOGIC ;
16969 
        WRAD7  : IN STD_ULOGIC ;
16970 
        WRAD6  : IN STD_ULOGIC ;
16971 
        WRAD5  : IN STD_ULOGIC ;
16972 
        WRAD4  : IN STD_ULOGIC ;
16973 
        WRAD3  : IN STD_ULOGIC ;
16974 
        WRAD2  : IN STD_ULOGIC ;
16975 
        WRAD1  : IN STD_ULOGIC ;
16976 
        WRAD0  : IN STD_ULOGIC ;
16977 
        WD35   : IN STD_ULOGIC ;
16978 
        WD34   : IN STD_ULOGIC ;
16979 
        WD33   : IN STD_ULOGIC ;
16980 
        WD32   : IN STD_ULOGIC ;
16981 
        WD31   : IN STD_ULOGIC ;
16982 
        WD30   : IN STD_ULOGIC ;
16983 
        WD29   : IN STD_ULOGIC ;
16984 
        WD28   : IN STD_ULOGIC ;
16985 
        WD27   : IN STD_ULOGIC ;
16986 
        WD26   : IN STD_ULOGIC ;
16987 
        WD25   : IN STD_ULOGIC ;
16988 
        WD24   : IN STD_ULOGIC ;
16989 
        WD23   : IN STD_ULOGIC ;
16990 
        WD22   : IN STD_ULOGIC ;
16991 
        WD21   : IN STD_ULOGIC ;
16992 
        WD20   : IN STD_ULOGIC ;
16993 
        WD19   : IN STD_ULOGIC ;
16994 
        WD18   : IN STD_ULOGIC ;
16995 
        WD17   : IN STD_ULOGIC ;
16996 
        WD16   : IN STD_ULOGIC ;
16997 
        WD15   : IN STD_ULOGIC ;
16998 
        WD14   : IN STD_ULOGIC ;
16999 
        WD13   : IN STD_ULOGIC ;
17000 
        WD12   : IN STD_ULOGIC ;
17001 
        WD11   : IN STD_ULOGIC ;
17002 
        WD10   : IN STD_ULOGIC ;
17003 
        WD9    : IN STD_ULOGIC ;
17004 
        WD8    : IN STD_ULOGIC ;
17005 
        WD7    : IN STD_ULOGIC ;
17006 
        WD6    : IN STD_ULOGIC ;
17007 
        WD5    : IN STD_ULOGIC ;
17008 
        WD4    : IN STD_ULOGIC ;
17009 
        WD3    : IN STD_ULOGIC ;
17010 
        WD2    : IN STD_ULOGIC ;
17011 
        WD1    : IN STD_ULOGIC ;
17012 
        WD0    : IN STD_ULOGIC ;
17013 
        WW2    : IN STD_ULOGIC ;
17014 
        WW1    : IN STD_ULOGIC ;
17015 
        WW0    : IN STD_ULOGIC ;
17016 
        WEN    : IN STD_ULOGIC ;
17017 
        WCLK   : IN STD_ULOGIC ;
17018 
        RDAD15 : IN STD_ULOGIC ;
17019 
        RDAD14 : IN STD_ULOGIC ;
17020 
        RDAD13 : IN STD_ULOGIC ;
17021 
        RDAD12 : IN STD_ULOGIC ;
17022 
        RDAD11 : IN STD_ULOGIC ;
17023 
        RDAD10 : IN STD_ULOGIC ;
17024 
        RDAD9  : IN STD_ULOGIC ;
17025 
        RDAD8  : IN STD_ULOGIC ;
17026 
        RDAD7  : IN STD_ULOGIC ;
17027 
        RDAD6  : IN STD_ULOGIC ;
17028 
        RDAD5  : IN STD_ULOGIC ;
17029 
        RDAD4  : IN STD_ULOGIC ;
17030 
        RDAD3  : IN STD_ULOGIC ;
17031 
        RDAD2  : IN STD_ULOGIC ;
17032 
        RDAD1  : IN STD_ULOGIC ;
17033 
        RDAD0  : IN STD_ULOGIC ;
17034 
        RW2    : IN STD_ULOGIC ;
17035 
        RW1    : IN STD_ULOGIC ;
17036 
        RW0    : IN STD_ULOGIC ;
17037 
        REN    : IN STD_ULOGIC ;
17038 
        RCLK   : IN STD_ULOGIC ;
17039 
        RD35   : OUT STD_ULOGIC ;
17040 
        RD34   : OUT STD_ULOGIC ;
17041 
        RD33   : OUT STD_ULOGIC ;
17042 
        RD32   : OUT STD_ULOGIC ;
17043 
        RD31   : OUT STD_ULOGIC ;
17044 
        RD30   : OUT STD_ULOGIC ;
17045 
        RD29   : OUT STD_ULOGIC ;
17046 
        RD28   : OUT STD_ULOGIC ;
17047 
        RD27   : OUT STD_ULOGIC ;
17048 
        RD26   : OUT STD_ULOGIC ;
17049 
        RD25   : OUT STD_ULOGIC ;
17050 
        RD24   : OUT STD_ULOGIC ;
17051 
        RD23   : OUT STD_ULOGIC ;
17052 
        RD22   : OUT STD_ULOGIC ;
17053 
        RD21   : OUT STD_ULOGIC ;
17054 
        RD20   : OUT STD_ULOGIC ;
17055 
        RD19   : OUT STD_ULOGIC ;
17056 
        RD18   : OUT STD_ULOGIC ;
17057 
        RD17   : OUT STD_ULOGIC ;
17058 
        RD16   : OUT STD_ULOGIC ;
17059 
        RD15   : OUT STD_ULOGIC ;
17060 
        RD14   : OUT STD_ULOGIC ;
17061 
        RD13   : OUT STD_ULOGIC ;
17062 
        RD12   : OUT STD_ULOGIC ;
17063 
        RD11   : OUT STD_ULOGIC ;
17064 
        RD10   : OUT STD_ULOGIC ;
17065 
        RD9    : OUT STD_ULOGIC ;
17066 
        RD8    : OUT STD_ULOGIC ;
17067 
        RD7    : OUT STD_ULOGIC ;
17068 
        RD6    : OUT STD_ULOGIC ;
17069 
        RD5    : OUT STD_ULOGIC ;
17070 
        RD4    : OUT STD_ULOGIC ;
17071 
        RD3    : OUT STD_ULOGIC ;
17072 
        RD2    : OUT STD_ULOGIC ;
17073 
        RD1    : OUT STD_ULOGIC ;
17074 
        RD0    : OUT STD_ULOGIC
17075 
        );
17076 
 
17077 
 
17078 
 
17079 
end component;
17080 
 
17081 
component DDR_OUT
17082 
    port(DR, DF, E, CLK, PRE, CLR : in std_logic;  Q : out std_logic) ;
17083 
end component;
17084 
 
17085 
component DDR_REG
17086 
    port(D, E, CLK, CLR, PRE : in std_logic;  QR, QF : out std_logic) ;
17087 
end component;
17088 
 
17089 
component PLL
17090 
--pragma translate_off
17091 
   generic(
17092 
      TimingChecksOn: Boolean := True;
17093 
      InstancePath: STRING := "*";
17094 
      Xon: Boolean := False;
17095 
      MsgOn: Boolean := True;
17096 
 
17097 
      f_REFCLK_LOCK          :  Integer := 3; -- Number of REFCLK pulses after which LOCK is raised
17098 
 
17099 
      tipd_PWRDWN            :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17100 
      tipd_REFCLK            :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17101 
      tipd_LOWFREQ           :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17102 
      tipd_OSC2              :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17103 
      tipd_OSC1              :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17104 
      tipd_OSC0              :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17105 
      tipd_DIVI5             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17106 
      tipd_DIVI4             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17107 
      tipd_DIVI3             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17108 
      tipd_DIVI2             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17109 
      tipd_DIVI1             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17110 
      tipd_DIVI0             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17111 
      tipd_DIVJ5             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17112 
      tipd_DIVJ4             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17113 
      tipd_DIVJ3             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17114 
      tipd_DIVJ2             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17115 
      tipd_DIVJ1             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17116 
      tipd_DIVJ0             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17117 
      tipd_DELAYLINE4        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17118 
      tipd_DELAYLINE3        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17119 
      tipd_DELAYLINE2        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17120 
      tipd_DELAYLINE1        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17121 
      tipd_DELAYLINE0        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17122 
 
17123 
      tpd_REFCLK_CLK1        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17124 
      tpd_REFCLK_CLK2        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17125 
      tpd_REFCLK_LOCK        :  VitalDelayType01 := (0.000 ns, 0.000 ns));
17126 
 
17127 
--pragma translate_on
17128 
   port(
17129 
      PWRDWN                  : in    STD_ULOGIC; -- Active high
17130 
      REFCLK                  : in    STD_ULOGIC;
17131 
      LOWFREQ                 : in    STD_ULOGIC;
17132 
      OSC2                    : in    STD_ULOGIC;
17133 
      OSC1                    : in    STD_ULOGIC;
17134 
      OSC0                    : in    STD_ULOGIC;
17135 
      DIVI5                   : in    STD_ULOGIC; -- Clock multiplier
17136 
      DIVI4                   : in    STD_ULOGIC; -- Clock multiplier
17137 
      DIVI3                   : in    STD_ULOGIC; -- Clock multiplier
17138 
      DIVI2                   : in    STD_ULOGIC; -- Clock multiplier
17139 
      DIVI1                   : in    STD_ULOGIC; -- Clock multiplier
17140 
      DIVI0                   : in    STD_ULOGIC; -- Clock multiplier
17141 
      DIVJ5                   : in    STD_ULOGIC; -- Clock divider
17142 
      DIVJ4                   : in    STD_ULOGIC; -- Clock divider
17143 
      DIVJ3                   : in    STD_ULOGIC; -- Clock divider
17144 
      DIVJ2                   : in    STD_ULOGIC; -- Clock divider
17145 
      DIVJ1                   : in    STD_ULOGIC; -- Clock divider
17146 
      DIVJ0                   : in    STD_ULOGIC; -- Clock divider
17147 
      DELAYLINE4              : in    STD_ULOGIC; -- Delay Value
17148 
      DELAYLINE3              : in    STD_ULOGIC; -- Delay Value
17149 
      DELAYLINE2              : in    STD_ULOGIC; -- Delay Value
17150 
      DELAYLINE1              : in    STD_ULOGIC; -- Delay Value
17151 
      DELAYLINE0              : in    STD_ULOGIC; -- Delay Value
17152 
      LOCK                    : out   STD_ULOGIC;
17153 
      CLK1                    : out   STD_ULOGIC;
17154 
      CLK2                    : out   STD_ULOGIC);
17155 
 
17156 
end component;
17157 
 
17158 
component PLLFB
17159 
--pragma translate_off
17160 
   generic(
17161 
      TimingChecksOn: Boolean := True;
17162 
      InstancePath: STRING := "*";
17163 
      Xon: Boolean := False;
17164 
      MsgOn: Boolean := True;
17165 
 
17166 
      f_REFCLK_LOCK          :  Integer := 3; -- Number of REFCLK pulses after which LOCK is raised
17167 
 
17168 
      tipd_PWRDWN            :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17169 
      tipd_REFCLK            :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17170 
      tipd_FB                :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17171 
      tipd_LOWFREQ           :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17172 
      tipd_OSC2              :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17173 
      tipd_OSC1              :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17174 
      tipd_OSC0              :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17175 
      tipd_DIVI5             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17176 
      tipd_DIVI4             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17177 
      tipd_DIVI3             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17178 
      tipd_DIVI2             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17179 
      tipd_DIVI1             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17180 
      tipd_DIVI0             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17181 
      tipd_DIVJ5             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17182 
      tipd_DIVJ4             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17183 
      tipd_DIVJ3             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17184 
      tipd_DIVJ2             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17185 
      tipd_DIVJ1             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17186 
      tipd_DIVJ0             :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17187 
      tipd_DELAYLINE4        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17188 
      tipd_DELAYLINE3        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17189 
      tipd_DELAYLINE2        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17190 
      tipd_DELAYLINE1        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17191 
      tipd_DELAYLINE0        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17192 
 
17193 
      tpd_REFCLK_CLK1        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17194 
      tpd_REFCLK_CLK2        :  VitalDelayType01 := (0.000 ns, 0.000 ns);
17195 
      tpd_REFCLK_LOCK        :  VitalDelayType01 := (0.000 ns, 0.000 ns));
17196 
 
17197 
--pragma translate_on
17198 
 
17199 
   port(
17200 
      PWRDWN                  : in    STD_ULOGIC; -- Active high
17201 
      REFCLK                  : in    STD_ULOGIC;
17202 
      FB                      : in    STD_ULOGIC;
17203 
      LOWFREQ                 : in    STD_ULOGIC;
17204 
      OSC2                    : in    STD_ULOGIC;
17205 
      OSC1                    : in    STD_ULOGIC;
17206 
      OSC0                    : in    STD_ULOGIC;
17207 
      DIVI5                   : in    STD_ULOGIC; -- Clock multiplier
17208 
      DIVI4                   : in    STD_ULOGIC; -- Clock multiplier
17209 
      DIVI3                   : in    STD_ULOGIC; -- Clock multiplier
17210 
      DIVI2                   : in    STD_ULOGIC; -- Clock multiplier
17211 
      DIVI1                   : in    STD_ULOGIC; -- Clock multiplier
17212 
      DIVI0                   : in    STD_ULOGIC; -- Clock multiplier
17213 
      DIVJ5                   : in    STD_ULOGIC; -- Clock divider
17214 
      DIVJ4                   : in    STD_ULOGIC; -- Clock divider
17215 
      DIVJ3                   : in    STD_ULOGIC; -- Clock divider
17216 
      DIVJ2                   : in    STD_ULOGIC; -- Clock divider
17217 
      DIVJ1                   : in    STD_ULOGIC; -- Clock divider
17218 
      DIVJ0                   : in    STD_ULOGIC; -- Clock divider
17219 
      DELAYLINE4              : in    STD_ULOGIC; -- Delay Value
17220 
      DELAYLINE3              : in    STD_ULOGIC; -- Delay Value
17221 
      DELAYLINE2              : in    STD_ULOGIC; -- Delay Value
17222 
      DELAYLINE1              : in    STD_ULOGIC; -- Delay Value
17223 
      DELAYLINE0              : in    STD_ULOGIC; -- Delay Value
17224 
      LOCK                    : out   STD_ULOGIC;
17225 
      CLK1                    : out   STD_ULOGIC;
17226 
      CLK2                    : out   STD_ULOGIC);
17227 
 
17228 
end component;
17229 
 
17230 
 
17231 
---------------- CELL:NOR5D ---------------
17232 
 
17233 
COMPONENT NOR5D
17234 
   port(
17235 
          A     : in std_logic;
17236 
          B     : in std_logic;
17237 
          C     : in std_logic;
17238 
          D     : in std_logic;
17239 
          E     : in std_logic;
17240 
          Y             : out std_logic);
17241 
END COMPONENT;
17242 
 
17243 
 
17244 
 
17245 
 
17246 
------ Component ADDSUB1 ------
17247 
 component ADDSUB1
17248 
--pragma translate_off
17249 
    generic(
17250 
                TimingChecksOn:Boolean :=True;
17251 
                Xon: Boolean :=False;
17252 
                InstancePath: STRING :="*";
17253 
                MsgOn: Boolean :=True;
17254 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
17255 
                tpd_FCI_S               : VitalDelayType01 := (0.100 ns, 0.100 ns);
17256 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
17257 
                tpd_A_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
17258 
                tpd_B_FCO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
17259 
                tpd_AS_FCO              : VitalDelayType01 := (0.100 ns, 0.100 ns);
17260 
                tpd_FCI_FCO             : VitalDelayType01 := (0.100 ns, 0.100 ns);
17261 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
17262 
                tipd_FCI                : VitalDelayType01 := (0.000 ns, 0.000 ns);
17263 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
17264 
                tipd_AS         : VitalDelayType01 := (0.000 ns, 0.000 ns));
17265 
 
17266 
 
17267 
--pragma translate_on
17268 
    port(
17269 
                A               : in    STD_ULOGIC;
17270 
                FCI             : in    STD_ULOGIC;
17271 
                B               : in    STD_ULOGIC;
17272 
                AS              : in    STD_ULOGIC;
17273 
                S               : out    STD_ULOGIC;
17274 
                FCO             : out    STD_ULOGIC);
17275 
 end component;
17276 
 
17277 
 
17278 
 
17279 
---------------- CELL:NAND5D ---------------
17280 
 
17281 
COMPONENT NAND5D
17282 
   port(
17283 
          A     : in std_logic;
17284 
          B     : in std_logic;
17285 
          C     : in std_logic;
17286 
          D     : in std_logic;
17287 
          E     : in std_logic;
17288 
          Y             : out std_logic);
17289 
END COMPONENT;
17290 
 
17291 
 
17292 
 
17293 
------ Component FA1A ------
17294 
 component FA1A
17295 
--pragma translate_off
17296 
    generic(
17297 
                TimingChecksOn:Boolean :=True;
17298 
                Xon: Boolean :=False;
17299 
                InstancePath: STRING :="*";
17300 
                MsgOn: Boolean :=True;
17301 
                tpd_CI_CO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
17302 
                tpd_B_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17303 
                tpd_A_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17304 
                tpd_CI_S                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17305 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
17306 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
17307 
                tipd_CI         : VitalDelayType01 := (0.000 ns, 0.000 ns);
17308 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
17309 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns));
17310 
 
17311 
 
17312 
--pragma translate_on
17313 
    port(
17314 
                CI              : in    STD_ULOGIC;
17315 
                B               : in    STD_ULOGIC;
17316 
                A               : in    STD_ULOGIC;
17317 
                CO              : out    STD_ULOGIC;
17318 
                S               : out    STD_ULOGIC);
17319 
 end component;
17320 
 
17321 
 
17322 
 
17323 
------ Component FA1B ------
17324 
 component FA1B
17325 
--pragma translate_off
17326 
    generic(
17327 
                TimingChecksOn:Boolean :=True;
17328 
                Xon: Boolean :=False;
17329 
                InstancePath: STRING :="*";
17330 
                MsgOn: Boolean :=True;
17331 
                tpd_A_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17332 
                tpd_B_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17333 
                tpd_CI_CO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
17334 
                tpd_CI_S                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17335 
                tpd_A_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
17336 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
17337 
                tipd_A          : VitalDelayType01 := (0.000 ns, 0.000 ns);
17338 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
17339 
                tipd_CI         : VitalDelayType01 := (0.000 ns, 0.000 ns));
17340 
 
17341 
 
17342 
--pragma translate_on
17343 
    port(
17344 
                A               : in    STD_ULOGIC;
17345 
                B               : in    STD_ULOGIC;
17346 
                CI              : in    STD_ULOGIC;
17347 
                CO              : out    STD_ULOGIC;
17348 
                S               : out    STD_ULOGIC);
17349 
 end component;
17350 
 
17351 
 
17352 
 
17353 
------ Component FA2A ------
17354 
 component FA2A
17355 
--pragma translate_off
17356 
    generic(
17357 
                TimingChecksOn:Boolean :=True;
17358 
                Xon: Boolean :=False;
17359 
                InstancePath: STRING :="*";
17360 
                MsgOn: Boolean :=True;
17361 
                tpd_CI_CO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
17362 
                tpd_B_CO                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17363 
                tpd_A0_CO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
17364 
                tpd_A1_CO               : VitalDelayType01 := (0.100 ns, 0.100 ns);
17365 
                tpd_A0_S                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17366 
                tpd_A1_S                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17367 
                tpd_B_S         : VitalDelayType01 := (0.100 ns, 0.100 ns);
17368 
                tpd_CI_S                : VitalDelayType01 := (0.100 ns, 0.100 ns);
17369 
                tipd_CI         : VitalDelayType01 := (0.000 ns, 0.000 ns);
17370 
                tipd_B          : VitalDelayType01 := (0.000 ns, 0.000 ns);
17371 
                tipd_A0         : VitalDelayType01 := (0.000 ns, 0.000 ns);
17372 
                tipd_A1         : VitalDelayType01 := (0.000 ns, 0.000 ns));
17373 
 
17374 
 
17375 
--pragma translate_on
17376 
    port(
17377 
                CI              : in    STD_ULOGIC;
17378 
                B               : in    STD_ULOGIC;
17379 
                A0              : in    STD_ULOGIC;
17380 
                A1              : in    STD_ULOGIC;
17381 
                CO              : out    STD_ULOGIC;
17382 
                S               : out    STD_ULOGIC);
17383 
 end component;
17384 
 
17385 
  attribute syn_tpd11 : string;
17386 
  attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";
17387 
  attribute syn_tpd12 : string;
17388 
  attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
17389 
  attribute syn_tpd13 : string;
17390 
  attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";
17391 
  attribute syn_tpd14 : string;
17392 
  attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
17393 
 
17394 
  attribute syn_black_box : boolean;
17395 
  attribute syn_black_box of RAM64K36 : component is true;
17396 
  attribute syn_tco1 : string;
17397 
  attribute syn_tco2 : string;
17398 
  attribute syn_tco1 of RAM64K36 : component is
17399 
  "RCLK->RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,RD10,RD11,RD12,RD13,RD14,RD15,RD16,RD17,RD18,RD19,RD20,RD21,RD22,RD23,RD24,RD25,RD26,RD27,RD28,RD29,RD30,RD31,RD32,RD33,RD34,RD35 = 4.0";
17400 
 
17401 
 END COMPONENTS;

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