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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [axcelerator/] [components/] [axcelerator_components_small.vhd] - Blame information for rev 2

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------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Package:     components
-- File:        components.vhd
-- Author:      Jiri Gaisler, Gaisler Research
-- Description: Simple Actel RAM and pad component declarations
-----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
package components is
 
-- Axcellerator rams
 
  component RAM64K36
    port(
    WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
    WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
    WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
    WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
    WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
    RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
    RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
    RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
    RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
    RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
  end component;
 
  attribute syn_black_box : boolean;
  attribute syn_black_box of RAM64K36 : component is true;
  attribute syn_tco1 : string;
  attribute syn_tco2 : string;
  attribute syn_tco1 of RAM64K36 : component is
  "RCLK->RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,RD10,RD11,RD12,RD13,RD14,RD15,RD16,RD17,RD18,RD19,RD20,RD21,RD22,RD23,RD24,RD25,RD26,RD27,RD28,RD29,RD30,RD31,RD32,RD33,RD34,RD35 = 4.0";
 
-- Buffers
 
  component inbuf_lvds port(Y : out std_logic; PADP : in std_logic; PADN : in std_logic); end component;
  component outbuf_lvds port(D : in std_logic; PADP : out std_logic; PADN : out std_logic); end component;
  component hclkbuf
  port( pad : in  std_logic; y   : out std_logic); end component;
  component clkbuf port(pad : in std_logic; y : out std_logic); end component;
  component inbuf port(pad :in std_logic; y : out std_logic); end component;
  component bibuf port(
    d, e : in  std_logic; pad : inout std_logic; y : out std_logic);
  end component;
  component outbuf port(d : in std_logic; pad : out std_logic); end component;
  component outbuf_f_8 port(d : in std_logic; pad : out std_logic); end component;
  component outbuf_f_12 port(d : in std_logic; pad : out std_logic); end component;
  component outbuf_f_16 port(d : in std_logic; pad : out std_logic); end component;
  component outbuf_f_24 port(d : in std_logic; pad : out std_logic); end component;
  component tribuff port(d, e : in std_logic; pad : out std_logic); end component;
 
  component hclkint port(a : in std_ulogic; y : out std_ulogic); end component;
  component clkint port(a : in std_ulogic; y : out std_ulogic); end component;
  component hclkbuf_pci
  port( pad : in  std_logic; y   : out std_logic); end component;
  component clkbuf_pci port(pad : in std_logic; y : out std_logic); end component;
  component inbuf_pci port(pad :in std_logic; y : out std_logic); end component;
  attribute syn_tpd11 : string;
  attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";
  component bibuf_pci port(
    d, e : in  std_logic; pad : inout std_logic; y : out std_logic);
  end component;
  attribute syn_tpd12 : string;
  attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
  component outbuf_pci port(d : in std_logic; pad : out std_logic); end component;
  attribute syn_tpd13 : string;
  attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";
  component tribuff_pci port(d, e : in std_logic; pad : out std_logic); end component;
  attribute syn_tpd14 : string;
  attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
 
 
-- 1553 -------------------------------
 
   component add1 is
      port(
      a : in std_logic;
      b : in std_logic;
      fci : in std_logic;
      s : out std_logic;
      fco : out std_logic);
   end component add1;
 
   component and2 is
      port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic);
   end component and2;
 
   component and2a is
      port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic);
   end component and2a;
 
   component and2b is
      port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic);
   end component and2b;
 
   component and3 is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      y : out std_logic);
   end component and3;
 
   component and3a is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      y : out std_logic);
   end component and3a;
 
   component and3b is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      y : out std_logic);
   end component and3b;
 
   component and3c is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      y : out std_logic);
   end component and3c;
 
   component and4 is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component and4;
 
   component and4a is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component and4a;
 
   component and4b is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component and4b;
 
   component and4c is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component and4c;
 
   component buff is
      port(
      a : in std_logic;
      y : out std_logic);
   end component buff;
 
   component cm8 is
      port(
      d0 : in std_logic;
      d1 : in std_logic;
      d2 : in std_logic;
      d3 : in std_logic;
      s00 : in std_logic;
      s01 : in std_logic;
      s10 : in std_logic;
      s11 : in std_logic;
      y : out std_logic);
   end component cm8;
 
   component cm8inv is
      port(
      a : in std_logic;
      y : out std_logic);
   end component cm8inv;
 
   component df1 is
      port(
      d : in std_logic;
      clk : in std_logic;
      q : out std_logic);
   end component df1;
 
   component dfc1b is
      port(
      d : in std_logic;
      clk : in std_logic;
      clr : in std_logic;
      q : out std_logic);
   end component dfc1b;
 
   component dfc1c is
      port(
      d : in std_logic;
      clk : in std_logic;
      clr : in std_logic;
      q : out std_logic);
   end component dfc1c;
 
   component dfc1d is
      port(
      d : in std_logic;
      clk : in std_logic;
      clr : in std_logic;
      q : out std_logic);
   end component dfc1d;
 
   component dfe1b is
      port(
      d : in std_logic;
      e : in std_logic;
      clk : in std_logic;
      q : out std_logic);
   end component dfe1b;
 
   component dfe3c is
      port(
      d : in std_logic;
      e : in std_logic;
      clk : in std_logic;
      clr : in std_logic;
      q : out std_logic);
   end component dfe3c;
 
   component dfe4f is
      port(
      d : in std_logic;
      e : in std_logic;
      clk : in std_logic;
      pre : in std_logic;
      q : out std_logic);
   end component dfe4f;
 
   component dfp1 is
      port(
      d : in std_logic;
      clk : in std_logic;
      pre : in std_logic;
      q : out std_logic);
   end component dfp1;
 
   component dfp1b is
      port(
      d : in std_logic;
      clk : in std_logic;
      pre : in std_logic;
      q : out std_logic);
   end component dfp1b;
 
   component dfp1d is
      port(
      d : in std_logic;
      clk : in std_logic;
      pre : in std_logic;
      q : out std_logic);
   end component dfp1d;
 
   component dfm
      port(
      clk : in std_logic;
      s : in std_logic;
      a : in std_logic;
      b : in std_logic;
      q : out std_logic);
 
 end component;
 
   component gnd is
      port(
      y : out std_logic);
   end component gnd;
 
   component inv is
      port(
      a : in std_logic;
      y : out std_logic);
   end component inv;
 
   component nand4 is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component nand4;
 
   component or2 is
      port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic);
   end component or2;
 
   component or2a is
      port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic);
   end component or2a;
 
   component or2b is
      port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic);
   end component or2b;
 
   component or3 is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      y : out std_logic);
   end component or3;
 
   component or3a is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      y : out std_logic);
   end component or3a;
 
   component or3b is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      y : out std_logic);
   end component or3b;
 
   component or3c is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      y : out std_logic);
   end component or3c;
 
   component or4 is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component or4;
 
   component or4a is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component or4a;
 
   component or4b is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component or4b;
 
   component or4c is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component or4c;
 
   component or4d is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      d : in std_logic;
      y : out std_logic);
   end component or4d;
 
   component sub1 is
      port(
      a : in std_logic;
      b : in std_logic;
      fci : in std_logic;
      s : out std_logic;
      fco : out std_logic);
   end component sub1;
 
   component vcc is
      port(
      y : out std_logic);
   end component vcc;
 
   component xa1 is
      port(
      a : in std_logic;
      b : in std_logic;
      c : in std_logic;
      y : out std_logic);
   end component xa1;
 
   component xnor2 is
      port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic);
   end component xnor2;
 
   component xor2 is
      port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic);
   end component xor2;
 
   component xor4 is
      port(a,b,c,d : in std_logic;
        y : out std_logic);
   end component xor4;
 
component mx2
   port(
   a : in std_logic;
   s : in std_logic;
   b : in std_logic;
   y : out std_logic);
end component;
 
 component ax1c
    port(
        a: in    std_logic;
        b: in    std_logic;
        c: in    std_logic;
        y: out   std_logic);
 end component;
 
component df1b
   port(
   d : in std_logic;
   clk : in std_logic;
   q : out std_logic);
end component;
 
component dfe1b
   port(
   d : in std_logic;
   e : in std_logic;
   clk : in std_logic;
   q : out std_logic);
end component;
 
component df1
   port(
   d : in std_logic;
   clk : in std_logic;
   q : out std_logic);
end component;
 
end;

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [axcelerator/] [components/] [axcelerator_components_small.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Package: components`
20			`-- File: components.vhd`
21			`-- Author: Jiri Gaisler, Gaisler Research`
22			`-- Description: Simple Actel RAM and pad component declarations`
23			`-----------------------------------------------------------------------------`
24
25			`library ieee;`
26			`use ieee.std_logic_1164.all;`
27
28			`package components is`
29
30			`-- Axcellerator rams`
31
32			`component RAM64K36`
33			`port(`
34			`WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,`
35			`WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,`
36			`WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,`
37			`WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,`
38			`WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,`
39			`RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,`
40			`RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;`
41			`RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,`
42			`RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,`
43			`RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);`
44			`end component;`
45
46			`attribute syn_black_box : boolean;`
47			`attribute syn_black_box of RAM64K36 : component is true;`
48			`attribute syn_tco1 : string;`
49			`attribute syn_tco2 : string;`
50			`attribute syn_tco1 of RAM64K36 : component is`
51			`"RCLK->RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,RD10,RD11,RD12,RD13,RD14,RD15,RD16,RD17,RD18,RD19,RD20,RD21,RD22,RD23,RD24,RD25,RD26,RD27,RD28,RD29,RD30,RD31,RD32,RD33,RD34,RD35 = 4.0";`
52
53			`-- Buffers`
54
55			`component inbuf_lvds port(Y : out std_logic; PADP : in std_logic; PADN : in std_logic); end component;`
56			`component outbuf_lvds port(D : in std_logic; PADP : out std_logic; PADN : out std_logic); end component;`
57			`component hclkbuf`
58			`port( pad : in std_logic; y : out std_logic); end component;`
59			`component clkbuf port(pad : in std_logic; y : out std_logic); end component;`
60			`component inbuf port(pad :in std_logic; y : out std_logic); end component;`
61			`component bibuf port(`
62			`d, e : in std_logic; pad : inout std_logic; y : out std_logic);`
63			`end component;`
64			`component outbuf port(d : in std_logic; pad : out std_logic); end component;`
65			`component outbuf_f_8 port(d : in std_logic; pad : out std_logic); end component;`
66			`component outbuf_f_12 port(d : in std_logic; pad : out std_logic); end component;`
67			`component outbuf_f_16 port(d : in std_logic; pad : out std_logic); end component;`
68			`component outbuf_f_24 port(d : in std_logic; pad : out std_logic); end component;`
69			`component tribuff port(d, e : in std_logic; pad : out std_logic); end component;`
70
71			`component hclkint port(a : in std_ulogic; y : out std_ulogic); end component;`
72			`component clkint port(a : in std_ulogic; y : out std_ulogic); end component;`
73			`component hclkbuf_pci`
74			`port( pad : in std_logic; y : out std_logic); end component;`
75			`component clkbuf_pci port(pad : in std_logic; y : out std_logic); end component;`
76			`component inbuf_pci port(pad :in std_logic; y : out std_logic); end component;`
77			`attribute syn_tpd11 : string;`
78			`attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";`
79			`component bibuf_pci port(`
80			`d, e : in std_logic; pad : inout std_logic; y : out std_logic);`
81			`end component;`
82			`attribute syn_tpd12 : string;`
83			`attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";`
84			`component outbuf_pci port(d : in std_logic; pad : out std_logic); end component;`
85			`attribute syn_tpd13 : string;`
86			`attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";`
87			`component tribuff_pci port(d, e : in std_logic; pad : out std_logic); end component;`
88			`attribute syn_tpd14 : string;`
89			`attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";`
90
91
92			`-- 1553 -------------------------------`
93
94			`component add1 is`
95			`port(`
96			`a : in std_logic;`
97			`b : in std_logic;`
98			`fci : in std_logic;`
99			`s : out std_logic;`
100			`fco : out std_logic);`
101			`end component add1;`
102
103			`component and2 is`
104			`port(`
105			`a : in std_logic;`
106			`b : in std_logic;`
107			`y : out std_logic);`
108			`end component and2;`
109
110			`component and2a is`
111			`port(`
112			`a : in std_logic;`
113			`b : in std_logic;`
114			`y : out std_logic);`
115			`end component and2a;`
116
117			`component and2b is`
118			`port(`
119			`a : in std_logic;`
120			`b : in std_logic;`
121			`y : out std_logic);`
122			`end component and2b;`
123
124			`component and3 is`
125			`port(`
126			`a : in std_logic;`
127			`b : in std_logic;`
128			`c : in std_logic;`
129			`y : out std_logic);`
130			`end component and3;`
131
132			`component and3a is`
133			`port(`
134			`a : in std_logic;`
135			`b : in std_logic;`
136			`c : in std_logic;`
137			`y : out std_logic);`
138			`end component and3a;`
139
140			`component and3b is`
141			`port(`
142			`a : in std_logic;`
143			`b : in std_logic;`
144			`c : in std_logic;`
145			`y : out std_logic);`
146			`end component and3b;`
147
148			`component and3c is`
149			`port(`
150			`a : in std_logic;`
151			`b : in std_logic;`
152			`c : in std_logic;`
153			`y : out std_logic);`
154			`end component and3c;`
155
156			`component and4 is`
157			`port(`
158			`a : in std_logic;`
159			`b : in std_logic;`
160			`c : in std_logic;`
161			`d : in std_logic;`
162			`y : out std_logic);`
163			`end component and4;`
164
165			`component and4a is`
166			`port(`
167			`a : in std_logic;`
168			`b : in std_logic;`
169			`c : in std_logic;`
170			`d : in std_logic;`
171			`y : out std_logic);`
172			`end component and4a;`
173
174			`component and4b is`
175			`port(`
176			`a : in std_logic;`
177			`b : in std_logic;`
178			`c : in std_logic;`
179			`d : in std_logic;`
180			`y : out std_logic);`
181			`end component and4b;`
182
183			`component and4c is`
184			`port(`
185			`a : in std_logic;`
186			`b : in std_logic;`
187			`c : in std_logic;`
188			`d : in std_logic;`
189			`y : out std_logic);`
190			`end component and4c;`
191
192			`component buff is`
193			`port(`
194			`a : in std_logic;`
195			`y : out std_logic);`
196			`end component buff;`
197
198			`component cm8 is`
199			`port(`
200			`d0 : in std_logic;`
201			`d1 : in std_logic;`
202			`d2 : in std_logic;`
203			`d3 : in std_logic;`
204			`s00 : in std_logic;`
205			`s01 : in std_logic;`
206			`s10 : in std_logic;`
207			`s11 : in std_logic;`
208			`y : out std_logic);`
209			`end component cm8;`
210
211			`component cm8inv is`
212			`port(`
213			`a : in std_logic;`
214			`y : out std_logic);`
215			`end component cm8inv;`
216
217			`component df1 is`
218			`port(`
219			`d : in std_logic;`
220			`clk : in std_logic;`
221			`q : out std_logic);`
222			`end component df1;`
223
224			`component dfc1b is`
225			`port(`
226			`d : in std_logic;`
227			`clk : in std_logic;`
228			`clr : in std_logic;`
229			`q : out std_logic);`
230			`end component dfc1b;`
231
232			`component dfc1c is`
233			`port(`
234			`d : in std_logic;`
235			`clk : in std_logic;`
236			`clr : in std_logic;`
237			`q : out std_logic);`
238			`end component dfc1c;`
239
240			`component dfc1d is`
241			`port(`
242			`d : in std_logic;`
243			`clk : in std_logic;`
244			`clr : in std_logic;`
245			`q : out std_logic);`
246			`end component dfc1d;`
247
248			`component dfe1b is`
249			`port(`
250			`d : in std_logic;`
251			`e : in std_logic;`
252			`clk : in std_logic;`
253			`q : out std_logic);`
254			`end component dfe1b;`
255
256			`component dfe3c is`
257			`port(`
258			`d : in std_logic;`
259			`e : in std_logic;`
260			`clk : in std_logic;`
261			`clr : in std_logic;`
262			`q : out std_logic);`
263			`end component dfe3c;`
264
265			`component dfe4f is`
266			`port(`
267			`d : in std_logic;`
268			`e : in std_logic;`
269			`clk : in std_logic;`
270			`pre : in std_logic;`
271			`q : out std_logic);`
272			`end component dfe4f;`
273
274			`component dfp1 is`
275			`port(`
276			`d : in std_logic;`
277			`clk : in std_logic;`
278			`pre : in std_logic;`
279			`q : out std_logic);`
280			`end component dfp1;`
281
282			`component dfp1b is`
283			`port(`
284			`d : in std_logic;`
285			`clk : in std_logic;`
286			`pre : in std_logic;`
287			`q : out std_logic);`
288			`end component dfp1b;`
289
290			`component dfp1d is`
291			`port(`
292			`d : in std_logic;`
293			`clk : in std_logic;`
294			`pre : in std_logic;`
295			`q : out std_logic);`
296			`end component dfp1d;`
297
298			`component dfm`
299			`port(`
300			`clk : in std_logic;`
301			`s : in std_logic;`
302			`a : in std_logic;`
303			`b : in std_logic;`
304			`q : out std_logic);`
305
306			`end component;`
307
308			`component gnd is`
309			`port(`
310			`y : out std_logic);`
311			`end component gnd;`
312
313			`component inv is`
314			`port(`
315			`a : in std_logic;`
316			`y : out std_logic);`
317			`end component inv;`
318
319			`component nand4 is`
320			`port(`
321			`a : in std_logic;`
322			`b : in std_logic;`
323			`c : in std_logic;`
324			`d : in std_logic;`
325			`y : out std_logic);`
326			`end component nand4;`
327
328			`component or2 is`
329			`port(`
330			`a : in std_logic;`
331			`b : in std_logic;`
332			`y : out std_logic);`
333			`end component or2;`
334
335			`component or2a is`
336			`port(`
337			`a : in std_logic;`
338			`b : in std_logic;`
339			`y : out std_logic);`
340			`end component or2a;`
341
342			`component or2b is`
343			`port(`
344			`a : in std_logic;`
345			`b : in std_logic;`
346			`y : out std_logic);`
347			`end component or2b;`
348
349			`component or3 is`
350			`port(`
351			`a : in std_logic;`
352			`b : in std_logic;`
353			`c : in std_logic;`
354			`y : out std_logic);`
355			`end component or3;`
356
357			`component or3a is`
358			`port(`
359			`a : in std_logic;`
360			`b : in std_logic;`
361			`c : in std_logic;`
362			`y : out std_logic);`
363			`end component or3a;`
364
365			`component or3b is`
366			`port(`
367			`a : in std_logic;`
368			`b : in std_logic;`
369			`c : in std_logic;`
370			`y : out std_logic);`
371			`end component or3b;`
372
373			`component or3c is`
374			`port(`
375			`a : in std_logic;`
376			`b : in std_logic;`
377			`c : in std_logic;`
378			`y : out std_logic);`
379			`end component or3c;`
380
381			`component or4 is`
382			`port(`
383			`a : in std_logic;`
384			`b : in std_logic;`
385			`c : in std_logic;`
386			`d : in std_logic;`
387			`y : out std_logic);`
388			`end component or4;`
389
390			`component or4a is`
391			`port(`
392			`a : in std_logic;`
393			`b : in std_logic;`
394			`c : in std_logic;`
395			`d : in std_logic;`
396			`y : out std_logic);`
397			`end component or4a;`
398
399			`component or4b is`
400			`port(`
401			`a : in std_logic;`
402			`b : in std_logic;`
403			`c : in std_logic;`
404			`d : in std_logic;`
405			`y : out std_logic);`
406			`end component or4b;`
407
408			`component or4c is`
409			`port(`
410			`a : in std_logic;`
411			`b : in std_logic;`
412			`c : in std_logic;`
413			`d : in std_logic;`
414			`y : out std_logic);`
415			`end component or4c;`
416
417			`component or4d is`
418			`port(`
419			`a : in std_logic;`
420			`b : in std_logic;`
421			`c : in std_logic;`
422			`d : in std_logic;`
423			`y : out std_logic);`
424			`end component or4d;`
425
426			`component sub1 is`
427			`port(`
428			`a : in std_logic;`
429			`b : in std_logic;`
430			`fci : in std_logic;`
431			`s : out std_logic;`
432			`fco : out std_logic);`
433			`end component sub1;`
434
435			`component vcc is`
436			`port(`
437			`y : out std_logic);`
438			`end component vcc;`
439
440			`component xa1 is`
441			`port(`
442			`a : in std_logic;`
443			`b : in std_logic;`
444			`c : in std_logic;`
445			`y : out std_logic);`
446			`end component xa1;`
447
448			`component xnor2 is`
449			`port(`
450			`a : in std_logic;`
451			`b : in std_logic;`
452			`y : out std_logic);`
453			`end component xnor2;`
454
455			`component xor2 is`
456			`port(`
457			`a : in std_logic;`
458			`b : in std_logic;`
459			`y : out std_logic);`
460			`end component xor2;`
461
462			`component xor4 is`
463			`port(a,b,c,d : in std_logic;`
464			`y : out std_logic);`
465			`end component xor4;`
466
467			`component mx2`
468			`port(`
469			`a : in std_logic;`
470			`s : in std_logic;`
471			`b : in std_logic;`
472			`y : out std_logic);`
473			`end component;`
474
475			`component ax1c`
476			`port(`
477			`a: in std_logic;`
478			`b: in std_logic;`
479			`c: in std_logic;`
480			`y: out std_logic);`
481			`end component;`
482
483			`component df1b`
484			`port(`
485			`d : in std_logic;`
486			`clk : in std_logic;`
487			`q : out std_logic);`
488			`end component;`
489
490			`component dfe1b`
491			`port(`
492			`d : in std_logic;`
493			`e : in std_logic;`
494			`clk : in std_logic;`
495			`q : out std_logic);`
496			`end component;`
497
498			`component df1`
499			`port(`
500			`d : in std_logic;`
501			`clk : in std_logic;`
502			`q : out std_logic);`
503			`end component;`
504
505			`end;`