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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [ec/] [orca/] [mem3.vhd] - Blame information for rev 2

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1 2 dimamali 
--
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----- package mem3 -----
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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PACKAGE mem3 IS
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   TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
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   TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
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   FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
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   FUNCTION str3_slv12 (hex: string) RETURN std_logic_vector;
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   FUNCTION data2data (data_w: integer) RETURN integer;
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   FUNCTION data2addr_w (data_w: integer) RETURN integer;
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   FUNCTION data2data_w (data_w: integer) RETURN integer;
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   FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector;
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   FUNCTION init_ram1 (hex: string) RETURN mem_type_6;
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   FUNCTION str2slv (str: in string) RETURN std_logic_vector;
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   FUNCTION Valid_Address (IN_ADDR : in std_logic_vector) return boolean;
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END mem3;
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PACKAGE BODY mem3 IS
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   FUNCTION hex2bin (hex: character) RETURN std_logic_vector IS
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        VARIABLE result : std_logic_vector (3 downto 0);
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   BEGIN
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        CASE hex IS
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          WHEN '0' =>
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             result := "0000";
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          WHEN '1' =>
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             result := "0001";
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          WHEN '2' =>
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             result := "0010";
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          WHEN '3' =>
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             result := "0011";
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          WHEN '4' =>
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             result := "0100";
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          WHEN '5' =>
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             result := "0101";
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          WHEN '6' =>
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             result := "0110";
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          WHEN '7' =>
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             result := "0111";
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          WHEN '8' =>
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             result := "1000";
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          WHEN '9' =>
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             result := "1001";
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          WHEN 'A'|'a' =>
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             result := "1010";
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          WHEN 'B'|'b' =>
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             result := "1011";
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          WHEN 'C'|'c' =>
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             result := "1100";
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          WHEN 'D'|'d' =>
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             result := "1101";
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          WHEN 'E'|'e' =>
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             result := "1110";
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          WHEN 'F'|'f' =>
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             result := "1111";
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          WHEN 'X'|'x' =>
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             result := "XXXX";
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          WHEN others =>
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             NULL;
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        END CASE;
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        RETURN result;
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   END;
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   FUNCTION str5_slv18 (s : string(5 downto 1)) return std_logic_vector is
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        VARIABLE result : std_logic_vector(17 downto 0);
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   BEGIN
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       FOR i in 0 to 3 LOOP
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          result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
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       END LOOP;
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          result(17 downto 16) := hex2bin(s(5))(1 downto 0);
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       RETURN result;
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   END;
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   FUNCTION str4_slv16 (s : string(4 downto 1)) return std_logic_vector is
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        VARIABLE result : std_logic_vector(15 downto 0);
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   BEGIN
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       FOR i in 0 to 3 LOOP
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          result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
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       END LOOP;
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       RETURN result;
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   END;
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   FUNCTION str3_slv12 (hex: string) return std_logic_vector is
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        VARIABLE result : std_logic_vector(11 downto 0);
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   BEGIN
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       FOR i in 0 to 2 LOOP
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          result(((i+1)*4)-1 downto (i*4)) := hex2bin(hex(i+1));
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       END LOOP;
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       RETURN result;
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   END;
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   FUNCTION data2addr_w (data_w : integer) return integer is
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        VARIABLE result : integer;
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   BEGIN
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        CASE data_w IS
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          WHEN 1 =>
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             result := 13;
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          WHEN 2 =>
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             result := 12;
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          WHEN 4 =>
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             result := 11;
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          WHEN 9 =>
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             result := 10;
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          WHEN 18 =>
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             result := 9;
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          WHEN 36 =>
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             result := 8;
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          WHEN others =>
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             NULL;
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        END CASE;
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       RETURN result;
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   END;
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   FUNCTION data2data_w (data_w : integer) return integer is
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        VARIABLE result : integer;
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   BEGIN
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        CASE data_w IS
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          WHEN 1 =>
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             result := 1;
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          WHEN 2 =>
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             result := 2;
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          WHEN 4 =>
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             result := 4;
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          WHEN 9 =>
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             result := 9;
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          WHEN 18 =>
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             result := 18;
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          WHEN 36 =>
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             result := 18;
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          WHEN others =>
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             NULL;
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        END CASE;
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       RETURN result;
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   END;
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   FUNCTION data2data (data_w : integer) return integer is
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        VARIABLE result : integer;
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   BEGIN
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        CASE data_w IS
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          WHEN 1 =>
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             result := 8;
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          WHEN 2 =>
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             result := 4;
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          WHEN 4 =>
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             result := 2;
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          WHEN 9 =>
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             result := 36864;
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          WHEN 18 =>
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             result := 36864;
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          WHEN 36 =>
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             result := 36864;
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          WHEN others =>
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             NULL;
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        END CASE;
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       RETURN result;
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   END;
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   FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector IS
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        CONSTANT length : integer := hex'length;
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        VARIABLE result1 : mem_type_5 (0 to ((length/5)-1));
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        VARIABLE result : std_logic_vector(((length*18)/5)-1 downto 0);
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   BEGIN
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       FOR i in 0 to ((length/5)-1) LOOP
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         result1(i) := str5_slv18(hex((i+1)*5 downto (i*5)+1));
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       END LOOP;
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       IF (DATA_WIDTH_A >= 9 and DATA_WIDTH_B >= 9) THEN
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          FOR j in 0 to 511 LOOP
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            result(((j*18) + 17) downto (j*18)) := result1(j)(17 downto 0);
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          END LOOP;
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       ELSE
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          FOR j in 0 to 511 LOOP
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            result(((j*18) + 7) downto (j*18)) := result1(j)(7 downto 0);
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            result((j*18) + 8) := '0';
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            result(((j*18) + 16) downto ((j*18) + 9)) := result1(j)(15 downto 8);
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            result((j*18) + 17) := '0';
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          END LOOP;
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       END IF;
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       RETURN result;
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   END;
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   FUNCTION init_ram1 (hex: string) RETURN mem_type_6 IS
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        CONSTANT length : integer := hex'length;
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        VARIABLE result : mem_type_6 (0 to ((length/4)-1));
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   BEGIN
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       FOR i in 0 to ((length/4)-1) LOOP
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         result(i) := str4_slv16(hex((i+1)*4 downto (i*4)+1));
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       END LOOP;
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       RETURN result;
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   END;
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-- String to std_logic_vector
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  FUNCTION str2slv (
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      str : in string
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  ) return std_logic_vector is
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  variable j : integer := str'length;
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  variable slv : std_logic_vector (str'length downto 1);
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  begin
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      for i in str'low to str'high loop
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          case str(i) is
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              when '0' => slv(j) := '0';
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              when '1' => slv(j) := '1';
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              when 'X' => slv(j) := 'X';
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              when 'U' => slv(j) := 'U';
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              when others => slv(j) := 'X';
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          end case;
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          j := j - 1;
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      end loop;
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      return slv;
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  end str2slv;
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function Valid_Address (
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    IN_ADDR : in std_logic_vector
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 ) return boolean is
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    variable v_Valid_Flag : boolean := TRUE;
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begin
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    for i in IN_ADDR'high downto IN_ADDR'low loop
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        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
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            v_Valid_Flag := FALSE;
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        end if;
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    end loop;
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    return v_Valid_Flag;
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end Valid_Address;
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END mem3 ;

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