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dimamali |
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----- package mem3 -----
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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PACKAGE mem3 IS
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TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
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TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
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FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
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FUNCTION str3_slv12 (hex: string) RETURN std_logic_vector;
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FUNCTION data2data (data_w: integer) RETURN integer;
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FUNCTION data2addr_w (data_w: integer) RETURN integer;
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FUNCTION data2data_w (data_w: integer) RETURN integer;
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FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector;
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FUNCTION init_ram1 (hex: string) RETURN mem_type_6;
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FUNCTION str2slv (str: in string) RETURN std_logic_vector;
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FUNCTION Valid_Address (IN_ADDR : in std_logic_vector) return boolean;
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END mem3;
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PACKAGE BODY mem3 IS
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FUNCTION hex2bin (hex: character) RETURN std_logic_vector IS
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VARIABLE result : std_logic_vector (3 downto 0);
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BEGIN
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CASE hex IS
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WHEN '0' =>
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result := "0000";
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WHEN '1' =>
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result := "0001";
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WHEN '2' =>
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result := "0010";
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WHEN '3' =>
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result := "0011";
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WHEN '4' =>
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result := "0100";
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WHEN '5' =>
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result := "0101";
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WHEN '6' =>
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result := "0110";
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WHEN '7' =>
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result := "0111";
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WHEN '8' =>
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result := "1000";
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WHEN '9' =>
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result := "1001";
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WHEN 'A'|'a' =>
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result := "1010";
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WHEN 'B'|'b' =>
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result := "1011";
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WHEN 'C'|'c' =>
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result := "1100";
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WHEN 'D'|'d' =>
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result := "1101";
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WHEN 'E'|'e' =>
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result := "1110";
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WHEN 'F'|'f' =>
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result := "1111";
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WHEN 'X'|'x' =>
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result := "XXXX";
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WHEN others =>
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NULL;
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END CASE;
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RETURN result;
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END;
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FUNCTION str5_slv18 (s : string(5 downto 1)) return std_logic_vector is
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VARIABLE result : std_logic_vector(17 downto 0);
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BEGIN
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FOR i in 0 to 3 LOOP
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result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
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END LOOP;
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result(17 downto 16) := hex2bin(s(5))(1 downto 0);
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RETURN result;
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END;
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FUNCTION str4_slv16 (s : string(4 downto 1)) return std_logic_vector is
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VARIABLE result : std_logic_vector(15 downto 0);
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BEGIN
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FOR i in 0 to 3 LOOP
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result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
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END LOOP;
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RETURN result;
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END;
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FUNCTION str3_slv12 (hex: string) return std_logic_vector is
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VARIABLE result : std_logic_vector(11 downto 0);
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BEGIN
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FOR i in 0 to 2 LOOP
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result(((i+1)*4)-1 downto (i*4)) := hex2bin(hex(i+1));
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END LOOP;
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RETURN result;
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END;
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FUNCTION data2addr_w (data_w : integer) return integer is
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VARIABLE result : integer;
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BEGIN
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CASE data_w IS
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WHEN 1 =>
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result := 13;
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WHEN 2 =>
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result := 12;
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WHEN 4 =>
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result := 11;
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WHEN 9 =>
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result := 10;
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WHEN 18 =>
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result := 9;
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WHEN 36 =>
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result := 8;
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WHEN others =>
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NULL;
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END CASE;
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RETURN result;
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END;
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FUNCTION data2data_w (data_w : integer) return integer is
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VARIABLE result : integer;
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BEGIN
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CASE data_w IS
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WHEN 1 =>
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result := 1;
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WHEN 2 =>
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result := 2;
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WHEN 4 =>
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result := 4;
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WHEN 9 =>
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result := 9;
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WHEN 18 =>
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result := 18;
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WHEN 36 =>
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result := 18;
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WHEN others =>
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NULL;
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END CASE;
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RETURN result;
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END;
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FUNCTION data2data (data_w : integer) return integer is
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VARIABLE result : integer;
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BEGIN
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CASE data_w IS
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WHEN 1 =>
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result := 8;
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WHEN 2 =>
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result := 4;
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WHEN 4 =>
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result := 2;
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WHEN 9 =>
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result := 36864;
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WHEN 18 =>
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result := 36864;
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WHEN 36 =>
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result := 36864;
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WHEN others =>
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NULL;
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END CASE;
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RETURN result;
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END;
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FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector IS
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CONSTANT length : integer := hex'length;
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VARIABLE result1 : mem_type_5 (0 to ((length/5)-1));
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VARIABLE result : std_logic_vector(((length*18)/5)-1 downto 0);
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BEGIN
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FOR i in 0 to ((length/5)-1) LOOP
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result1(i) := str5_slv18(hex((i+1)*5 downto (i*5)+1));
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END LOOP;
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IF (DATA_WIDTH_A >= 9 and DATA_WIDTH_B >= 9) THEN
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FOR j in 0 to 511 LOOP
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result(((j*18) + 17) downto (j*18)) := result1(j)(17 downto 0);
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END LOOP;
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ELSE
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FOR j in 0 to 511 LOOP
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result(((j*18) + 7) downto (j*18)) := result1(j)(7 downto 0);
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result((j*18) + 8) := '0';
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result(((j*18) + 16) downto ((j*18) + 9)) := result1(j)(15 downto 8);
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result((j*18) + 17) := '0';
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END LOOP;
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END IF;
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RETURN result;
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END;
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FUNCTION init_ram1 (hex: string) RETURN mem_type_6 IS
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CONSTANT length : integer := hex'length;
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VARIABLE result : mem_type_6 (0 to ((length/4)-1));
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BEGIN
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FOR i in 0 to ((length/4)-1) LOOP
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result(i) := str4_slv16(hex((i+1)*4 downto (i*4)+1));
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END LOOP;
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RETURN result;
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END;
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-- String to std_logic_vector
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FUNCTION str2slv (
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str : in string
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) return std_logic_vector is
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variable j : integer := str'length;
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variable slv : std_logic_vector (str'length downto 1);
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begin
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for i in str'low to str'high loop
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case str(i) is
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when '0' => slv(j) := '0';
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when '1' => slv(j) := '1';
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when 'X' => slv(j) := 'X';
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when 'U' => slv(j) := 'U';
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when others => slv(j) := 'X';
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end case;
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j := j - 1;
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end loop;
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return slv;
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end str2slv;
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function Valid_Address (
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IN_ADDR : in std_logic_vector
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) return boolean is
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variable v_Valid_Flag : boolean := TRUE;
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begin
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for i in IN_ADDR'high downto IN_ADDR'low loop
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if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
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v_Valid_Flag := FALSE;
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end if;
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end loop;
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return v_Valid_Flag;
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end Valid_Address;
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END mem3 ;
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--
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-----cell dp8ka----
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.vital_timing.all;
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use ieee.vital_primitives.all;
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--use ieee.std_logic_unsigned.all;
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library ec;
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use ec.global.gsrnet;
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use ec.global.purnet;
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use ec.mem3.all;
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library grlib;
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use grlib.stdlib.all;
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-- entity declaration --
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ENTITY dp8ka IS
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GENERIC (
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DATA_WIDTH_A : Integer := 18;
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DATA_WIDTH_B : Integer := 18;
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REGMODE_A : String := "NOREG";
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REGMODE_B : String := "NOREG";
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RESETMODE : String := "ASYNC";
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CSDECODE_A : String := "000";
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CSDECODE_B : String := "000";
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WRITEMODE_A : String := "NORMAL";
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WRITEMODE_B : String := "NORMAL";
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GSR : String := "ENABLED";
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initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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-- miscellaneous vital GENERICs
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "dp8ka";
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-- input SIGNAL delays
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tipd_ada12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_ada0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_dia0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
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tipd_clka : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
336 |
|
|
tipd_cea : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
337 |
|
|
tipd_wea : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
338 |
|
|
tipd_csa0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
339 |
|
|
tipd_csa1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
340 |
|
|
tipd_csa2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
341 |
|
|
tipd_rsta : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
342 |
|
|
|
343 |
|
|
tipd_adb12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
344 |
|
|
tipd_adb11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
345 |
|
|
tipd_adb10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
346 |
|
|
tipd_adb9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
347 |
|
|
tipd_adb8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
348 |
|
|
tipd_adb7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
349 |
|
|
tipd_adb6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
350 |
|
|
tipd_adb5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
351 |
|
|
tipd_adb4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
352 |
|
|
tipd_adb3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
353 |
|
|
tipd_adb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
354 |
|
|
tipd_adb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
355 |
|
|
tipd_adb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
356 |
|
|
tipd_dib17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
357 |
|
|
tipd_dib16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
358 |
|
|
tipd_dib15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
359 |
|
|
tipd_dib14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
360 |
|
|
tipd_dib13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
361 |
|
|
tipd_dib12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
362 |
|
|
tipd_dib11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
363 |
|
|
tipd_dib10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
364 |
|
|
tipd_dib9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
365 |
|
|
tipd_dib8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
366 |
|
|
tipd_dib7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
367 |
|
|
tipd_dib6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
368 |
|
|
tipd_dib5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
369 |
|
|
tipd_dib4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
370 |
|
|
tipd_dib3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
371 |
|
|
tipd_dib2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
372 |
|
|
tipd_dib1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
373 |
|
|
tipd_dib0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
374 |
|
|
tipd_clkb : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
375 |
|
|
tipd_ceb : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
376 |
|
|
tipd_web : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
377 |
|
|
tipd_csb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
378 |
|
|
tipd_csb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
379 |
|
|
tipd_csb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
380 |
|
|
tipd_rstb : VitalDelayType01 := (0.0 ns, 0.0 ns);
|
381 |
|
|
|
382 |
|
|
-- propagation delays
|
383 |
|
|
|
384 |
|
|
-- setup and hold constraints
|
385 |
|
|
|
386 |
|
|
-- pulse width constraints
|
387 |
|
|
tperiod_clka : VitalDelayType := 0.001 ns;
|
388 |
|
|
tpw_clka_posedge : VitalDelayType := 0.001 ns;
|
389 |
|
|
tpw_clka_negedge : VitalDelayType := 0.001 ns;
|
390 |
|
|
tperiod_clkb : VitalDelayType := 0.001 ns;
|
391 |
|
|
tpw_clkb_posedge : VitalDelayType := 0.001 ns;
|
392 |
|
|
tpw_clkb_negedge : VitalDelayType := 0.001 ns);
|
393 |
|
|
|
394 |
|
|
PORT(
|
395 |
|
|
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
|
396 |
|
|
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
|
397 |
|
|
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
|
398 |
|
|
ada9, ada10, ada11, ada12 : in std_logic := 'X';
|
399 |
|
|
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
|
400 |
|
|
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
|
401 |
|
|
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
|
402 |
|
|
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
|
403 |
|
|
adb9, adb10, adb11, adb12 : in std_logic := 'X';
|
404 |
|
|
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
|
405 |
|
|
|
406 |
|
|
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
|
407 |
|
|
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
|
408 |
|
|
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
|
409 |
|
|
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
|
410 |
|
|
);
|
411 |
|
|
|
412 |
|
|
ATTRIBUTE Vital_Level0 OF dp8ka : ENTITY IS TRUE;
|
413 |
|
|
|
414 |
|
|
END dp8ka ;
|
415 |
|
|
|
416 |
|
|
-- ARCHITECTURE body --
|
417 |
|
|
ARCHITECTURE V OF dp8ka IS
|
418 |
|
|
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
|
419 |
|
|
|
420 |
|
|
--SIGNAL DECLARATIONS----
|
421 |
|
|
|
422 |
|
|
SIGNAL ada_ipd : std_logic_vector(12 downto 0) := (others => '0');
|
423 |
|
|
SIGNAL dia_ipd : std_logic_vector(17 downto 0) := (others => '0');
|
424 |
|
|
SIGNAL clka_ipd : std_logic := '0';
|
425 |
|
|
SIGNAL cea_ipd : std_logic := '0';
|
426 |
|
|
SIGNAL wrea_ipd : std_logic := '0';
|
427 |
|
|
SIGNAL csa_ipd : std_logic_vector(2 downto 0) := "000";
|
428 |
|
|
SIGNAL rsta_ipd : std_logic := '0';
|
429 |
|
|
SIGNAL adb_ipd : std_logic_vector(12 downto 0) := "XXXXXXXXXXXXX";
|
430 |
|
|
SIGNAL dib_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
|
431 |
|
|
SIGNAL clkb_ipd : std_logic := '0';
|
432 |
|
|
SIGNAL ceb_ipd : std_logic := '0';
|
433 |
|
|
SIGNAL wreb_ipd : std_logic := '0';
|
434 |
|
|
SIGNAL csb_ipd : std_logic_vector(2 downto 0) := "000";
|
435 |
|
|
SIGNAL rstb_ipd : std_logic := '0';
|
436 |
|
|
SIGNAL csa_en : std_logic := '0';
|
437 |
|
|
SIGNAL csb_en : std_logic := '0';
|
438 |
|
|
SIGNAL g_reset : std_logic := '0';
|
439 |
|
|
CONSTANT ADDR_WIDTH_A : integer := data2addr_w(DATA_WIDTH_A);
|
440 |
|
|
CONSTANT ADDR_WIDTH_B : integer := data2addr_w(DATA_WIDTH_B);
|
441 |
|
|
CONSTANT new_data_width_a : integer := data2data_w(DATA_WIDTH_A);
|
442 |
|
|
CONSTANT new_data_width_b : integer := data2data_w(DATA_WIDTH_B);
|
443 |
|
|
CONSTANT div_a : integer := data2data(DATA_WIDTH_A);
|
444 |
|
|
CONSTANT div_b : integer := data2data(DATA_WIDTH_B);
|
445 |
|
|
SIGNAL dia_node : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
|
446 |
|
|
SIGNAL dib_node : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
|
447 |
|
|
SIGNAL ada_node : std_logic_vector((ADDR_WIDTH_A - 1) downto 0) := (others => '0');
|
448 |
|
|
SIGNAL adb_node : std_logic_vector((ADDR_WIDTH_B - 1) downto 0) := (others => '0');
|
449 |
|
|
SIGNAL diab_node : std_logic_vector(35 downto 0) := (others => '0');
|
450 |
|
|
SIGNAL rsta_int : std_logic := '0';
|
451 |
|
|
SIGNAL rstb_int : std_logic := '0';
|
452 |
|
|
SIGNAL rsta_reg : std_logic := '0';
|
453 |
|
|
SIGNAL rstb_reg : std_logic := '0';
|
454 |
|
|
SIGNAL reseta : std_logic := '0';
|
455 |
|
|
SIGNAL resetb : std_logic := '0';
|
456 |
|
|
SIGNAL dia_reg : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
|
457 |
|
|
SIGNAL dib_reg : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
|
458 |
|
|
SIGNAL ada_reg : std_logic_vector((ADDR_WIDTH_A - 1) downto 0);
|
459 |
|
|
SIGNAL adb_reg : std_logic_vector((ADDR_WIDTH_B - 1) downto 0);
|
460 |
|
|
SIGNAL diab_reg : std_logic_vector(35 downto 0) := (others => '0');
|
461 |
|
|
SIGNAL wrena_reg : std_logic := '0';
|
462 |
|
|
SIGNAL clka_valid : std_logic := '0';
|
463 |
|
|
SIGNAL clkb_valid : std_logic := '0';
|
464 |
|
|
SIGNAL clka_valid1 : std_logic := '0';
|
465 |
|
|
SIGNAL clkb_valid1 : std_logic := '0';
|
466 |
|
|
SIGNAL wrenb_reg : std_logic := '0';
|
467 |
|
|
SIGNAL rena_reg : std_logic := '0';
|
468 |
|
|
SIGNAL renb_reg : std_logic := '0';
|
469 |
|
|
SIGNAL rsta_sig : std_logic := '0';
|
470 |
|
|
SIGNAL rstb_sig : std_logic := '0';
|
471 |
|
|
SIGNAL doa_node : std_logic_vector(17 downto 0) := (others => '0');
|
472 |
|
|
SIGNAL doa_node_tr : std_logic_vector(17 downto 0) := (others => '0');
|
473 |
|
|
SIGNAL doa_node_wt : std_logic_vector(17 downto 0) := (others => '0');
|
474 |
|
|
SIGNAL doa_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
|
475 |
|
|
SIGNAL dob_node : std_logic_vector(17 downto 0) := (others => '0');
|
476 |
|
|
SIGNAL dob_node_tr : std_logic_vector(17 downto 0) := (others => '0');
|
477 |
|
|
SIGNAL dob_node_wt : std_logic_vector(17 downto 0) := (others => '0');
|
478 |
|
|
SIGNAL dob_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
|
479 |
|
|
SIGNAL doa_reg : std_logic_vector(17 downto 0) := (others => '0');
|
480 |
|
|
SIGNAL dob_reg : std_logic_vector(17 downto 0) := (others => '0');
|
481 |
|
|
SIGNAL doab_reg : std_logic_vector(17 downto 0) := (others => '0');
|
482 |
|
|
SIGNAL doa_int : std_logic_vector(17 downto 0) := (others => '0');
|
483 |
|
|
SIGNAL dob_int : std_logic_vector(17 downto 0) := (others => '0');
|
484 |
|
|
|
485 |
|
|
CONSTANT initval : string(2560 downto 1) := (
|
486 |
|
|
initval_1f(3 to 82)&initval_1e(3 to 82)&initval_1d(3 to 82)&initval_1c(3 to 82)&
|
487 |
|
|
initval_1b(3 to 82)&initval_1a(3 to 82)&initval_19(3 to 82)&initval_18(3 to 82)&
|
488 |
|
|
initval_17(3 to 82)&initval_16(3 to 82)&initval_15(3 to 82)&initval_14(3 to 82)&
|
489 |
|
|
initval_13(3 to 82)&initval_12(3 to 82)&initval_11(3 to 82)&initval_10(3 to 82)&
|
490 |
|
|
initval_0f(3 to 82)&initval_0e(3 to 82)&initval_0d(3 to 82)&initval_0c(3 to 82)&
|
491 |
|
|
initval_0b(3 to 82)&initval_0a(3 to 82)&initval_09(3 to 82)&initval_08(3 to 82)&
|
492 |
|
|
initval_07(3 to 82)&initval_06(3 to 82)&initval_05(3 to 82)&initval_04(3 to 82)&
|
493 |
|
|
initval_03(3 to 82)&initval_02(3 to 82)&initval_01(3 to 82)&initval_00(3 to 82));
|
494 |
|
|
SIGNAL MEM : std_logic_vector(9215 downto 0) := init_ram (initval, DATA_WIDTH_A, DATA_WIDTH_B);
|
495 |
|
|
SIGNAL j : integer := 0;
|
496 |
|
|
BEGIN
|
497 |
|
|
|
498 |
|
|
-----------------------
|
499 |
|
|
-- input path delays
|
500 |
|
|
-----------------------
|
501 |
|
|
WireDelay : BLOCK
|
502 |
|
|
BEGIN
|
503 |
|
|
VitalWireDelay(ada_ipd(0), ada0, tipd_ada0);
|
504 |
|
|
VitalWireDelay(ada_ipd(1), ada1, tipd_ada1);
|
505 |
|
|
VitalWireDelay(ada_ipd(2), ada2, tipd_ada2);
|
506 |
|
|
VitalWireDelay(ada_ipd(3), ada3, tipd_ada3);
|
507 |
|
|
VitalWireDelay(ada_ipd(4), ada4, tipd_ada4);
|
508 |
|
|
VitalWireDelay(ada_ipd(5), ada5, tipd_ada5);
|
509 |
|
|
VitalWireDelay(ada_ipd(6), ada6, tipd_ada6);
|
510 |
|
|
VitalWireDelay(ada_ipd(7), ada7, tipd_ada7);
|
511 |
|
|
VitalWireDelay(ada_ipd(8), ada8, tipd_ada8);
|
512 |
|
|
VitalWireDelay(ada_ipd(9), ada9, tipd_ada9);
|
513 |
|
|
VitalWireDelay(ada_ipd(10), ada10, tipd_ada10);
|
514 |
|
|
VitalWireDelay(ada_ipd(11), ada11, tipd_ada11);
|
515 |
|
|
VitalWireDelay(ada_ipd(12), ada12, tipd_ada12);
|
516 |
|
|
VitalWireDelay(dia_ipd(0), dia0, tipd_dia0);
|
517 |
|
|
VitalWireDelay(dia_ipd(1), dia1, tipd_dia1);
|
518 |
|
|
VitalWireDelay(dia_ipd(2), dia2, tipd_dia2);
|
519 |
|
|
VitalWireDelay(dia_ipd(3), dia3, tipd_dia3);
|
520 |
|
|
VitalWireDelay(dia_ipd(4), dia4, tipd_dia4);
|
521 |
|
|
VitalWireDelay(dia_ipd(5), dia5, tipd_dia5);
|
522 |
|
|
VitalWireDelay(dia_ipd(6), dia6, tipd_dia6);
|
523 |
|
|
VitalWireDelay(dia_ipd(7), dia7, tipd_dia7);
|
524 |
|
|
VitalWireDelay(dia_ipd(8), dia8, tipd_dia8);
|
525 |
|
|
VitalWireDelay(dia_ipd(9), dia9, tipd_dia9);
|
526 |
|
|
VitalWireDelay(dia_ipd(10), dia10, tipd_dia10);
|
527 |
|
|
VitalWireDelay(dia_ipd(11), dia11, tipd_dia11);
|
528 |
|
|
VitalWireDelay(dia_ipd(12), dia12, tipd_dia12);
|
529 |
|
|
VitalWireDelay(dia_ipd(13), dia13, tipd_dia13);
|
530 |
|
|
VitalWireDelay(dia_ipd(14), dia14, tipd_dia14);
|
531 |
|
|
VitalWireDelay(dia_ipd(15), dia15, tipd_dia15);
|
532 |
|
|
VitalWireDelay(dia_ipd(16), dia16, tipd_dia16);
|
533 |
|
|
VitalWireDelay(dia_ipd(17), dia17, tipd_dia17);
|
534 |
|
|
VitalWireDelay(clka_ipd, clka, tipd_clka);
|
535 |
|
|
VitalWireDelay(wrea_ipd, wea, tipd_wea);
|
536 |
|
|
VitalWireDelay(cea_ipd, cea, tipd_cea);
|
537 |
|
|
VitalWireDelay(csa_ipd(0), csa0, tipd_csa0);
|
538 |
|
|
VitalWireDelay(csa_ipd(1), csa1, tipd_csa1);
|
539 |
|
|
VitalWireDelay(csa_ipd(2), csa2, tipd_csa2);
|
540 |
|
|
VitalWireDelay(rsta_ipd, rsta, tipd_rsta);
|
541 |
|
|
VitalWireDelay(adb_ipd(0), adb0, tipd_adb0);
|
542 |
|
|
VitalWireDelay(adb_ipd(1), adb1, tipd_adb1);
|
543 |
|
|
VitalWireDelay(adb_ipd(2), adb2, tipd_adb2);
|
544 |
|
|
VitalWireDelay(adb_ipd(3), adb3, tipd_adb3);
|
545 |
|
|
VitalWireDelay(adb_ipd(4), adb4, tipd_adb4);
|
546 |
|
|
VitalWireDelay(adb_ipd(5), adb5, tipd_adb5);
|
547 |
|
|
VitalWireDelay(adb_ipd(6), adb6, tipd_adb6);
|
548 |
|
|
VitalWireDelay(adb_ipd(7), adb7, tipd_adb7);
|
549 |
|
|
VitalWireDelay(adb_ipd(8), adb8, tipd_adb8);
|
550 |
|
|
VitalWireDelay(adb_ipd(9), adb9, tipd_adb9);
|
551 |
|
|
VitalWireDelay(adb_ipd(10), adb10, tipd_adb10);
|
552 |
|
|
VitalWireDelay(adb_ipd(11), adb11, tipd_adb11);
|
553 |
|
|
VitalWireDelay(adb_ipd(12), adb12, tipd_adb12);
|
554 |
|
|
VitalWireDelay(dib_ipd(0), dib0, tipd_dib0);
|
555 |
|
|
VitalWireDelay(dib_ipd(1), dib1, tipd_dib1);
|
556 |
|
|
VitalWireDelay(dib_ipd(2), dib2, tipd_dib2);
|
557 |
|
|
VitalWireDelay(dib_ipd(3), dib3, tipd_dib3);
|
558 |
|
|
VitalWireDelay(dib_ipd(4), dib4, tipd_dib4);
|
559 |
|
|
VitalWireDelay(dib_ipd(5), dib5, tipd_dib5);
|
560 |
|
|
VitalWireDelay(dib_ipd(6), dib6, tipd_dib6);
|
561 |
|
|
VitalWireDelay(dib_ipd(7), dib7, tipd_dib7);
|
562 |
|
|
VitalWireDelay(dib_ipd(8), dib8, tipd_dib8);
|
563 |
|
|
VitalWireDelay(dib_ipd(9), dib9, tipd_dib9);
|
564 |
|
|
VitalWireDelay(dib_ipd(10), dib10, tipd_dib10);
|
565 |
|
|
VitalWireDelay(dib_ipd(11), dib11, tipd_dib11);
|
566 |
|
|
VitalWireDelay(dib_ipd(12), dib12, tipd_dib12);
|
567 |
|
|
VitalWireDelay(dib_ipd(13), dib13, tipd_dib13);
|
568 |
|
|
VitalWireDelay(dib_ipd(14), dib14, tipd_dib14);
|
569 |
|
|
VitalWireDelay(dib_ipd(15), dib15, tipd_dib15);
|
570 |
|
|
VitalWireDelay(dib_ipd(16), dib16, tipd_dib16);
|
571 |
|
|
VitalWireDelay(dib_ipd(17), dib17, tipd_dib17);
|
572 |
|
|
VitalWireDelay(clkb_ipd, clkb, tipd_clkb);
|
573 |
|
|
VitalWireDelay(wreb_ipd, web, tipd_web);
|
574 |
|
|
VitalWireDelay(ceb_ipd, ceb, tipd_ceb);
|
575 |
|
|
VitalWireDelay(csb_ipd(0), csb0, tipd_csb0);
|
576 |
|
|
VitalWireDelay(csb_ipd(1), csb1, tipd_csb1);
|
577 |
|
|
VitalWireDelay(csb_ipd(2), csb2, tipd_csb2);
|
578 |
|
|
VitalWireDelay(rstb_ipd, rstb, tipd_rstb);
|
579 |
|
|
END BLOCK;
|
580 |
|
|
|
581 |
|
|
GLOBALRESET : PROCESS (purnet, gsrnet)
|
582 |
|
|
BEGIN
|
583 |
|
|
IF (GSR = "DISABLED") THEN
|
584 |
|
|
g_reset <= purnet;
|
585 |
|
|
ELSE
|
586 |
|
|
g_reset <= purnet AND gsrnet;
|
587 |
|
|
END IF;
|
588 |
|
|
END PROCESS;
|
589 |
|
|
|
590 |
|
|
rsta_sig <= rsta_ipd or (not g_reset);
|
591 |
|
|
rstb_sig <= rstb_ipd or (not g_reset);
|
592 |
|
|
|
593 |
|
|
-- set_reset <= g_reset and (not reset_ipd);
|
594 |
|
|
ada_node <= ada_ipd(12 downto (13 - ADDR_WIDTH_A));
|
595 |
|
|
adb_node <= adb_ipd(12 downto (13 - ADDR_WIDTH_B));
|
596 |
|
|
|
597 |
|
|
-- chip select A decode
|
598 |
|
|
P1 : PROCESS(csa_ipd)
|
599 |
|
|
BEGIN
|
600 |
|
|
IF (csa_ipd = "000" and CSDECODE_A = "000") THEN
|
601 |
|
|
csa_en <= '1';
|
602 |
|
|
ELSIF (csa_ipd = "001" and CSDECODE_A = "001") THEN
|
603 |
|
|
csa_en <= '1';
|
604 |
|
|
ELSIF (csa_ipd = "010" and CSDECODE_A = "010") THEN
|
605 |
|
|
csa_en <= '1';
|
606 |
|
|
ELSIF (csa_ipd = "011" and CSDECODE_A = "011") THEN
|
607 |
|
|
csa_en <= '1';
|
608 |
|
|
ELSIF (csa_ipd = "100" and CSDECODE_A = "100") THEN
|
609 |
|
|
csa_en <= '1';
|
610 |
|
|
ELSIF (csa_ipd = "101" and CSDECODE_A = "101") THEN
|
611 |
|
|
csa_en <= '1';
|
612 |
|
|
ELSIF (csa_ipd = "110" and CSDECODE_A = "110") THEN
|
613 |
|
|
csa_en <= '1';
|
614 |
|
|
ELSIF (csa_ipd = "111" and CSDECODE_A = "111") THEN
|
615 |
|
|
csa_en <= '1';
|
616 |
|
|
ELSE
|
617 |
|
|
csa_en <= '0';
|
618 |
|
|
END IF;
|
619 |
|
|
END PROCESS;
|
620 |
|
|
|
621 |
|
|
P2 : PROCESS(csb_ipd)
|
622 |
|
|
BEGIN
|
623 |
|
|
IF (csb_ipd = "000" and CSDECODE_B = "000") THEN
|
624 |
|
|
csb_en <= '1';
|
625 |
|
|
ELSIF (csb_ipd = "001" and CSDECODE_B = "001") THEN
|
626 |
|
|
csb_en <= '1';
|
627 |
|
|
ELSIF (csb_ipd = "010" and CSDECODE_B = "010") THEN
|
628 |
|
|
csb_en <= '1';
|
629 |
|
|
ELSIF (csb_ipd = "011" and CSDECODE_B = "011") THEN
|
630 |
|
|
csb_en <= '1';
|
631 |
|
|
ELSIF (csb_ipd = "100" and CSDECODE_B = "100") THEN
|
632 |
|
|
csb_en <= '1';
|
633 |
|
|
ELSIF (csb_ipd = "101" and CSDECODE_B = "101") THEN
|
634 |
|
|
csb_en <= '1';
|
635 |
|
|
ELSIF (csb_ipd = "110" and CSDECODE_B = "110") THEN
|
636 |
|
|
csb_en <= '1';
|
637 |
|
|
ELSIF (csb_ipd = "111" and CSDECODE_B = "111") THEN
|
638 |
|
|
csb_en <= '1';
|
639 |
|
|
ELSE
|
640 |
|
|
csb_en <= '0';
|
641 |
|
|
END IF;
|
642 |
|
|
END PROCESS;
|
643 |
|
|
|
644 |
|
|
P3 : PROCESS(dia_ipd)
|
645 |
|
|
BEGIN
|
646 |
|
|
CASE DATA_WIDTH_A IS
|
647 |
|
|
WHEN 1 =>
|
648 |
|
|
dia_node <= dia_ipd(11 downto 11);
|
649 |
|
|
WHEN 2 =>
|
650 |
|
|
dia_node <= (dia_ipd(1), dia_ipd(11));
|
651 |
|
|
WHEN 4 =>
|
652 |
|
|
dia_node <= dia_ipd(3 downto 0);
|
653 |
|
|
WHEN 9 =>
|
654 |
|
|
dia_node <= dia_ipd(8 downto 0);
|
655 |
|
|
WHEN 18 =>
|
656 |
|
|
dia_node <= dia_ipd;
|
657 |
|
|
WHEN 36 =>
|
658 |
|
|
dia_node <= dia_ipd;
|
659 |
|
|
WHEN others =>
|
660 |
|
|
NULL;
|
661 |
|
|
END CASE;
|
662 |
|
|
END PROCESS;
|
663 |
|
|
|
664 |
|
|
P4 : PROCESS(dib_ipd)
|
665 |
|
|
BEGIN
|
666 |
|
|
CASE DATA_WIDTH_B IS
|
667 |
|
|
WHEN 1 =>
|
668 |
|
|
dib_node <= dib_ipd(11 downto 11);
|
669 |
|
|
WHEN 2 =>
|
670 |
|
|
dib_node <= (dib_ipd(1), dib_ipd(11));
|
671 |
|
|
WHEN 4 =>
|
672 |
|
|
dib_node <= dib_ipd(3 downto 0);
|
673 |
|
|
WHEN 9 =>
|
674 |
|
|
dib_node <= dib_ipd(8 downto 0);
|
675 |
|
|
WHEN 18 =>
|
676 |
|
|
dib_node <= dib_ipd;
|
677 |
|
|
WHEN 36 =>
|
678 |
|
|
dib_node <= dib_ipd;
|
679 |
|
|
WHEN others =>
|
680 |
|
|
NULL;
|
681 |
|
|
END CASE;
|
682 |
|
|
END PROCESS;
|
683 |
|
|
|
684 |
|
|
diab_node <= (dib_ipd & dia_ipd);
|
685 |
|
|
|
686 |
|
|
P107 : PROCESS(clka_ipd)
|
687 |
|
|
BEGIN
|
688 |
|
|
IF (clka_ipd'event and clka_ipd = '1' and clka_ipd'last_value = '0') THEN
|
689 |
|
|
IF ((g_reset = '0') or (rsta_ipd = '1')) THEN
|
690 |
|
|
clka_valid <= '0';
|
691 |
|
|
ELSE
|
692 |
|
|
IF (cea_ipd = '1') THEN
|
693 |
|
|
IF (csa_en = '1') THEN
|
694 |
|
|
clka_valid <= '1', '0' after 0.01 ns;
|
695 |
|
|
ELSE
|
696 |
|
|
clka_valid <= '0';
|
697 |
|
|
END IF;
|
698 |
|
|
ELSE
|
699 |
|
|
clka_valid <= '0';
|
700 |
|
|
END IF;
|
701 |
|
|
END IF;
|
702 |
|
|
END IF;
|
703 |
|
|
END PROCESS;
|
704 |
|
|
|
705 |
|
|
P108 : PROCESS(clkb_ipd)
|
706 |
|
|
BEGIN
|
707 |
|
|
IF (clkb_ipd'event and clkb_ipd = '1' and clkb_ipd'last_value = '0') THEN
|
708 |
|
|
IF ((g_reset = '0') or (rstb_ipd = '1')) THEN
|
709 |
|
|
clkb_valid <= '0';
|
710 |
|
|
ELSE
|
711 |
|
|
IF (ceb_ipd = '1') THEN
|
712 |
|
|
IF (csb_en = '1') THEN
|
713 |
|
|
clkb_valid <= '1', '0' after 0.01 ns;
|
714 |
|
|
ELSE
|
715 |
|
|
clkb_valid <= '0';
|
716 |
|
|
END IF;
|
717 |
|
|
ELSE
|
718 |
|
|
clkb_valid <= '0';
|
719 |
|
|
END IF;
|
720 |
|
|
END IF;
|
721 |
|
|
END IF;
|
722 |
|
|
END PROCESS;
|
723 |
|
|
|
724 |
|
|
clka_valid1 <= clka_valid;
|
725 |
|
|
clkb_valid1 <= clkb_valid;
|
726 |
|
|
|
727 |
|
|
P7 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
|
728 |
|
|
BEGIN
|
729 |
|
|
IF (g_reset = '0') THEN
|
730 |
|
|
dia_reg <= (others => '0');
|
731 |
|
|
diab_reg <= (others => '0');
|
732 |
|
|
ada_reg <= (others => '0');
|
733 |
|
|
wrena_reg <= '0';
|
734 |
|
|
rena_reg <= '0';
|
735 |
|
|
ELSIF (RESETMODE = "ASYNC") THEN
|
736 |
|
|
IF (rsta_ipd = '1') THEN
|
737 |
|
|
dia_reg <= (others => '0');
|
738 |
|
|
diab_reg <= (others => '0');
|
739 |
|
|
ada_reg <= (others => '0');
|
740 |
|
|
wrena_reg <= '0';
|
741 |
|
|
rena_reg <= '0';
|
742 |
|
|
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
|
743 |
|
|
IF (cea_ipd = '1') THEN
|
744 |
|
|
dia_reg <= dia_node;
|
745 |
|
|
diab_reg <= diab_node;
|
746 |
|
|
ada_reg <= ada_node;
|
747 |
|
|
wrena_reg <= (wrea_ipd and csa_en);
|
748 |
|
|
rena_reg <= ((not wrea_ipd) and csa_en);
|
749 |
|
|
END IF;
|
750 |
|
|
END IF;
|
751 |
|
|
ELSIF (RESETMODE = "SYNC") THEN
|
752 |
|
|
IF (clka_ipd'event and clka_ipd = '1') THEN
|
753 |
|
|
IF (rsta_ipd = '1') THEN
|
754 |
|
|
dia_reg <= (others => '0');
|
755 |
|
|
diab_reg <= (others => '0');
|
756 |
|
|
ada_reg <= (others => '0');
|
757 |
|
|
wrena_reg <= '0';
|
758 |
|
|
rena_reg <= '0';
|
759 |
|
|
ELSIF (cea_ipd = '1') THEN
|
760 |
|
|
dia_reg <= dia_node;
|
761 |
|
|
diab_reg <= diab_node;
|
762 |
|
|
ada_reg <= ada_node;
|
763 |
|
|
wrena_reg <= (wrea_ipd and csa_en);
|
764 |
|
|
rena_reg <= ((not wrea_ipd) and csa_en);
|
765 |
|
|
END IF;
|
766 |
|
|
END IF;
|
767 |
|
|
END IF;
|
768 |
|
|
|
769 |
|
|
IF (g_reset = '0') THEN
|
770 |
|
|
dib_reg <= (others => '0');
|
771 |
|
|
adb_reg <= (others => '0');
|
772 |
|
|
wrenb_reg <= '0';
|
773 |
|
|
renb_reg <= '0';
|
774 |
|
|
ELSIF (RESETMODE = "ASYNC") THEN
|
775 |
|
|
IF (rstb_ipd = '1') THEN
|
776 |
|
|
dib_reg <= (others => '0');
|
777 |
|
|
adb_reg <= (others => '0');
|
778 |
|
|
wrenb_reg <= '0';
|
779 |
|
|
renb_reg <= '0';
|
780 |
|
|
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
|
781 |
|
|
IF (ceb_ipd = '1') THEN
|
782 |
|
|
dib_reg <= dib_node;
|
783 |
|
|
adb_reg <= adb_node;
|
784 |
|
|
wrenb_reg <= (wreb_ipd and csb_en);
|
785 |
|
|
renb_reg <= ((not wreb_ipd) and csb_en);
|
786 |
|
|
END IF;
|
787 |
|
|
END IF;
|
788 |
|
|
ELSIF (RESETMODE = "SYNC") THEN
|
789 |
|
|
IF (clkb_ipd'event and clkb_ipd = '1') THEN
|
790 |
|
|
IF (rstb_ipd = '1') THEN
|
791 |
|
|
dib_reg <= (others => '0');
|
792 |
|
|
adb_reg <= (others => '0');
|
793 |
|
|
wrenb_reg <= '0';
|
794 |
|
|
renb_reg <= '0';
|
795 |
|
|
ELSIF (ceb_ipd = '1') THEN
|
796 |
|
|
dib_reg <= dib_node;
|
797 |
|
|
adb_reg <= adb_node;
|
798 |
|
|
wrenb_reg <= (wreb_ipd and csb_en);
|
799 |
|
|
renb_reg <= ((not wreb_ipd) and csb_en);
|
800 |
|
|
END IF;
|
801 |
|
|
END IF;
|
802 |
|
|
END IF;
|
803 |
|
|
END PROCESS;
|
804 |
|
|
|
805 |
|
|
-- Warning for collision
|
806 |
|
|
|
807 |
|
|
PW : PROCESS(ada_reg, adb_reg, wrena_reg, wrenb_reg, clka_valid, clkb_valid, rena_reg,
|
808 |
|
|
renb_reg)
|
809 |
|
|
VARIABLE WADDR_A_VALID : boolean := TRUE;
|
810 |
|
|
VARIABLE WADDR_B_VALID : boolean := TRUE;
|
811 |
|
|
VARIABLE ADDR_A : integer := 0;
|
812 |
|
|
VARIABLE ADDR_B : integer := 0;
|
813 |
|
|
VARIABLE DN_ADDR_A : integer := 0;
|
814 |
|
|
VARIABLE UP_ADDR_A : integer := 0;
|
815 |
|
|
VARIABLE DN_ADDR_B : integer := 0;
|
816 |
|
|
VARIABLE UP_ADDR_B : integer := 0;
|
817 |
|
|
BEGIN
|
818 |
|
|
WADDR_A_VALID := Valid_Address (ada_reg);
|
819 |
|
|
WADDR_B_VALID := Valid_Address (adb_reg);
|
820 |
|
|
|
821 |
|
|
IF (WADDR_A_VALID = TRUE) THEN
|
822 |
|
|
ADDR_A := conv_integer(ada_reg);
|
823 |
|
|
END IF;
|
824 |
|
|
IF (WADDR_B_VALID = TRUE) THEN
|
825 |
|
|
ADDR_B := conv_integer(adb_reg);
|
826 |
|
|
END IF;
|
827 |
|
|
|
828 |
|
|
DN_ADDR_A := (ADDR_A * DATA_WIDTH_A);
|
829 |
|
|
UP_ADDR_A := (((ADDR_A + 1) * DATA_WIDTH_A) - 1);
|
830 |
|
|
DN_ADDR_B := (ADDR_B * DATA_WIDTH_B);
|
831 |
|
|
UP_ADDR_B := (((ADDR_B + 1) * DATA_WIDTH_B) - 1);
|
832 |
|
|
|
833 |
|
|
IF ((wrena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
|
834 |
|
|
IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
|
835 |
|
|
assert false
|
836 |
|
|
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
|
837 |
|
|
severity error;
|
838 |
|
|
END IF;
|
839 |
|
|
END IF;
|
840 |
|
|
|
841 |
|
|
-- IF ((wrena_reg = '1' and clka_valid = '1') and (renb_reg = '1' and clkb_valid = '1')) THEN
|
842 |
|
|
-- IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
|
843 |
|
|
-- assert false
|
844 |
|
|
-- report " Write/Read collision! Writing through Port A and reading through Port B from the same memory location may give wrong output."
|
845 |
|
|
-- severity warning;
|
846 |
|
|
-- END IF;
|
847 |
|
|
-- END IF;
|
848 |
|
|
|
849 |
|
|
-- IF ((rena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
|
850 |
|
|
-- IF (not((UP_ADDR_A <= DN_ADDR_B) or (DN_ADDR_A >= UP_ADDR_B))) THEN
|
851 |
|
|
-- assert false
|
852 |
|
|
-- report " Write/Read collision! Writing through Port B and reading through Port A from the same memory location may give wrong output."
|
853 |
|
|
-- severity warning;
|
854 |
|
|
-- END IF;
|
855 |
|
|
-- END IF;
|
856 |
|
|
END PROCESS;
|
857 |
|
|
|
858 |
|
|
|
859 |
|
|
|
860 |
|
|
-- Writing to the memory
|
861 |
|
|
|
862 |
|
|
P8 : PROCESS(ada_reg, dia_reg, diab_reg, wrena_reg, dib_reg, adb_reg,
|
863 |
|
|
wrenb_reg, clka_valid, clkb_valid)
|
864 |
|
|
VARIABLE WADDR_A_VALID : boolean := TRUE;
|
865 |
|
|
VARIABLE WADDR_B_VALID : boolean := TRUE;
|
866 |
|
|
VARIABLE WADDR_A : integer := 0;
|
867 |
|
|
VARIABLE WADDR_B : integer := 0;
|
868 |
|
|
VARIABLE dout_node_rbr : std_logic_vector(35 downto 0);
|
869 |
|
|
BEGIN
|
870 |
|
|
WADDR_A_VALID := Valid_Address (ada_reg);
|
871 |
|
|
WADDR_B_VALID := Valid_Address (adb_reg);
|
872 |
|
|
|
873 |
|
|
IF (WADDR_A_VALID = TRUE) THEN
|
874 |
|
|
WADDR_A := conv_integer(ada_reg);
|
875 |
|
|
END IF;
|
876 |
|
|
IF (WADDR_B_VALID = TRUE) THEN
|
877 |
|
|
WADDR_B := conv_integer(adb_reg);
|
878 |
|
|
END IF;
|
879 |
|
|
|
880 |
|
|
IF (DATA_WIDTH_A = 36) THEN
|
881 |
|
|
IF (wrena_reg = '1' and clka_valid = '1') THEN
|
882 |
|
|
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
|
883 |
|
|
dout_node_rbr(i) := MEM((WADDR_A * DATA_WIDTH_A) + i);
|
884 |
|
|
END LOOP;
|
885 |
|
|
doa_node_rbr <= dout_node_rbr(17 downto 0);
|
886 |
|
|
dob_node_rbr <= dout_node_rbr(35 downto 18);
|
887 |
|
|
|
888 |
|
|
FOR i IN 0 TO 8 LOOP
|
889 |
|
|
MEM((WADDR_A * DATA_WIDTH_A) + i) <= diab_reg(i);
|
890 |
|
|
END LOOP;
|
891 |
|
|
|
892 |
|
|
FOR i IN 0 TO 8 LOOP
|
893 |
|
|
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= diab_reg(i + 9);
|
894 |
|
|
END LOOP;
|
895 |
|
|
|
896 |
|
|
FOR i IN 0 TO 8 LOOP
|
897 |
|
|
MEM((WADDR_A * DATA_WIDTH_A) + i + 18) <= diab_reg(i + 18);
|
898 |
|
|
END LOOP;
|
899 |
|
|
|
900 |
|
|
FOR i IN 0 TO 8 LOOP
|
901 |
|
|
MEM((WADDR_A * DATA_WIDTH_A) + i + 27) <= diab_reg(i + 27);
|
902 |
|
|
END LOOP;
|
903 |
|
|
END IF;
|
904 |
|
|
ELSE
|
905 |
|
|
IF (DATA_WIDTH_A = 18) THEN
|
906 |
|
|
IF (wrena_reg = '1' and clka_valid = '1') THEN
|
907 |
|
|
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
|
908 |
|
|
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
|
909 |
|
|
END LOOP;
|
910 |
|
|
|
911 |
|
|
FOR i IN 0 TO 8 LOOP
|
912 |
|
|
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
|
913 |
|
|
END LOOP;
|
914 |
|
|
|
915 |
|
|
FOR i IN 0 TO 8 LOOP
|
916 |
|
|
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= dia_reg(i + 9);
|
917 |
|
|
END LOOP;
|
918 |
|
|
END IF;
|
919 |
|
|
ELSIF (DATA_WIDTH_A = 9) THEN
|
920 |
|
|
IF (wrena_reg = '1' and clka_valid = '1') THEN
|
921 |
|
|
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
|
922 |
|
|
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
|
923 |
|
|
END LOOP;
|
924 |
|
|
|
925 |
|
|
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
|
926 |
|
|
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
|
927 |
|
|
END LOOP;
|
928 |
|
|
END IF;
|
929 |
|
|
ELSE
|
930 |
|
|
IF (wrena_reg = '1' and clka_valid = '1') THEN
|
931 |
|
|
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
|
932 |
|
|
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
|
933 |
|
|
END LOOP;
|
934 |
|
|
|
935 |
|
|
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
|
936 |
|
|
MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i) <= dia_reg(i);
|
937 |
|
|
END LOOP;
|
938 |
|
|
END IF;
|
939 |
|
|
END IF;
|
940 |
|
|
|
941 |
|
|
IF (DATA_WIDTH_B = 18) THEN
|
942 |
|
|
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
|
943 |
|
|
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
|
944 |
|
|
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
|
945 |
|
|
END LOOP;
|
946 |
|
|
|
947 |
|
|
FOR i IN 0 TO 8 LOOP
|
948 |
|
|
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
|
949 |
|
|
END LOOP;
|
950 |
|
|
|
951 |
|
|
FOR i IN 0 TO 8 LOOP
|
952 |
|
|
MEM((WADDR_B * DATA_WIDTH_B) + i + 9) <= dib_reg(i + 9);
|
953 |
|
|
END LOOP;
|
954 |
|
|
END IF;
|
955 |
|
|
ELSIF (DATA_WIDTH_B = 9) THEN
|
956 |
|
|
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
|
957 |
|
|
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
|
958 |
|
|
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
|
959 |
|
|
END LOOP;
|
960 |
|
|
|
961 |
|
|
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
|
962 |
|
|
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
|
963 |
|
|
END LOOP;
|
964 |
|
|
END IF;
|
965 |
|
|
ELSE
|
966 |
|
|
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
|
967 |
|
|
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
|
968 |
|
|
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
|
969 |
|
|
END LOOP;
|
970 |
|
|
|
971 |
|
|
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
|
972 |
|
|
MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i) <= dib_reg(i);
|
973 |
|
|
END LOOP;
|
974 |
|
|
END IF;
|
975 |
|
|
END IF;
|
976 |
|
|
END IF;
|
977 |
|
|
END PROCESS;
|
978 |
|
|
|
979 |
|
|
P9 : PROCESS(ada_reg, rena_reg, adb_reg, renb_reg, MEM, clka_valid1, clkb_valid1, rsta_sig, rstb_sig, doa_node_rbr, dob_node_rbr)
|
980 |
|
|
VARIABLE RADDR_A_VALID : boolean := TRUE;
|
981 |
|
|
VARIABLE RADDR_B_VALID : boolean := TRUE;
|
982 |
|
|
VARIABLE RADDR_A : integer := 0;
|
983 |
|
|
VARIABLE RADDR_B : integer := 0;
|
984 |
|
|
VARIABLE dout_node_tr : std_logic_vector(35 downto 0);
|
985 |
|
|
VARIABLE dout_node_wt : std_logic_vector(35 downto 0);
|
986 |
|
|
BEGIN
|
987 |
|
|
RADDR_A_VALID := Valid_Address (ada_reg);
|
988 |
|
|
RADDR_B_VALID := Valid_Address (adb_reg);
|
989 |
|
|
|
990 |
|
|
IF (RADDR_A_VALID = TRUE) THEN
|
991 |
|
|
RADDR_A := conv_integer(ada_reg);
|
992 |
|
|
END IF;
|
993 |
|
|
IF (RADDR_B_VALID = TRUE) THEN
|
994 |
|
|
RADDR_B := conv_integer(adb_reg);
|
995 |
|
|
END IF;
|
996 |
|
|
|
997 |
|
|
IF (DATA_WIDTH_B = 36) THEN
|
998 |
|
|
IF (rstb_sig = '1') THEN
|
999 |
|
|
IF (RESETMODE = "SYNC") THEN
|
1000 |
|
|
IF (clkb_ipd = '1') THEN
|
1001 |
|
|
doa_node <= (others => '0');
|
1002 |
|
|
dob_node <= (others => '0');
|
1003 |
|
|
END IF;
|
1004 |
|
|
ELSIF (RESETMODE = "ASYNC") THEN
|
1005 |
|
|
doa_node <= (others => '0');
|
1006 |
|
|
dob_node <= (others => '0');
|
1007 |
|
|
END IF;
|
1008 |
|
|
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
|
1009 |
|
|
IF (renb_reg = '1') THEN
|
1010 |
|
|
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
|
1011 |
|
|
dout_node_tr(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
|
1012 |
|
|
END LOOP;
|
1013 |
|
|
doa_node <= dout_node_tr(17 downto 0);
|
1014 |
|
|
dob_node <= dout_node_tr(35 downto 18);
|
1015 |
|
|
ELSIF (renb_reg = '0') THEN
|
1016 |
|
|
IF (WRITEMODE_B = "WRITETHROUGH") THEN
|
1017 |
|
|
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
|
1018 |
|
|
dout_node_wt(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
|
1019 |
|
|
END LOOP;
|
1020 |
|
|
doa_node <= dout_node_wt(17 downto 0);
|
1021 |
|
|
dob_node <= dout_node_wt(35 downto 18);
|
1022 |
|
|
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
|
1023 |
|
|
doa_node <= doa_node_rbr;
|
1024 |
|
|
dob_node <= dob_node_rbr;
|
1025 |
|
|
END IF;
|
1026 |
|
|
END IF;
|
1027 |
|
|
END IF;
|
1028 |
|
|
ELSE
|
1029 |
|
|
IF (rsta_sig = '1') THEN
|
1030 |
|
|
IF (RESETMODE = "SYNC") THEN
|
1031 |
|
|
IF (clka_ipd = '1') THEN
|
1032 |
|
|
doa_node <= (others => '0');
|
1033 |
|
|
END IF;
|
1034 |
|
|
ELSIF (RESETMODE = "ASYNC") THEN
|
1035 |
|
|
doa_node <= (others => '0');
|
1036 |
|
|
END IF;
|
1037 |
|
|
ELSIF (clka_valid1'event and clka_valid1 = '1') THEN
|
1038 |
|
|
IF (rena_reg = '1') THEN
|
1039 |
|
|
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
|
1040 |
|
|
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
|
1041 |
|
|
END LOOP;
|
1042 |
|
|
ELSIF (rena_reg = '0') THEN
|
1043 |
|
|
IF (WRITEMODE_A = "WRITETHROUGH") THEN
|
1044 |
|
|
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
|
1045 |
|
|
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
|
1046 |
|
|
END LOOP;
|
1047 |
|
|
ELSIF (WRITEMODE_A = "READBEFOREWRITE") THEN
|
1048 |
|
|
doa_node <= doa_node_rbr;
|
1049 |
|
|
END IF;
|
1050 |
|
|
END IF;
|
1051 |
|
|
END IF;
|
1052 |
|
|
|
1053 |
|
|
IF (rstb_sig = '1') THEN
|
1054 |
|
|
IF (RESETMODE = "SYNC") THEN
|
1055 |
|
|
IF (clkb_ipd = '1') THEN
|
1056 |
|
|
dob_node <= (others => '0');
|
1057 |
|
|
END IF;
|
1058 |
|
|
ELSIF (RESETMODE = "ASYNC") THEN
|
1059 |
|
|
dob_node <= (others => '0');
|
1060 |
|
|
END IF;
|
1061 |
|
|
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
|
1062 |
|
|
IF (renb_reg = '1') THEN
|
1063 |
|
|
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
|
1064 |
|
|
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
|
1065 |
|
|
END LOOP;
|
1066 |
|
|
ELSIF (renb_reg = '0') THEN
|
1067 |
|
|
IF (WRITEMODE_B = "WRITETHROUGH") THEN
|
1068 |
|
|
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
|
1069 |
|
|
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
|
1070 |
|
|
END LOOP;
|
1071 |
|
|
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
|
1072 |
|
|
dob_node <= dob_node_rbr;
|
1073 |
|
|
END IF;
|
1074 |
|
|
END IF;
|
1075 |
|
|
END IF;
|
1076 |
|
|
END IF;
|
1077 |
|
|
END PROCESS;
|
1078 |
|
|
|
1079 |
|
|
P10 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
|
1080 |
|
|
BEGIN
|
1081 |
|
|
IF (g_reset = '0') THEN
|
1082 |
|
|
doa_reg <= (others => '0');
|
1083 |
|
|
ELSIF (RESETMODE = "ASYNC") THEN
|
1084 |
|
|
IF (rsta_ipd = '1') THEN
|
1085 |
|
|
doa_reg <= (others => '0');
|
1086 |
|
|
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
|
1087 |
|
|
IF (cea_ipd = '1') THEN
|
1088 |
|
|
doa_reg <= doa_node;
|
1089 |
|
|
END IF;
|
1090 |
|
|
END IF;
|
1091 |
|
|
ELSIF (RESETMODE = "SYNC") THEN
|
1092 |
|
|
IF (clka_ipd'event and clka_ipd = '1') THEN
|
1093 |
|
|
IF (cea_ipd = '1') THEN
|
1094 |
|
|
IF (rsta_ipd = '1') THEN
|
1095 |
|
|
doa_reg <= (others => '0');
|
1096 |
|
|
ELSIF (rsta_ipd = '0') THEN
|
1097 |
|
|
doa_reg <= doa_node;
|
1098 |
|
|
END IF;
|
1099 |
|
|
END IF;
|
1100 |
|
|
END IF;
|
1101 |
|
|
END IF;
|
1102 |
|
|
|
1103 |
|
|
IF (g_reset = '0') THEN
|
1104 |
|
|
dob_reg <= (others => '0');
|
1105 |
|
|
doab_reg <= (others => '0');
|
1106 |
|
|
ELSIF (RESETMODE = "ASYNC") THEN
|
1107 |
|
|
IF (rstb_ipd = '1') THEN
|
1108 |
|
|
dob_reg <= (others => '0');
|
1109 |
|
|
doab_reg <= (others => '0');
|
1110 |
|
|
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
|
1111 |
|
|
IF (ceb_ipd = '1') THEN
|
1112 |
|
|
dob_reg <= dob_node;
|
1113 |
|
|
doab_reg <= doa_node;
|
1114 |
|
|
END IF;
|
1115 |
|
|
END IF;
|
1116 |
|
|
ELSIF (RESETMODE = "SYNC") THEN
|
1117 |
|
|
IF (clkb_ipd'event and clkb_ipd = '1') THEN
|
1118 |
|
|
IF (ceb_ipd = '1') THEN
|
1119 |
|
|
IF (rstb_ipd = '1') THEN
|
1120 |
|
|
dob_reg <= (others => '0');
|
1121 |
|
|
doab_reg <= (others => '0');
|
1122 |
|
|
ELSIF (rstb_ipd = '0') THEN
|
1123 |
|
|
dob_reg <= dob_node;
|
1124 |
|
|
doab_reg <= doa_node;
|
1125 |
|
|
END IF;
|
1126 |
|
|
END IF;
|
1127 |
|
|
END IF;
|
1128 |
|
|
END IF;
|
1129 |
|
|
END PROCESS;
|
1130 |
|
|
|
1131 |
|
|
P11 : PROCESS(doa_node, dob_node, doa_reg, dob_reg, doab_reg)
|
1132 |
|
|
BEGIN
|
1133 |
|
|
IF (REGMODE_A = "OUTREG") THEN
|
1134 |
|
|
IF (DATA_WIDTH_B = 36) THEN
|
1135 |
|
|
doa_int <= doab_reg;
|
1136 |
|
|
ELSE
|
1137 |
|
|
doa_int <= doa_reg;
|
1138 |
|
|
END IF;
|
1139 |
|
|
ELSE
|
1140 |
|
|
doa_int <= doa_node;
|
1141 |
|
|
END IF;
|
1142 |
|
|
|
1143 |
|
|
IF (REGMODE_B = "OUTREG") THEN
|
1144 |
|
|
dob_int <= dob_reg;
|
1145 |
|
|
ELSE
|
1146 |
|
|
dob_int <= dob_node;
|
1147 |
|
|
END IF;
|
1148 |
|
|
END PROCESS;
|
1149 |
|
|
|
1150 |
|
|
(doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7, doa6,
|
1151 |
|
|
doa5, doa4, doa3, doa2, doa1, doa0) <= doa_int;
|
1152 |
|
|
|
1153 |
|
|
(dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10, dob9, dob8, dob7, dob6,
|
1154 |
|
|
dob5, dob4, dob3, dob2, dob1, dob0) <= dob_int;
|
1155 |
|
|
|
1156 |
|
|
END V;
|
1157 |
|
|
|
1158 |
|
|
|
1159 |
|
|
--
|
1160 |
|
|
-----cell sp8ka----
|
1161 |
|
|
--
|
1162 |
|
|
|
1163 |
|
|
library ieee;
|
1164 |
|
|
use ieee.std_logic_1164.all;
|
1165 |
|
|
use ieee.vital_timing.all;
|
1166 |
|
|
use ieee.vital_primitives.all;
|
1167 |
|
|
library ec;
|
1168 |
|
|
use ec.global.gsrnet;
|
1169 |
|
|
use ec.global.purnet;
|
1170 |
|
|
use ec.mem3.all;
|
1171 |
|
|
|
1172 |
|
|
-- entity declaration --
|
1173 |
|
|
ENTITY sp8ka IS
|
1174 |
|
|
GENERIC (
|
1175 |
|
|
DATA_WIDTH : Integer := 18;
|
1176 |
|
|
REGMODE : String := "NOREG";
|
1177 |
|
|
RESETMODE : String := "ASYNC";
|
1178 |
|
|
CSDECODE : String := "000";
|
1179 |
|
|
WRITEMODE : String := "NORMAL";
|
1180 |
|
|
GSR : String := "ENABLED";
|
1181 |
|
|
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1182 |
|
|
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1183 |
|
|
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1184 |
|
|
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1185 |
|
|
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1186 |
|
|
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1187 |
|
|
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1188 |
|
|
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1189 |
|
|
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1190 |
|
|
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1191 |
|
|
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1192 |
|
|
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1193 |
|
|
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1194 |
|
|
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1195 |
|
|
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1196 |
|
|
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1197 |
|
|
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1198 |
|
|
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1199 |
|
|
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1200 |
|
|
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1201 |
|
|
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1202 |
|
|
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1203 |
|
|
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1204 |
|
|
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1205 |
|
|
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1206 |
|
|
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1207 |
|
|
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1208 |
|
|
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1209 |
|
|
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1210 |
|
|
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1211 |
|
|
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1212 |
|
|
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
|
1213 |
|
|
|
1214 |
|
|
PORT(
|
1215 |
|
|
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
|
1216 |
|
|
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
|
1217 |
|
|
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
|
1218 |
|
|
ad9, ad10, ad11, ad12 : in std_logic := 'X';
|
1219 |
|
|
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
|
1220 |
|
|
|
1221 |
|
|
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
|
1222 |
|
|
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
|
1223 |
|
|
);
|
1224 |
|
|
|
1225 |
|
|
ATTRIBUTE Vital_Level0 OF sp8ka : ENTITY IS TRUE;
|
1226 |
|
|
|
1227 |
|
|
END sp8ka ;
|
1228 |
|
|
|
1229 |
|
|
architecture V of sp8ka is
|
1230 |
|
|
|
1231 |
|
|
signal lo: std_logic := '0';
|
1232 |
|
|
signal hi: std_logic := '1';
|
1233 |
|
|
|
1234 |
|
|
component dp8ka
|
1235 |
|
|
GENERIC(
|
1236 |
|
|
DATA_WIDTH_A : in Integer;
|
1237 |
|
|
DATA_WIDTH_B : in Integer;
|
1238 |
|
|
REGMODE_A : in String;
|
1239 |
|
|
REGMODE_B : in String;
|
1240 |
|
|
RESETMODE : in String;
|
1241 |
|
|
CSDECODE_A : in String;
|
1242 |
|
|
CSDECODE_B : in String;
|
1243 |
|
|
WRITEMODE_A : in String;
|
1244 |
|
|
WRITEMODE_B : in String;
|
1245 |
|
|
GSR : in String;
|
1246 |
|
|
initval_00 : in string;
|
1247 |
|
|
initval_01 : in string;
|
1248 |
|
|
initval_02 : in string;
|
1249 |
|
|
initval_03 : in string;
|
1250 |
|
|
initval_04 : in string;
|
1251 |
|
|
initval_05 : in string;
|
1252 |
|
|
initval_06 : in string;
|
1253 |
|
|
initval_07 : in string;
|
1254 |
|
|
initval_08 : in string;
|
1255 |
|
|
initval_09 : in string;
|
1256 |
|
|
initval_0a : in string;
|
1257 |
|
|
initval_0b : in string;
|
1258 |
|
|
initval_0c : in string;
|
1259 |
|
|
initval_0d : in string;
|
1260 |
|
|
initval_0e : in string;
|
1261 |
|
|
initval_0f : in string;
|
1262 |
|
|
initval_10 : in string;
|
1263 |
|
|
initval_11 : in string;
|
1264 |
|
|
initval_12 : in string;
|
1265 |
|
|
initval_13 : in string;
|
1266 |
|
|
initval_14 : in string;
|
1267 |
|
|
initval_15 : in string;
|
1268 |
|
|
initval_16 : in string;
|
1269 |
|
|
initval_17 : in string;
|
1270 |
|
|
initval_18 : in string;
|
1271 |
|
|
initval_19 : in string;
|
1272 |
|
|
initval_1a : in string;
|
1273 |
|
|
initval_1b : in string;
|
1274 |
|
|
initval_1c : in string;
|
1275 |
|
|
initval_1d : in string;
|
1276 |
|
|
initval_1e : in string;
|
1277 |
|
|
initval_1f : in string);
|
1278 |
|
|
|
1279 |
|
|
PORT(
|
1280 |
|
|
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
|
1281 |
|
|
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
|
1282 |
|
|
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
|
1283 |
|
|
ada9, ada10, ada11, ada12 : in std_logic;
|
1284 |
|
|
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
|
1285 |
|
|
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
|
1286 |
|
|
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
|
1287 |
|
|
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
|
1288 |
|
|
adb9, adb10, adb11, adb12 : in std_logic;
|
1289 |
|
|
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
|
1290 |
|
|
|
1291 |
|
|
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
|
1292 |
|
|
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
|
1293 |
|
|
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
|
1294 |
|
|
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
|
1295 |
|
|
);
|
1296 |
|
|
END COMPONENT;
|
1297 |
|
|
|
1298 |
|
|
begin
|
1299 |
|
|
-- component instantiation statements
|
1300 |
|
|
dp8ka_inst : dp8ka
|
1301 |
|
|
generic map (DATA_WIDTH_A => DATA_WIDTH,
|
1302 |
|
|
DATA_WIDTH_B => DATA_WIDTH,
|
1303 |
|
|
REGMODE_A => REGMODE,
|
1304 |
|
|
REGMODE_B => REGMODE,
|
1305 |
|
|
RESETMODE => RESETMODE,
|
1306 |
|
|
CSDECODE_A => CSDECODE,
|
1307 |
|
|
CSDECODE_B => CSDECODE,
|
1308 |
|
|
WRITEMODE_A => WRITEMODE,
|
1309 |
|
|
WRITEMODE_B => WRITEMODE,
|
1310 |
|
|
GSR => GSR,
|
1311 |
|
|
initval_00 => initval_00,
|
1312 |
|
|
initval_01 => initval_01,
|
1313 |
|
|
initval_02 => initval_02,
|
1314 |
|
|
initval_03 => initval_03,
|
1315 |
|
|
initval_04 => initval_04,
|
1316 |
|
|
initval_05 => initval_05,
|
1317 |
|
|
initval_06 => initval_06,
|
1318 |
|
|
initval_07 => initval_07,
|
1319 |
|
|
initval_08 => initval_08,
|
1320 |
|
|
initval_09 => initval_09,
|
1321 |
|
|
initval_0a => initval_0a,
|
1322 |
|
|
initval_0b => initval_0b,
|
1323 |
|
|
initval_0c => initval_0c,
|
1324 |
|
|
initval_0d => initval_0d,
|
1325 |
|
|
initval_0e => initval_0e,
|
1326 |
|
|
initval_0f => initval_0f,
|
1327 |
|
|
initval_10 => initval_10,
|
1328 |
|
|
initval_11 => initval_11,
|
1329 |
|
|
initval_12 => initval_12,
|
1330 |
|
|
initval_13 => initval_13,
|
1331 |
|
|
initval_14 => initval_14,
|
1332 |
|
|
initval_15 => initval_15,
|
1333 |
|
|
initval_16 => initval_16,
|
1334 |
|
|
initval_17 => initval_17,
|
1335 |
|
|
initval_18 => initval_18,
|
1336 |
|
|
initval_19 => initval_19,
|
1337 |
|
|
initval_1a => initval_1a,
|
1338 |
|
|
initval_1b => initval_1b,
|
1339 |
|
|
initval_1c => initval_1c,
|
1340 |
|
|
initval_1d => initval_1d,
|
1341 |
|
|
initval_1e => initval_1e,
|
1342 |
|
|
initval_1f => initval_1f)
|
1343 |
|
|
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
|
1344 |
|
|
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
|
1345 |
|
|
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
|
1346 |
|
|
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => lo,
|
1347 |
|
|
dib1 => lo, dib2 => lo, dib3 => lo, dib4 => lo, dib5 => lo,
|
1348 |
|
|
dib6 => lo, dib7 => lo, dib8 => lo, dib9 => lo, dib10 => lo,
|
1349 |
|
|
dib11 => lo, dib12 => lo, dib13 => lo, dib14 => lo, dib15 => lo,
|
1350 |
|
|
dib16 => lo, dib17 => lo,
|
1351 |
|
|
cea => ce, clka => clk, wea => we, csa0 => cs0, csa1 => cs1, csa2 => cs2,
|
1352 |
|
|
rsta => rst, ada0 => ad0, ada1 => ad1, ada2 => ad2, ada3 => ad3,
|
1353 |
|
|
ada4 => ad4, ada5 => ad5, ada6 => ad6, ada7 => ad7, ada8 => ad8,
|
1354 |
|
|
ada9 => ad9, ada10 => ad10, ada11 => ad11, ada12 => ad12,
|
1355 |
|
|
ceb => lo, clkb => lo, web => lo, csb0 => lo, csb1 => lo, csb2 => lo,
|
1356 |
|
|
rstb => hi, adb0 => lo, adb1 => lo, adb2 => lo, adb3 => lo,
|
1357 |
|
|
adb4 => lo, adb5 => lo, adb6 => lo, adb7 => lo, adb8 => lo,
|
1358 |
|
|
adb9 => lo, adb10 => lo, adb11 => lo, adb12 => lo,
|
1359 |
|
|
dob0 => open, dob1 => open, dob2 => open, dob3 => open,
|
1360 |
|
|
dob4 => open, dob5 => open, dob6 => open, dob7 => open, dob8 => open,
|
1361 |
|
|
dob9 => open, dob10 => open, dob11 => open, dob12 => open, dob13 => open,
|
1362 |
|
|
dob14 => open, dob15 => open, dob16 => open, dob17 => open, doa0 => do0,
|
1363 |
|
|
doa1 => do1, doa2 => do2, doa3 => do3, doa4 => do4, doa5 => do5,
|
1364 |
|
|
doa6 => do6, doa7 => do7, doa8 => do8, doa9 => do9, doa10 => do10,
|
1365 |
|
|
doa11 => do11, doa12 => do12, doa13 => do13, doa14 => do14, doa15 => do15,
|
1366 |
|
|
doa16 => do16, doa17 => do17);
|
1367 |
|
|
|
1368 |
|
|
end V;
|
1369 |
|
|
|
1370 |
|
|
--
|
1371 |
|
|
-----cell pdp8ka----
|
1372 |
|
|
--
|
1373 |
|
|
|
1374 |
|
|
library ieee;
|
1375 |
|
|
use ieee.std_logic_1164.all;
|
1376 |
|
|
use ieee.vital_timing.all;
|
1377 |
|
|
use ieee.vital_primitives.all;
|
1378 |
|
|
library ec;
|
1379 |
|
|
use ec.global.gsrnet;
|
1380 |
|
|
use ec.global.purnet;
|
1381 |
|
|
use ec.mem3.all;
|
1382 |
|
|
|
1383 |
|
|
-- entity declaration --
|
1384 |
|
|
ENTITY pdp8ka IS
|
1385 |
|
|
GENERIC (
|
1386 |
|
|
DATA_WIDTH_W : Integer := 18;
|
1387 |
|
|
DATA_WIDTH_R : Integer := 18;
|
1388 |
|
|
REGMODE : String := "NOREG";
|
1389 |
|
|
RESETMODE : String := "ASYNC";
|
1390 |
|
|
CSDECODE_W : String := "000";
|
1391 |
|
|
CSDECODE_R : String := "000";
|
1392 |
|
|
GSR : String := "ENABLED";
|
1393 |
|
|
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1394 |
|
|
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1395 |
|
|
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1396 |
|
|
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1397 |
|
|
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1398 |
|
|
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1399 |
|
|
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1400 |
|
|
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1401 |
|
|
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1402 |
|
|
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1403 |
|
|
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1404 |
|
|
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1405 |
|
|
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1406 |
|
|
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1407 |
|
|
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1408 |
|
|
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1409 |
|
|
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1410 |
|
|
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1411 |
|
|
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1412 |
|
|
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1413 |
|
|
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1414 |
|
|
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1415 |
|
|
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1416 |
|
|
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1417 |
|
|
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1418 |
|
|
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1419 |
|
|
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1420 |
|
|
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1421 |
|
|
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1422 |
|
|
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1423 |
|
|
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
1424 |
|
|
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
|
1425 |
|
|
|
1426 |
|
|
PORT(
|
1427 |
|
|
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
|
1428 |
|
|
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
|
1429 |
|
|
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
|
1430 |
|
|
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
|
1431 |
|
|
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
|
1432 |
|
|
adw9, adw10, adw11, adw12 : in std_logic := 'X';
|
1433 |
|
|
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
|
1434 |
|
|
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
|
1435 |
|
|
adr9, adr10, adr11, adr12 : in std_logic := 'X';
|
1436 |
|
|
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
|
1437 |
|
|
|
1438 |
|
|
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
|
1439 |
|
|
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
|
1440 |
|
|
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
|
1441 |
|
|
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
|
1442 |
|
|
);
|
1443 |
|
|
|
1444 |
|
|
ATTRIBUTE Vital_Level0 OF pdp8ka : ENTITY IS TRUE;
|
1445 |
|
|
|
1446 |
|
|
END pdp8ka ;
|
1447 |
|
|
|
1448 |
|
|
architecture V of pdp8ka is
|
1449 |
|
|
|
1450 |
|
|
signal lo: std_logic := '0';
|
1451 |
|
|
|
1452 |
|
|
component dp8ka
|
1453 |
|
|
GENERIC(
|
1454 |
|
|
DATA_WIDTH_A : in Integer;
|
1455 |
|
|
DATA_WIDTH_B : in Integer;
|
1456 |
|
|
REGMODE_A : in String;
|
1457 |
|
|
REGMODE_B : in String;
|
1458 |
|
|
RESETMODE : in String;
|
1459 |
|
|
CSDECODE_A : in String;
|
1460 |
|
|
CSDECODE_B : in String;
|
1461 |
|
|
GSR : in String;
|
1462 |
|
|
initval_00 : in string;
|
1463 |
|
|
initval_01 : in string;
|
1464 |
|
|
initval_02 : in string;
|
1465 |
|
|
initval_03 : in string;
|
1466 |
|
|
initval_04 : in string;
|
1467 |
|
|
initval_05 : in string;
|
1468 |
|
|
initval_06 : in string;
|
1469 |
|
|
initval_07 : in string;
|
1470 |
|
|
initval_08 : in string;
|
1471 |
|
|
initval_09 : in string;
|
1472 |
|
|
initval_0a : in string;
|
1473 |
|
|
initval_0b : in string;
|
1474 |
|
|
initval_0c : in string;
|
1475 |
|
|
initval_0d : in string;
|
1476 |
|
|
initval_0e : in string;
|
1477 |
|
|
initval_0f : in string;
|
1478 |
|
|
initval_10 : in string;
|
1479 |
|
|
initval_11 : in string;
|
1480 |
|
|
initval_12 : in string;
|
1481 |
|
|
initval_13 : in string;
|
1482 |
|
|
initval_14 : in string;
|
1483 |
|
|
initval_15 : in string;
|
1484 |
|
|
initval_16 : in string;
|
1485 |
|
|
initval_17 : in string;
|
1486 |
|
|
initval_18 : in string;
|
1487 |
|
|
initval_19 : in string;
|
1488 |
|
|
initval_1a : in string;
|
1489 |
|
|
initval_1b : in string;
|
1490 |
|
|
initval_1c : in string;
|
1491 |
|
|
initval_1d : in string;
|
1492 |
|
|
initval_1e : in string;
|
1493 |
|
|
initval_1f : in string);
|
1494 |
|
|
|
1495 |
|
|
PORT(
|
1496 |
|
|
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
|
1497 |
|
|
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
|
1498 |
|
|
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
|
1499 |
|
|
ada9, ada10, ada11, ada12 : in std_logic;
|
1500 |
|
|
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
|
1501 |
|
|
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
|
1502 |
|
|
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
|
1503 |
|
|
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
|
1504 |
|
|
adb9, adb10, adb11, adb12 : in std_logic;
|
1505 |
|
|
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
|
1506 |
|
|
|
1507 |
|
|
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
|
1508 |
|
|
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
|
1509 |
|
|
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
|
1510 |
|
|
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
|
1511 |
|
|
);
|
1512 |
|
|
END COMPONENT;
|
1513 |
|
|
|
1514 |
|
|
begin
|
1515 |
|
|
-- component instantiation statements
|
1516 |
|
|
dp8ka_inst : dp8ka
|
1517 |
|
|
generic map (DATA_WIDTH_A => DATA_WIDTH_W,
|
1518 |
|
|
DATA_WIDTH_B => DATA_WIDTH_R,
|
1519 |
|
|
REGMODE_A => REGMODE,
|
1520 |
|
|
REGMODE_B => REGMODE,
|
1521 |
|
|
RESETMODE => RESETMODE,
|
1522 |
|
|
CSDECODE_A => CSDECODE_W,
|
1523 |
|
|
CSDECODE_B => CSDECODE_R,
|
1524 |
|
|
GSR => GSR,
|
1525 |
|
|
initval_00 => initval_00,
|
1526 |
|
|
initval_01 => initval_01,
|
1527 |
|
|
initval_02 => initval_02,
|
1528 |
|
|
initval_03 => initval_03,
|
1529 |
|
|
initval_04 => initval_04,
|
1530 |
|
|
initval_05 => initval_05,
|
1531 |
|
|
initval_06 => initval_06,
|
1532 |
|
|
initval_07 => initval_07,
|
1533 |
|
|
initval_08 => initval_08,
|
1534 |
|
|
initval_09 => initval_09,
|
1535 |
|
|
initval_0a => initval_0a,
|
1536 |
|
|
initval_0b => initval_0b,
|
1537 |
|
|
initval_0c => initval_0c,
|
1538 |
|
|
initval_0d => initval_0d,
|
1539 |
|
|
initval_0e => initval_0e,
|
1540 |
|
|
initval_0f => initval_0f,
|
1541 |
|
|
initval_10 => initval_10,
|
1542 |
|
|
initval_11 => initval_11,
|
1543 |
|
|
initval_12 => initval_12,
|
1544 |
|
|
initval_13 => initval_13,
|
1545 |
|
|
initval_14 => initval_14,
|
1546 |
|
|
initval_15 => initval_15,
|
1547 |
|
|
initval_16 => initval_16,
|
1548 |
|
|
initval_17 => initval_17,
|
1549 |
|
|
initval_18 => initval_18,
|
1550 |
|
|
initval_19 => initval_19,
|
1551 |
|
|
initval_1a => initval_1a,
|
1552 |
|
|
initval_1b => initval_1b,
|
1553 |
|
|
initval_1c => initval_1c,
|
1554 |
|
|
initval_1d => initval_1d,
|
1555 |
|
|
initval_1e => initval_1e,
|
1556 |
|
|
initval_1f => initval_1f)
|
1557 |
|
|
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
|
1558 |
|
|
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
|
1559 |
|
|
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
|
1560 |
|
|
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => di18,
|
1561 |
|
|
dib1 => di19, dib2 => di20, dib3 => di21, dib4 => di22, dib5 => di23,
|
1562 |
|
|
dib6 => di24, dib7 => di25, dib8 => di26, dib9 => di27, dib10 => di28,
|
1563 |
|
|
dib11 => di29, dib12 => di30, dib13 => di31, dib14 => di32, dib15 => di33,
|
1564 |
|
|
dib16 => di34, dib17 => di35,
|
1565 |
|
|
cea => cew, clka => clkw, wea => we, csa0 => csw0, csa1 => csw1, csa2 => csw2,
|
1566 |
|
|
rsta => rst, ada0 => adw0, ada1 => adw1, ada2 => adw2, ada3 => adw3,
|
1567 |
|
|
ada4 => adw4, ada5 => adw5, ada6 => adw6, ada7 => adw7, ada8 => adw8,
|
1568 |
|
|
ada9 => adw9, ada10 => adw10, ada11 => adw11, ada12 => adw12,
|
1569 |
|
|
ceb => cer, clkb => clkr, web => lo, csb0 => csr0, csb1 => csr1, csb2 => csr2,
|
1570 |
|
|
rstb => rst, adb0 => adr0, adb1 => adr1, adb2 => adr2, adb3 => adr3,
|
1571 |
|
|
adb4 => adr4, adb5 => adr5, adb6 => adr6, adb7 => adr7, adb8 => adr8,
|
1572 |
|
|
adb9 => adr9, adb10 => adr10, adb11 => adr11, adb12 => adr12,
|
1573 |
|
|
dob0 => do0, dob1 => do1, dob2 => do2, dob3 => do3,
|
1574 |
|
|
dob4 => do4, dob5 => do5, dob6 => do6, dob7 => do7, dob8 => do8,
|
1575 |
|
|
dob9 => do9, dob10 => do10, dob11 => do11, dob12 => do12, dob13 => do13,
|
1576 |
|
|
dob14 => do14, dob15 => do15, dob16 => do16, dob17 => do17, doa0 => do18,
|
1577 |
|
|
doa1 => do19, doa2 => do20, doa3 => do21, doa4 => do22, doa5 => do23,
|
1578 |
|
|
doa6 => do24, doa7 => do25, doa8 => do26, doa9 => do27, doa10 => do28,
|
1579 |
|
|
doa11 => do29, doa12 => do30, doa13 => do31, doa14 => do32, doa15 => do33,
|
1580 |
|
|
doa16 => do34, doa17 => do35);
|
1581 |
|
|
|
1582 |
|
|
end V;
|
1583 |
|
|
|
1584 |
|
|
|