Subversion Repositories mips_enhanced

-- Copyright (C) 1991-2006 Altera Corporation

-- Your use of Altera Corporation's design tools, logic functions 

-- and other software and tools, and its AMPP partner logic 

-- functions, and any output files any of the foregoing 

-- (including device programming or simulation files), and any 

-- associated documentation or information are expressly subject 

-- to the terms and conditions of the Altera Program License 

-- Subscription Agreement, Altera MegaCore Function License 

-- Agreement, or other applicable license agreement, including, 

-- without limitation, that your use is for the sole purpose of 

-- programming logic devices manufactured by Altera and sold by 

-- Altera or its authorized distributors.  Please refer to the 

-- applicable agreement for further details.

-- Quartus II 6.0 Build 178 04/27/2006

LIBRARY IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.VITAL_Timing.all;

use work.stratixii_atom_pack.all;

package STRATIXII_COMPONENTS is

--

-- STRATIXII_LCELL_FF

--

component stratixii_lcell_ff

    generic (

             x_on_violation : string := "on";

             lpm_type : string := "stratixii_lcell_ff";

             tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;

             tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;

             tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;

             tsetup_sload_clk_noedge_posedge    : VitalDelayType := DefSetupHoldCnst;

             tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;

             thold_datain_clk_noedge_posedge    : VitalDelayType := DefSetupHoldCnst;

             thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;

             thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;

             thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;

             thold_ena_clk_noedge_posedge       : VitalDelayType := DefSetupHoldCnst;

             tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;

             tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;

             tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;

             tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;

             tipd_clk : VitalDelayType01 := DefPropDelay01;

             tipd_datain : VitalDelayType01 := DefPropDelay01;

             tipd_adatasdata : VitalDelayType01 := DefPropDelay01;

             tipd_sclr : VitalDelayType01 := DefPropDelay01;

             tipd_sload : VitalDelayType01 := DefPropDelay01;

             tipd_aclr : VitalDelayType01 := DefPropDelay01;

             tipd_aload : VitalDelayType01 := DefPropDelay01;

             tipd_ena : VitalDelayType01 := DefPropDelay01;

             TimingChecksOn: Boolean := True;

             MsgOn: Boolean := DefGlitchMsgOn;

             XOn: Boolean := DefGlitchXOn;

             MsgOnChecks: Boolean := DefMsgOnChecks;

             XOnChecks: Boolean := DefXOnChecks;

             InstancePath: STRING := "*"

            );

    port (

          datain : in std_logic := '0';

          clk : in std_logic := '0';

          aclr : in std_logic := '0';

          aload : in std_logic := '0';

          sclr : in std_logic := '0';

          sload : in std_logic := '0';

          ena : in std_logic := '1';

          adatasdata : in std_logic := '0';

          devclrn : in std_logic := '1';

          devpor : in std_logic := '1';

          regout : out std_logic

         );

end component;

--

-- STRATIXII_LCELL_COMB

--

component stratixii_lcell_comb

    generic (

             lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');

             shared_arith : string := "off";

             extended_lut : string := "off";

             lpm_type : string := "stratixii_lcell_comb";

             TimingChecksOn: Boolean := True;

             MsgOn: Boolean := DefGlitchMsgOn;

             XOn: Boolean := DefGlitchXOn;

             MsgOnChecks: Boolean := DefMsgOnChecks;

             XOnChecks: Boolean := DefXOnChecks;

             InstancePath: STRING := "*";

             tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;

             tpd_datab_combout : VitalDelayType01 := DefPropDelay01;

             tpd_datac_combout : VitalDelayType01 := DefPropDelay01;

             tpd_datad_combout : VitalDelayType01 := DefPropDelay01;

             tpd_datae_combout : VitalDelayType01 := DefPropDelay01;

             tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;

             tpd_datag_combout : VitalDelayType01 := DefPropDelay01;

             tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;

             tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;

             tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;

             tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;

             tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;

             tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;

             tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;

             tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;

             tpd_datab_cout : VitalDelayType01 := DefPropDelay01;

             tpd_datac_cout : VitalDelayType01 := DefPropDelay01;

             tpd_datad_cout : VitalDelayType01 := DefPropDelay01;

             tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;

             tpd_cin_cout : VitalDelayType01 := DefPropDelay01;

             tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;

             tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;

             tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;

             tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;

             tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;

             tipd_dataa : VitalDelayType01 := DefPropDelay01;

             tipd_datab : VitalDelayType01 := DefPropDelay01;

             tipd_datac : VitalDelayType01 := DefPropDelay01;

             tipd_datad : VitalDelayType01 := DefPropDelay01;

             tipd_datae : VitalDelayType01 := DefPropDelay01;

             tipd_dataf : VitalDelayType01 := DefPropDelay01;

             tipd_datag : VitalDelayType01 := DefPropDelay01;

             tipd_cin : VitalDelayType01 := DefPropDelay01;

             tipd_sharein : VitalDelayType01 := DefPropDelay01

            );

    port (

          dataa : in std_logic := '0';

          datab : in std_logic := '0';

          datac : in std_logic := '0';

          datad : in std_logic := '0';

          datae : in std_logic := '0';

          dataf : in std_logic := '0';

          datag : in std_logic := '0';

          cin : in std_logic := '0';

          sharein : in std_logic := '0';

          combout : out std_logic;

          sumout : out std_logic;

          cout : out std_logic;

          shareout : out std_logic

         );

end component;

--

-- STRATIXII_IO

--

component  stratixii_io

generic (

         operation_mode : string := "input";

         ddio_mode : string := "none";

         open_drain_output : string := "false";

         bus_hold : string := "false";

         output_register_mode : string := "none";

         output_async_reset : string := "none";

         output_power_up : string := "low";

         output_sync_reset : string := "none";

         tie_off_output_clock_enable : string := "false";

         oe_register_mode : string := "none";

         oe_async_reset : string := "none";

         oe_power_up : string := "low";

         oe_sync_reset : string := "none";

         tie_off_oe_clock_enable : string := "false";

         input_register_mode : string := "none";

         input_async_reset : string := "none";

         input_power_up : string := "low";

         input_sync_reset : string := "none";

         extend_oe_disable : string := "false";

         dqs_input_frequency : string := "10000 ps";

         dqs_out_mode : string := "none";

         dqs_delay_buffer_mode : string := "low";

         dqs_phase_shift : integer := 0;

         inclk_input : string := "normal";

         ddioinclk_input : string := "negated_inclk";

         dqs_offsetctrl_enable : string := "false";

         dqs_ctrl_latches_enable : string := "false";

         dqs_edge_detect_enable : string := "false";

         gated_dqs : string := "false";

         sim_dqs_intrinsic_delay : integer := 0;

         sim_dqs_delay_increment : integer := 0;

         sim_dqs_offset_increment : integer := 0;

         lpm_type : string := "stratixii_io"

        );

port (

      datain          : in std_logic := '0';

      ddiodatain      : in std_logic := '0';

      oe              : in std_logic := '1';

      outclk          : in std_logic := '0';

      outclkena       : in std_logic := '1';

      inclk           : in std_logic := '0';

      inclkena        : in std_logic := '1';

      areset          : in std_logic := '0';

      sreset          : in std_logic := '0';

      ddioinclk       : in std_logic := '0';

      delayctrlin     : in std_logic_vector(5 downto 0) := "000000";

      offsetctrlin    : in std_logic_vector(5 downto 0) := "000000";

      dqsupdateen     : in std_logic := '0';

      linkin              : in std_logic := '0';

      terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";

      devclrn         : in std_logic := '1';

      devpor          : in std_logic := '1';

      devoe           : in std_logic := '0';

      padio           : inout std_logic;

      combout         : out std_logic;

      regout          : out std_logic;

      ddioregout      : out std_logic;

      dqsbusout           : out std_logic;

      linkout             : out std_logic

 );

end component;

--

-- STRATIXII_CLKCTRL

--

component stratixii_clkctrl

    generic (

             clock_type : STRING := "Auto";

             lpm_type : STRING := "stratixii_clkctrl";

             TimingChecksOn : Boolean := True;

             MsgOn : Boolean := DefGlitchMsgOn;

             XOn : Boolean := DefGlitchXOn;

             MsgOnChecks : Boolean := DefMsgOnChecks;

             XOnChecks : Boolean := DefXOnChecks;

             InstancePath : STRING := "*";

             tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);

             tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);

             tipd_ena : VitalDelayType01 := DefPropDelay01

             );

    port (

          inclk       : in std_logic_vector(3 downto 0) := "0000";

          clkselect   : in std_logic_vector(1 downto 0) := "00";

          ena         : in std_logic := '1';

          devclrn     : in std_logic := '1';

          devpor      : in std_logic := '1';

          outclk      : out std_logic

         );

end component;

--

-- STRATIXII_MAC_MULT

--

component stratixii_mac_mult

  generic

    (

      dataa_width       : integer := 18;

      datab_width       : integer := 18;

      dataa_clock       : string := "none";

      datab_clock       : string := "none";

      signa_clock       : string := "none";

      signb_clock       : string := "none";

      round_clock       : string := "none";

      saturate_clock    : string := "none";

      output_clock      : string := "none";

      dataa_clear       : string := "none";

      datab_clear       : string := "none";

      signa_clear       : string := "none";

      signb_clear       : string := "none";

      round_clear       : string := "none";

      saturate_clear    : string := "none";

      output_clear      : string := "none";

      bypass_multiplier : string := "no";

      mode_clock        : string := "none";

      zeroacc_clock     : string := "none";

      mode_clear        : string := "none";

      zeroacc_clear     : string := "none";

      signa_internally_grounded : string := "false";

      signb_internally_grounded : string := "false";

      lpm_hint          : string := "true";

      dynamic_mode      : string := "no";

      lpm_type          : string := "stratixii_mac_mult"

    );

  port

    (

      dataa                   : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');

      datab                   : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');

      scanina                 : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');

      scaninb                 : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');

      sourcea                 : IN std_logic := '0';

      sourceb                 : IN std_logic := '0';

      signa                   : IN std_logic := '0';

      signb                   : IN std_logic := '0';

      round                   : IN std_logic := '0';

      saturate                : IN std_logic := '0';

      clk                     : IN std_logic_vector(3 DOWNTO 0) := (others => '0');

      aclr                    : IN std_logic_vector(3 DOWNTO 0) := (others => '0');

      ena                     : IN std_logic_vector(3 DOWNTO 0) := (others => '0');

      mode                    : IN std_logic := '0';

      zeroacc                 : IN std_logic := '0';

      dataout                 : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);

      scanouta                : OUT std_logic_vector(dataa_width-1 DOWNTO 0);

      scanoutb                : OUT std_logic_vector(datab_width-1 DOWNTO 0);

      devclrn   : in std_logic := '1';

      devpor    : in std_logic := '1'

    );

end component;

--

-- STRATIXII_MAC_OUT

--

component stratixii_mac_out

  generic

    (

      operation_mode    : string := "output_only";

      dataa_width       : integer := 1;

      datab_width       : integer := 1;

      datac_width       : integer := 1;

      datad_width       : integer := 1;

      dataout_width     : integer := 144;

      addnsub0_clock    : string := "none";

      addnsub1_clock    : string := "none";

      zeroacc_clock     : string := "none";

      round0_clock      : string := "none";

      round1_clock      : string := "none";

      saturate_clock    : string := "none";

      multabsaturate_clock : string := "none";

      multcdsaturate_clock : string := "none";

      signa_clock       : string := "none";

      signb_clock       : string := "none";

      output_clock      : string := "none";

      addnsub0_clear    : string := "none";

      addnsub1_clear    : string := "none";

      zeroacc_clear     : string := "none";

      round0_clear : string := "none";

      round1_clear : string := "none";

      saturate_clear : string := "none";

      multabsaturate_clear : string := "none";

      multcdsaturate_clear : string := "none";

      signa_clear       : string := "none";

      signb_clear       : string := "none";

      output_clear      : string := "none";

      addnsub0_pipeline_clock   : string := "none";

      addnsub1_pipeline_clock   : string := "none";

      round0_pipeline_clock     : string := "none";

      round1_pipeline_clock     : string := "none";

      saturate_pipeline_clock   : string := "none";

      multabsaturate_pipeline_clock : string := "none";

      multcdsaturate_pipeline_clock : string := "none";

      zeroacc_pipeline_clock    : string := "none";

      signa_pipeline_clock      : string := "none";

      signb_pipeline_clock      : string := "none";

      addnsub0_pipeline_clear   : string := "none";

      addnsub1_pipeline_clear   : string := "none";

      round0_pipeline_clear     : string := "none";

      round1_pipeline_clear     : string := "none";

      saturate_pipeline_clear   : string := "none";

      multabsaturate_pipeline_clear : string := "none";

      multcdsaturate_pipeline_clear : string := "none";

      zeroacc_pipeline_clear : string := "none";

      signa_pipeline_clear : string := "none";

      signb_pipeline_clear : string := "none";

      mode0_clock       : string := "none";

      mode1_clock       : string := "none";

      zeroacc1_clock    : string := "none";

      saturate1_clock   : string := "none";

      output1_clock     : string := "none";

      output2_clock     : string := "none";

      output3_clock     : string := "none";

      output4_clock     : string := "none";

      output5_clock     : string := "none";

      output6_clock     : string := "none";

      output7_clock     : string := "none";

      mode0_clear       : string := "none";

      mode1_clear       : string := "none";

      zeroacc1_clear    : string := "none";

      saturate1_clear   : string := "none";

      output1_clear     : string := "none";

      output2_clear     : string := "none";

      output3_clear     : string := "none";

      output4_clear     : string := "none";

      output5_clear     : string := "none";

      output6_clear     : string := "none";

      output7_clear     : string := "none";

      mode0_pipeline_clock      : string := "none";

      mode1_pipeline_clock      : string := "none";

      zeroacc1_pipeline_clock   : string := "none";

      saturate1_pipeline_clock  : string := "none";

      mode0_pipeline_clear      : string := "none";

      mode1_pipeline_clear      : string := "none";

      zeroacc1_pipeline_clear   : string := "none";

      saturate1_pipeline_clear  : string := "none";

      dataa_forced_to_zero      : string := "no";

      datac_forced_to_zero      : string := "no";

      lpm_hint                  : string := "true";

      lpm_type                  : string := "stratixii_mac_out"

    );

  port

    (

      dataa     : in std_logic_vector (dataa_width - 1 downto 0) := (others => '0');

      datab     : in std_logic_vector (datab_width - 1 downto 0) := (others => '0');

      datac     : in std_logic_vector (datac_width - 1 downto 0) := (others => '0');

      datad     : in std_logic_vector (datad_width - 1 downto 0) := (others => '0');

      zeroacc   : in std_logic := '0';

      addnsub0  : in std_logic := '1';

      addnsub1  : in std_logic := '1';

      round0    : in std_logic := '0';

      round1    : in std_logic := '0';

      saturate  : in std_logic := '0';

      multabsaturate : in std_logic := '0';

      multcdsaturate : in std_logic := '0';

      signa     : in std_logic := '1';

      signb     : in std_logic := '1';

      clk       : in std_logic_vector (3 downto 0) := "0000";

      aclr      : in std_logic_vector (3 downto 0) := "0000";

      ena       : in std_logic_vector (3 downto 0) := "1111";

      mode0     : in std_logic := '0';

      mode1     : in std_logic := '0';

      zeroacc1  : in std_logic := '0';

      saturate1 : in std_logic := '0';

      dataout   : out std_logic_vector (dataout_width -1 downto 0);

      accoverflow : out std_logic;

      devclrn   : in std_logic := '1';

      devpor    : in std_logic := '1'

      );

end component;

--

-- STRATIXII_PLL

--

COMPONENT stratixii_pll

    GENERIC (operation_mode              : string := "normal";

             pll_type                    : string := "auto";

             compensate_clock            : string := "clk0";

             feedback_source             : string := "e0";

             qualify_conf_done           : string := "off";

             test_input_comp_delay       : integer := 0;

             test_feedback_comp_delay    : integer := 0;

             inclk0_input_frequency      : integer := 10000;

             inclk1_input_frequency      : integer := 10000;

             gate_lock_signal            : string := "yes";

             gate_lock_counter           : integer := 1;

             self_reset_on_gated_loss_lock : string := "off";

             valid_lock_multiplier       : integer := 1;

             invalid_lock_multiplier     : integer := 5;

             switch_over_type            : string := "auto";

             switch_over_on_lossclk      : string := "off";

             switch_over_on_gated_lock   : string := "off";

             switch_over_counter         : integer := 1;

             enable_switch_over_counter  : string := "off";

             bandwidth                   : integer := 0;

             bandwidth_type              : string := "auto";

             down_spread                 : string := "0 %";

             spread_frequency            : integer := 0;

             clk0_output_frequency       : integer := 0;

             clk0_multiply_by            : integer := 1;

             clk0_divide_by              : integer := 1;

             clk0_phase_shift            : string := "0";

             clk0_duty_cycle             : integer := 50;

             clk1_output_frequency       : integer := 0;

             clk1_multiply_by            : integer := 1;

             clk1_divide_by              : integer := 1;

             clk1_phase_shift            : string := "0";

             clk1_duty_cycle             : integer := 50;

             clk2_output_frequency       : integer := 0;

             clk2_multiply_by            : integer := 1;

             clk2_divide_by              : integer := 1;

             clk2_phase_shift            : string := "0";

             clk2_duty_cycle             : integer := 50;

             clk3_output_frequency       : integer := 0;

             clk3_multiply_by            : integer := 1;

             clk3_divide_by              : integer := 1;

             clk3_phase_shift            : string := "0";

             clk3_duty_cycle             : integer := 50;

             clk4_output_frequency       : integer := 0;

             clk4_multiply_by            : integer := 1;

             clk4_divide_by              : integer := 1;

             clk4_phase_shift            : string := "0";

             clk4_duty_cycle             : integer := 50;

             clk5_output_frequency       : integer := 0;

             clk5_multiply_by            : integer := 1;

             clk5_divide_by              : integer := 1;

             clk5_phase_shift            : string := "0";

             clk5_duty_cycle             : integer := 50;

             pfd_min                     : integer := 0;

             pfd_max                     : integer := 0;

             vco_min                     : integer := 0;

             vco_max                     : integer := 0;

             vco_center                  : integer := 0;

             -- ADVANCED USE PARAMETERS

             m_initial                   : integer := 1;

             m                           : integer := 1;

             n                           : integer := 1;

             m2                          : integer := 1;

             n2                          : integer := 1;

             ss                          : integer := 0;

             c0_high                     : integer := 1;

             c0_low                      : integer := 1;

             c0_initial                  : integer := 1;

             c0_mode                     : string := "bypass";

             c0_ph                       : integer := 0;

             c1_high                     : integer := 1;

             c1_low                      : integer := 1;

             c1_initial                  : integer := 1;

             c1_mode                     : string := "bypass";

             c1_ph                       : integer := 0;

             c2_high                     : integer := 1;

             c2_low                      : integer := 1;

             c2_initial                  : integer := 1;

             c2_mode                     : string := "bypass";

             c2_ph                       : integer := 0;

             c3_high                     : integer := 1;

             c3_low                      : integer := 1;

             c3_initial                  : integer := 1;

             c3_mode                     : string := "bypass";

             c3_ph                       : integer := 0;

             c4_high                     : integer := 1;

             c4_low                      : integer := 1;

             c4_initial                  : integer := 1;

             c4_mode                     : string := "bypass";

             c4_ph                       : integer := 0;

             c5_high                     : integer := 1;

             c5_low                      : integer := 1;

             c5_initial                  : integer := 1;

             c5_mode                     : string := "bypass";

             c5_ph                       : integer := 0;

             m_ph                        : integer := 0;

             clk0_counter                : string := "c0";

             clk1_counter                : string := "c1";

             clk2_counter                : string := "c2";

             clk3_counter                : string := "c3";

             clk4_counter                : string := "c4";

             clk5_counter                : string := "c5";

             c1_use_casc_in              : string := "off";

             c2_use_casc_in              : string := "off";

             c3_use_casc_in              : string := "off";

             c4_use_casc_in              : string := "off";

             c5_use_casc_in              : string := "off";

             m_test_source               : integer := 5;

             c0_test_source              : integer := 5;

             c1_test_source              : integer := 5;

             c2_test_source              : integer := 5;

             c3_test_source              : integer := 5;

             c4_test_source              : integer := 5;

             c5_test_source              : integer := 5;

             enable0_counter             : string := "c0";

             enable1_counter             : string := "c1";

             sclkout0_phase_shift        : string := "0";

             sclkout1_phase_shift        : string := "0";

             charge_pump_current         : integer := 0;

             loop_filter_c               : integer := 1;

             loop_filter_r               : string := "1.0" ;

             common_rx_tx                : string := "off";

             rx_outclock_resource        : string := "auto";

             use_vco_bypass              : string := "false";

             use_dc_coupling             : string := "false";

             pll_compensation_delay      : integer := 0;

             simulation_type             : string := "functional";