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-- Copyright (C) 1991-2007 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- Quartus II 7.2 Build 207 09/26/2007
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.VITAL_Timing.all;
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use IEEE.VITAL_Primitives.all;
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package stratixiii_atom_pack is
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function str_to_bin (lut_mask : string ) return std_logic_vector;
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function product(list : std_logic_vector) return std_logic ;
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function alt_conv_integer(arg : in std_logic_vector) return integer;
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-- default generic values
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CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
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CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
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CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
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CONSTANT DefSetupHoldCnst : TIME := 0 ns;
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CONSTANT DefPulseWdthCnst : TIME := 0 ns;
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-- default control options
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-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
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-- change default delay type to Transport : for spr 68748
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CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
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CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
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CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
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CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
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CONSTANT DefXOnChecks : BOOLEAN := TRUE;
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-- output strength mapping
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-- UX01ZWHL-
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CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
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CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
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CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
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-- primitive result strength mapping
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CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
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CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
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CONSTANT L : VitalTableSymbolType := '0';
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CONSTANT H : VitalTableSymbolType := '1';
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CONSTANT x : VitalTableSymbolType := '-';
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CONSTANT S : VitalTableSymbolType := 'S';
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CONSTANT R : VitalTableSymbolType := '/';
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CONSTANT U : VitalTableSymbolType := 'X';
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CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
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-- Declare array types for CAM_SLICE
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TYPE stratixiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
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function int2str( value : integer ) return string;
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function map_x_to_0 (value : std_logic) return std_logic;
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function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
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end stratixiii_atom_pack;
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library IEEE;
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use IEEE.std_logic_1164.all;
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package body stratixiii_atom_pack is
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type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
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function str_to_bin (lut_mask : string) return std_logic_vector is
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variable slice : masklength := (OTHERS => "0000");
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variable mask : std_logic_vector(15 downto 0);
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begin
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for i in 1 to lut_mask'length loop
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case lut_mask(i) is
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when '0' => slice(i) := "0000";
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when '1' => slice(i) := "0001";
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when '2' => slice(i) := "0010";
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when '3' => slice(i) := "0011";
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when '4' => slice(i) := "0100";
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when '5' => slice(i) := "0101";
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when '6' => slice(i) := "0110";
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when '7' => slice(i) := "0111";
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when '8' => slice(i) := "1000";
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when '9' => slice(i) := "1001";
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when 'a' => slice(i) := "1010";
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when 'A' => slice(i) := "1010";
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when 'b' => slice(i) := "1011";
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when 'B' => slice(i) := "1011";
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when 'c' => slice(i) := "1100";
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when 'C' => slice(i) := "1100";
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when 'd' => slice(i) := "1101";
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when 'D' => slice(i) := "1101";
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when 'e' => slice(i) := "1110";
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when 'E' => slice(i) := "1110";
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when others => slice(i) := "1111";
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end case;
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end loop;
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mask := (slice(1) & slice(2) & slice(3) & slice(4));
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return (mask);
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end str_to_bin;
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function product (list: std_logic_vector) return std_logic is
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begin
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for i in 0 to 31 loop
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if list(i) = '0' then
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return ('0');
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end if;
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end loop;
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return ('1');
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end product;
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function alt_conv_integer(arg : in std_logic_vector) return integer is
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variable result : integer;
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begin
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result := 0;
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for i in arg'range loop
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if arg(i) = '1' then
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result := result + 2**i;
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end if;
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end loop;
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return result;
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end alt_conv_integer;
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function int2str( value : integer ) return string is
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variable ivalue,index : integer;
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variable digit : integer;
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variable line_no: string(8 downto 1) := " ";
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begin
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ivalue := value;
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index := 1;
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if (ivalue = 0) then
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line_no := " 0";
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end if;
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while (ivalue > 0) loop
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digit := ivalue MOD 10;
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ivalue := ivalue/10;
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case digit is
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when 0 =>
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line_no(index) := '0';
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when 1 =>
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line_no(index) := '1';
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when 2 =>
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line_no(index) := '2';
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when 3 =>
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line_no(index) := '3';
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when 4 =>
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line_no(index) := '4';
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when 5 =>
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line_no(index) := '5';
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when 6 =>
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line_no(index) := '6';
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when 7 =>
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line_no(index) := '7';
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when 8 =>
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line_no(index) := '8';
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when 9 =>
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line_no(index) := '9';
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when others =>
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ASSERT FALSE
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REPORT "Illegal number!"
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SEVERITY ERROR;
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end case;
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index := index + 1;
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end loop;
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return line_no;
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end;
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function map_x_to_0 (value : std_logic) return std_logic is
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begin
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if (Is_X (value) = TRUE) then
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return '0';
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else
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return value;
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end if;
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end;
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function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
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variable Temp : TIME;
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variable TransitionTime : TIME := TIME'HIGH;
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variable PathDelay : TIME := TIME'HIGH;
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begin
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for i IN Paths'RANGE loop
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next when not Paths(i).PathCondition;
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next when Paths(i).InputChangeTime > TransitionTime;
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Temp := Paths(i).PathDelay(tr01);
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if Paths(i).InputChangeTime < TransitionTime then
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PathDelay := Temp;
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else
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if Temp < PathDelay then
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PathDelay := Temp;
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end if;
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end if;
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TransitionTime := Paths(i).InputChangeTime;
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end loop;
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return PathDelay;
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end;
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end stratixiii_atom_pack;
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Library ieee;
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use ieee.std_logic_1164.all;
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Package stratixiii_pllpack is
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procedure find_simple_integer_fraction( numerator : in integer;
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denominator : in integer;
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max_denom : in integer;
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fraction_num : out integer;
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fraction_div : out integer);
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procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
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vco_phase_shift_step : in integer;
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clk0_mult: in integer; clk1_mult: in integer;
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clk2_mult: in integer; clk3_mult: in integer;
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clk4_mult: in integer; clk5_mult: in integer;
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clk6_mult: in integer; clk7_mult: in integer;
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clk8_mult: in integer; clk9_mult: in integer;
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clk0_div : in integer; clk1_div : in integer;
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clk2_div : in integer; clk3_div : in integer;
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clk4_div : in integer; clk5_div : in integer;
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clk6_div : in integer; clk7_div : in integer;
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clk8_div : in integer; clk9_div : in integer;
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m : out integer;
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n : out integer );
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function gcd (X: integer; Y: integer) return integer;
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function count_digit (X: integer) return integer;
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function scale_num (X: integer; Y: integer) return integer;
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function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
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A5: integer; A6: integer; A7: integer;
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A8: integer; A9: integer; A10: integer; P: integer) return integer;
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function output_counter_value (clk_divide: integer; clk_mult : integer ;
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M: integer; N: integer ) return integer;
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function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
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function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
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return integer;
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function counter_low (output_counter_value: integer; duty_cycle: integer)
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return integer;
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function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
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t5: integer; t6: integer; t7: integer; t8: integer;
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t9: integer; t10: integer) return integer;
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function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
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t5: integer; t6: integer; t7: integer; t8: integer;
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t9: integer; t10: integer) return integer;
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function counter_time_delay ( clk_time_delay: integer;
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m_time_delay: integer; n_time_delay: integer)
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return integer;
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function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
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function counter_initial (tap_phase: integer; m: integer; n: integer)
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return integer;
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function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
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function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
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function translate_string (mode : string) return string;
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function str2int (s : string) return integer;
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function dqs_str2int (s : string) return integer;
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end stratixiii_pllpack;
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package body stratixiii_pllpack is
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-- finds the closest integer fraction of a given pair of numerator and denominator.
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procedure find_simple_integer_fraction( numerator : in integer;
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denominator : in integer;
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max_denom : in integer;
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fraction_num : out integer;
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fraction_div : out integer) is
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constant MAX_ITER : integer := 20;
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type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
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variable quotient_array : INT_ARRAY;
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variable int_loop_iter : integer;
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variable int_quot : integer;
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variable m_value : integer;
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variable d_value : integer;
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variable old_m_value : integer;
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variable swap : integer;
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variable loop_iter : integer;
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variable num : integer;
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variable den : integer;
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variable i_max_iter : integer;
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begin
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loop_iter := 0;
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if (numerator = 0) then
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num := 1;
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else
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num := numerator;
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end if;
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if (denominator = 0) then
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den := 1;
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else
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den := denominator;
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end if;
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i_max_iter := max_iter;
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while (loop_iter < i_max_iter) loop
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|
|
int_quot := num / den;
|
| 344 |
|
|
quotient_array(loop_iter) := int_quot;
|
| 345 |
|
|
num := num - (den*int_quot);
|
| 346 |
|
|
loop_iter := loop_iter+1;
|
| 347 |
|
|
|
| 348 |
|
|
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
|
| 349 |
|
|
-- calculate the numerator and denominator if there is a restriction on the
|
| 350 |
|
|
-- max denom value or if the loop is ending
|
| 351 |
|
|
m_value := 0;
|
| 352 |
|
|
d_value := 1;
|
| 353 |
|
|
-- get the rounded value at this stage for the remaining fraction
|
| 354 |
|
|
if (den /= 0) then
|
| 355 |
|
|
m_value := (2*num/den);
|
| 356 |
|
|
end if;
|
| 357 |
|
|
-- calculate the fraction numerator and denominator at this stage
|
| 358 |
|
|
for int_loop_iter in (loop_iter-1) downto 0 loop
|
| 359 |
|
|
if (m_value = 0) then
|
| 360 |
|
|
m_value := quotient_array(int_loop_iter);
|
| 361 |
|
|
d_value := 1;
|
| 362 |
|
|
else
|
| 363 |
|
|
old_m_value := m_value;
|
| 364 |
|
|
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
|
| 365 |
|
|
d_value := old_m_value;
|
| 366 |
|
|
end if;
|
| 367 |
|
|
end loop;
|
| 368 |
|
|
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
|
| 369 |
|
|
if ((d_value <= max_denom) or (max_denom = -1)) then
|
| 370 |
|
|
if ((m_value = 0) or (d_value = 0)) then
|
| 371 |
|
|
fraction_num := numerator;
|
| 372 |
|
|
fraction_div := denominator;
|
| 373 |
|
|
else
|
| 374 |
|
|
fraction_num := m_value;
|
| 375 |
|
|
fraction_div := d_value;
|
| 376 |
|
|
end if;
|
| 377 |
|
|
end if;
|
| 378 |
|
|
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
|
| 379 |
|
|
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
|
| 380 |
|
|
i_max_iter := loop_iter;
|
| 381 |
|
|
end if;
|
| 382 |
|
|
end if;
|
| 383 |
|
|
-- swap the numerator and denominator for the next round
|
| 384 |
|
|
swap := den;
|
| 385 |
|
|
den := num;
|
| 386 |
|
|
num := swap;
|
| 387 |
|
|
end loop;
|
| 388 |
|
|
end find_simple_integer_fraction;
|
| 389 |
|
|
|
| 390 |
|
|
-- find the M and N values for Manual phase based on the following 5 criterias:
|
| 391 |
|
|
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
|
| 392 |
|
|
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
|
| 393 |
|
|
-- 3. M is less than 512
|
| 394 |
|
|
-- 4. N is less than 512
|
| 395 |
|
|
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
|
| 396 |
|
|
-- of the desired vco-phase-shift-step
|
| 397 |
|
|
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
|
| 398 |
|
|
vco_phase_shift_step : in integer;
|
| 399 |
|
|
clk0_mult: in integer; clk1_mult: in integer;
|
| 400 |
|
|
clk2_mult: in integer; clk3_mult: in integer;
|
| 401 |
|
|
clk4_mult: in integer; clk5_mult: in integer;
|
| 402 |
|
|
clk6_mult: in integer; clk7_mult: in integer;
|
| 403 |
|
|
clk8_mult: in integer; clk9_mult: in integer;
|
| 404 |
|
|
clk0_div : in integer; clk1_div : in integer;
|
| 405 |
|
|
clk2_div : in integer; clk3_div : in integer;
|
| 406 |
|
|
clk4_div : in integer; clk5_div : in integer;
|
| 407 |
|
|
clk6_div : in integer; clk7_div : in integer;
|
| 408 |
|
|
clk8_div : in integer; clk9_div : in integer;
|
| 409 |
|
|
m : out integer;
|
| 410 |
|
|
n : out integer ) is
|
| 411 |
|
|
constant MAX_M : integer := 511;
|
| 412 |
|
|
constant MAX_N : integer := 511;
|
| 413 |
|
|
constant MAX_PFD : integer := 720;
|
| 414 |
|
|
constant MIN_PFD : integer := 5;
|
| 415 |
|
|
constant MAX_VCO : integer := 1300;
|
| 416 |
|
|
constant MIN_VCO : integer := 300;
|
| 417 |
|
|
|
| 418 |
|
|
variable vco_period : integer;
|
| 419 |
|
|
variable pfd_freq : integer;
|
| 420 |
|
|
variable vco_freq : integer;
|
| 421 |
|
|
variable vco_ps_step_value : integer;
|
| 422 |
|
|
|
| 423 |
|
|
variable i_m : integer;
|
| 424 |
|
|
variable i_n : integer;
|
| 425 |
|
|
variable i_pre_m : integer;
|
| 426 |
|
|
variable i_pre_n : integer;
|
| 427 |
|
|
|
| 428 |
|
|
variable i_max_iter : integer;
|
| 429 |
|
|
variable loop_iter : integer;
|
| 430 |
|
|
begin
|
| 431 |
|
|
|
| 432 |
|
|
loop_iter := 0;
|
| 433 |
|
|
i_max_iter := MAX_N;
|
| 434 |
|
|
vco_period := vco_phase_shift_step * 8;
|
| 435 |
|
|
|
| 436 |
|
|
while (loop_iter < i_max_iter) loop
|
| 437 |
|
|
loop_iter := loop_iter+1;
|
| 438 |
|
|
|
| 439 |
|
|
i_pre_m := i_m;
|
| 440 |
|
|
i_pre_n := i_n;
|
| 441 |
|
|
|
| 442 |
|
|
find_simple_integer_fraction(inclock_period, vco_period,
|
| 443 |
|
|
loop_iter, i_m, i_n);
|
| 444 |
|
|
|
| 445 |
|
|
if (((clk0_div * i_m) rem (clk0_mult * i_n) /= 0) or
|
| 446 |
|
|
((clk1_div * i_m) rem (clk1_mult * i_n) /= 0) or
|
| 447 |
|
|
((clk2_div * i_m) rem (clk2_mult * i_n) /= 0) or
|
| 448 |
|
|
((clk3_div * i_m) rem (clk3_mult * i_n) /= 0) or
|
| 449 |
|
|
((clk4_div * i_m) rem (clk4_mult * i_n) /= 0) or
|
| 450 |
|
|
((clk5_div * i_m) rem (clk5_mult * i_n) /= 0) or
|
| 451 |
|
|
((clk6_div * i_m) rem (clk6_mult * i_n) /= 0) or
|
| 452 |
|
|
((clk7_div * i_m) rem (clk7_mult * i_n) /= 0) or
|
| 453 |
|
|
((clk8_div * i_m) rem (clk8_mult * i_n) /= 0) or
|
| 454 |
|
|
((clk9_div * i_m) rem (clk9_mult * i_n) /= 0) )
|
| 455 |
|
|
then
|
| 456 |
|
|
if (loop_iter = 1)
|
| 457 |
|
|
then
|
| 458 |
|
|
n := 1;
|
| 459 |
|
|
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
|
| 460 |
|
|
clk4_mult, clk5_mult, clk6_mult,
|
| 461 |
|
|
clk7_mult, clk8_mult, clk9_mult, inclock_period);
|
| 462 |
|
|
else
|
| 463 |
|
|
m := i_pre_m;
|
| 464 |
|
|
n := i_pre_n;
|
| 465 |
|
|
end if;
|
| 466 |
|
|
|
| 467 |
|
|
i_max_iter := loop_iter;
|
| 468 |
|
|
else
|
| 469 |
|
|
m := i_m;
|
| 470 |
|
|
n := i_n;
|
| 471 |
|
|
end if;
|
| 472 |
|
|
|
| 473 |
|
|
pfd_freq := 1000000 / (inclock_period * i_n);
|
| 474 |
|
|
vco_freq := (1000000 * i_m) / (inclock_period * i_n);
|
| 475 |
|
|
vco_ps_step_value := (inclock_period * i_n) / (8 * i_m);
|
| 476 |
|
|
|
| 477 |
|
|
if ( (i_m < max_m) and (i_n < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
|
| 478 |
|
|
(vco_freq >= min_vco) and (vco_freq <= max_vco) and
|
| 479 |
|
|
(abs(vco_ps_step_value - vco_phase_shift_step) <= 2) )
|
| 480 |
|
|
then
|
| 481 |
|
|
i_max_iter := loop_iter;
|
| 482 |
|
|
end if;
|
| 483 |
|
|
end loop;
|
| 484 |
|
|
end find_m_and_n_4_manual_phase;
|
| 485 |
|
|
|
| 486 |
|
|
-- find the greatest common denominator of X and Y
|
| 487 |
|
|
function gcd (X: integer; Y: integer) return integer is
|
| 488 |
|
|
variable L, S, R, G : integer := 1;
|
| 489 |
|
|
begin
|
| 490 |
|
|
if (X < Y) then -- find which is smaller.
|
| 491 |
|
|
S := X;
|
| 492 |
|
|
L := Y;
|
| 493 |
|
|
else
|
| 494 |
|
|
S := Y;
|
| 495 |
|
|
L := X;
|
| 496 |
|
|
end if;
|
| 497 |
|
|
|
| 498 |
|
|
R := S;
|
| 499 |
|
|
while ( R > 1) loop
|
| 500 |
|
|
S := L;
|
| 501 |
|
|
L := R;
|
| 502 |
|
|
R := S rem L; -- divide bigger number by smaller.
|
| 503 |
|
|
-- remainder becomes smaller number.
|
| 504 |
|
|
end loop;
|
| 505 |
|
|
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
|
| 506 |
|
|
G := L;
|
| 507 |
|
|
else
|
| 508 |
|
|
G := R;
|
| 509 |
|
|
end if;
|
| 510 |
|
|
|
| 511 |
|
|
return G;
|
| 512 |
|
|
end gcd;
|
| 513 |
|
|
|
| 514 |
|
|
-- count the number of digits in the given integer
|
| 515 |
|
|
function count_digit (X: integer)
|
| 516 |
|
|
return integer is
|
| 517 |
|
|
variable count, result: integer := 0;
|
| 518 |
|
|
begin
|
| 519 |
|
|
result := X;
|
| 520 |
|
|
while (result /= 0) loop
|
| 521 |
|
|
result := (result / 10);
|
| 522 |
|
|
count := count + 1;
|
| 523 |
|
|
end loop;
|
| 524 |
|
|
|
| 525 |
|
|
return count;
|
| 526 |
|
|
end count_digit;
|
| 527 |
|
|
|
| 528 |
|
|
-- reduce the given huge number to Y significant digits
|
| 529 |
|
|
function scale_num (X: integer; Y: integer)
|
| 530 |
|
|
return integer is
|
| 531 |
|
|
variable count : integer := 0;
|
| 532 |
|
|
variable lc, fac_ten, result: integer := 1;
|
| 533 |
|
|
begin
|
| 534 |
|
|
count := count_digit(X);
|
| 535 |
|
|
|
| 536 |
|
|
for lc in 1 to (count-Y) loop
|
| 537 |
|
|
fac_ten := fac_ten * 10;
|
| 538 |
|
|
end loop;
|
| 539 |
|
|
|
| 540 |
|
|
result := (X / fac_ten);
|
| 541 |
|
|
|
| 542 |
|
|
return result;
|
| 543 |
|
|
end scale_num;
|
| 544 |
|
|
|
| 545 |
|
|
-- find the least common multiple of A1 to A10
|
| 546 |
|
|
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
|
| 547 |
|
|
A5: integer; A6: integer; A7: integer;
|
| 548 |
|
|
A8: integer; A9: integer; A10: integer; P: integer)
|
| 549 |
|
|
return integer is
|
| 550 |
|
|
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
|
| 551 |
|
|
begin
|
| 552 |
|
|
M1 := (A1 * A2)/gcd(A1, A2);
|
| 553 |
|
|
M2 := (M1 * A3)/gcd(M1, A3);
|
| 554 |
|
|
M3 := (M2 * A4)/gcd(M2, A4);
|
| 555 |
|
|
M4 := (M3 * A5)/gcd(M3, A5);
|
| 556 |
|
|
M5 := (M4 * A6)/gcd(M4, A6);
|
| 557 |
|
|
M6 := (M5 * A7)/gcd(M5, A7);
|
| 558 |
|
|
M7 := (M6 * A8)/gcd(M6, A8);
|
| 559 |
|
|
M8 := (M7 * A9)/gcd(M7, A9);
|
| 560 |
|
|
M9 := (M8 * A10)/gcd(M8, A10);
|
| 561 |
|
|
if (M9 < 3) then
|
| 562 |
|
|
R := 10;
|
| 563 |
|
|
elsif (M9 = 3) then
|
| 564 |
|
|
R := 9;
|
| 565 |
|
|
elsif ((M9 <= 10) and (M9 > 3)) then
|
| 566 |
|
|
R := 4 * M9;
|
| 567 |
|
|
elsif (M9 > 1000) then
|
| 568 |
|
|
R := scale_num(M9,3);
|
| 569 |
|
|
else
|
| 570 |
|
|
R := M9 ;
|
| 571 |
|
|
end if;
|
| 572 |
|
|
|
| 573 |
|
|
return R;
|
| 574 |
|
|
end lcm;
|
| 575 |
|
|
|
| 576 |
|
|
-- find the factor of division of the output clock frequency compared to the VCO
|
| 577 |
|
|
function output_counter_value (clk_divide: integer; clk_mult: integer ;
|
| 578 |
|
|
M: integer; N: integer ) return integer is
|
| 579 |
|
|
variable R: integer := 1;
|
| 580 |
|
|
begin
|
| 581 |
|
|
R := (clk_divide * M)/(clk_mult * N);
|
| 582 |
|
|
|
| 583 |
|
|
return R;
|
| 584 |
|
|
end output_counter_value;
|
| 585 |
|
|
|
| 586 |
|
|
-- find the mode of each PLL counter - bypass, even or odd
|
| 587 |
|
|
function counter_mode (duty_cycle: integer; output_counter_value: integer)
|
| 588 |
|
|
return string is
|
| 589 |
|
|
variable R: string (1 to 6) := " ";
|
| 590 |
|
|
variable counter_value: integer := 1;
|
| 591 |
|
|
begin
|
| 592 |
|
|
counter_value := (2*duty_cycle*output_counter_value)/100;
|
| 593 |
|
|
if output_counter_value = 1 then
|
| 594 |
|
|
R := "bypass";
|
| 595 |
|
|
elsif (counter_value REM 2) = 0 then
|
| 596 |
|
|
R := " even";
|
| 597 |
|
|
else
|
| 598 |
|
|
R := " odd";
|
| 599 |
|
|
end if;
|
| 600 |
|
|
|
| 601 |
|
|
return R;
|
| 602 |
|
|
end counter_mode;
|
| 603 |
|
|
|
| 604 |
|
|
-- find the number of VCO clock cycles to hold the output clock high
|
| 605 |
|
|
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
|
| 606 |
|
|
return integer is
|
| 607 |
|
|
variable R: integer := 1;
|
| 608 |
|
|
variable half_cycle_high : integer := 1;
|
| 609 |
|
|
begin
|
| 610 |
|
|
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
|
| 611 |
|
|
if (half_cycle_high REM 2 = 0) then
|
| 612 |
|
|
R := half_cycle_high/2 ;
|
| 613 |
|
|
else
|
| 614 |
|
|
R := (half_cycle_high/2) + 1;
|
| 615 |
|
|
end if;
|
| 616 |
|
|
|
| 617 |
|
|
return R;
|
| 618 |
|
|
end;
|
| 619 |
|
|
|
| 620 |
|
|
-- find the number of VCO clock cycles to hold the output clock low
|
| 621 |
|
|
function counter_low (output_counter_value: integer; duty_cycle: integer)
|
| 622 |
|
|
return integer is
|
| 623 |
|
|
variable R, R1: integer := 1;
|
| 624 |
|
|
variable half_cycle_high : integer := 1;
|
| 625 |
|
|
begin
|
| 626 |
|
|
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
|
| 627 |
|
|
if (half_cycle_high REM 2 = 0) then
|
| 628 |
|
|
R1 := half_cycle_high/2 ;
|
| 629 |
|
|
else
|
| 630 |
|
|
R1 := (half_cycle_high/2) + 1;
|
| 631 |
|
|
end if;
|
| 632 |
|
|
|
| 633 |
|
|
R := output_counter_value - R1;
|
| 634 |
|
|
|
| 635 |
|
|
return R;
|
| 636 |
|
|
end;
|
| 637 |
|
|
|
| 638 |
|
|
-- find the smallest time delay amongst t1 to t10
|
| 639 |
|
|
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
|
| 640 |
|
|
t5: integer; t6: integer; t7: integer; t8: integer;
|
| 641 |
|
|
t9: integer; t10: integer) return integer is
|
| 642 |
|
|
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
|
| 643 |
|
|
begin
|
| 644 |
|
|
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
|
| 645 |
|
|
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
|
| 646 |
|
|
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
|
| 647 |
|
|
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
|
| 648 |
|
|
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
|
| 649 |
|
|
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
|
| 650 |
|
|
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
|
| 651 |
|
|
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
|
| 652 |
|
|
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
|
| 653 |
|
|
if (m9 > 0) then return m9; else return 0; end if;
|
| 654 |
|
|
end;
|
| 655 |
|
|
|
| 656 |
|
|
-- find the numerically largest negative number, and return its absolute value
|
| 657 |
|
|
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
|
| 658 |
|
|
t5: integer; t6: integer; t7: integer; t8: integer;
|
| 659 |
|
|
t9: integer; t10: integer) return integer is
|
| 660 |
|
|
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
|
| 661 |
|
|
begin
|
| 662 |
|
|
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
|
| 663 |
|
|
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
|
| 664 |
|
|
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
|
| 665 |
|
|
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
|
| 666 |
|
|
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
|
| 667 |
|
|
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
|
| 668 |
|
|
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
|
| 669 |
|
|
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
|
| 670 |
|
|
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
|
| 671 |
|
|
if (m9 < 0) then return (0 - m9); else return 0; end if;
|
| 672 |
|
|
end;
|
| 673 |
|
|
|
| 674 |
|
|
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
|
| 675 |
|
|
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
|
| 676 |
|
|
begin
|
| 677 |
|
|
return (tap_phase + ph_base);
|
| 678 |
|
|
end;
|
| 679 |
|
|
|
| 680 |
|
|
-- find the time delay for each PLL counter
|
| 681 |
|
|
function counter_time_delay (clk_time_delay: integer;
|
| 682 |
|
|
m_time_delay: integer; n_time_delay: integer)
|
| 683 |
|
|
return integer is
|
| 684 |
|
|
variable R: integer := 0;
|
| 685 |
|
|
begin
|
| 686 |
|
|
R := clk_time_delay + m_time_delay - n_time_delay;
|
| 687 |
|
|
|
| 688 |
|
|
return R;
|
| 689 |
|
|
end;
|
| 690 |
|
|
|
| 691 |
|
|
-- calculate the given phase shift (in ps) in terms of degrees
|
| 692 |
|
|
function get_phase_degree (phase_shift: integer; clk_period: integer)
|
| 693 |
|
|
return integer is
|
| 694 |
|
|
variable result: integer := 0;
|
| 695 |
|
|
begin
|
| 696 |
|
|
result := ( phase_shift * 360 ) / clk_period;
|
| 697 |
|
|
-- to round up the calculation result
|
| 698 |
|
|
if (result > 0) then
|
| 699 |
|
|
result := result + 1;
|
| 700 |
|
|
elsif (result < 0) then
|
| 701 |
|
|
result := result - 1;
|
| 702 |
|
|
else
|
| 703 |
|
|
result := 0;
|
| 704 |
|
|
end if;
|
| 705 |
|
|
|
| 706 |
|
|
return result;
|
| 707 |
|
|
end;
|
| 708 |
|
|
|
| 709 |
|
|
-- find the number of VCO clock cycles to wait initially before the first rising
|
| 710 |
|
|
-- edge of the output clock
|
| 711 |
|
|
function counter_initial (tap_phase: integer; m: integer; n: integer)
|
| 712 |
|
|
return integer is
|
| 713 |
|
|
variable R: integer;
|
| 714 |
|
|
variable R1: real;
|
| 715 |
|
|
begin
|
| 716 |
|
|
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.5;
|
| 717 |
|
|
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
|
| 718 |
|
|
-- This checking will ensure that the rounding up is done.
|
| 719 |
|
|
if (R1 >= 0.5) and (R1 <= 1.0) then
|
| 720 |
|
|
R1 := 1.0;
|
| 721 |
|
|
end if;
|
| 722 |
|
|
|
| 723 |
|
|
R := integer(R1);
|
| 724 |
|
|
|
| 725 |
|
|
return R;
|
| 726 |
|
|
end;
|
| 727 |
|
|
|
| 728 |
|
|
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
|
| 729 |
|
|
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
|
| 730 |
|
|
variable R: integer := 0;
|
| 731 |
|
|
begin
|
| 732 |
|
|
-- 0.5 is added for proper rounding of the tap_phase.
|
| 733 |
|
|
R := (integer(real(tap_phase * m / n)+ 0.5) REM 360)/45;
|
| 734 |
|
|
|
| 735 |
|
|
return R;
|
| 736 |
|
|
end;
|
| 737 |
|
|
|
| 738 |
|
|
-- convert given string to length 6 by padding with spaces
|
| 739 |
|
|
function translate_string (mode : string) return string is
|
| 740 |
|
|
variable new_mode : string (1 to 6) := " ";
|
| 741 |
|
|
begin
|
| 742 |
|
|
if (mode = "bypass") then
|
| 743 |
|
|
new_mode := "bypass";
|
| 744 |
|
|
elsif (mode = "even") then
|
| 745 |
|
|
new_mode := " even";
|
| 746 |
|
|
elsif (mode = "odd") then
|
| 747 |
|
|
new_mode := " odd";
|
| 748 |
|
|
end if;
|
| 749 |
|
|
|
| 750 |
|
|
return new_mode;
|
| 751 |
|
|
end;
|
| 752 |
|
|
|
| 753 |
|
|
function str2int (s : string) return integer is
|
| 754 |
|
|
variable len : integer := s'length;
|
| 755 |
|
|
variable newdigit : integer := 0;
|
| 756 |
|
|
variable sign : integer := 1;
|
| 757 |
|
|
variable digit : integer := 0;
|
| 758 |
|
|
begin
|
| 759 |
|
|
for i in 1 to len loop
|
| 760 |
|
|
case s(i) is
|
| 761 |
|
|
when '-' =>
|
| 762 |
|
|
if i = 1 then
|
| 763 |
|
|
sign := -1;
|
| 764 |
|
|
else
|
| 765 |
|
|
ASSERT FALSE
|
| 766 |
|
|
REPORT "Illegal Character "& s(i) & "i n string parameter! "
|
| 767 |
|
|
SEVERITY ERROR;
|
| 768 |
|
|
end if;
|
| 769 |
|
|
when '0' =>
|
| 770 |
|
|
digit := 0;
|
| 771 |
|
|
when '1' =>
|
| 772 |
|
|
digit := 1;
|
| 773 |
|
|
when '2' =>
|
| 774 |
|
|
digit := 2;
|
| 775 |
|
|
when '3' =>
|
| 776 |
|
|
digit := 3;
|
| 777 |
|
|
when '4' =>
|
| 778 |
|
|
digit := 4;
|
| 779 |
|
|
when '5' =>
|
| 780 |
|
|
digit := 5;
|
| 781 |
|
|
when '6' =>
|
| 782 |
|
|
digit := 6;
|
| 783 |
|
|
when '7' =>
|
| 784 |
|
|
digit := 7;
|
| 785 |
|
|
when '8' =>
|
| 786 |
|
|
digit := 8;
|
| 787 |
|
|
when '9' =>
|
| 788 |
|
|
digit := 9;
|
| 789 |
|
|
when others =>
|
| 790 |
|
|
ASSERT FALSE
|
| 791 |
|
|
REPORT "Illegal Character "& s(i) & "in string parameter! "
|
| 792 |
|
|
SEVERITY ERROR;
|
| 793 |
|
|
end case;
|
| 794 |
|
|
newdigit := newdigit * 10 + digit;
|
| 795 |
|
|
end loop;
|
| 796 |
|
|
|
| 797 |
|
|
return (sign*newdigit);
|
| 798 |
|
|
end;
|
| 799 |
|
|
|
| 800 |
|
|
function dqs_str2int (s : string) return integer is
|
| 801 |
|
|
variable len : integer := s'length;
|
| 802 |
|
|
variable newdigit : integer := 0;
|
| 803 |
|
|
variable sign : integer := 1;
|
| 804 |
|
|
variable digit : integer := 0;
|
| 805 |
|
|
variable err : boolean := false;
|
| 806 |
|
|
begin
|
| 807 |
|
|
for i in 1 to len loop
|
| 808 |
|
|
case s(i) is
|
| 809 |
|
|
when '-' =>
|
| 810 |
|
|
if i = 1 then
|
| 811 |
|
|
sign := -1;
|
| 812 |
|
|
else
|
| 813 |
|
|
ASSERT FALSE
|
| 814 |
|
|
REPORT "Illegal Character "& s(i) & " in string parameter! "
|
| 815 |
|
|
SEVERITY ERROR;
|
| 816 |
|
|
err := true;
|
| 817 |
|
|
end if;
|
| 818 |
|
|
when '0' =>
|
| 819 |
|
|
digit := 0;
|
| 820 |
|
|
when '1' =>
|
| 821 |
|
|
digit := 1;
|
| 822 |
|
|
when '2' =>
|
| 823 |
|
|
digit := 2;
|
| 824 |
|
|
when '3' =>
|
| 825 |
|
|
digit := 3;
|
| 826 |
|
|
when '4' =>
|
| 827 |
|
|
digit := 4;
|
| 828 |
|
|
when '5' =>
|
| 829 |
|
|
digit := 5;
|
| 830 |
|
|
when '6' =>
|
| 831 |
|
|
digit := 6;
|
| 832 |
|
|
when '7' =>
|
| 833 |
|
|
digit := 7;
|
| 834 |
|
|
when '8' =>
|
| 835 |
|
|
digit := 8;
|
| 836 |
|
|
when '9' =>
|
| 837 |
|
|
digit := 9;
|
| 838 |
|
|
when others =>
|
| 839 |
|
|
-- set error flag
|
| 840 |
|
|
err := true;
|
| 841 |
|
|
end case;
|
| 842 |
|
|
if (err) then
|
| 843 |
|
|
err := false;
|
| 844 |
|
|
else
|
| 845 |
|
|
newdigit := newdigit * 10 + digit;
|
| 846 |
|
|
end if;
|
| 847 |
|
|
end loop;
|
| 848 |
|
|
|
| 849 |
|
|
return (sign*newdigit);
|
| 850 |
|
|
end;
|
| 851 |
|
|
|
| 852 |
|
|
end stratixiii_pllpack;
|
| 853 |
|
|
|
| 854 |
|
|
--
|
| 855 |
|
|
--
|
| 856 |
|
|
-- DFFE Model
|
| 857 |
|
|
--
|
| 858 |
|
|
--
|
| 859 |
|
|
|
| 860 |
|
|
LIBRARY IEEE;
|
| 861 |
|
|
use IEEE.STD_LOGIC_1164.all;
|
| 862 |
|
|
use IEEE.VITAL_Timing.all;
|
| 863 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 864 |
|
|
use work.stratixiii_atom_pack.all;
|
| 865 |
|
|
|
| 866 |
|
|
entity stratixiii_dffe is
|
| 867 |
|
|
generic(
|
| 868 |
|
|
TimingChecksOn: Boolean := True;
|
| 869 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 870 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 871 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 872 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 873 |
|
|
InstancePath: STRING := "*";
|
| 874 |
|
|
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 875 |
|
|
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 876 |
|
|
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 877 |
|
|
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 878 |
|
|
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 879 |
|
|
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 880 |
|
|
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 881 |
|
|
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 882 |
|
|
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 883 |
|
|
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 884 |
|
|
tipd_D : VitalDelayType01 := DefPropDelay01;
|
| 885 |
|
|
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
|
| 886 |
|
|
tipd_PRN : VitalDelayType01 := DefPropDelay01;
|
| 887 |
|
|
tipd_CLK : VitalDelayType01 := DefPropDelay01;
|
| 888 |
|
|
tipd_ENA : VitalDelayType01 := DefPropDelay01);
|
| 889 |
|
|
|
| 890 |
|
|
port(
|
| 891 |
|
|
Q : out STD_LOGIC := '0';
|
| 892 |
|
|
D : in STD_LOGIC;
|
| 893 |
|
|
CLRN : in STD_LOGIC;
|
| 894 |
|
|
PRN : in STD_LOGIC;
|
| 895 |
|
|
CLK : in STD_LOGIC;
|
| 896 |
|
|
ENA : in STD_LOGIC);
|
| 897 |
|
|
attribute VITAL_LEVEL0 of stratixiii_dffe : entity is TRUE;
|
| 898 |
|
|
end stratixiii_dffe;
|
| 899 |
|
|
|
| 900 |
|
|
-- architecture body --
|
| 901 |
|
|
|
| 902 |
|
|
architecture behave of stratixiii_dffe is
|
| 903 |
|
|
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
|
| 904 |
|
|
|
| 905 |
|
|
signal D_ipd : STD_ULOGIC := 'U';
|
| 906 |
|
|
signal CLRN_ipd : STD_ULOGIC := 'U';
|
| 907 |
|
|
signal PRN_ipd : STD_ULOGIC := 'U';
|
| 908 |
|
|
signal CLK_ipd : STD_ULOGIC := 'U';
|
| 909 |
|
|
signal ENA_ipd : STD_ULOGIC := 'U';
|
| 910 |
|
|
|
| 911 |
|
|
begin
|
| 912 |
|
|
|
| 913 |
|
|
---------------------
|
| 914 |
|
|
-- INPUT PATH DELAYs
|
| 915 |
|
|
---------------------
|
| 916 |
|
|
WireDelay : block
|
| 917 |
|
|
begin
|
| 918 |
|
|
VitalWireDelay (D_ipd, D, tipd_D);
|
| 919 |
|
|
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
|
| 920 |
|
|
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
|
| 921 |
|
|
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
|
| 922 |
|
|
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
|
| 923 |
|
|
end block;
|
| 924 |
|
|
--------------------
|
| 925 |
|
|
-- BEHAVIOR SECTION
|
| 926 |
|
|
--------------------
|
| 927 |
|
|
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
|
| 928 |
|
|
|
| 929 |
|
|
-- timing check results
|
| 930 |
|
|
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
|
| 931 |
|
|
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
|
| 932 |
|
|
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
|
| 933 |
|
|
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
|
| 934 |
|
|
|
| 935 |
|
|
-- functionality results
|
| 936 |
|
|
VARIABLE Violation : STD_ULOGIC := '0';
|
| 937 |
|
|
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
|
| 938 |
|
|
VARIABLE D_delayed : STD_ULOGIC := 'U';
|
| 939 |
|
|
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
|
| 940 |
|
|
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
|
| 941 |
|
|
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
|
| 942 |
|
|
|
| 943 |
|
|
-- output glitch detection variables
|
| 944 |
|
|
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
|
| 945 |
|
|
|
| 946 |
|
|
|
| 947 |
|
|
CONSTANT dffe_Q_tab : VitalStateTableType := (
|
| 948 |
|
|
( L, L, x, x, x, x, x, x, x, L ),
|
| 949 |
|
|
( L, H, L, H, H, x, x, H, x, H ),
|
| 950 |
|
|
( L, H, L, H, x, L, x, H, x, H ),
|
| 951 |
|
|
( L, H, L, x, H, H, x, H, x, H ),
|
| 952 |
|
|
( L, H, H, x, x, x, H, x, x, S ),
|
| 953 |
|
|
( L, H, x, x, x, x, L, x, x, H ),
|
| 954 |
|
|
( L, H, x, x, x, x, H, L, x, S ),
|
| 955 |
|
|
( L, x, L, L, L, x, H, H, x, L ),
|
| 956 |
|
|
( L, x, L, L, x, L, H, H, x, L ),
|
| 957 |
|
|
( L, x, L, x, L, H, H, H, x, L ),
|
| 958 |
|
|
( L, x, x, x, x, x, x, x, x, S ));
|
| 959 |
|
|
begin
|
| 960 |
|
|
|
| 961 |
|
|
------------------------
|
| 962 |
|
|
-- Timing Check Section
|
| 963 |
|
|
------------------------
|
| 964 |
|
|
if (TimingChecksOn) then
|
| 965 |
|
|
VitalSetupHoldCheck (
|
| 966 |
|
|
Violation => Tviol_D_CLK,
|
| 967 |
|
|
TimingData => TimingData_D_CLK,
|
| 968 |
|
|
TestSignal => D_ipd,
|
| 969 |
|
|
TestSignalName => "D",
|
| 970 |
|
|
RefSignal => CLK_ipd,
|
| 971 |
|
|
RefSignalName => "CLK",
|
| 972 |
|
|
SetupHigh => tsetup_D_CLK_noedge_posedge,
|
| 973 |
|
|
SetupLow => tsetup_D_CLK_noedge_posedge,
|
| 974 |
|
|
HoldHigh => thold_D_CLK_noedge_posedge,
|
| 975 |
|
|
HoldLow => thold_D_CLK_noedge_posedge,
|
| 976 |
|
|
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
|
| 977 |
|
|
RefTransition => '/',
|
| 978 |
|
|
HeaderMsg => InstancePath & "/DFFE",
|
| 979 |
|
|
XOn => XOnChecks,
|
| 980 |
|
|
MsgOn => MsgOnChecks );
|
| 981 |
|
|
|
| 982 |
|
|
VitalSetupHoldCheck (
|
| 983 |
|
|
Violation => Tviol_ENA_CLK,
|
| 984 |
|
|
TimingData => TimingData_ENA_CLK,
|
| 985 |
|
|
TestSignal => ENA_ipd,
|
| 986 |
|
|
TestSignalName => "ENA",
|
| 987 |
|
|
RefSignal => CLK_ipd,
|
| 988 |
|
|
RefSignalName => "CLK",
|
| 989 |
|
|
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
|
| 990 |
|
|
SetupLow => tsetup_ENA_CLK_noedge_posedge,
|
| 991 |
|
|
HoldHigh => thold_ENA_CLK_noedge_posedge,
|
| 992 |
|
|
HoldLow => thold_ENA_CLK_noedge_posedge,
|
| 993 |
|
|
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
|
| 994 |
|
|
RefTransition => '/',
|
| 995 |
|
|
HeaderMsg => InstancePath & "/DFFE",
|
| 996 |
|
|
XOn => XOnChecks,
|
| 997 |
|
|
MsgOn => MsgOnChecks );
|
| 998 |
|
|
end if;
|
| 999 |
|
|
|
| 1000 |
|
|
-------------------------
|
| 1001 |
|
|
-- Functionality Section
|
| 1002 |
|
|
-------------------------
|
| 1003 |
|
|
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
|
| 1004 |
|
|
VitalStateTable(
|
| 1005 |
|
|
StateTable => dffe_Q_tab,
|
| 1006 |
|
|
DataIn => (
|
| 1007 |
|
|
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
|
| 1008 |
|
|
Result => Results,
|
| 1009 |
|
|
NumStates => 1,
|
| 1010 |
|
|
PreviousDataIn => PrevData_Q);
|
| 1011 |
|
|
D_delayed := D_ipd;
|
| 1012 |
|
|
CLK_delayed := CLK_ipd;
|
| 1013 |
|
|
ENA_delayed := ENA_ipd;
|
| 1014 |
|
|
|
| 1015 |
|
|
----------------------
|
| 1016 |
|
|
-- Path Delay Section
|
| 1017 |
|
|
----------------------
|
| 1018 |
|
|
VitalPathDelay01 (
|
| 1019 |
|
|
OutSignal => Q,
|
| 1020 |
|
|
OutSignalName => "Q",
|
| 1021 |
|
|
OutTemp => Results(1),
|
| 1022 |
|
|
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
|
| 1023 |
|
|
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
|
| 1024 |
|
|
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
|
| 1025 |
|
|
GlitchData => Q_VitalGlitchData,
|
| 1026 |
|
|
Mode => DefGlitchMode,
|
| 1027 |
|
|
XOn => XOn,
|
| 1028 |
|
|
MsgOn => MsgOn );
|
| 1029 |
|
|
|
| 1030 |
|
|
end process;
|
| 1031 |
|
|
|
| 1032 |
|
|
end behave;
|
| 1033 |
|
|
|
| 1034 |
|
|
--
|
| 1035 |
|
|
--
|
| 1036 |
|
|
-- stratixiii_mux21 Model
|
| 1037 |
|
|
--
|
| 1038 |
|
|
--
|
| 1039 |
|
|
|
| 1040 |
|
|
LIBRARY IEEE;
|
| 1041 |
|
|
use ieee.std_logic_1164.all;
|
| 1042 |
|
|
use IEEE.VITAL_Timing.all;
|
| 1043 |
|
|
use work.stratixiii_atom_pack.all;
|
| 1044 |
|
|
|
| 1045 |
|
|
entity stratixiii_mux21 is
|
| 1046 |
|
|
generic(
|
| 1047 |
|
|
TimingChecksOn: Boolean := True;
|
| 1048 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 1049 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 1050 |
|
|
InstancePath: STRING := "*";
|
| 1051 |
|
|
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
|
| 1052 |
|
|
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
|
| 1053 |
|
|
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
|
| 1054 |
|
|
tipd_A : VitalDelayType01 := DefPropDelay01;
|
| 1055 |
|
|
tipd_B : VitalDelayType01 := DefPropDelay01;
|
| 1056 |
|
|
tipd_S : VitalDelayType01 := DefPropDelay01);
|
| 1057 |
|
|
port (
|
| 1058 |
|
|
A : in std_logic := '0';
|
| 1059 |
|
|
B : in std_logic := '0';
|
| 1060 |
|
|
S : in std_logic := '0';
|
| 1061 |
|
|
MO : out std_logic);
|
| 1062 |
|
|
attribute VITAL_LEVEL0 of stratixiii_mux21 : entity is TRUE;
|
| 1063 |
|
|
end stratixiii_mux21;
|
| 1064 |
|
|
|
| 1065 |
|
|
architecture AltVITAL of stratixiii_mux21 is
|
| 1066 |
|
|
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
|
| 1067 |
|
|
|
| 1068 |
|
|
signal A_ipd, B_ipd, S_ipd : std_logic;
|
| 1069 |
|
|
|
| 1070 |
|
|
begin
|
| 1071 |
|
|
|
| 1072 |
|
|
---------------------
|
| 1073 |
|
|
-- INPUT PATH DELAYs
|
| 1074 |
|
|
---------------------
|
| 1075 |
|
|
WireDelay : block
|
| 1076 |
|
|
begin
|
| 1077 |
|
|
VitalWireDelay (A_ipd, A, tipd_A);
|
| 1078 |
|
|
VitalWireDelay (B_ipd, B, tipd_B);
|
| 1079 |
|
|
VitalWireDelay (S_ipd, S, tipd_S);
|
| 1080 |
|
|
end block;
|
| 1081 |
|
|
|
| 1082 |
|
|
--------------------
|
| 1083 |
|
|
-- BEHAVIOR SECTION
|
| 1084 |
|
|
--------------------
|
| 1085 |
|
|
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
|
| 1086 |
|
|
|
| 1087 |
|
|
-- output glitch detection variables
|
| 1088 |
|
|
VARIABLE MO_GlitchData : VitalGlitchDataType;
|
| 1089 |
|
|
|
| 1090 |
|
|
variable tmp_MO : std_logic;
|
| 1091 |
|
|
begin
|
| 1092 |
|
|
-------------------------
|
| 1093 |
|
|
-- Functionality Section
|
| 1094 |
|
|
-------------------------
|
| 1095 |
|
|
if (S_ipd = '1') then
|
| 1096 |
|
|
tmp_MO := B_ipd;
|
| 1097 |
|
|
else
|
| 1098 |
|
|
tmp_MO := A_ipd;
|
| 1099 |
|
|
end if;
|
| 1100 |
|
|
|
| 1101 |
|
|
----------------------
|
| 1102 |
|
|
-- Path Delay Section
|
| 1103 |
|
|
----------------------
|
| 1104 |
|
|
VitalPathDelay01 (
|
| 1105 |
|
|
OutSignal => MO,
|
| 1106 |
|
|
OutSignalName => "MO",
|
| 1107 |
|
|
OutTemp => tmp_MO,
|
| 1108 |
|
|
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
|
| 1109 |
|
|
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
|
| 1110 |
|
|
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
|
| 1111 |
|
|
GlitchData => MO_GlitchData,
|
| 1112 |
|
|
Mode => DefGlitchMode,
|
| 1113 |
|
|
XOn => XOn,
|
| 1114 |
|
|
MsgOn => MsgOn );
|
| 1115 |
|
|
|
| 1116 |
|
|
end process;
|
| 1117 |
|
|
end AltVITAL;
|
| 1118 |
|
|
|
| 1119 |
|
|
--
|
| 1120 |
|
|
--
|
| 1121 |
|
|
-- stratixiii_mux41 Model
|
| 1122 |
|
|
--
|
| 1123 |
|
|
--
|
| 1124 |
|
|
|
| 1125 |
|
|
LIBRARY IEEE;
|
| 1126 |
|
|
use ieee.std_logic_1164.all;
|
| 1127 |
|
|
use IEEE.VITAL_Timing.all;
|
| 1128 |
|
|
use work.stratixiii_atom_pack.all;
|
| 1129 |
|
|
|
| 1130 |
|
|
entity stratixiii_mux41 is
|
| 1131 |
|
|
generic(
|
| 1132 |
|
|
TimingChecksOn: Boolean := True;
|
| 1133 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 1134 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 1135 |
|
|
InstancePath: STRING := "*";
|
| 1136 |
|
|
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
|
| 1137 |
|
|
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
|
| 1138 |
|
|
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
|
| 1139 |
|
|
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
|
| 1140 |
|
|
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
|
| 1141 |
|
|
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
|
| 1142 |
|
|
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
|
| 1143 |
|
|
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
|
| 1144 |
|
|
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
|
| 1145 |
|
|
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
|
| 1146 |
|
|
);
|
| 1147 |
|
|
port (
|
| 1148 |
|
|
IN0 : in std_logic := '0';
|
| 1149 |
|
|
IN1 : in std_logic := '0';
|
| 1150 |
|
|
IN2 : in std_logic := '0';
|
| 1151 |
|
|
IN3 : in std_logic := '0';
|
| 1152 |
|
|
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
|
| 1153 |
|
|
MO : out std_logic
|
| 1154 |
|
|
);
|
| 1155 |
|
|
attribute VITAL_LEVEL0 of stratixiii_mux41 : entity is TRUE;
|
| 1156 |
|
|
end stratixiii_mux41;
|
| 1157 |
|
|
|
| 1158 |
|
|
architecture AltVITAL of stratixiii_mux41 is
|
| 1159 |
|
|
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
|
| 1160 |
|
|
|
| 1161 |
|
|
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
|
| 1162 |
|
|
signal S_ipd : std_logic_vector(1 downto 0);
|
| 1163 |
|
|
|
| 1164 |
|
|
begin
|
| 1165 |
|
|
|
| 1166 |
|
|
---------------------
|
| 1167 |
|
|
-- INPUT PATH DELAYs
|
| 1168 |
|
|
---------------------
|
| 1169 |
|
|
WireDelay : block
|
| 1170 |
|
|
begin
|
| 1171 |
|
|
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
|
| 1172 |
|
|
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
|
| 1173 |
|
|
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
|
| 1174 |
|
|
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
|
| 1175 |
|
|
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
|
| 1176 |
|
|
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
|
| 1177 |
|
|
end block;
|
| 1178 |
|
|
|
| 1179 |
|
|
--------------------
|
| 1180 |
|
|
-- BEHAVIOR SECTION
|
| 1181 |
|
|
--------------------
|
| 1182 |
|
|
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
|
| 1183 |
|
|
|
| 1184 |
|
|
-- output glitch detection variables
|
| 1185 |
|
|
VARIABLE MO_GlitchData : VitalGlitchDataType;
|
| 1186 |
|
|
|
| 1187 |
|
|
variable tmp_MO : std_logic;
|
| 1188 |
|
|
begin
|
| 1189 |
|
|
-------------------------
|
| 1190 |
|
|
-- Functionality Section
|
| 1191 |
|
|
-------------------------
|
| 1192 |
|
|
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
|
| 1193 |
|
|
tmp_MO := IN3_ipd;
|
| 1194 |
|
|
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
|
| 1195 |
|
|
tmp_MO := IN2_ipd;
|
| 1196 |
|
|
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
|
| 1197 |
|
|
tmp_MO := IN1_ipd;
|
| 1198 |
|
|
else
|
| 1199 |
|
|
tmp_MO := IN0_ipd;
|
| 1200 |
|
|
end if;
|
| 1201 |
|
|
|
| 1202 |
|
|
----------------------
|
| 1203 |
|
|
-- Path Delay Section
|
| 1204 |
|
|
----------------------
|
| 1205 |
|
|
VitalPathDelay01 (
|
| 1206 |
|
|
OutSignal => MO,
|
| 1207 |
|
|
OutSignalName => "MO",
|
| 1208 |
|
|
OutTemp => tmp_MO,
|
| 1209 |
|
|
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
|
| 1210 |
|
|
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
|
| 1211 |
|
|
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
|
| 1212 |
|
|
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
|
| 1213 |
|
|
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
|
| 1214 |
|
|
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
|
| 1215 |
|
|
GlitchData => MO_GlitchData,
|
| 1216 |
|
|
Mode => DefGlitchMode,
|
| 1217 |
|
|
XOn => XOn,
|
| 1218 |
|
|
MsgOn => MsgOn );
|
| 1219 |
|
|
|
| 1220 |
|
|
end process;
|
| 1221 |
|
|
end AltVITAL;
|
| 1222 |
|
|
|
| 1223 |
|
|
--
|
| 1224 |
|
|
--
|
| 1225 |
|
|
-- stratixiii_and1 Model
|
| 1226 |
|
|
--
|
| 1227 |
|
|
--
|
| 1228 |
|
|
LIBRARY IEEE;
|
| 1229 |
|
|
use IEEE.STD_LOGIC_1164.all;
|
| 1230 |
|
|
use IEEE.VITAL_Timing.all;
|
| 1231 |
|
|
use work.stratixiii_atom_pack.all;
|
| 1232 |
|
|
|
| 1233 |
|
|
-- entity declaration --
|
| 1234 |
|
|
entity stratixiii_and1 is
|
| 1235 |
|
|
generic(
|
| 1236 |
|
|
TimingChecksOn: Boolean := True;
|
| 1237 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 1238 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 1239 |
|
|
InstancePath: STRING := "*";
|
| 1240 |
|
|
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
|
| 1241 |
|
|
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
|
| 1242 |
|
|
|
| 1243 |
|
|
port(
|
| 1244 |
|
|
Y : out STD_LOGIC;
|
| 1245 |
|
|
IN1 : in STD_LOGIC);
|
| 1246 |
|
|
attribute VITAL_LEVEL0 of stratixiii_and1 : entity is TRUE;
|
| 1247 |
|
|
end stratixiii_and1;
|
| 1248 |
|
|
|
| 1249 |
|
|
-- architecture body --
|
| 1250 |
|
|
|
| 1251 |
|
|
architecture AltVITAL of stratixiii_and1 is
|
| 1252 |
|
|
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
|
| 1253 |
|
|
|
| 1254 |
|
|
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
|
| 1255 |
|
|
|
| 1256 |
|
|
begin
|
| 1257 |
|
|
|
| 1258 |
|
|
---------------------
|
| 1259 |
|
|
-- INPUT PATH DELAYs
|
| 1260 |
|
|
---------------------
|
| 1261 |
|
|
WireDelay : block
|
| 1262 |
|
|
begin
|
| 1263 |
|
|
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
|
| 1264 |
|
|
end block;
|
| 1265 |
|
|
--------------------
|
| 1266 |
|
|
-- BEHAVIOR SECTION
|
| 1267 |
|
|
--------------------
|
| 1268 |
|
|
VITALBehavior : process (IN1_ipd)
|
| 1269 |
|
|
|
| 1270 |
|
|
|
| 1271 |
|
|
-- functionality results
|
| 1272 |
|
|
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
|
| 1273 |
|
|
ALIAS Y_zd : STD_ULOGIC is Results(1);
|
| 1274 |
|
|
|
| 1275 |
|
|
-- output glitch detection variables
|
| 1276 |
|
|
VARIABLE Y_GlitchData : VitalGlitchDataType;
|
| 1277 |
|
|
|
| 1278 |
|
|
begin
|
| 1279 |
|
|
|
| 1280 |
|
|
-------------------------
|
| 1281 |
|
|
-- Functionality Section
|
| 1282 |
|
|
-------------------------
|
| 1283 |
|
|
Y_zd := TO_X01(IN1_ipd);
|
| 1284 |
|
|
|
| 1285 |
|
|
----------------------
|
| 1286 |
|
|
-- Path Delay Section
|
| 1287 |
|
|
----------------------
|
| 1288 |
|
|
VitalPathDelay01 (
|
| 1289 |
|
|
OutSignal => Y,
|
| 1290 |
|
|
OutSignalName => "Y",
|
| 1291 |
|
|
OutTemp => Y_zd,
|
| 1292 |
|
|
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
|
| 1293 |
|
|
GlitchData => Y_GlitchData,
|
| 1294 |
|
|
Mode => DefGlitchMode,
|
| 1295 |
|
|
XOn => XOn,
|
| 1296 |
|
|
MsgOn => MsgOn );
|
| 1297 |
|
|
|
| 1298 |
|
|
end process;
|
| 1299 |
|
|
end AltVITAL;
|
| 1300 |
|
|
-------------------------------------------------------------------
|
| 1301 |
|
|
--
|
| 1302 |
|
|
-- Entity Name : stratixiii_jtag
|
| 1303 |
|
|
--
|
| 1304 |
|
|
-- Description : Stratix JTAG VHDL Simulation model
|
| 1305 |
|
|
--
|
| 1306 |
|
|
-------------------------------------------------------------------
|
| 1307 |
|
|
LIBRARY IEEE;
|
| 1308 |
|
|
use IEEE.std_logic_1164.all;
|
| 1309 |
|
|
use work.stratixiii_atom_pack.all;
|
| 1310 |
|
|
|
| 1311 |
|
|
entity stratixiii_jtag is
|
| 1312 |
|
|
generic (
|
| 1313 |
|
|
lpm_type : string := "stratixiii_jtag"
|
| 1314 |
|
|
);
|
| 1315 |
|
|
port (
|
| 1316 |
|
|
tms : in std_logic;
|
| 1317 |
|
|
tck : in std_logic;
|
| 1318 |
|
|
tdi : in std_logic;
|
| 1319 |
|
|
ntrst : in std_logic;
|
| 1320 |
|
|
tdoutap : in std_logic;
|
| 1321 |
|
|
tdouser : in std_logic;
|
| 1322 |
|
|
tdo: out std_logic;
|
| 1323 |
|
|
tmsutap: out std_logic;
|
| 1324 |
|
|
tckutap: out std_logic;
|
| 1325 |
|
|
tdiutap: out std_logic;
|
| 1326 |
|
|
shiftuser: out std_logic;
|
| 1327 |
|
|
clkdruser: out std_logic;
|
| 1328 |
|
|
updateuser: out std_logic;
|
| 1329 |
|
|
runidleuser: out std_logic;
|
| 1330 |
|
|
usr1user: out std_logic
|
| 1331 |
|
|
);
|
| 1332 |
|
|
end stratixiii_jtag;
|
| 1333 |
|
|
|
| 1334 |
|
|
architecture architecture_jtag of stratixiii_jtag is
|
| 1335 |
|
|
begin
|
| 1336 |
|
|
|
| 1337 |
|
|
end architecture_jtag;
|
| 1338 |
|
|
|
| 1339 |
|
|
-------------------------------------------------------------------
|
| 1340 |
|
|
--
|
| 1341 |
|
|
-- Entity Name : stratixiii_crcblock
|
| 1342 |
|
|
--
|
| 1343 |
|
|
-- Description : Stratix CRCBLOCK VHDL Simulation model
|
| 1344 |
|
|
--
|
| 1345 |
|
|
-------------------------------------------------------------------
|
| 1346 |
|
|
LIBRARY IEEE;
|
| 1347 |
|
|
use IEEE.std_logic_1164.all;
|
| 1348 |
|
|
use work.stratixiii_atom_pack.all;
|
| 1349 |
|
|
|
| 1350 |
|
|
entity stratixiii_crcblock is
|
| 1351 |
|
|
generic (
|
| 1352 |
|
|
oscillator_divider : integer := 1;
|
| 1353 |
|
|
lpm_type : string := "stratixiii_crcblock"
|
| 1354 |
|
|
);
|
| 1355 |
|
|
port (
|
| 1356 |
|
|
clk : in std_logic;
|
| 1357 |
|
|
shiftnld : in std_logic;
|
| 1358 |
|
|
crcerror : out std_logic;
|
| 1359 |
|
|
regout : out std_logic
|
| 1360 |
|
|
);
|
| 1361 |
|
|
end stratixiii_crcblock;
|
| 1362 |
|
|
|
| 1363 |
|
|
architecture architecture_crcblock of stratixiii_crcblock is
|
| 1364 |
|
|
begin
|
| 1365 |
|
|
|
| 1366 |
|
|
end architecture_crcblock;
|
| 1367 |
|
|
---------------------------------------------------------------------
|
| 1368 |
|
|
--
|
| 1369 |
|
|
-- Entity Name : stratixiii_lcell_comb
|
| 1370 |
|
|
--
|
| 1371 |
|
|
-- Description : Stratix III LCELL_COMB VHDL simulation model
|
| 1372 |
|
|
--
|
| 1373 |
|
|
--
|
| 1374 |
|
|
---------------------------------------------------------------------
|
| 1375 |
|
|
|
| 1376 |
|
|
LIBRARY IEEE;
|
| 1377 |
|
|
use IEEE.std_logic_1164.all;
|
| 1378 |
|
|
use IEEE.VITAL_Timing.all;
|
| 1379 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 1380 |
|
|
use work.stratixiii_atom_pack.all;
|
| 1381 |
|
|
|
| 1382 |
|
|
entity stratixiii_lcell_comb is
|
| 1383 |
|
|
generic (
|
| 1384 |
|
|
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
|
| 1385 |
|
|
shared_arith : string := "off";
|
| 1386 |
|
|
extended_lut : string := "off";
|
| 1387 |
|
|
dont_touch : string := "off";
|
| 1388 |
|
|
lpm_type : string := "stratixiii_lcell_comb";
|
| 1389 |
|
|
TimingChecksOn: Boolean := True;
|
| 1390 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 1391 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 1392 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 1393 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 1394 |
|
|
InstancePath: STRING := "*";
|
| 1395 |
|
|
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
|
| 1396 |
|
|
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
|
| 1397 |
|
|
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
|
| 1398 |
|
|
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
|
| 1399 |
|
|
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
|
| 1400 |
|
|
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
|
| 1401 |
|
|
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
|
| 1402 |
|
|
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
|
| 1403 |
|
|
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
|
| 1404 |
|
|
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
|
| 1405 |
|
|
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
|
| 1406 |
|
|
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
|
| 1407 |
|
|
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
|
| 1408 |
|
|
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
|
| 1409 |
|
|
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
|
| 1410 |
|
|
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
|
| 1411 |
|
|
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
|
| 1412 |
|
|
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
|
| 1413 |
|
|
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
|
| 1414 |
|
|
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
|
| 1415 |
|
|
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
|
| 1416 |
|
|
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
|
| 1417 |
|
|
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
|
| 1418 |
|
|
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
|
| 1419 |
|
|
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
|
| 1420 |
|
|
tipd_dataa : VitalDelayType01 := DefPropDelay01;
|
| 1421 |
|
|
tipd_datab : VitalDelayType01 := DefPropDelay01;
|
| 1422 |
|
|
tipd_datac : VitalDelayType01 := DefPropDelay01;
|
| 1423 |
|
|
tipd_datad : VitalDelayType01 := DefPropDelay01;
|
| 1424 |
|
|
tipd_datae : VitalDelayType01 := DefPropDelay01;
|
| 1425 |
|
|
tipd_dataf : VitalDelayType01 := DefPropDelay01;
|
| 1426 |
|
|
tipd_datag : VitalDelayType01 := DefPropDelay01;
|
| 1427 |
|
|
tipd_cin : VitalDelayType01 := DefPropDelay01;
|
| 1428 |
|
|
tipd_sharein : VitalDelayType01 := DefPropDelay01
|
| 1429 |
|
|
);
|
| 1430 |
|
|
|
| 1431 |
|
|
port (
|
| 1432 |
|
|
dataa : in std_logic := '0';
|
| 1433 |
|
|
datab : in std_logic := '0';
|
| 1434 |
|
|
datac : in std_logic := '0';
|
| 1435 |
|
|
datad : in std_logic := '0';
|
| 1436 |
|
|
datae : in std_logic := '0';
|
| 1437 |
|
|
dataf : in std_logic := '0';
|
| 1438 |
|
|
datag : in std_logic := '0';
|
| 1439 |
|
|
cin : in std_logic := '0';
|
| 1440 |
|
|
sharein : in std_logic := '0';
|
| 1441 |
|
|
combout : out std_logic;
|
| 1442 |
|
|
sumout : out std_logic;
|
| 1443 |
|
|
cout : out std_logic;
|
| 1444 |
|
|
shareout : out std_logic
|
| 1445 |
|
|
);
|
| 1446 |
|
|
attribute VITAL_LEVEL0 of stratixiii_lcell_comb : entity is TRUE;
|
| 1447 |
|
|
end stratixiii_lcell_comb;
|
| 1448 |
|
|
|
| 1449 |
|
|
architecture vital_lcell_comb of stratixiii_lcell_comb is
|
| 1450 |
|
|
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
|
| 1451 |
|
|
signal dataa_ipd : std_logic;
|
| 1452 |
|
|
signal datab_ipd : std_logic;
|
| 1453 |
|
|
signal datac_ipd : std_logic;
|
| 1454 |
|
|
signal datad_ipd : std_logic;
|
| 1455 |
|
|
signal datae_ipd : std_logic;
|
| 1456 |
|
|
signal dataf_ipd : std_logic;
|
| 1457 |
|
|
signal datag_ipd : std_logic;
|
| 1458 |
|
|
signal cin_ipd : std_logic;
|
| 1459 |
|
|
signal sharein_ipd : std_logic;
|
| 1460 |
|
|
signal f2_input3 : std_logic;
|
| 1461 |
|
|
-- sub masks
|
| 1462 |
|
|
signal f0_mask : std_logic_vector(15 downto 0);
|
| 1463 |
|
|
signal f1_mask : std_logic_vector(15 downto 0);
|
| 1464 |
|
|
signal f2_mask : std_logic_vector(15 downto 0);
|
| 1465 |
|
|
signal f3_mask : std_logic_vector(15 downto 0);
|
| 1466 |
|
|
begin
|
| 1467 |
|
|
|
| 1468 |
|
|
---------------------
|
| 1469 |
|
|
-- INPUT PATH DELAYs
|
| 1470 |
|
|
---------------------
|
| 1471 |
|
|
WireDelay : block
|
| 1472 |
|
|
begin
|
| 1473 |
|
|
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
|
| 1474 |
|
|
VitalWireDelay (datab_ipd, datab, tipd_datab);
|
| 1475 |
|
|
VitalWireDelay (datac_ipd, datac, tipd_datac);
|
| 1476 |
|
|
VitalWireDelay (datad_ipd, datad, tipd_datad);
|
| 1477 |
|
|
VitalWireDelay (datae_ipd, datae, tipd_datae);
|
| 1478 |
|
|
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
|
| 1479 |
|
|
VitalWireDelay (datag_ipd, datag, tipd_datag);
|
| 1480 |
|
|
VitalWireDelay (cin_ipd, cin, tipd_cin);
|
| 1481 |
|
|
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
|
| 1482 |
|
|
end block;
|
| 1483 |
|
|
|
| 1484 |
|
|
f0_mask <= lut_mask(15 downto 0);
|
| 1485 |
|
|
f1_mask <= lut_mask(31 downto 16);
|
| 1486 |
|
|
f2_mask <= lut_mask(47 downto 32);
|
| 1487 |
|
|
f3_mask <= lut_mask(63 downto 48);
|
| 1488 |
|
|
|
| 1489 |
|
|
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
|
| 1490 |
|
|
|
| 1491 |
|
|
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
|
| 1492 |
|
|
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
|
| 1493 |
|
|
sharein_ipd)
|
| 1494 |
|
|
|
| 1495 |
|
|
variable combout_VitalGlitchData : VitalGlitchDataType;
|
| 1496 |
|
|
variable sumout_VitalGlitchData : VitalGlitchDataType;
|
| 1497 |
|
|
variable cout_VitalGlitchData : VitalGlitchDataType;
|
| 1498 |
|
|
variable shareout_VitalGlitchData : VitalGlitchDataType;
|
| 1499 |
|
|
-- sub lut outputs
|
| 1500 |
|
|
variable f0_out : std_logic;
|
| 1501 |
|
|
variable f1_out : std_logic;
|
| 1502 |
|
|
variable f2_out : std_logic;
|
| 1503 |
|
|
variable f3_out : std_logic;
|
| 1504 |
|
|
-- muxed output
|
| 1505 |
|
|
variable g0_out : std_logic;
|
| 1506 |
|
|
variable g1_out : std_logic;
|
| 1507 |
|
|
-- internal variables
|
| 1508 |
|
|
variable f2_f : std_logic;
|
| 1509 |
|
|
variable adder_input2 : std_logic;
|
| 1510 |
|
|
-- output variables
|
| 1511 |
|
|
variable combout_tmp : std_logic;
|
| 1512 |
|
|
variable sumout_tmp : std_logic;
|
| 1513 |
|
|
variable cout_tmp : std_logic;
|
| 1514 |
|
|
-- temp variable for NCVHDL
|
| 1515 |
|
|
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
|
| 1516 |
|
|
|
| 1517 |
|
|
begin
|
| 1518 |
|
|
|
| 1519 |
|
|
lut_mask_var := lut_mask;
|
| 1520 |
|
|
|
| 1521 |
|
|
------------------------
|
| 1522 |
|
|
-- Timing Check Section
|
| 1523 |
|
|
------------------------
|
| 1524 |
|
|
|
| 1525 |
|
|
f0_out := VitalMUX(data => f0_mask,
|
| 1526 |
|
|
dselect => (datad_ipd,
|
| 1527 |
|
|
datac_ipd,
|
| 1528 |
|
|
datab_ipd,
|
| 1529 |
|
|
dataa_ipd));
|
| 1530 |
|
|
f1_out := VitalMUX(data => f1_mask,
|
| 1531 |
|
|
dselect => (datad_ipd,
|
| 1532 |
|
|
f2_input3,
|
| 1533 |
|
|
datab_ipd,
|
| 1534 |
|
|
dataa_ipd));
|
| 1535 |
|
|
f2_out := VitalMUX(data => f2_mask,
|
| 1536 |
|
|
dselect => (datad_ipd,
|
| 1537 |
|
|
datac_ipd,
|
| 1538 |
|
|
datab_ipd,
|
| 1539 |
|
|
dataa_ipd));
|
| 1540 |
|
|
f3_out := VitalMUX(data => f3_mask,
|
| 1541 |
|
|
dselect => (datad_ipd,
|
| 1542 |
|
|
f2_input3,
|
| 1543 |
|
|
datab_ipd,
|
| 1544 |
|
|
dataa_ipd));
|
| 1545 |
|
|
|
| 1546 |
|
|
-- combout
|
| 1547 |
|
|
if (extended_lut = "on") then
|
| 1548 |
|
|
if (datae_ipd = '0') then
|
| 1549 |
|
|
g0_out := f0_out;
|
| 1550 |
|
|
g1_out := f2_out;
|
| 1551 |
|
|
elsif (datae_ipd = '1') then
|
| 1552 |
|
|
g0_out := f1_out;
|
| 1553 |
|
|
g1_out := f3_out;
|
| 1554 |
|
|
else
|
| 1555 |
|
|
g0_out := 'X';
|
| 1556 |
|
|
g1_out := 'X';
|
| 1557 |
|
|
end if;
|
| 1558 |
|
|
|
| 1559 |
|
|
if (dataf_ipd = '0') then
|
| 1560 |
|
|
combout_tmp := g0_out;
|
| 1561 |
|
|
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
|
| 1562 |
|
|
combout_tmp := g1_out;
|
| 1563 |
|
|
else
|
| 1564 |
|
|
combout_tmp := 'X';
|
| 1565 |
|
|
end if;
|
| 1566 |
|
|
else
|
| 1567 |
|
|
combout_tmp := VitalMUX(data => lut_mask_var,
|
| 1568 |
|
|
dselect => (dataf_ipd,
|
| 1569 |
|
|
datae_ipd,
|
| 1570 |
|
|
datad_ipd,
|
| 1571 |
|
|
datac_ipd,
|
| 1572 |
|
|
datab_ipd,
|
| 1573 |
|
|
dataa_ipd));
|
| 1574 |
|
|
end if;
|
| 1575 |
|
|
|
| 1576 |
|
|
-- sumout and cout
|
| 1577 |
|
|
f2_f := VitalMUX(data => f2_mask,
|
| 1578 |
|
|
dselect => (dataf_ipd,
|
| 1579 |
|
|
datac_ipd,
|
| 1580 |
|
|
datab_ipd,
|
| 1581 |
|
|
dataa_ipd));
|
| 1582 |
|
|
|
| 1583 |
|
|
if (shared_arith = "on") then
|
| 1584 |
|
|
adder_input2 := sharein_ipd;
|
| 1585 |
|
|
else
|
| 1586 |
|
|
adder_input2 := NOT f2_f;
|
| 1587 |
|
|
end if;
|
| 1588 |
|
|
|
| 1589 |
|
|
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
|
| 1590 |
|
|
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
|
| 1591 |
|
|
(f0_out AND adder_input2);
|
| 1592 |
|
|
|
| 1593 |
|
|
----------------------
|
| 1594 |
|
|
-- Path Delay Section
|
| 1595 |
|
|
----------------------
|
| 1596 |
|
|
|
| 1597 |
|
|
VitalPathDelay01 (
|
| 1598 |
|
|
OutSignal => combout,
|
| 1599 |
|
|
OutSignalName => "COMBOUT",
|
| 1600 |
|
|
OutTemp => combout_tmp,
|
| 1601 |
|
|
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
|
| 1602 |
|
|
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
|
| 1603 |
|
|
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
|
| 1604 |
|
|
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
|
| 1605 |
|
|
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
|
| 1606 |
|
|
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
|
| 1607 |
|
|
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
|
| 1608 |
|
|
GlitchData => combout_VitalGlitchData,
|
| 1609 |
|
|
Mode => DefGlitchMode,
|
| 1610 |
|
|
XOn => XOn,
|
| 1611 |
|
|
MsgOn => MsgOn );
|
| 1612 |
|
|
|
| 1613 |
|
|
VitalPathDelay01 (
|
| 1614 |
|
|
OutSignal => sumout,
|
| 1615 |
|
|
OutSignalName => "SUMOUT",
|
| 1616 |
|
|
OutTemp => sumout_tmp,
|
| 1617 |
|
|
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
|
| 1618 |
|
|
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
|
| 1619 |
|
|
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
|
| 1620 |
|
|
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
|
| 1621 |
|
|
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
|
| 1622 |
|
|
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
|
| 1623 |
|
|
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
|
| 1624 |
|
|
GlitchData => sumout_VitalGlitchData,
|
| 1625 |
|
|
Mode => DefGlitchMode,
|
| 1626 |
|
|
XOn => XOn,
|
| 1627 |
|
|
MsgOn => MsgOn );
|
| 1628 |
|
|
|
| 1629 |
|
|
VitalPathDelay01 (
|
| 1630 |
|
|
OutSignal => cout,
|
| 1631 |
|
|
OutSignalName => "COUT",
|
| 1632 |
|
|
OutTemp => cout_tmp,
|
| 1633 |
|
|
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
|
| 1634 |
|
|
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
|
| 1635 |
|
|
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
|
| 1636 |
|
|
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
|
| 1637 |
|
|
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
|
| 1638 |
|
|
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
|
| 1639 |
|
|
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
|
| 1640 |
|
|
GlitchData => cout_VitalGlitchData,
|
| 1641 |
|
|
Mode => DefGlitchMode,
|
| 1642 |
|
|
XOn => XOn,
|
| 1643 |
|
|
MsgOn => MsgOn );
|
| 1644 |
|
|
|
| 1645 |
|
|
VitalPathDelay01 (
|
| 1646 |
|
|
OutSignal => shareout,
|
| 1647 |
|
|
OutSignalName => "SHAREOUT",
|
| 1648 |
|
|
OutTemp => f2_out,
|
| 1649 |
|
|
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
|
| 1650 |
|
|
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
|
| 1651 |
|
|
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
|
| 1652 |
|
|
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
|
| 1653 |
|
|
GlitchData => shareout_VitalGlitchData,
|
| 1654 |
|
|
Mode => DefGlitchMode,
|
| 1655 |
|
|
XOn => XOn,
|
| 1656 |
|
|
MsgOn => MsgOn );
|
| 1657 |
|
|
|
| 1658 |
|
|
end process;
|
| 1659 |
|
|
|
| 1660 |
|
|
end vital_lcell_comb;
|
| 1661 |
|
|
|
| 1662 |
|
|
|
| 1663 |
|
|
---------------------------------------------------------------------
|
| 1664 |
|
|
--
|
| 1665 |
|
|
-- Entity Name : stratixiii_routing_wire
|
| 1666 |
|
|
--
|
| 1667 |
|
|
-- Description : Stratix III Routing Wire VHDL simulation model
|
| 1668 |
|
|
--
|
| 1669 |
|
|
--
|
| 1670 |
|
|
---------------------------------------------------------------------
|
| 1671 |
|
|
|
| 1672 |
|
|
LIBRARY IEEE;
|
| 1673 |
|
|
use IEEE.std_logic_1164.all;
|
| 1674 |
|
|
use IEEE.VITAL_Timing.all;
|
| 1675 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 1676 |
|
|
use work.stratixiii_atom_pack.all;
|
| 1677 |
|
|
|
| 1678 |
|
|
ENTITY stratixiii_routing_wire is
|
| 1679 |
|
|
generic (
|
| 1680 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 1681 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 1682 |
|
|
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
|
| 1683 |
|
|
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
|
| 1684 |
|
|
tipd_datain : VitalDelayType01 := DefPropDelay01
|
| 1685 |
|
|
);
|
| 1686 |
|
|
PORT (
|
| 1687 |
|
|
datain : in std_logic;
|
| 1688 |
|
|
dataout : out std_logic
|
| 1689 |
|
|
);
|
| 1690 |
|
|
attribute VITAL_LEVEL0 of stratixiii_routing_wire : entity is TRUE;
|
| 1691 |
|
|
end stratixiii_routing_wire;
|
| 1692 |
|
|
|
| 1693 |
|
|
ARCHITECTURE behave of stratixiii_routing_wire is
|
| 1694 |
|
|
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
|
| 1695 |
|
|
signal datain_ipd : std_logic;
|
| 1696 |
|
|
signal datainglitch_inert : std_logic;
|
| 1697 |
|
|
begin
|
| 1698 |
|
|
---------------------
|
| 1699 |
|
|
-- INPUT PATH DELAYs
|
| 1700 |
|
|
---------------------
|
| 1701 |
|
|
WireDelay : block
|
| 1702 |
|
|
begin
|
| 1703 |
|
|
VitalWireDelay (datain_ipd, datain, tipd_datain);
|
| 1704 |
|
|
end block;
|
| 1705 |
|
|
|
| 1706 |
|
|
VITAL: process(datain_ipd, datainglitch_inert)
|
| 1707 |
|
|
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
|
| 1708 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 1709 |
|
|
|
| 1710 |
|
|
begin
|
| 1711 |
|
|
----------------------
|
| 1712 |
|
|
-- Path Delay Section
|
| 1713 |
|
|
----------------------
|
| 1714 |
|
|
VitalPathDelay01 (
|
| 1715 |
|
|
OutSignal => datainglitch_inert,
|
| 1716 |
|
|
OutSignalName => "datainglitch_inert",
|
| 1717 |
|
|
OutTemp => datain_ipd,
|
| 1718 |
|
|
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
|
| 1719 |
|
|
GlitchData => datain_inert_VitalGlitchData,
|
| 1720 |
|
|
Mode => VitalInertial,
|
| 1721 |
|
|
XOn => XOn,
|
| 1722 |
|
|
MsgOn => MsgOn );
|
| 1723 |
|
|
|
| 1724 |
|
|
VitalPathDelay01 (
|
| 1725 |
|
|
OutSignal => dataout,
|
| 1726 |
|
|
OutSignalName => "dataout",
|
| 1727 |
|
|
OutTemp => datainglitch_inert,
|
| 1728 |
|
|
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
|
| 1729 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 1730 |
|
|
Mode => DefGlitchMode,
|
| 1731 |
|
|
XOn => XOn,
|
| 1732 |
|
|
MsgOn => MsgOn );
|
| 1733 |
|
|
|
| 1734 |
|
|
end process;
|
| 1735 |
|
|
|
| 1736 |
|
|
end behave;
|
| 1737 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 1738 |
|
|
--
|
| 1739 |
|
|
-- Module Name : stratixiii_lvds_tx_reg
|
| 1740 |
|
|
--
|
| 1741 |
|
|
-- Description : Simulation model for a simple DFF.
|
| 1742 |
|
|
-- This is used for registering the enable inputs.
|
| 1743 |
|
|
-- No timing, powers upto 0.
|
| 1744 |
|
|
--
|
| 1745 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 1746 |
|
|
|
| 1747 |
|
|
LIBRARY IEEE, std;
|
| 1748 |
|
|
USE ieee.std_logic_1164.all;
|
| 1749 |
|
|
--USE ieee.std_logic_unsigned.all;
|
| 1750 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 1751 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 1752 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 1753 |
|
|
|
| 1754 |
|
|
ENTITY stratixiii_lvds_tx_reg is
|
| 1755 |
|
|
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
|
| 1756 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 1757 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 1758 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 1759 |
|
|
TimingChecksOn : Boolean := True;
|
| 1760 |
|
|
InstancePath : String := "*";
|
| 1761 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 1762 |
|
|
tipd_ena : VitalDelayType01 := DefpropDelay01;
|
| 1763 |
|
|
tipd_d : VitalDelayType01 := DefpropDelay01;
|
| 1764 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 1765 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 1766 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
|
| 1767 |
|
|
);
|
| 1768 |
|
|
|
| 1769 |
|
|
PORT ( q : OUT std_logic;
|
| 1770 |
|
|
clk : IN std_logic;
|
| 1771 |
|
|
ena : IN std_logic;
|
| 1772 |
|
|
d : IN std_logic;
|
| 1773 |
|
|
clrn : IN std_logic;
|
| 1774 |
|
|
prn : IN std_logic
|
| 1775 |
|
|
);
|
| 1776 |
|
|
attribute VITAL_LEVEL0 of stratixiii_lvds_tx_reg : ENTITY is TRUE;
|
| 1777 |
|
|
END stratixiii_lvds_tx_reg;
|
| 1778 |
|
|
|
| 1779 |
|
|
ARCHITECTURE vital_stratixiii_lvds_tx_reg of stratixiii_lvds_tx_reg is
|
| 1780 |
|
|
|
| 1781 |
|
|
attribute VITAL_LEVEL0 of vital_stratixiii_lvds_tx_reg : architecture is TRUE;
|
| 1782 |
|
|
|
| 1783 |
|
|
-- INTERNAL SIGNALS
|
| 1784 |
|
|
signal clk_ipd : std_logic;
|
| 1785 |
|
|
signal d_ipd : std_logic;
|
| 1786 |
|
|
signal ena_ipd : std_logic;
|
| 1787 |
|
|
|
| 1788 |
|
|
begin
|
| 1789 |
|
|
|
| 1790 |
|
|
----------------------
|
| 1791 |
|
|
-- INPUT PATH DELAYs
|
| 1792 |
|
|
----------------------
|
| 1793 |
|
|
WireDelay : block
|
| 1794 |
|
|
begin
|
| 1795 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 1796 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 1797 |
|
|
VitalWireDelay (d_ipd, d, tipd_d);
|
| 1798 |
|
|
end block;
|
| 1799 |
|
|
|
| 1800 |
|
|
process (clk_ipd, clrn, prn)
|
| 1801 |
|
|
variable q_tmp : std_logic := '0';
|
| 1802 |
|
|
variable q_VitalGlitchData : VitalGlitchDataType;
|
| 1803 |
|
|
variable Tviol_d_clk : std_ulogic := '0';
|
| 1804 |
|
|
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 1805 |
|
|
begin
|
| 1806 |
|
|
|
| 1807 |
|
|
------------------------
|
| 1808 |
|
|
-- Timing Check Section
|
| 1809 |
|
|
------------------------
|
| 1810 |
|
|
if (TimingChecksOn) then
|
| 1811 |
|
|
VitalSetupHoldCheck (
|
| 1812 |
|
|
Violation => Tviol_d_clk,
|
| 1813 |
|
|
TimingData => TimingData_d_clk,
|
| 1814 |
|
|
TestSignal => d_ipd,
|
| 1815 |
|
|
TestSignalName => "d",
|
| 1816 |
|
|
RefSignal => clk_ipd,
|
| 1817 |
|
|
RefSignalName => "clk",
|
| 1818 |
|
|
SetupHigh => tsetup_d_clk_noedge_posedge,
|
| 1819 |
|
|
SetupLow => tsetup_d_clk_noedge_posedge,
|
| 1820 |
|
|
HoldHigh => thold_d_clk_noedge_posedge,
|
| 1821 |
|
|
HoldLow => thold_d_clk_noedge_posedge,
|
| 1822 |
|
|
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
|
| 1823 |
|
|
RefTransition => '/',
|
| 1824 |
|
|
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_reg",
|
| 1825 |
|
|
XOn => XOnChecks,
|
| 1826 |
|
|
MsgOn => MsgOnChecks );
|
| 1827 |
|
|
end if;
|
| 1828 |
|
|
|
| 1829 |
|
|
if (prn = '0') then
|
| 1830 |
|
|
q_tmp := '1';
|
| 1831 |
|
|
elsif (clrn = '0') then
|
| 1832 |
|
|
q_tmp := '0';
|
| 1833 |
|
|
elsif (clk_ipd'event and clk_ipd = '1') then
|
| 1834 |
|
|
if (ena_ipd = '1') then
|
| 1835 |
|
|
q_tmp := d_ipd;
|
| 1836 |
|
|
end if;
|
| 1837 |
|
|
end if;
|
| 1838 |
|
|
|
| 1839 |
|
|
----------------------
|
| 1840 |
|
|
-- Path Delay Section
|
| 1841 |
|
|
----------------------
|
| 1842 |
|
|
VitalPathDelay01 (
|
| 1843 |
|
|
OutSignal => q,
|
| 1844 |
|
|
OutSignalName => "Q",
|
| 1845 |
|
|
OutTemp => q_tmp,
|
| 1846 |
|
|
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
|
| 1847 |
|
|
GlitchData => q_VitalGlitchData,
|
| 1848 |
|
|
Mode => DefGlitchMode,
|
| 1849 |
|
|
XOn => XOn,
|
| 1850 |
|
|
MsgOn => MsgOn );
|
| 1851 |
|
|
|
| 1852 |
|
|
end process;
|
| 1853 |
|
|
|
| 1854 |
|
|
end vital_stratixiii_lvds_tx_reg;
|
| 1855 |
|
|
|
| 1856 |
|
|
--////////////////////////////////////////////////////////////////////////////
|
| 1857 |
|
|
--
|
| 1858 |
|
|
-- Entity name : stratixiii_lvds_tx_parallel_register
|
| 1859 |
|
|
--
|
| 1860 |
|
|
-- Description : Register for the 10 data input channels of the Stratix III
|
| 1861 |
|
|
-- LVDS Tx
|
| 1862 |
|
|
--
|
| 1863 |
|
|
--////////////////////////////////////////////////////////////////////////////
|
| 1864 |
|
|
|
| 1865 |
|
|
LIBRARY IEEE, std;
|
| 1866 |
|
|
USE IEEE.std_logic_1164.all;
|
| 1867 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 1868 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 1869 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 1870 |
|
|
USE std.textio.all;
|
| 1871 |
|
|
|
| 1872 |
|
|
ENTITY stratixiii_lvds_tx_parallel_register is
|
| 1873 |
|
|
GENERIC ( channel_width : integer := 10;
|
| 1874 |
|
|
TimingChecksOn : Boolean := True;
|
| 1875 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 1876 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 1877 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 1878 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 1879 |
|
|
InstancePath : String := "*";
|
| 1880 |
|
|
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 1881 |
|
|
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 1882 |
|
|
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 1883 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 1884 |
|
|
tipd_enable : VitalDelayType01 := DefpropDelay01;
|
| 1885 |
|
|
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
|
| 1886 |
|
|
);
|
| 1887 |
|
|
|
| 1888 |
|
|
PORT ( clk : in std_logic;
|
| 1889 |
|
|
enable : in std_logic;
|
| 1890 |
|
|
datain : in std_logic_vector(channel_width - 1 downto 0);
|
| 1891 |
|
|
devclrn : in std_logic := '1';
|
| 1892 |
|
|
devpor : in std_logic := '1';
|
| 1893 |
|
|
dataout : out std_logic_vector(channel_width - 1 downto 0)
|
| 1894 |
|
|
);
|
| 1895 |
|
|
|
| 1896 |
|
|
END stratixiii_lvds_tx_parallel_register;
|
| 1897 |
|
|
|
| 1898 |
|
|
ARCHITECTURE vital_tx_reg of stratixiii_lvds_tx_parallel_register is
|
| 1899 |
|
|
signal clk_ipd : std_logic;
|
| 1900 |
|
|
signal enable_ipd : std_logic;
|
| 1901 |
|
|
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
|
| 1902 |
|
|
|
| 1903 |
|
|
begin
|
| 1904 |
|
|
|
| 1905 |
|
|
----------------------
|
| 1906 |
|
|
-- INPUT PATH DELAYs
|
| 1907 |
|
|
----------------------
|
| 1908 |
|
|
WireDelay : block
|
| 1909 |
|
|
begin
|
| 1910 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 1911 |
|
|
VitalWireDelay (enable_ipd, enable, tipd_enable);
|
| 1912 |
|
|
loopbits : FOR i in datain'RANGE GENERATE
|
| 1913 |
|
|
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
|
| 1914 |
|
|
END GENERATE;
|
| 1915 |
|
|
end block;
|
| 1916 |
|
|
|
| 1917 |
|
|
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
|
| 1918 |
|
|
variable Tviol_datain_clk : std_ulogic := '0';
|
| 1919 |
|
|
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 1920 |
|
|
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
|
| 1921 |
|
|
variable i : integer := 0;
|
| 1922 |
|
|
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
|
| 1923 |
|
|
variable CQDelay : TIME := 0 ns;
|
| 1924 |
|
|
begin
|
| 1925 |
|
|
|
| 1926 |
|
|
if (now = 0 ns) then
|
| 1927 |
|
|
dataout_tmp := (OTHERS => '0');
|
| 1928 |
|
|
end if;
|
| 1929 |
|
|
|
| 1930 |
|
|
------------------------
|
| 1931 |
|
|
-- Timing Check Section
|
| 1932 |
|
|
------------------------
|
| 1933 |
|
|
if (TimingChecksOn) then
|
| 1934 |
|
|
|
| 1935 |
|
|
VitalSetupHoldCheck (
|
| 1936 |
|
|
Violation => Tviol_datain_clk,
|
| 1937 |
|
|
TimingData => TimingData_datain_clk,
|
| 1938 |
|
|
TestSignal => datain_ipd,
|
| 1939 |
|
|
TestSignalName => "DATAIN",
|
| 1940 |
|
|
RefSignal => clk_ipd,
|
| 1941 |
|
|
RefSignalName => "CLK",
|
| 1942 |
|
|
SetupHigh => tsetup_datain_clk_noedge_posedge,
|
| 1943 |
|
|
SetupLow => tsetup_datain_clk_noedge_posedge,
|
| 1944 |
|
|
HoldHigh => thold_datain_clk_noedge_posedge,
|
| 1945 |
|
|
HoldLow => thold_datain_clk_noedge_posedge,
|
| 1946 |
|
|
RefTransition => '/',
|
| 1947 |
|
|
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_parallel_register",
|
| 1948 |
|
|
XOn => XOn,
|
| 1949 |
|
|
MsgOn => MsgOnChecks );
|
| 1950 |
|
|
end if;
|
| 1951 |
|
|
|
| 1952 |
|
|
if ((devpor = '0') or (devclrn = '0')) then
|
| 1953 |
|
|
dataout_tmp := (OTHERS => '0');
|
| 1954 |
|
|
else
|
| 1955 |
|
|
if (clk_ipd'event and clk_ipd = '1') then
|
| 1956 |
|
|
if (enable_ipd = '1') then
|
| 1957 |
|
|
dataout_tmp := datain_ipd;
|
| 1958 |
|
|
end if;
|
| 1959 |
|
|
end if;
|
| 1960 |
|
|
end if;
|
| 1961 |
|
|
|
| 1962 |
|
|
----------------------
|
| 1963 |
|
|
-- Path Delay Section
|
| 1964 |
|
|
----------------------
|
| 1965 |
|
|
CQDelay := SelectDelay(
|
| 1966 |
|
|
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
|
| 1967 |
|
|
);
|
| 1968 |
|
|
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
|
| 1969 |
|
|
|
| 1970 |
|
|
end process;
|
| 1971 |
|
|
|
| 1972 |
|
|
end vital_tx_reg;
|
| 1973 |
|
|
|
| 1974 |
|
|
--////////////////////////////////////////////////////////////////////////////
|
| 1975 |
|
|
--
|
| 1976 |
|
|
-- Entity name : stratixiii_lvds_tx_out_block
|
| 1977 |
|
|
--
|
| 1978 |
|
|
-- Description : Negative-edge triggered register on the Tx output.
|
| 1979 |
|
|
-- Also, optionally generates an identical/inverted output clock
|
| 1980 |
|
|
--
|
| 1981 |
|
|
--////////////////////////////////////////////////////////////////////////////
|
| 1982 |
|
|
|
| 1983 |
|
|
LIBRARY IEEE, std;
|
| 1984 |
|
|
USE IEEE.std_logic_1164.all;
|
| 1985 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 1986 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 1987 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 1988 |
|
|
USE std.textio.all;
|
| 1989 |
|
|
|
| 1990 |
|
|
ENTITY stratixiii_lvds_tx_out_block is
|
| 1991 |
|
|
GENERIC ( bypass_serializer : String := "false";
|
| 1992 |
|
|
invert_clock : String := "false";
|
| 1993 |
|
|
use_falling_clock_edge : String := "false";
|
| 1994 |
|
|
TimingChecksOn : Boolean := True;
|
| 1995 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 1996 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 1997 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 1998 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 1999 |
|
|
InstancePath : String := "*";
|
| 2000 |
|
|
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
|
| 2001 |
|
|
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
|
| 2002 |
|
|
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
|
| 2003 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 2004 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01
|
| 2005 |
|
|
);
|
| 2006 |
|
|
|
| 2007 |
|
|
PORT ( clk : in std_logic;
|
| 2008 |
|
|
datain : in std_logic;
|
| 2009 |
|
|
devclrn : in std_logic := '1';
|
| 2010 |
|
|
devpor : in std_logic := '1';
|
| 2011 |
|
|
dataout : out std_logic
|
| 2012 |
|
|
);
|
| 2013 |
|
|
|
| 2014 |
|
|
END stratixiii_lvds_tx_out_block;
|
| 2015 |
|
|
|
| 2016 |
|
|
ARCHITECTURE vital_tx_out_block of stratixiii_lvds_tx_out_block is
|
| 2017 |
|
|
signal clk_ipd : std_logic;
|
| 2018 |
|
|
signal datain_ipd : std_logic;
|
| 2019 |
|
|
signal inv_clk : integer;
|
| 2020 |
|
|
|
| 2021 |
|
|
begin
|
| 2022 |
|
|
|
| 2023 |
|
|
----------------------
|
| 2024 |
|
|
-- INPUT PATH DELAYs
|
| 2025 |
|
|
----------------------
|
| 2026 |
|
|
WireDelay : block
|
| 2027 |
|
|
begin
|
| 2028 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 2029 |
|
|
VitalWireDelay (datain_ipd, datain, tipd_datain);
|
| 2030 |
|
|
end block;
|
| 2031 |
|
|
|
| 2032 |
|
|
|
| 2033 |
|
|
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
|
| 2034 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 2035 |
|
|
variable dataout_tmp : std_logic;
|
| 2036 |
|
|
begin
|
| 2037 |
|
|
if (now = 0 ns) then
|
| 2038 |
|
|
dataout_tmp := '0';
|
| 2039 |
|
|
else
|
| 2040 |
|
|
if (bypass_serializer = "false") then
|
| 2041 |
|
|
if (use_falling_clock_edge = "false") then
|
| 2042 |
|
|
dataout_tmp := datain_ipd;
|
| 2043 |
|
|
end if;
|
| 2044 |
|
|
|
| 2045 |
|
|
if (clk_ipd'event and clk_ipd = '0') then
|
| 2046 |
|
|
if (use_falling_clock_edge = "true") then
|
| 2047 |
|
|
dataout_tmp := datain_ipd;
|
| 2048 |
|
|
end if;
|
| 2049 |
|
|
end if;
|
| 2050 |
|
|
else
|
| 2051 |
|
|
if (invert_clock = "false") then
|
| 2052 |
|
|
dataout_tmp := clk_ipd;
|
| 2053 |
|
|
else
|
| 2054 |
|
|
dataout_tmp := NOT (clk_ipd);
|
| 2055 |
|
|
end if;
|
| 2056 |
|
|
|
| 2057 |
|
|
if (invert_clock = "false") then
|
| 2058 |
|
|
inv_clk <= 0;
|
| 2059 |
|
|
else
|
| 2060 |
|
|
inv_clk <= 1;
|
| 2061 |
|
|
end if;
|
| 2062 |
|
|
end if;
|
| 2063 |
|
|
end if;
|
| 2064 |
|
|
|
| 2065 |
|
|
----------------------
|
| 2066 |
|
|
-- Path Delay Section
|
| 2067 |
|
|
----------------------
|
| 2068 |
|
|
|
| 2069 |
|
|
if (bypass_serializer = "false") then
|
| 2070 |
|
|
VitalPathDelay01 (
|
| 2071 |
|
|
OutSignal => dataout,
|
| 2072 |
|
|
OutSignalName => "DATAOUT",
|
| 2073 |
|
|
OutTemp => dataout_tmp,
|
| 2074 |
|
|
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
|
| 2075 |
|
|
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
|
| 2076 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 2077 |
|
|
Mode => DefGlitchMode,
|
| 2078 |
|
|
XOn => XOn,
|
| 2079 |
|
|
MsgOn => MsgOn );
|
| 2080 |
|
|
end if;
|
| 2081 |
|
|
|
| 2082 |
|
|
if (bypass_serializer = "true") then
|
| 2083 |
|
|
VitalPathDelay01 (
|
| 2084 |
|
|
OutSignal => dataout,
|
| 2085 |
|
|
OutSignalName => "DATAOUT",
|
| 2086 |
|
|
OutTemp => dataout_tmp,
|
| 2087 |
|
|
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
|
| 2088 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 2089 |
|
|
Mode => DefGlitchMode,
|
| 2090 |
|
|
XOn => XOn,
|
| 2091 |
|
|
MsgOn => MsgOn );
|
| 2092 |
|
|
end if;
|
| 2093 |
|
|
end process;
|
| 2094 |
|
|
end vital_tx_out_block;
|
| 2095 |
|
|
|
| 2096 |
|
|
--////////////////////////////////////////////////////////////////////////////
|
| 2097 |
|
|
--
|
| 2098 |
|
|
-- Entity name : stratixiii_lvds_transmitter
|
| 2099 |
|
|
--
|
| 2100 |
|
|
-- Description : Timing simulation model for the Stratix III LVDS Tx WYSIWYG.
|
| 2101 |
|
|
-- It instantiates the following sub-modules :
|
| 2102 |
|
|
-- 1) primitive DFFE
|
| 2103 |
|
|
-- 2) Stratix III_lvds_tx_parallel_register and
|
| 2104 |
|
|
-- 3) Stratix III_lvds_tx_out_block
|
| 2105 |
|
|
--
|
| 2106 |
|
|
--////////////////////////////////////////////////////////////////////////////
|
| 2107 |
|
|
LIBRARY IEEE, std;
|
| 2108 |
|
|
USE IEEE.std_logic_1164.all;
|
| 2109 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 2110 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 2111 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 2112 |
|
|
USE std.textio.all;
|
| 2113 |
|
|
USE work.stratixiii_lvds_tx_parallel_register;
|
| 2114 |
|
|
USE work.stratixiii_lvds_tx_out_block;
|
| 2115 |
|
|
USE work.stratixiii_lvds_tx_reg;
|
| 2116 |
|
|
|
| 2117 |
|
|
ENTITY stratixiii_lvds_transmitter is
|
| 2118 |
|
|
GENERIC ( channel_width : integer := 10;
|
| 2119 |
|
|
bypass_serializer : String := "false";
|
| 2120 |
|
|
invert_clock : String := "false";
|
| 2121 |
|
|
use_falling_clock_edge : String := "false";
|
| 2122 |
|
|
use_serial_data_input : String := "false";
|
| 2123 |
|
|
use_post_dpa_serial_data_input : String := "false";
|
| 2124 |
|
|
is_used_as_outclk : String := "false";
|
| 2125 |
|
|
tx_output_path_delay_engineering_bits : Integer := -1;
|
| 2126 |
|
|
enable_dpaclk_to_lvdsout : string := "off";
|
| 2127 |
|
|
preemphasis_setting : integer := 0;
|
| 2128 |
|
|
vod_setting : integer := 0;
|
| 2129 |
|
|
differential_drive : integer := 0;
|
| 2130 |
|
|
lpm_type : string := "stratixiii_lvds_transmitter";
|
| 2131 |
|
|
TimingChecksOn : Boolean := True;
|
| 2132 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 2133 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 2134 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 2135 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 2136 |
|
|
InstancePath : String := "*";
|
| 2137 |
|
|
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 2138 |
|
|
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
|
| 2139 |
|
|
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
|
| 2140 |
|
|
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
|
| 2141 |
|
|
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
|
| 2142 |
|
|
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
|
| 2143 |
|
|
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
|
| 2144 |
|
|
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
|
| 2145 |
|
|
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
|
| 2146 |
|
|
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
|
| 2147 |
|
|
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
|
| 2148 |
|
|
);
|
| 2149 |
|
|
|
| 2150 |
|
|
PORT ( clk0 : in std_logic;
|
| 2151 |
|
|
enable0 : in std_logic;
|
| 2152 |
|
|
datain : in std_logic_vector(channel_width - 1 downto 0);
|
| 2153 |
|
|
serialdatain : in std_logic := '0';
|
| 2154 |
|
|
postdpaserialdatain : in std_logic := '0';
|
| 2155 |
|
|
dpaclkin : in std_logic := '0';
|
| 2156 |
|
|
devclrn : in std_logic := '1';
|
| 2157 |
|
|
devpor : in std_logic := '1';
|
| 2158 |
|
|
dataout : out std_logic;
|
| 2159 |
|
|
serialfdbkout : out std_logic
|
| 2160 |
|
|
);
|
| 2161 |
|
|
|
| 2162 |
|
|
end stratixiii_lvds_transmitter;
|
| 2163 |
|
|
|
| 2164 |
|
|
ARCHITECTURE vital_transmitter_atom of stratixiii_lvds_transmitter is
|
| 2165 |
|
|
|
| 2166 |
|
|
signal clk0_ipd : std_logic;
|
| 2167 |
|
|
signal serialdatain_ipd : std_logic;
|
| 2168 |
|
|
signal postdpaserialdatain_ipd : std_logic;
|
| 2169 |
|
|
signal dpaclkin_ipd : std_logic;
|
| 2170 |
|
|
|
| 2171 |
|
|
signal input_data : std_logic_vector(channel_width - 1 downto 0);
|
| 2172 |
|
|
signal txload0 : std_logic;
|
| 2173 |
|
|
signal shift_out : std_logic;
|
| 2174 |
|
|
|
| 2175 |
|
|
signal clk0_dly0 : std_logic;
|
| 2176 |
|
|
signal clk0_dly1 : std_logic;
|
| 2177 |
|
|
signal clk0_dly2 : std_logic;
|
| 2178 |
|
|
|
| 2179 |
|
|
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
|
| 2180 |
|
|
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
|
| 2181 |
|
|
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
|
| 2182 |
|
|
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
|
| 2183 |
|
|
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
|
| 2184 |
|
|
|
| 2185 |
|
|
signal vcc : std_logic := '1';
|
| 2186 |
|
|
signal tmp_dataout : std_logic;
|
| 2187 |
|
|
|
| 2188 |
|
|
COMPONENT stratixiii_lvds_tx_parallel_register
|
| 2189 |
|
|
GENERIC ( channel_width : integer := 10;
|
| 2190 |
|
|
TimingChecksOn : Boolean := True;
|
| 2191 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 2192 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 2193 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 2194 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 2195 |
|
|
InstancePath : String := "*";
|
| 2196 |
|
|
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 2197 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 2198 |
|
|
tipd_enable : VitalDelayType01 := DefpropDelay01;
|
| 2199 |
|
|
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
|
| 2200 |
|
|
);
|
| 2201 |
|
|
|
| 2202 |
|
|
PORT ( clk : in std_logic;
|
| 2203 |
|
|
enable : in std_logic;
|
| 2204 |
|
|
datain : in std_logic_vector(channel_width - 1 downto 0);
|
| 2205 |
|
|
devclrn : in std_logic := '1';
|
| 2206 |
|
|
devpor : in std_logic := '1';
|
| 2207 |
|
|
dataout : out std_logic_vector(channel_width - 1 downto 0)
|
| 2208 |
|
|
);
|
| 2209 |
|
|
|
| 2210 |
|
|
END COMPONENT;
|
| 2211 |
|
|
|
| 2212 |
|
|
COMPONENT stratixiii_lvds_tx_out_block
|
| 2213 |
|
|
GENERIC ( bypass_serializer : String := "false";
|
| 2214 |
|
|
invert_clock : String := "false";
|
| 2215 |
|
|
use_falling_clock_edge : String := "false";
|
| 2216 |
|
|
TimingChecksOn : Boolean := True;
|
| 2217 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 2218 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 2219 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 2220 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 2221 |
|
|
InstancePath : String := "*";
|
| 2222 |
|
|
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
|
| 2223 |
|
|
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
|
| 2224 |
|
|
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
|
| 2225 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 2226 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01
|
| 2227 |
|
|
);
|
| 2228 |
|
|
|
| 2229 |
|
|
PORT ( clk : in std_logic;
|
| 2230 |
|
|
datain : in std_logic;
|
| 2231 |
|
|
devclrn : in std_logic := '1';
|
| 2232 |
|
|
devpor : in std_logic := '1';
|
| 2233 |
|
|
dataout : out std_logic
|
| 2234 |
|
|
);
|
| 2235 |
|
|
END COMPONENT;
|
| 2236 |
|
|
|
| 2237 |
|
|
COMPONENT stratixiii_lvds_tx_reg
|
| 2238 |
|
|
GENERIC (TimingChecksOn : Boolean := true;
|
| 2239 |
|
|
InstancePath : STRING := "*";
|
| 2240 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 2241 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 2242 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 2243 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 2244 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 2245 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 2246 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 2247 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 2248 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 2249 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01
|
| 2250 |
|
|
);
|
| 2251 |
|
|
|
| 2252 |
|
|
PORT ( q : out STD_LOGIC := '0';
|
| 2253 |
|
|
d : in STD_LOGIC := '1';
|
| 2254 |
|
|
clrn : in STD_LOGIC := '1';
|
| 2255 |
|
|
prn : in STD_LOGIC := '1';
|
| 2256 |
|
|
clk : in STD_LOGIC := '0';
|
| 2257 |
|
|
ena : in STD_LOGIC := '1'
|
| 2258 |
|
|
);
|
| 2259 |
|
|
END COMPONENT;
|
| 2260 |
|
|
|
| 2261 |
|
|
begin
|
| 2262 |
|
|
|
| 2263 |
|
|
----------------------
|
| 2264 |
|
|
-- INPUT PATH DELAYs
|
| 2265 |
|
|
----------------------
|
| 2266 |
|
|
WireDelay : block
|
| 2267 |
|
|
begin
|
| 2268 |
|
|
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
|
| 2269 |
|
|
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
|
| 2270 |
|
|
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);
|
| 2271 |
|
|
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
|
| 2272 |
|
|
end block;
|
| 2273 |
|
|
|
| 2274 |
|
|
txload0_reg: stratixiii_lvds_tx_reg
|
| 2275 |
|
|
PORT MAP (d => enable0,
|
| 2276 |
|
|
clrn => vcc,
|
| 2277 |
|
|
prn => vcc,
|
| 2278 |
|
|
ena => vcc,
|
| 2279 |
|
|
clk => clk0_dly2,
|
| 2280 |
|
|
q => txload0
|
| 2281 |
|
|
);
|
| 2282 |
|
|
|
| 2283 |
|
|
input_reg: stratixiii_lvds_tx_parallel_register
|
| 2284 |
|
|
GENERIC MAP ( channel_width => channel_width)
|
| 2285 |
|
|
PORT MAP ( clk => txload0,
|
| 2286 |
|
|
enable => vcc,
|
| 2287 |
|
|
datain => datain_dly,
|
| 2288 |
|
|
dataout => input_data,
|
| 2289 |
|
|
devclrn => devclrn,
|
| 2290 |
|
|
devpor => devpor
|
| 2291 |
|
|
);
|
| 2292 |
|
|
|
| 2293 |
|
|
output_module: stratixiii_lvds_tx_out_block
|
| 2294 |
|
|
GENERIC MAP ( bypass_serializer => bypass_serializer,
|
| 2295 |
|
|
use_falling_clock_edge => use_falling_clock_edge,
|
| 2296 |
|
|
invert_clock => invert_clock)
|
| 2297 |
|
|
PORT MAP ( clk => clk0_dly2,
|
| 2298 |
|
|
datain => shift_out,
|
| 2299 |
|
|
dataout => tmp_dataout,
|
| 2300 |
|
|
devclrn => devclrn,
|
| 2301 |
|
|
devpor => devpor
|
| 2302 |
|
|
);
|
| 2303 |
|
|
|
| 2304 |
|
|
clk_delay: process (clk0_ipd, datain)
|
| 2305 |
|
|
begin
|
| 2306 |
|
|
clk0_dly0 <= clk0_ipd;
|
| 2307 |
|
|
datain_dly1 <= datain;
|
| 2308 |
|
|
end process;
|
| 2309 |
|
|
|
| 2310 |
|
|
clk_delay1: process (clk0_dly0, datain_dly1)
|
| 2311 |
|
|
begin
|
| 2312 |
|
|
clk0_dly1 <= clk0_dly0;
|
| 2313 |
|
|
datain_dly2 <= datain_dly1;
|
| 2314 |
|
|
end process;
|
| 2315 |
|
|
|
| 2316 |
|
|
clk_delay2: process (clk0_dly1, datain_dly2)
|
| 2317 |
|
|
begin
|
| 2318 |
|
|
clk0_dly2 <= clk0_dly1;
|
| 2319 |
|
|
datain_dly3 <= datain_dly2;
|
| 2320 |
|
|
end process;
|
| 2321 |
|
|
|
| 2322 |
|
|
data_delay: process (datain_dly3)
|
| 2323 |
|
|
begin
|
| 2324 |
|
|
datain_dly4 <= datain_dly3;
|
| 2325 |
|
|
end process;
|
| 2326 |
|
|
|
| 2327 |
|
|
data_delay1: process (datain_dly4)
|
| 2328 |
|
|
begin
|
| 2329 |
|
|
datain_dly <= datain_dly4;
|
| 2330 |
|
|
end process;
|
| 2331 |
|
|
|
| 2332 |
|
|
VITAL: process (clk0_ipd, devclrn, devpor)
|
| 2333 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 2334 |
|
|
variable i : integer := 0;
|
| 2335 |
|
|
variable shift_data : std_logic_vector(channel_width-1 downto 0);
|
| 2336 |
|
|
begin
|
| 2337 |
|
|
if (now = 0 ns) then
|
| 2338 |
|
|
shift_data := (OTHERS => '0');
|
| 2339 |
|
|
end if;
|
| 2340 |
|
|
|
| 2341 |
|
|
if ((devpor = '0') or (devclrn = '0')) then
|
| 2342 |
|
|
shift_data := (OTHERS => '0');
|
| 2343 |
|
|
else
|
| 2344 |
|
|
if (bypass_serializer = "false") then
|
| 2345 |
|
|
if (clk0_ipd'event and clk0_ipd = '1') then
|
| 2346 |
|
|
if (txload0 = '1') then
|
| 2347 |
|
|
shift_data := input_data;
|
| 2348 |
|
|
end if;
|
| 2349 |
|
|
|
| 2350 |
|
|
shift_out <= shift_data(channel_width - 1);
|
| 2351 |
|
|
|
| 2352 |
|
|
for i in channel_width-1 downto 1 loop
|
| 2353 |
|
|
shift_data(i) := shift_data(i - 1);
|
| 2354 |
|
|
end loop;
|
| 2355 |
|
|
end if;
|
| 2356 |
|
|
end if;
|
| 2357 |
|
|
end if;
|
| 2358 |
|
|
|
| 2359 |
|
|
end process;
|
| 2360 |
|
|
|
| 2361 |
|
|
process (serialdatain_ipd,
|
| 2362 |
|
|
postdpaserialdatain_ipd,
|
| 2363 |
|
|
dpaclkin_ipd,
|
| 2364 |
|
|
tmp_dataout
|
| 2365 |
|
|
)
|
| 2366 |
|
|
variable dataout_tmp : std_logic := '0';
|
| 2367 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 2368 |
|
|
begin
|
| 2369 |
|
|
if (serialdatain_ipd'event and use_serial_data_input = "true") then
|
| 2370 |
|
|
dataout_tmp := serialdatain_ipd;
|
| 2371 |
|
|
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
|
| 2372 |
|
|
dataout_tmp := postdpaserialdatain_ipd;
|
| 2373 |
|
|
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then
|
| 2374 |
|
|
dataout_tmp := dpaclkin_ipd;
|
| 2375 |
|
|
else
|
| 2376 |
|
|
dataout_tmp := tmp_dataout;
|
| 2377 |
|
|
end if;
|
| 2378 |
|
|
|
| 2379 |
|
|
----------------------
|
| 2380 |
|
|
-- Path Delay Section
|
| 2381 |
|
|
----------------------
|
| 2382 |
|
|
if (use_serial_data_input = "true") then
|
| 2383 |
|
|
VitalPathDelay01 (
|
| 2384 |
|
|
OutSignal => dataout,
|
| 2385 |
|
|
OutSignalName => "DATAOUT",
|
| 2386 |
|
|
OutTemp => dataout_tmp,
|
| 2387 |
|
|
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
|
| 2388 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 2389 |
|
|
Mode => DefGlitchMode,
|
| 2390 |
|
|
XOn => XOn,
|
| 2391 |
|
|
MsgOn => MsgOn );
|
| 2392 |
|
|
|
| 2393 |
|
|
elsif (use_post_dpa_serial_data_input = "true") then
|
| 2394 |
|
|
VitalPathDelay01 (
|
| 2395 |
|
|
OutSignal => dataout,
|
| 2396 |
|
|
OutSignalName => "DATAOUT",
|
| 2397 |
|
|
OutTemp => dataout_tmp,
|
| 2398 |
|
|
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
|
| 2399 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 2400 |
|
|
Mode => DefGlitchMode,
|
| 2401 |
|
|
XOn => XOn,
|
| 2402 |
|
|
MsgOn => MsgOn );
|
| 2403 |
|
|
elsif (enable_dpaclk_to_lvdsout = "on") then
|
| 2404 |
|
|
VitalPathDelay01 (
|
| 2405 |
|
|
OutSignal => dataout,
|
| 2406 |
|
|
OutSignalName => "DATAOUT",
|
| 2407 |
|
|
OutTemp => dataout_tmp,
|
| 2408 |
|
|
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)),
|
| 2409 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 2410 |
|
|
Mode => DefGlitchMode,
|
| 2411 |
|
|
XOn => XOn,
|
| 2412 |
|
|
MsgOn => MsgOn );
|
| 2413 |
|
|
else
|
| 2414 |
|
|
VitalPathDelay01 (
|
| 2415 |
|
|
OutSignal => dataout,
|
| 2416 |
|
|
OutSignalName => "DATAOUT",
|
| 2417 |
|
|
OutTemp => dataout_tmp,
|
| 2418 |
|
|
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
|
| 2419 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 2420 |
|
|
Mode => DefGlitchMode,
|
| 2421 |
|
|
XOn => XOn,
|
| 2422 |
|
|
MsgOn => MsgOn );
|
| 2423 |
|
|
end if;
|
| 2424 |
|
|
end process;
|
| 2425 |
|
|
|
| 2426 |
|
|
end vital_transmitter_atom;
|
| 2427 |
|
|
--
|
| 2428 |
|
|
--
|
| 2429 |
|
|
-- STRATIXIII_RUBLOCK Model
|
| 2430 |
|
|
--
|
| 2431 |
|
|
--
|
| 2432 |
|
|
LIBRARY IEEE;
|
| 2433 |
|
|
use IEEE.std_logic_1164.all;
|
| 2434 |
|
|
use IEEE.std_logic_arith.all;
|
| 2435 |
|
|
use work.stratixiii_atom_pack.all;
|
| 2436 |
|
|
|
| 2437 |
|
|
entity stratixiii_rublock is
|
| 2438 |
|
|
generic
|
| 2439 |
|
|
(
|
| 2440 |
|
|
sim_init_config : string := "factory";
|
| 2441 |
|
|
sim_init_watchdog_value : integer := 0;
|
| 2442 |
|
|
sim_init_status : integer := 0;
|
| 2443 |
|
|
lpm_type : string := "stratixiii_rublock"
|
| 2444 |
|
|
);
|
| 2445 |
|
|
port
|
| 2446 |
|
|
(
|
| 2447 |
|
|
clk : in std_logic;
|
| 2448 |
|
|
shiftnld : in std_logic;
|
| 2449 |
|
|
captnupdt : in std_logic;
|
| 2450 |
|
|
regin : in std_logic;
|
| 2451 |
|
|
rsttimer : in std_logic;
|
| 2452 |
|
|
rconfig : in std_logic;
|
| 2453 |
|
|
regout : out std_logic
|
| 2454 |
|
|
);
|
| 2455 |
|
|
|
| 2456 |
|
|
end stratixiii_rublock;
|
| 2457 |
|
|
|
| 2458 |
|
|
architecture architecture_rublock of stratixiii_rublock is
|
| 2459 |
|
|
|
| 2460 |
|
|
begin
|
| 2461 |
|
|
|
| 2462 |
|
|
end architecture_rublock;
|
| 2463 |
|
|
|
| 2464 |
|
|
|
| 2465 |
|
|
----------------------------------------------------------------------------
|
| 2466 |
|
|
-- Module Name : stratixiii_ram_register
|
| 2467 |
|
|
-- Description : Register module for RAM inputs/outputs
|
| 2468 |
|
|
----------------------------------------------------------------------------
|
| 2469 |
|
|
|
| 2470 |
|
|
LIBRARY IEEE;
|
| 2471 |
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
| 2472 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 2473 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 2474 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 2475 |
|
|
|
| 2476 |
|
|
ENTITY stratixiii_ram_register IS
|
| 2477 |
|
|
|
| 2478 |
|
|
GENERIC (
|
| 2479 |
|
|
width : INTEGER := 1;
|
| 2480 |
|
|
preset : STD_LOGIC := '0';
|
| 2481 |
|
|
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
|
| 2482 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 2483 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 2484 |
|
|
tipd_stall : VitalDelayType01 := DefPropDelay01;
|
| 2485 |
|
|
tipd_aclr : VitalDelayType01 := DefPropDelay01;
|
| 2486 |
|
|
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
|
| 2487 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 2488 |
|
|
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 2489 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 2490 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 2491 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 2492 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 2493 |
|
|
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 2494 |
|
|
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 2495 |
|
|
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 2496 |
|
|
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
|
| 2497 |
|
|
);
|
| 2498 |
|
|
|
| 2499 |
|
|
PORT (
|
| 2500 |
|
|
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
|
| 2501 |
|
|
clk : IN STD_LOGIC;
|
| 2502 |
|
|
ena : IN STD_LOGIC;
|
| 2503 |
|
|
stall : IN STD_LOGIC;
|
| 2504 |
|
|
aclr : IN STD_LOGIC;
|
| 2505 |
|
|
devclrn : IN STD_LOGIC;
|
| 2506 |
|
|
devpor : IN STD_LOGIC;
|
| 2507 |
|
|
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
|
| 2508 |
|
|
aclrout : OUT STD_LOGIC
|
| 2509 |
|
|
);
|
| 2510 |
|
|
|
| 2511 |
|
|
END stratixiii_ram_register;
|
| 2512 |
|
|
|
| 2513 |
|
|
ARCHITECTURE reg_arch OF stratixiii_ram_register IS
|
| 2514 |
|
|
|
| 2515 |
|
|
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
|
| 2516 |
|
|
SIGNAL clk_ipd : STD_LOGIC;
|
| 2517 |
|
|
SIGNAL ena_ipd : STD_LOGIC;
|
| 2518 |
|
|
SIGNAL aclr_ipd : STD_LOGIC;
|
| 2519 |
|
|
SIGNAL stall_ipd : STD_LOGIC;
|
| 2520 |
|
|
|
| 2521 |
|
|
BEGIN
|
| 2522 |
|
|
|
| 2523 |
|
|
WireDelay : BLOCK
|
| 2524 |
|
|
BEGIN
|
| 2525 |
|
|
loopbits : FOR i in d'RANGE GENERATE
|
| 2526 |
|
|
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
|
| 2527 |
|
|
END GENERATE;
|
| 2528 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 2529 |
|
|
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
|
| 2530 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 2531 |
|
|
VitalWireDelay (stall_ipd, stall, tipd_stall);
|
| 2532 |
|
|
END BLOCK;
|
| 2533 |
|
|
|
| 2534 |
|
|
-- REMSTRATIXIII PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
|
| 2535 |
|
|
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
|
| 2536 |
|
|
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
|
| 2537 |
|
|
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
|
| 2538 |
|
|
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
|
| 2539 |
|
|
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
|
| 2540 |
|
|
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
|
| 2541 |
|
|
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
|
| 2542 |
|
|
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 2543 |
|
|
VARIABLE Tviol_ena : STD_ULOGIC := '0';
|
| 2544 |
|
|
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
|
| 2545 |
|
|
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
|
| 2546 |
|
|
VARIABLE CQDelay : TIME := 0 ns;
|
| 2547 |
|
|
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
|
| 2548 |
|
|
BEGIN
|
| 2549 |
|
|
|
| 2550 |
|
|
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
|
| 2551 |
|
|
q_reg := (OTHERS => preset);
|
| 2552 |
|
|
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
|
| 2553 |
|
|
q_reg := d_ipd;
|
| 2554 |
|
|
END IF;
|
| 2555 |
|
|
|
| 2556 |
|
|
-- Timing checks
|
| 2557 |
|
|
VitalSetupHoldCheck (
|
| 2558 |
|
|
Violation => Tviol_clk_ena,
|
| 2559 |
|
|
TimingData => TimingData_clk_ena,
|
| 2560 |
|
|
TestSignal => ena_ipd,
|
| 2561 |
|
|
TestSignalName => "ena",
|
| 2562 |
|
|
RefSignal => clk_ipd,
|
| 2563 |
|
|
RefSignalName => "clk",
|
| 2564 |
|
|
SetupHigh => tsetup_ena_clk_noedge_posedge,
|
| 2565 |
|
|
SetupLow => tsetup_ena_clk_noedge_posedge,
|
| 2566 |
|
|
HoldHigh => thold_ena_clk_noedge_posedge,
|
| 2567 |
|
|
HoldLow => thold_ena_clk_noedge_posedge,
|
| 2568 |
|
|
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
|
| 2569 |
|
|
RefTransition => '/',
|
| 2570 |
|
|
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
|
| 2571 |
|
|
XOn => DefXOnChecks,
|
| 2572 |
|
|
MsgOn => DefMsgOnChecks );
|
| 2573 |
|
|
|
| 2574 |
|
|
VitalSetupHoldCheck (
|
| 2575 |
|
|
Violation => Tviol_clk_ena,
|
| 2576 |
|
|
TimingData => TimingData_clk_stall,
|
| 2577 |
|
|
TestSignal => stall_ipd,
|
| 2578 |
|
|
TestSignalName => "stall",
|
| 2579 |
|
|
RefSignal => clk_ipd,
|
| 2580 |
|
|
RefSignalName => "clk",
|
| 2581 |
|
|
SetupHigh => tsetup_stall_clk_noedge_posedge,
|
| 2582 |
|
|
SetupLow => tsetup_stall_clk_noedge_posedge,
|
| 2583 |
|
|
HoldHigh => thold_stall_clk_noedge_posedge,
|
| 2584 |
|
|
HoldLow => thold_stall_clk_noedge_posedge,
|
| 2585 |
|
|
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
|
| 2586 |
|
|
RefTransition => '/',
|
| 2587 |
|
|
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
|
| 2588 |
|
|
XOn => DefXOnChecks,
|
| 2589 |
|
|
MsgOn => DefMsgOnChecks );
|
| 2590 |
|
|
|
| 2591 |
|
|
VitalSetupHoldCheck (
|
| 2592 |
|
|
Violation => Tviol_clk_aclr,
|
| 2593 |
|
|
TimingData => TimingData_clk_aclr,
|
| 2594 |
|
|
TestSignal => aclr_ipd,
|
| 2595 |
|
|
TestSignalName => "aclr",
|
| 2596 |
|
|
RefSignal => clk_ipd,
|
| 2597 |
|
|
RefSignalName => "clk",
|
| 2598 |
|
|
SetupHigh => tsetup_aclr_clk_noedge_posedge,
|
| 2599 |
|
|
SetupLow => tsetup_aclr_clk_noedge_posedge,
|
| 2600 |
|
|
HoldHigh => thold_aclr_clk_noedge_posedge,
|
| 2601 |
|
|
HoldLow => thold_aclr_clk_noedge_posedge,
|
| 2602 |
|
|
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
|
| 2603 |
|
|
RefTransition => '/',
|
| 2604 |
|
|
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
|
| 2605 |
|
|
XOn => DefXOnChecks,
|
| 2606 |
|
|
MsgOn => DefMsgOnChecks );
|
| 2607 |
|
|
|
| 2608 |
|
|
VitalSetupHoldCheck (
|
| 2609 |
|
|
Violation => Tviol_data_clk,
|
| 2610 |
|
|
TimingData => TimingData_data_clk,
|
| 2611 |
|
|
TestSignal => d_ipd,
|
| 2612 |
|
|
TestSignalName => "data",
|
| 2613 |
|
|
RefSignal => clk_ipd,
|
| 2614 |
|
|
RefSignalName => "clk",
|
| 2615 |
|
|
SetupHigh => tsetup_d_clk_noedge_posedge,
|
| 2616 |
|
|
SetupLow => tsetup_d_clk_noedge_posedge,
|
| 2617 |
|
|
HoldHigh => thold_d_clk_noedge_posedge,
|
| 2618 |
|
|
HoldLow => thold_d_clk_noedge_posedge,
|
| 2619 |
|
|
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
|
| 2620 |
|
|
RefTransition => '/',
|
| 2621 |
|
|
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
|
| 2622 |
|
|
XOn => DefXOnChecks,
|
| 2623 |
|
|
MsgOn => DefMsgOnChecks );
|
| 2624 |
|
|
|
| 2625 |
|
|
VitalPeriodPulseCheck (
|
| 2626 |
|
|
Violation => Tviol_ena,
|
| 2627 |
|
|
PeriodData => PeriodData_ena,
|
| 2628 |
|
|
TestSignal => ena_ipd,
|
| 2629 |
|
|
TestSignalName => "ena",
|
| 2630 |
|
|
PulseWidthHigh => tpw_ena_posedge,
|
| 2631 |
|
|
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
|
| 2632 |
|
|
XOn => DefXOnChecks,
|
| 2633 |
|
|
MsgOn => DefMsgOnChecks );
|
| 2634 |
|
|
|
| 2635 |
|
|
-- Path Delay Selection
|
| 2636 |
|
|
CQDelay := SelectDelay (
|
| 2637 |
|
|
Paths => (
|
| 2638 |
|
|
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
|
| 2639 |
|
|
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
|
| 2640 |
|
|
)
|
| 2641 |
|
|
);
|
| 2642 |
|
|
q <= TRANSPORT q_reg AFTER CQDelay;
|
| 2643 |
|
|
|
| 2644 |
|
|
END PROCESS;
|
| 2645 |
|
|
|
| 2646 |
|
|
aclrout <= aclr_ipd;
|
| 2647 |
|
|
|
| 2648 |
|
|
END reg_arch;
|
| 2649 |
|
|
|
| 2650 |
|
|
----------------------------------------------------------------------------
|
| 2651 |
|
|
-- Module Name : stratixiii_ram_pulse_generator
|
| 2652 |
|
|
-- Description : Generate pulse to initiate memory read/write operations
|
| 2653 |
|
|
----------------------------------------------------------------------------
|
| 2654 |
|
|
|
| 2655 |
|
|
LIBRARY IEEE;
|
| 2656 |
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
| 2657 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 2658 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 2659 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 2660 |
|
|
|
| 2661 |
|
|
ENTITY stratixiii_ram_pulse_generator IS
|
| 2662 |
|
|
GENERIC (
|
| 2663 |
|
|
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
|
| 2664 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 2665 |
|
|
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
|
| 2666 |
|
|
);
|
| 2667 |
|
|
PORT (
|
| 2668 |
|
|
clk,ena : IN STD_LOGIC;
|
| 2669 |
|
|
delaywrite : IN STD_LOGIC := '0';
|
| 2670 |
|
|
pulse,cycle : OUT STD_LOGIC
|
| 2671 |
|
|
);
|
| 2672 |
|
|
ATTRIBUTE VITAL_Level0 OF stratixiii_ram_pulse_generator:ENTITY IS TRUE;
|
| 2673 |
|
|
END stratixiii_ram_pulse_generator;
|
| 2674 |
|
|
|
| 2675 |
|
|
ARCHITECTURE pgen_arch OF stratixiii_ram_pulse_generator IS
|
| 2676 |
|
|
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
|
| 2677 |
|
|
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
|
| 2678 |
|
|
SIGNAL state : STD_LOGIC;
|
| 2679 |
|
|
BEGIN
|
| 2680 |
|
|
|
| 2681 |
|
|
WireDelay : BLOCK
|
| 2682 |
|
|
BEGIN
|
| 2683 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 2684 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 2685 |
|
|
END BLOCK;
|
| 2686 |
|
|
|
| 2687 |
|
|
PROCESS (clk_ipd,state)
|
| 2688 |
|
|
BEGIN
|
| 2689 |
|
|
IF (state = '1' AND state'EVENT) THEN
|
| 2690 |
|
|
state <= '0';
|
| 2691 |
|
|
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
|
| 2692 |
|
|
IF (delaywrite = '1') THEN
|
| 2693 |
|
|
state <= '1' AFTER 1 NS; -- delayed write
|
| 2694 |
|
|
ELSE
|
| 2695 |
|
|
state <= '1';
|
| 2696 |
|
|
END IF;
|
| 2697 |
|
|
END IF;
|
| 2698 |
|
|
END PROCESS;
|
| 2699 |
|
|
|
| 2700 |
|
|
PathDelay : PROCESS
|
| 2701 |
|
|
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
|
| 2702 |
|
|
BEGIN
|
| 2703 |
|
|
WAIT UNTIL state'EVENT;
|
| 2704 |
|
|
VitalPathDelay01 (
|
| 2705 |
|
|
OutSignal => pulse,
|
| 2706 |
|
|
OutSignalName => "pulse",
|
| 2707 |
|
|
OutTemp => state,
|
| 2708 |
|
|
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
|
| 2709 |
|
|
GlitchData => pulse_VitalGlitchData,
|
| 2710 |
|
|
Mode => DefGlitchMode,
|
| 2711 |
|
|
XOn => DefXOnChecks,
|
| 2712 |
|
|
MsgOn => DefMsgOnChecks
|
| 2713 |
|
|
);
|
| 2714 |
|
|
END PROCESS;
|
| 2715 |
|
|
|
| 2716 |
|
|
cycle <= clk_ipd;
|
| 2717 |
|
|
|
| 2718 |
|
|
END pgen_arch;
|
| 2719 |
|
|
|
| 2720 |
|
|
LIBRARY IEEE;
|
| 2721 |
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
| 2722 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 2723 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 2724 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 2725 |
|
|
USE work.stratixiii_ram_register;
|
| 2726 |
|
|
USE work.stratixiii_ram_pulse_generator;
|
| 2727 |
|
|
|
| 2728 |
|
|
ENTITY stratixiii_ram_block IS
|
| 2729 |
|
|
GENERIC (
|
| 2730 |
|
|
-- -------- GLOBAL PARAMETERS ---------
|
| 2731 |
|
|
operation_mode : STRING := "single_port";
|
| 2732 |
|
|
mixed_port_feed_through_mode : STRING := "dont_care";
|
| 2733 |
|
|
ram_block_type : STRING := "auto";
|
| 2734 |
|
|
logical_ram_name : STRING := "ram_name";
|
| 2735 |
|
|
init_file : STRING := "init_file.hex";
|
| 2736 |
|
|
init_file_layout : STRING := "none";
|
| 2737 |
|
|
enable_ecc : STRING := "false";
|
| 2738 |
|
|
data_interleave_width_in_bits : INTEGER := 1;
|
| 2739 |
|
|
data_interleave_offset_in_bits : INTEGER := 1;
|
| 2740 |
|
|
port_a_logical_ram_depth : INTEGER := 0;
|
| 2741 |
|
|
port_a_logical_ram_width : INTEGER := 0;
|
| 2742 |
|
|
port_a_first_address : INTEGER := 0;
|
| 2743 |
|
|
port_a_last_address : INTEGER := 0;
|
| 2744 |
|
|
port_a_first_bit_number : INTEGER := 0;
|
| 2745 |
|
|
port_a_address_clear : STRING := "none";
|
| 2746 |
|
|
port_a_data_out_clear : STRING := "none";
|
| 2747 |
|
|
port_a_data_in_clock : STRING := "clock0";
|
| 2748 |
|
|
port_a_address_clock : STRING := "clock0";
|
| 2749 |
|
|
port_a_write_enable_clock : STRING := "clock0";
|
| 2750 |
|
|
port_a_read_enable_clock : STRING := "clock0";
|
| 2751 |
|
|
port_a_byte_enable_clock : STRING := "clock0";
|
| 2752 |
|
|
port_a_data_out_clock : STRING := "none";
|
| 2753 |
|
|
port_a_data_width : INTEGER := 1;
|
| 2754 |
|
|
port_a_address_width : INTEGER := 1;
|
| 2755 |
|
|
port_a_byte_enable_mask_width : INTEGER := 1;
|
| 2756 |
|
|
port_b_logical_ram_depth : INTEGER := 0;
|
| 2757 |
|
|
port_b_logical_ram_width : INTEGER := 0;
|
| 2758 |
|
|
port_b_first_address : INTEGER := 0;
|
| 2759 |
|
|
port_b_last_address : INTEGER := 0;
|
| 2760 |
|
|
port_b_first_bit_number : INTEGER := 0;
|
| 2761 |
|
|
port_b_address_clear : STRING := "none";
|
| 2762 |
|
|
port_b_data_out_clear : STRING := "none";
|
| 2763 |
|
|
port_b_data_in_clock : STRING := "clock1";
|
| 2764 |
|
|
port_b_address_clock : STRING := "clock1";
|
| 2765 |
|
|
port_b_write_enable_clock: STRING := "clock1";
|
| 2766 |
|
|
port_b_read_enable_clock: STRING := "clock1";
|
| 2767 |
|
|
port_b_byte_enable_clock : STRING := "clock1";
|
| 2768 |
|
|
port_b_data_out_clock : STRING := "none";
|
| 2769 |
|
|
port_b_data_width : INTEGER := 1;
|
| 2770 |
|
|
port_b_address_width : INTEGER := 1;
|
| 2771 |
|
|
port_b_byte_enable_mask_width : INTEGER := 1;
|
| 2772 |
|
|
|
| 2773 |
|
|
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
|
| 2774 |
|
|
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
|
| 2775 |
|
|
power_up_uninitialized : STRING := "false";
|
| 2776 |
|
|
port_b_byte_size : INTEGER := 0;
|
| 2777 |
|
|
port_a_byte_size : INTEGER := 0;
|
| 2778 |
|
|
lpm_type : string := "stratixiii_ram_block";
|
| 2779 |
|
|
lpm_hint : string := "true";
|
| 2780 |
|
|
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
|
| 2781 |
|
|
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
|
| 2782 |
|
|
clk0_output_clock_enable : STRING := "none"; -- ena0,none
|
| 2783 |
|
|
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
|
| 2784 |
|
|
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
|
| 2785 |
|
|
clk1_output_clock_enable : STRING := "none"; -- ena1,none
|
| 2786 |
|
|
mem_init0 : BIT_VECTOR := X"0";
|
| 2787 |
|
|
mem_init1 : BIT_VECTOR := X"0";
|
| 2788 |
|
|
mem_init2 : BIT_VECTOR := X"0";
|
| 2789 |
|
|
mem_init3 : BIT_VECTOR := X"0";
|
| 2790 |
|
|
mem_init4 : BIT_VECTOR := X"0";
|
| 2791 |
|
|
mem_init5 : BIT_VECTOR := X"0";
|
| 2792 |
|
|
mem_init6 : BIT_VECTOR := X"0";
|
| 2793 |
|
|
mem_init7 : BIT_VECTOR := X"0";
|
| 2794 |
|
|
mem_init8 : BIT_VECTOR := X"0";
|
| 2795 |
|
|
mem_init9 : BIT_VECTOR := X"0";
|
| 2796 |
|
|
mem_init10 : BIT_VECTOR := X"0";
|
| 2797 |
|
|
mem_init11 : BIT_VECTOR := X"0";
|
| 2798 |
|
|
mem_init12 : BIT_VECTOR := X"0";
|
| 2799 |
|
|
mem_init13 : BIT_VECTOR := X"0";
|
| 2800 |
|
|
mem_init14 : BIT_VECTOR := X"0";
|
| 2801 |
|
|
mem_init15 : BIT_VECTOR := X"0";
|
| 2802 |
|
|
mem_init16 : BIT_VECTOR := X"0";
|
| 2803 |
|
|
mem_init17 : BIT_VECTOR := X"0";
|
| 2804 |
|
|
mem_init18 : BIT_VECTOR := X"0";
|
| 2805 |
|
|
mem_init19 : BIT_VECTOR := X"0";
|
| 2806 |
|
|
mem_init20 : BIT_VECTOR := X"0";
|
| 2807 |
|
|
mem_init21 : BIT_VECTOR := X"0";
|
| 2808 |
|
|
mem_init22 : BIT_VECTOR := X"0";
|
| 2809 |
|
|
mem_init23 : BIT_VECTOR := X"0";
|
| 2810 |
|
|
mem_init24 : BIT_VECTOR := X"0";
|
| 2811 |
|
|
mem_init25 : BIT_VECTOR := X"0";
|
| 2812 |
|
|
mem_init26 : BIT_VECTOR := X"0";
|
| 2813 |
|
|
mem_init27 : BIT_VECTOR := X"0";
|
| 2814 |
|
|
mem_init28 : BIT_VECTOR := X"0";
|
| 2815 |
|
|
mem_init29 : BIT_VECTOR := X"0";
|
| 2816 |
|
|
mem_init30 : BIT_VECTOR := X"0";
|
| 2817 |
|
|
mem_init31 : BIT_VECTOR := X"0";
|
| 2818 |
|
|
mem_init32 : BIT_VECTOR := X"0";
|
| 2819 |
|
|
mem_init33 : BIT_VECTOR := X"0";
|
| 2820 |
|
|
mem_init34 : BIT_VECTOR := X"0";
|
| 2821 |
|
|
mem_init35 : BIT_VECTOR := X"0";
|
| 2822 |
|
|
mem_init36 : BIT_VECTOR := X"0";
|
| 2823 |
|
|
mem_init37 : BIT_VECTOR := X"0";
|
| 2824 |
|
|
mem_init38 : BIT_VECTOR := X"0";
|
| 2825 |
|
|
mem_init39 : BIT_VECTOR := X"0";
|
| 2826 |
|
|
mem_init40 : BIT_VECTOR := X"0";
|
| 2827 |
|
|
mem_init41 : BIT_VECTOR := X"0";
|
| 2828 |
|
|
mem_init42 : BIT_VECTOR := X"0";
|
| 2829 |
|
|
mem_init43 : BIT_VECTOR := X"0";
|
| 2830 |
|
|
mem_init44 : BIT_VECTOR := X"0";
|
| 2831 |
|
|
mem_init45 : BIT_VECTOR := X"0";
|
| 2832 |
|
|
mem_init46 : BIT_VECTOR := X"0";
|
| 2833 |
|
|
mem_init47 : BIT_VECTOR := X"0";
|
| 2834 |
|
|
mem_init48 : BIT_VECTOR := X"0";
|
| 2835 |
|
|
mem_init49 : BIT_VECTOR := X"0";
|
| 2836 |
|
|
mem_init50 : BIT_VECTOR := X"0";
|
| 2837 |
|
|
mem_init51 : BIT_VECTOR := X"0";
|
| 2838 |
|
|
mem_init52 : BIT_VECTOR := X"0";
|
| 2839 |
|
|
mem_init53 : BIT_VECTOR := X"0";
|
| 2840 |
|
|
mem_init54 : BIT_VECTOR := X"0";
|
| 2841 |
|
|
mem_init55 : BIT_VECTOR := X"0";
|
| 2842 |
|
|
mem_init56 : BIT_VECTOR := X"0";
|
| 2843 |
|
|
mem_init57 : BIT_VECTOR := X"0";
|
| 2844 |
|
|
mem_init58 : BIT_VECTOR := X"0";
|
| 2845 |
|
|
mem_init59 : BIT_VECTOR := X"0";
|
| 2846 |
|
|
mem_init60 : BIT_VECTOR := X"0";
|
| 2847 |
|
|
mem_init61 : BIT_VECTOR := X"0";
|
| 2848 |
|
|
mem_init62 : BIT_VECTOR := X"0";
|
| 2849 |
|
|
mem_init63 : BIT_VECTOR := X"0";
|
| 2850 |
|
|
mem_init64 : BIT_VECTOR := X"0";
|
| 2851 |
|
|
mem_init65 : BIT_VECTOR := X"0";
|
| 2852 |
|
|
mem_init66 : BIT_VECTOR := X"0";
|
| 2853 |
|
|
mem_init67 : BIT_VECTOR := X"0";
|
| 2854 |
|
|
mem_init68 : BIT_VECTOR := X"0";
|
| 2855 |
|
|
mem_init69 : BIT_VECTOR := X"0";
|
| 2856 |
|
|
mem_init70 : BIT_VECTOR := X"0";
|
| 2857 |
|
|
mem_init71 : BIT_VECTOR := X"0";
|
| 2858 |
|
|
connectivity_checking : string := "off"
|
| 2859 |
|
|
);
|
| 2860 |
|
|
-- -------- PORT DECLARATIONS ---------
|
| 2861 |
|
|
PORT (
|
| 2862 |
|
|
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
|
| 2863 |
|
|
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
|
| 2864 |
|
|
portawe : IN STD_LOGIC := '0';
|
| 2865 |
|
|
portare : IN STD_LOGIC := '1';
|
| 2866 |
|
|
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
|
| 2867 |
|
|
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
|
| 2868 |
|
|
portbwe : IN STD_LOGIC := '0';
|
| 2869 |
|
|
portbre : IN STD_LOGIC := '1';
|
| 2870 |
|
|
clk0 : IN STD_LOGIC := '0';
|
| 2871 |
|
|
clk1 : IN STD_LOGIC := '0';
|
| 2872 |
|
|
ena0 : IN STD_LOGIC := '1';
|
| 2873 |
|
|
ena1 : IN STD_LOGIC := '1';
|
| 2874 |
|
|
ena2 : IN STD_LOGIC := '1';
|
| 2875 |
|
|
ena3 : IN STD_LOGIC := '1';
|
| 2876 |
|
|
clr0 : IN STD_LOGIC := '0';
|
| 2877 |
|
|
clr1 : IN STD_LOGIC := '0';
|
| 2878 |
|
|
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
|
| 2879 |
|
|
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
|
| 2880 |
|
|
devclrn : IN STD_LOGIC := '1';
|
| 2881 |
|
|
devpor : IN STD_LOGIC := '1';
|
| 2882 |
|
|
portaaddrstall : IN STD_LOGIC := '0';
|
| 2883 |
|
|
portbaddrstall : IN STD_LOGIC := '0';
|
| 2884 |
|
|
eccstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
|
| 2885 |
|
|
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
|
| 2886 |
|
|
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
|
| 2887 |
|
|
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
|
| 2888 |
|
|
);
|
| 2889 |
|
|
|
| 2890 |
|
|
END stratixiii_ram_block;
|
| 2891 |
|
|
|
| 2892 |
|
|
ARCHITECTURE block_arch OF stratixiii_ram_block IS
|
| 2893 |
|
|
|
| 2894 |
|
|
COMPONENT stratixiii_ram_pulse_generator
|
| 2895 |
|
|
PORT (
|
| 2896 |
|
|
clk : IN STD_LOGIC;
|
| 2897 |
|
|
ena : IN STD_LOGIC;
|
| 2898 |
|
|
delaywrite : IN STD_LOGIC := '0';
|
| 2899 |
|
|
pulse : OUT STD_LOGIC;
|
| 2900 |
|
|
cycle : OUT STD_LOGIC
|
| 2901 |
|
|
);
|
| 2902 |
|
|
END COMPONENT;
|
| 2903 |
|
|
|
| 2904 |
|
|
COMPONENT stratixiii_ram_register
|
| 2905 |
|
|
GENERIC (
|
| 2906 |
|
|
preset : STD_LOGIC := '0';
|
| 2907 |
|
|
width : integer := 1
|
| 2908 |
|
|
);
|
| 2909 |
|
|
PORT (
|
| 2910 |
|
|
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
|
| 2911 |
|
|
clk : IN STD_LOGIC;
|
| 2912 |
|
|
aclr : IN STD_LOGIC;
|
| 2913 |
|
|
devclrn : IN STD_LOGIC;
|
| 2914 |
|
|
devpor : IN STD_LOGIC;
|
| 2915 |
|
|
ena : IN STD_LOGIC;
|
| 2916 |
|
|
stall : IN STD_LOGIC;
|
| 2917 |
|
|
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
|
| 2918 |
|
|
aclrout : OUT STD_LOGIC
|
| 2919 |
|
|
);
|
| 2920 |
|
|
END COMPONENT;
|
| 2921 |
|
|
|
| 2922 |
|
|
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
|
| 2923 |
|
|
VARIABLE c: INTEGER;
|
| 2924 |
|
|
BEGIN
|
| 2925 |
|
|
IF (condition) THEN c := a; ELSE c := b; END IF;
|
| 2926 |
|
|
RETURN c;
|
| 2927 |
|
|
END;
|
| 2928 |
|
|
|
| 2929 |
|
|
SUBTYPE port_type IS BOOLEAN;
|
| 2930 |
|
|
|
| 2931 |
|
|
CONSTANT primary : port_type := TRUE;
|
| 2932 |
|
|
CONSTANT secondary : port_type := FALSE;
|
| 2933 |
|
|
|
| 2934 |
|
|
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
|
| 2935 |
|
|
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
|
| 2936 |
|
|
|
| 2937 |
|
|
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
|
| 2938 |
|
|
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
|
| 2939 |
|
|
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
|
| 2940 |
|
|
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
|
| 2941 |
|
|
|
| 2942 |
|
|
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
|
| 2943 |
|
|
AND (port_a_data_width /= port_b_data_width);
|
| 2944 |
|
|
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
|
| 2945 |
|
|
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
|
| 2946 |
|
|
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
|
| 2947 |
|
|
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
|
| 2948 |
|
|
|
| 2949 |
|
|
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
|
| 2950 |
|
|
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
|
| 2951 |
|
|
|
| 2952 |
|
|
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
|
| 2953 |
|
|
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
|
| 2954 |
|
|
|
| 2955 |
|
|
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
|
| 2956 |
|
|
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
|
| 2957 |
|
|
|
| 2958 |
|
|
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
|
| 2959 |
|
|
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
|
| 2960 |
|
|
|
| 2961 |
|
|
CONSTANT ram_type : BOOLEAN := FALSE;
|
| 2962 |
|
|
|
| 2963 |
|
|
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
|
| 2964 |
|
|
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
|
| 2965 |
|
|
|
| 2966 |
|
|
-- Hardware write modes
|
| 2967 |
|
|
|
| 2968 |
|
|
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
|
| 2969 |
|
|
operation_mode = "bidir_dual_port") AND
|
| 2970 |
|
|
(port_b_address_clock = "clock1");
|
| 2971 |
|
|
CONSTANT both_new_data_same_port : BOOLEAN := (
|
| 2972 |
|
|
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
|
| 2973 |
|
|
(port_a_read_during_write_mode = "dont_care")) AND
|
| 2974 |
|
|
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
|
| 2975 |
|
|
(port_b_read_during_write_mode = "dont_care"))
|
| 2976 |
|
|
);
|
| 2977 |
|
|
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
|
| 2978 |
|
|
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
|
| 2979 |
|
|
|
| 2980 |
|
|
SIGNAL delay_write_pulse_a : STD_LOGIC ;
|
| 2981 |
|
|
SIGNAL delay_write_pulse_b : STD_LOGIC ;
|
| 2982 |
|
|
|
| 2983 |
|
|
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
|
| 2984 |
|
|
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
|
| 2985 |
|
|
|
| 2986 |
|
|
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
|
| 2987 |
|
|
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
|
| 2988 |
|
|
|
| 2989 |
|
|
SIGNAL read_before_write_a : BOOLEAN;
|
| 2990 |
|
|
SIGNAL read_before_write_b : BOOLEAN;
|
| 2991 |
|
|
|
| 2992 |
|
|
-- -------- internal signals ---------
|
| 2993 |
|
|
-- clock / clock enable
|
| 2994 |
|
|
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
|
| 2995 |
|
|
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
|
| 2996 |
|
|
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
|
| 2997 |
|
|
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
|
| 2998 |
|
|
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
|
| 2999 |
|
|
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
|
| 3000 |
|
|
|
| 3001 |
|
|
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
|
| 3002 |
|
|
SIGNAL clk_a_core : STD_LOGIC;
|
| 3003 |
|
|
|
| 3004 |
|
|
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
|
| 3005 |
|
|
SIGNAL clk_b_core : STD_LOGIC;
|
| 3006 |
|
|
|
| 3007 |
|
|
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
|
| 3008 |
|
|
|
| 3009 |
|
|
-- asynch clear
|
| 3010 |
|
|
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
|
| 3011 |
|
|
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
|
| 3012 |
|
|
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
|
| 3013 |
|
|
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
|
| 3014 |
|
|
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
|
| 3015 |
|
|
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
|
| 3016 |
|
|
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
|
| 3017 |
|
|
|
| 3018 |
|
|
|
| 3019 |
|
|
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
|
| 3020 |
|
|
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
|
| 3021 |
|
|
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
|
| 3022 |
|
|
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
|
| 3023 |
|
|
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
|
| 3024 |
|
|
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
|
| 3025 |
|
|
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
|
| 3026 |
|
|
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
|
| 3027 |
|
|
SIGNAL clear_asserted_during_write : clear_vec_type;
|
| 3028 |
|
|
|
| 3029 |
|
|
|
| 3030 |
|
|
-- port A registers
|
| 3031 |
|
|
SIGNAL we_a_reg : STD_LOGIC;
|
| 3032 |
|
|
SIGNAL re_a_reg : STD_LOGIC;
|
| 3033 |
|
|
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
|
| 3034 |
|
|
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
|
| 3035 |
|
|
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
|
| 3036 |
|
|
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
|
| 3037 |
|
|
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
|
| 3038 |
|
|
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
|
| 3039 |
|
|
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
|
| 3040 |
|
|
-- port B registers
|
| 3041 |
|
|
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
|
| 3042 |
|
|
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
|
| 3043 |
|
|
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
|
| 3044 |
|
|
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
|
| 3045 |
|
|
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
|
| 3046 |
|
|
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
|
| 3047 |
|
|
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
|
| 3048 |
|
|
-- pulses
|
| 3049 |
|
|
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
|
| 3050 |
|
|
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
|
| 3051 |
|
|
SIGNAL rw_pulse : pulse_vec;
|
| 3052 |
|
|
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
|
| 3053 |
|
|
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
|
| 3054 |
|
|
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
|
| 3055 |
|
|
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
|
| 3056 |
|
|
-- registered address
|
| 3057 |
|
|
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
|
| 3058 |
|
|
-- input/output
|
| 3059 |
|
|
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
|
| 3060 |
|
|
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
|
| 3061 |
|
|
-- overlapping location write
|
| 3062 |
|
|
SIGNAL dual_write : BOOLEAN;
|
| 3063 |
|
|
-- byte enable mask write
|
| 3064 |
|
|
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
|
| 3065 |
|
|
SIGNAL be_mask_write : be_mask_write_vec;
|
| 3066 |
|
|
-- memory core
|
| 3067 |
|
|
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
|
| 3068 |
|
|
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
|
| 3069 |
|
|
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
|
| 3070 |
|
|
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
|
| 3071 |
|
|
SIGNAL mem : mem_type;
|
| 3072 |
|
|
SIGNAL init_mem : BOOLEAN := FALSE;
|
| 3073 |
|
|
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
|
| 3074 |
|
|
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
|
| 3075 |
|
|
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
|
| 3076 |
|
|
SIGNAL mem_data : mem_row_type;
|
| 3077 |
|
|
SIGNAL old_mem_data : mem_row_type;
|
| 3078 |
|
|
SIGNAL mem_unit_data : mem_col_type;
|
| 3079 |
|
|
|
| 3080 |
|
|
-- latches
|
| 3081 |
|
|
TYPE read_latch_rec IS RECORD
|
| 3082 |
|
|
prime : mem_row_type;
|
| 3083 |
|
|
sec : mem_col_type;
|
| 3084 |
|
|
END RECORD;
|
| 3085 |
|
|
SIGNAL read_latch : read_latch_rec;
|
| 3086 |
|
|
-- (row,column) coordinates
|
| 3087 |
|
|
SIGNAL row_sec,col_sec : INTEGER;
|
| 3088 |
|
|
-- byte enable
|
| 3089 |
|
|
TYPE mask_type IS (normal,inverse);
|
| 3090 |
|
|
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
|
| 3091 |
|
|
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
|
| 3092 |
|
|
TYPE mask_rec IS RECORD
|
| 3093 |
|
|
prime : mask_prime_type;
|
| 3094 |
|
|
sec : mask_sec_type;
|
| 3095 |
|
|
END RECORD;
|
| 3096 |
|
|
SIGNAL mask_vector : mask_rec;
|
| 3097 |
|
|
SIGNAL mask_vector_common : mem_col_type;
|
| 3098 |
|
|
|
| 3099 |
|
|
FUNCTION get_mask(
|
| 3100 |
|
|
b_ena : IN STD_LOGIC_VECTOR;
|
| 3101 |
|
|
mode : port_type;
|
| 3102 |
|
|
CONSTANT b_ena_width ,byte_size: INTEGER
|
| 3103 |
|
|
) RETURN mask_rec IS
|
| 3104 |
|
|
|
| 3105 |
|
|
VARIABLE l : INTEGER;
|
| 3106 |
|
|
VARIABLE mask : mask_rec := (
|
| 3107 |
|
|
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
|
| 3108 |
|
|
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
|
| 3109 |
|
|
);
|
| 3110 |
|
|
BEGIN
|
| 3111 |
|
|
FOR l in 0 TO b_ena_width - 1 LOOP
|
| 3112 |
|
|
IF (b_ena(l) = '0') THEN
|
| 3113 |
|
|
IF (mode = primary) THEN
|
| 3114 |
|
|
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
|
| 3115 |
|
|
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
|
| 3116 |
|
|
ELSE
|
| 3117 |
|
|
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
|
| 3118 |
|
|
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
|
| 3119 |
|
|
END IF;
|
| 3120 |
|
|
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
|
| 3121 |
|
|
IF (mode = primary) THEN
|
| 3122 |
|
|
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
|
| 3123 |
|
|
ELSE
|
| 3124 |
|
|
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
|
| 3125 |
|
|
END IF;
|
| 3126 |
|
|
END IF;
|
| 3127 |
|
|
END LOOP;
|
| 3128 |
|
|
RETURN mask;
|
| 3129 |
|
|
END get_mask;
|
| 3130 |
|
|
-- port active for read/write
|
| 3131 |
|
|
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
|
| 3132 |
|
|
SIGNAL active_a_in,active_b_in : STD_LOGIC;
|
| 3133 |
|
|
SIGNAL active_write_a : BOOLEAN;
|
| 3134 |
|
|
SIGNAL active_write_b : BOOLEAN;
|
| 3135 |
|
|
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
|
| 3136 |
|
|
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
|
| 3137 |
|
|
SIGNAL active_a_core, active_b_core : BOOLEAN;
|
| 3138 |
|
|
SIGNAL wire_vcc : STD_LOGIC := '1';
|
| 3139 |
|
|
SIGNAL wire_gnd : STD_LOGIC := '0';
|
| 3140 |
|
|
|
| 3141 |
|
|
|
| 3142 |
|
|
|
| 3143 |
|
|
|
| 3144 |
|
|
|
| 3145 |
|
|
|
| 3146 |
|
|
BEGIN
|
| 3147 |
|
|
-- memory initialization
|
| 3148 |
|
|
init_mem <= TRUE;
|
| 3149 |
|
|
-- hardware write modes
|
| 3150 |
|
|
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
|
| 3151 |
|
|
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
|
| 3152 |
|
|
" FW" WHEN (dual_clock OR (
|
| 3153 |
|
|
mixed_port_feed_through_mode = "dont_care" AND
|
| 3154 |
|
|
both_new_data_same_port
|
| 3155 |
|
|
)) ELSE
|
| 3156 |
|
|
" DW";
|
| 3157 |
|
|
|
| 3158 |
|
|
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
|
| 3159 |
|
|
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
|
| 3160 |
|
|
" FW" WHEN (dual_clock OR (
|
| 3161 |
|
|
mixed_port_feed_through_mode = "dont_care" AND
|
| 3162 |
|
|
both_new_data_same_port
|
| 3163 |
|
|
)) ELSE
|
| 3164 |
|
|
" DW";
|
| 3165 |
|
|
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
|
| 3166 |
|
|
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
|
| 3167 |
|
|
read_before_write_a <= (hw_write_mode_a = "R+W");
|
| 3168 |
|
|
read_before_write_b <= (hw_write_mode_b = "R+W");
|
| 3169 |
|
|
|
| 3170 |
|
|
-- -------- core logic ---------------
|
| 3171 |
|
|
clk_a_in <= clk0;
|
| 3172 |
|
|
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
|
| 3173 |
|
|
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
|
| 3174 |
|
|
|
| 3175 |
|
|
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
|
| 3176 |
|
|
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
|
| 3177 |
|
|
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
|
| 3178 |
|
|
|
| 3179 |
|
|
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
|
| 3180 |
|
|
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
|
| 3181 |
|
|
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
|
| 3182 |
|
|
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
|
| 3183 |
|
|
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
|
| 3184 |
|
|
clk1;
|
| 3185 |
|
|
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
|
| 3186 |
|
|
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
|
| 3187 |
|
|
clk1;
|
| 3188 |
|
|
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
|
| 3189 |
|
|
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
|
| 3190 |
|
|
|
| 3191 |
|
|
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
|
| 3192 |
|
|
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
|
| 3193 |
|
|
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
|
| 3194 |
|
|
|
| 3195 |
|
|
datain_a_clr_in <= '0';
|
| 3196 |
|
|
datain_b_clr_in <= '0';
|
| 3197 |
|
|
|
| 3198 |
|
|
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
|
| 3199 |
|
|
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
|
| 3200 |
|
|
|
| 3201 |
|
|
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
|
| 3202 |
|
|
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
|
| 3203 |
|
|
|
| 3204 |
|
|
byteena_a_clr_in <= '0';
|
| 3205 |
|
|
byteena_b_clr_in <= '0';
|
| 3206 |
|
|
we_a_clr_in <= '0';
|
| 3207 |
|
|
re_a_clr_in <= '0';
|
| 3208 |
|
|
we_b_clr_in <= '0';
|
| 3209 |
|
|
re_b_clr_in <= '0';
|
| 3210 |
|
|
|
| 3211 |
|
|
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
|
| 3212 |
|
|
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
|
| 3213 |
|
|
ena2;
|
| 3214 |
|
|
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
|
| 3215 |
|
|
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
|
| 3216 |
|
|
ena2;
|
| 3217 |
|
|
|
| 3218 |
|
|
be_mask_write(primary_port_is_a) <= be_mask_write_a;
|
| 3219 |
|
|
be_mask_write(primary_port_is_b) <= be_mask_write_b;
|
| 3220 |
|
|
|
| 3221 |
|
|
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
|
| 3222 |
|
|
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
|
| 3223 |
|
|
ena2;
|
| 3224 |
|
|
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
|
| 3225 |
|
|
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
|
| 3226 |
|
|
ena3;
|
| 3227 |
|
|
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
|
| 3228 |
|
|
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
|
| 3229 |
|
|
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
|
| 3230 |
|
|
ena2;
|
| 3231 |
|
|
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
|
| 3232 |
|
|
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
|
| 3233 |
|
|
ena3;
|
| 3234 |
|
|
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
|
| 3235 |
|
|
|
| 3236 |
|
|
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
|
| 3237 |
|
|
|
| 3238 |
|
|
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
|
| 3239 |
|
|
|
| 3240 |
|
|
-- Store core clock enable value for delayed write
|
| 3241 |
|
|
-- port A core active
|
| 3242 |
|
|
active_a_core_in_vec(0) <= active_a_core_in;
|
| 3243 |
|
|
active_core_port_a : stratixiii_ram_register
|
| 3244 |
|
|
GENERIC MAP ( width => 1 )
|
| 3245 |
|
|
PORT MAP (
|
| 3246 |
|
|
d => active_a_core_in_vec,
|
| 3247 |
|
|
clk => clk_a_in,
|
| 3248 |
|
|
aclr => wire_gnd,
|
| 3249 |
|
|
devclrn => wire_vcc,devpor => wire_vcc,
|
| 3250 |
|
|
ena => wire_vcc,
|
| 3251 |
|
|
stall => wire_gnd,
|
| 3252 |
|
|
q => active_a_core_out
|
| 3253 |
|
|
);
|
| 3254 |
|
|
active_a_core <= (active_a_core_out(0) = '1');
|
| 3255 |
|
|
|
| 3256 |
|
|
-- port B core active
|
| 3257 |
|
|
active_b_core_in_vec(0) <= active_b_core_in;
|
| 3258 |
|
|
active_core_port_b : stratixiii_ram_register
|
| 3259 |
|
|
GENERIC MAP ( width => 1 )
|
| 3260 |
|
|
PORT MAP (
|
| 3261 |
|
|
d => active_b_core_in_vec,
|
| 3262 |
|
|
clk => clk_b_in,
|
| 3263 |
|
|
aclr => wire_gnd,
|
| 3264 |
|
|
devclrn => wire_vcc,devpor => wire_vcc,
|
| 3265 |
|
|
ena => wire_vcc,
|
| 3266 |
|
|
stall => wire_gnd,
|
| 3267 |
|
|
q => active_b_core_out
|
| 3268 |
|
|
);
|
| 3269 |
|
|
active_b_core <= (active_b_core_out(0) = '1');
|
| 3270 |
|
|
|
| 3271 |
|
|
|
| 3272 |
|
|
|
| 3273 |
|
|
-- ------ A input registers
|
| 3274 |
|
|
-- write enable
|
| 3275 |
|
|
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
|
| 3276 |
|
|
we_a_register : stratixiii_ram_register
|
| 3277 |
|
|
GENERIC MAP ( width => 1 )
|
| 3278 |
|
|
PORT MAP (
|
| 3279 |
|
|
d => we_a_reg_in,
|
| 3280 |
|
|
clk => clk_a_wena,
|
| 3281 |
|
|
aclr => we_a_clr_in,
|
| 3282 |
|
|
devclrn => devclrn,
|
| 3283 |
|
|
devpor => devpor,
|
| 3284 |
|
|
stall => wire_gnd,
|
| 3285 |
|
|
ena => active_a_core_in,
|
| 3286 |
|
|
q => we_a_reg_out,
|
| 3287 |
|
|
aclrout => we_a_clr
|
| 3288 |
|
|
);
|
| 3289 |
|
|
we_a_reg <= we_a_reg_out(0);
|
| 3290 |
|
|
-- read enable
|
| 3291 |
|
|
re_a_reg_in(0) <= portare;
|
| 3292 |
|
|
re_a_register : stratixiii_ram_register
|
| 3293 |
|
|
GENERIC MAP ( width => 1 )
|
| 3294 |
|
|
PORT MAP (
|
| 3295 |
|
|
d => re_a_reg_in,
|
| 3296 |
|
|
clk => clk_a_rena,
|
| 3297 |
|
|
aclr => re_a_clr_in,
|
| 3298 |
|
|
devclrn => devclrn,
|
| 3299 |
|
|
devpor => devpor,
|
| 3300 |
|
|
stall => wire_gnd,
|
| 3301 |
|
|
ena => active_a_core_in,
|
| 3302 |
|
|
q => re_a_reg_out,
|
| 3303 |
|
|
aclrout => re_a_clr
|
| 3304 |
|
|
);
|
| 3305 |
|
|
re_a_reg <= re_a_reg_out(0);
|
| 3306 |
|
|
|
| 3307 |
|
|
-- address
|
| 3308 |
|
|
addr_a_register : stratixiii_ram_register
|
| 3309 |
|
|
GENERIC MAP ( width => port_a_address_width )
|
| 3310 |
|
|
PORT MAP (
|
| 3311 |
|
|
d => portaaddr,
|
| 3312 |
|
|
clk => clk_a_in,
|
| 3313 |
|
|
aclr => addr_a_clr_in,
|
| 3314 |
|
|
devclrn => devclrn,
|
| 3315 |
|
|
devpor => devpor,
|
| 3316 |
|
|
stall => portaaddrstall,
|
| 3317 |
|
|
ena => active_a_in,
|
| 3318 |
|
|
q => addr_a_reg,
|
| 3319 |
|
|
aclrout => addr_a_clr
|
| 3320 |
|
|
);
|
| 3321 |
|
|
-- data
|
| 3322 |
|
|
datain_a_register : stratixiii_ram_register
|
| 3323 |
|
|
GENERIC MAP ( width => port_a_data_width )
|
| 3324 |
|
|
PORT MAP (
|
| 3325 |
|
|
d => portadatain,
|
| 3326 |
|
|
clk => clk_a_in,
|
| 3327 |
|
|
aclr => datain_a_clr_in,
|
| 3328 |
|
|
devclrn => devclrn,
|
| 3329 |
|
|
devpor => devpor,
|
| 3330 |
|
|
stall => wire_gnd,
|
| 3331 |
|
|
ena => active_a_in,
|
| 3332 |
|
|
q => datain_a_reg,
|
| 3333 |
|
|
aclrout => datain_a_clr
|
| 3334 |
|
|
);
|
| 3335 |
|
|
-- byte enable
|
| 3336 |
|
|
byteena_a_register : stratixiii_ram_register
|
| 3337 |
|
|
GENERIC MAP (
|
| 3338 |
|
|
width => port_a_byte_enable_mask_width,
|
| 3339 |
|
|
preset => '1'
|
| 3340 |
|
|
)
|
| 3341 |
|
|
PORT MAP (
|
| 3342 |
|
|
d => portabyteenamasks,
|
| 3343 |
|
|
clk => clk_a_byteena,
|
| 3344 |
|
|
aclr => byteena_a_clr_in,
|
| 3345 |
|
|
devclrn => devclrn,
|
| 3346 |
|
|
devpor => devpor,
|
| 3347 |
|
|
stall => wire_gnd,
|
| 3348 |
|
|
ena => active_a_in,
|
| 3349 |
|
|
q => byteena_a_reg,
|
| 3350 |
|
|
aclrout => byteena_a_clr
|
| 3351 |
|
|
);
|
| 3352 |
|
|
-- ------ B input registers
|
| 3353 |
|
|
|
| 3354 |
|
|
-- read enable
|
| 3355 |
|
|
re_b_reg_in(0) <= portbre;
|
| 3356 |
|
|
re_b_register : stratixiii_ram_register
|
| 3357 |
|
|
GENERIC MAP (
|
| 3358 |
|
|
width => 1
|
| 3359 |
|
|
)
|
| 3360 |
|
|
PORT MAP (
|
| 3361 |
|
|
d => re_b_reg_in,
|
| 3362 |
|
|
clk => clk_b_in,
|
| 3363 |
|
|
aclr => re_b_clr_in,
|
| 3364 |
|
|
devclrn => devclrn,
|
| 3365 |
|
|
devpor => devpor,
|
| 3366 |
|
|
stall => wire_gnd,
|
| 3367 |
|
|
ena => active_b_core_in,
|
| 3368 |
|
|
q => re_b_reg_out,
|
| 3369 |
|
|
aclrout => re_b_clr
|
| 3370 |
|
|
);
|
| 3371 |
|
|
re_b_reg <= re_b_reg_out(0);
|
| 3372 |
|
|
|
| 3373 |
|
|
-- write enable
|
| 3374 |
|
|
we_b_reg_in(0) <= portbwe;
|
| 3375 |
|
|
we_b_register : stratixiii_ram_register
|
| 3376 |
|
|
GENERIC MAP (
|
| 3377 |
|
|
width => 1
|
| 3378 |
|
|
)
|
| 3379 |
|
|
PORT MAP (
|
| 3380 |
|
|
d => we_b_reg_in,
|
| 3381 |
|
|
clk => clk_b_in,
|
| 3382 |
|
|
aclr => we_b_clr_in,
|
| 3383 |
|
|
devclrn => devclrn,
|
| 3384 |
|
|
devpor => devpor,
|
| 3385 |
|
|
stall => wire_gnd,
|
| 3386 |
|
|
ena => active_b_core_in,
|
| 3387 |
|
|
q => we_b_reg_out,
|
| 3388 |
|
|
aclrout => we_b_clr
|
| 3389 |
|
|
);
|
| 3390 |
|
|
we_b_reg <= we_b_reg_out(0);
|
| 3391 |
|
|
|
| 3392 |
|
|
-- address
|
| 3393 |
|
|
addr_b_register : stratixiii_ram_register
|
| 3394 |
|
|
GENERIC MAP ( width => port_b_address_width )
|
| 3395 |
|
|
PORT MAP (
|
| 3396 |
|
|
d => portbaddr,
|
| 3397 |
|
|
clk => clk_b_in,
|
| 3398 |
|
|
aclr => addr_b_clr_in,
|
| 3399 |
|
|
devclrn => devclrn,
|
| 3400 |
|
|
devpor => devpor,
|
| 3401 |
|
|
stall => portbaddrstall,
|
| 3402 |
|
|
ena => active_b_in,
|
| 3403 |
|
|
q => addr_b_reg,
|
| 3404 |
|
|
aclrout => addr_b_clr
|
| 3405 |
|
|
);
|
| 3406 |
|
|
-- data
|
| 3407 |
|
|
datain_b_register : stratixiii_ram_register
|
| 3408 |
|
|
GENERIC MAP ( width => port_b_data_width )
|
| 3409 |
|
|
PORT MAP (
|
| 3410 |
|
|
d => portbdatain,
|
| 3411 |
|
|
clk => clk_b_in,
|
| 3412 |
|
|
aclr => datain_b_clr_in,
|
| 3413 |
|
|
devclrn => devclrn,
|
| 3414 |
|
|
devpor => devpor,
|
| 3415 |
|
|
stall => wire_gnd,
|
| 3416 |
|
|
ena => active_b_in,
|
| 3417 |
|
|
q => datain_b_reg,
|
| 3418 |
|
|
aclrout => datain_b_clr
|
| 3419 |
|
|
);
|
| 3420 |
|
|
-- byte enable
|
| 3421 |
|
|
byteena_b_register : stratixiii_ram_register
|
| 3422 |
|
|
GENERIC MAP (
|
| 3423 |
|
|
width => port_b_byte_enable_mask_width,
|
| 3424 |
|
|
preset => '1'
|
| 3425 |
|
|
)
|
| 3426 |
|
|
PORT MAP (
|
| 3427 |
|
|
d => portbbyteenamasks,
|
| 3428 |
|
|
clk => clk_b_byteena,
|
| 3429 |
|
|
aclr => byteena_b_clr_in,
|
| 3430 |
|
|
devclrn => devclrn,
|
| 3431 |
|
|
devpor => devpor,
|
| 3432 |
|
|
stall => wire_gnd,
|
| 3433 |
|
|
ena => active_b_in,
|
| 3434 |
|
|
q => byteena_b_reg,
|
| 3435 |
|
|
aclrout => byteena_b_clr
|
| 3436 |
|
|
);
|
| 3437 |
|
|
|
| 3438 |
|
|
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
|
| 3439 |
|
|
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
|
| 3440 |
|
|
|
| 3441 |
|
|
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
|
| 3442 |
|
|
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
|
| 3443 |
|
|
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
|
| 3444 |
|
|
|
| 3445 |
|
|
-- Write pulse generation
|
| 3446 |
|
|
wpgen_a_clk <= clk_a_in;
|
| 3447 |
|
|
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
|
| 3448 |
|
|
|
| 3449 |
|
|
wpgen_a : stratixiii_ram_pulse_generator
|
| 3450 |
|
|
PORT MAP (
|
| 3451 |
|
|
clk => wpgen_a_clk,
|
| 3452 |
|
|
ena => wpgen_a_clkena,
|
| 3453 |
|
|
delaywrite => delay_write_pulse_a,
|
| 3454 |
|
|
pulse => write_pulse(primary_port_is_a),
|
| 3455 |
|
|
cycle => write_cycle_a
|
| 3456 |
|
|
);
|
| 3457 |
|
|
|
| 3458 |
|
|
wpgen_b_clk <= clk_b_in;
|
| 3459 |
|
|
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
|
| 3460 |
|
|
|
| 3461 |
|
|
|
| 3462 |
|
|
wpgen_b : stratixiii_ram_pulse_generator
|
| 3463 |
|
|
PORT MAP (
|
| 3464 |
|
|
clk => wpgen_b_clk,
|
| 3465 |
|
|
ena => wpgen_b_clkena,
|
| 3466 |
|
|
delaywrite => delay_write_pulse_b,
|
| 3467 |
|
|
pulse => write_pulse(primary_port_is_b),
|
| 3468 |
|
|
cycle => write_cycle_b
|
| 3469 |
|
|
);
|
| 3470 |
|
|
|
| 3471 |
|
|
-- Read pulse generation
|
| 3472 |
|
|
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
|
| 3473 |
|
|
|
| 3474 |
|
|
rpgen_a : stratixiii_ram_pulse_generator
|
| 3475 |
|
|
PORT MAP (
|
| 3476 |
|
|
clk => clk_a_in,
|
| 3477 |
|
|
ena => rpgen_a_clkena,
|
| 3478 |
|
|
cycle => clk_a_core,
|
| 3479 |
|
|
pulse => read_pulse(primary_port_is_a)
|
| 3480 |
|
|
);
|
| 3481 |
|
|
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
|
| 3482 |
|
|
rpgen_b : stratixiii_ram_pulse_generator
|
| 3483 |
|
|
PORT MAP (
|
| 3484 |
|
|
clk => clk_b_in,
|
| 3485 |
|
|
ena => rpgen_b_clkena,
|
| 3486 |
|
|
cycle => clk_b_core,
|
| 3487 |
|
|
pulse => read_pulse(primary_port_is_b)
|
| 3488 |
|
|
);
|
| 3489 |
|
|
|
| 3490 |
|
|
-- Read-during-Write pulse generation
|
| 3491 |
|
|
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
|
| 3492 |
|
|
rwpgen_a : stratixiii_ram_pulse_generator
|
| 3493 |
|
|
PORT MAP (
|
| 3494 |
|
|
clk => clk_a_in,
|
| 3495 |
|
|
ena => rwpgen_a_clkena,
|
| 3496 |
|
|
pulse => rw_pulse(primary_port_is_a)
|
| 3497 |
|
|
);
|
| 3498 |
|
|
|
| 3499 |
|
|
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
|
| 3500 |
|
|
rwpgen_b : stratixiii_ram_pulse_generator
|
| 3501 |
|
|
PORT MAP (
|
| 3502 |
|
|
clk => clk_b_in,
|
| 3503 |
|
|
ena => rwpgen_b_clkena,
|
| 3504 |
|
|
pulse => rw_pulse(primary_port_is_b)
|
| 3505 |
|
|
);
|
| 3506 |
|
|
|
| 3507 |
|
|
-- Create internal masks for byte enable processing
|
| 3508 |
|
|
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
|
| 3509 |
|
|
VARIABLE mask : mask_rec;
|
| 3510 |
|
|
BEGIN
|
| 3511 |
|
|
IF (byteena_a_reg'EVENT) THEN
|
| 3512 |
|
|
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
|
| 3513 |
|
|
IF (primary_port_is_a) THEN
|
| 3514 |
|
|
mask_vector.prime <= mask.prime;
|
| 3515 |
|
|
ELSE
|
| 3516 |
|
|
mask_vector.sec <= mask.sec;
|
| 3517 |
|
|
END IF;
|
| 3518 |
|
|
END IF;
|
| 3519 |
|
|
IF (byteena_b_reg'EVENT) THEN
|
| 3520 |
|
|
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
|
| 3521 |
|
|
IF (primary_port_is_b) THEN
|
| 3522 |
|
|
mask_vector.prime <= mask.prime;
|
| 3523 |
|
|
ELSE
|
| 3524 |
|
|
mask_vector.sec <= mask.sec;
|
| 3525 |
|
|
END IF;
|
| 3526 |
|
|
END IF;
|
| 3527 |
|
|
END PROCESS mask_create;
|
| 3528 |
|
|
|
| 3529 |
|
|
-- (row,col) coordinates
|
| 3530 |
|
|
row_sec <= addr_sec_reg / num_cols;
|
| 3531 |
|
|
col_sec <= addr_sec_reg mod num_cols;
|
| 3532 |
|
|
|
| 3533 |
|
|
|
| 3534 |
|
|
|
| 3535 |
|
|
|
| 3536 |
|
|
mem_rw : PROCESS (init_mem,
|
| 3537 |
|
|
write_pulse,read_pulse,read_pulse_feedthru,
|
| 3538 |
|
|
rw_pulse,
|
| 3539 |
|
|
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
|
| 3540 |
|
|
-- mem init
|
| 3541 |
|
|
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
|
| 3542 |
|
|
VARIABLE addr_range_init,row,col,index : INTEGER;
|
| 3543 |
|
|
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
|
| 3544 |
|
|
VARIABLE mem_val : mem_type;
|
| 3545 |
|
|
-- read/write
|
| 3546 |
|
|
VARIABLE mem_data_p : mem_row_type;
|
| 3547 |
|
|
VARIABLE old_mem_data_p : mem_row_type;
|
| 3548 |
|
|
VARIABLE row_prime,col_prime : INTEGER;
|
| 3549 |
|
|
VARIABLE access_same_location : BOOLEAN;
|
| 3550 |
|
|
VARIABLE read_during_write : rw_type;
|
| 3551 |
|
|
BEGIN
|
| 3552 |
|
|
|
| 3553 |
|
|
read_during_write := (FALSE,FALSE);
|
| 3554 |
|
|
-- Memory initialization
|
| 3555 |
|
|
IF (init_mem'EVENT) THEN
|
| 3556 |
|
|
-- Initialize output latches to 0
|
| 3557 |
|
|
IF (primary_port_is_a) THEN
|
| 3558 |
|
|
dataout_prime <= (OTHERS => '0');
|
| 3559 |
|
|
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
|
| 3560 |
|
|
ELSE
|
| 3561 |
|
|
dataout_sec <= (OTHERS => '0');
|
| 3562 |
|
|
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
|
| 3563 |
|
|
END IF;
|
| 3564 |
|
|
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
|
| 3565 |
|
|
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
|
| 3566 |
|
|
END IF;
|
| 3567 |
|
|
IF (primary_port_is_a) THEN
|
| 3568 |
|
|
addr_range_init := port_a_last_address - port_a_first_address + 1;
|
| 3569 |
|
|
ELSE
|
| 3570 |
|
|
addr_range_init := port_b_last_address - port_b_first_address + 1;
|
| 3571 |
|
|
END IF;
|
| 3572 |
|
|
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
|
| 3573 |
|
|
mem_init_std := to_stdlogicvector(
|
| 3574 |
|
|
mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
|
| 3575 |
|
|
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
|
| 3576 |
|
|
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
|
| 3577 |
|
|
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
|
| 3578 |
|
|
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
|
| 3579 |
|
|
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
|
| 3580 |
|
|
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
|
| 3581 |
|
|
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
|
| 3582 |
|
|
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
|
| 3583 |
|
|
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
|
| 3584 |
|
|
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
|
| 3585 |
|
|
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
|
| 3586 |
|
|
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
|
| 3587 |
|
|
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
|
| 3588 |
|
|
mem_init0) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
|
| 3589 |
|
|
FOR row IN 0 TO addr_range_init - 1 LOOP
|
| 3590 |
|
|
FOR col IN 0 to num_cols - 1 LOOP
|
| 3591 |
|
|
index := row * data_width;
|
| 3592 |
|
|
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
|
| 3593 |
|
|
index + col*data_unit_width);
|
| 3594 |
|
|
END LOOP;
|
| 3595 |
|
|
END LOOP;
|
| 3596 |
|
|
END IF;
|
| 3597 |
|
|
mem <= mem_val;
|
| 3598 |
|
|
END IF;
|
| 3599 |
|
|
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
|
| 3600 |
|
|
-- Read before Write stage 1 : read data from memory
|
| 3601 |
|
|
-- Read before Write stage 2 : send data to output
|
| 3602 |
|
|
IF (rw_pulse(primary)'EVENT) THEN
|
| 3603 |
|
|
IF (rw_pulse(primary) = '1') THEN
|
| 3604 |
|
|
read_latch.prime <= mem(addr_prime_reg);
|
| 3605 |
|
|
ELSE
|
| 3606 |
|
|
IF (be_mask_write(primary)) THEN
|
| 3607 |
|
|
FOR i IN 0 TO data_width - 1 LOOP
|
| 3608 |
|
|
IF (mask_vector.prime(normal)(i) = 'X') THEN
|
| 3609 |
|
|
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
|
| 3610 |
|
|
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
|
| 3611 |
|
|
END IF;
|
| 3612 |
|
|
END LOOP;
|
| 3613 |
|
|
ELSE
|
| 3614 |
|
|
FOR i IN 0 TO data_width - 1 LOOP
|
| 3615 |
|
|
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
|
| 3616 |
|
|
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
|
| 3617 |
|
|
END LOOP;
|
| 3618 |
|
|
END IF;
|
| 3619 |
|
|
END IF;
|
| 3620 |
|
|
END IF;
|
| 3621 |
|
|
IF (rw_pulse(secondary)'EVENT) THEN
|
| 3622 |
|
|
IF (rw_pulse(secondary) = '1') THEN
|
| 3623 |
|
|
read_latch.sec <= mem(row_sec)(col_sec);
|
| 3624 |
|
|
ELSE
|
| 3625 |
|
|
IF (be_mask_write(secondary)) THEN
|
| 3626 |
|
|
FOR i IN 0 TO data_unit_width - 1 LOOP
|
| 3627 |
|
|
IF (mask_vector.sec(normal)(i) = 'X') THEN
|
| 3628 |
|
|
dataout_sec(i) <= read_latch.sec(i);
|
| 3629 |
|
|
END IF;
|
| 3630 |
|
|
END LOOP;
|
| 3631 |
|
|
ELSE
|
| 3632 |
|
|
dataout_sec <= read_latch.sec;
|
| 3633 |
|
|
END IF;
|
| 3634 |
|
|
END IF;
|
| 3635 |
|
|
END IF;
|
| 3636 |
|
|
|
| 3637 |
|
|
-- Write stage 1 : X to buffer
|
| 3638 |
|
|
-- Write stage 2 : actual data to memory
|
| 3639 |
|
|
IF (write_pulse(primary)'EVENT) THEN
|
| 3640 |
|
|
IF (write_pulse(primary) = '1') THEN
|
| 3641 |
|
|
old_mem_data_p := mem(addr_prime_reg);
|
| 3642 |
|
|
mem_data_p := mem(addr_prime_reg);
|
| 3643 |
|
|
FOR i IN 0 TO num_cols - 1 LOOP
|
| 3644 |
|
|
mem_data_p(i) := mem_data_p(i) XOR
|
| 3645 |
|
|
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
|
| 3646 |
|
|
END LOOP;
|
| 3647 |
|
|
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
|
| 3648 |
|
|
IF (read_during_write(secondary)) THEN
|
| 3649 |
|
|
read_latch.sec <= old_mem_data_p(col_sec);
|
| 3650 |
|
|
ELSE
|
| 3651 |
|
|
mem_data <= mem_data_p;
|
| 3652 |
|
|
END IF;
|
| 3653 |
|
|
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
|
| 3654 |
|
|
FOR i IN 0 TO data_width - 1 LOOP
|
| 3655 |
|
|
IF (mask_vector.prime(normal)(i) = '0') THEN
|
| 3656 |
|
|
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
|
| 3657 |
|
|
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
|
| 3658 |
|
|
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
|
| 3659 |
|
|
END IF;
|
| 3660 |
|
|
END LOOP;
|
| 3661 |
|
|
END IF;
|
| 3662 |
|
|
END IF;
|
| 3663 |
|
|
|
| 3664 |
|
|
IF (write_pulse(secondary)'EVENT) THEN
|
| 3665 |
|
|
IF (write_pulse(secondary) = '1') THEN
|
| 3666 |
|
|
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
|
| 3667 |
|
|
IF (read_during_write(primary)) THEN
|
| 3668 |
|
|
read_latch.prime <= mem(addr_prime_reg);
|
| 3669 |
|
|
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
|
| 3670 |
|
|
ELSE
|
| 3671 |
|
|
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
|
| 3672 |
|
|
END IF;
|
| 3673 |
|
|
|
| 3674 |
|
|
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
|
| 3675 |
|
|
mask_vector_common <=
|
| 3676 |
|
|
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
|
| 3677 |
|
|
mask_vector.sec(inverse);
|
| 3678 |
|
|
dual_write <= TRUE;
|
| 3679 |
|
|
END IF;
|
| 3680 |
|
|
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
|
| 3681 |
|
|
FOR i IN 0 TO data_unit_width - 1 LOOP
|
| 3682 |
|
|
IF (mask_vector.sec(normal)(i) = '0') THEN
|
| 3683 |
|
|
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
|
| 3684 |
|
|
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
|
| 3685 |
|
|
mem(row_sec)(col_sec)(i) <= 'X';
|
| 3686 |
|
|
END IF;
|
| 3687 |
|
|
END LOOP;
|
| 3688 |
|
|
END IF;
|
| 3689 |
|
|
END IF;
|
| 3690 |
|
|
-- Simultaneous write
|
| 3691 |
|
|
IF (dual_write AND write_pulse = "00") THEN
|
| 3692 |
|
|
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
|
| 3693 |
|
|
dual_write <= FALSE;
|
| 3694 |
|
|
END IF;
|
| 3695 |
|
|
-- Read stage 1 : read data
|
| 3696 |
|
|
-- Read stage 2 : send data to output
|
| 3697 |
|
|
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
|
| 3698 |
|
|
IF (read_pulse(primary) = '1') THEN
|
| 3699 |
|
|
read_latch.prime <= mem(addr_prime_reg);
|
| 3700 |
|
|
IF (access_same_location AND write_pulse(secondary) = '1') THEN
|
| 3701 |
|
|
read_latch.prime(col_sec) <= mem_unit_data;
|
| 3702 |
|
|
END IF;
|
| 3703 |
|
|
ELSE
|
| 3704 |
|
|
FOR i IN 0 TO data_width - 1 LOOP
|
| 3705 |
|
|
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
|
| 3706 |
|
|
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
|
| 3707 |
|
|
END LOOP;
|
| 3708 |
|
|
END IF;
|
| 3709 |
|
|
END IF;
|
| 3710 |
|
|
|
| 3711 |
|
|
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
|
| 3712 |
|
|
IF (read_pulse(secondary) = '1') THEN
|
| 3713 |
|
|
IF (access_same_location AND write_pulse(primary) = '1') THEN
|
| 3714 |
|
|
read_latch.sec <= mem_data(col_sec);
|
| 3715 |
|
|
ELSE
|
| 3716 |
|
|
read_latch.sec <= mem(row_sec)(col_sec);
|
| 3717 |
|
|
END IF;
|
| 3718 |
|
|
ELSE
|
| 3719 |
|
|
dataout_sec <= read_latch.sec;
|
| 3720 |
|
|
END IF;
|
| 3721 |
|
|
END IF;
|
| 3722 |
|
|
-- Same port feed thru
|
| 3723 |
|
|
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
|
| 3724 |
|
|
IF (be_mask_write(primary)) THEN
|
| 3725 |
|
|
FOR i IN 0 TO data_width - 1 LOOP
|
| 3726 |
|
|
IF (mask_vector.prime(normal)(i) = '0') THEN
|
| 3727 |
|
|
dataout_prime(i) <= datain_prime_reg(i);
|
| 3728 |
|
|
END IF;
|
| 3729 |
|
|
END LOOP;
|
| 3730 |
|
|
ELSE
|
| 3731 |
|
|
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
|
| 3732 |
|
|
END IF;
|
| 3733 |
|
|
END IF;
|
| 3734 |
|
|
|
| 3735 |
|
|
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
|
| 3736 |
|
|
IF (be_mask_write(secondary)) THEN
|
| 3737 |
|
|
FOR i IN 0 TO data_unit_width - 1 LOOP
|
| 3738 |
|
|
IF (mask_vector.sec(normal)(i) = '0') THEN
|
| 3739 |
|
|
dataout_sec(i) <= datain_sec_reg(i);
|
| 3740 |
|
|
END IF;
|
| 3741 |
|
|
END LOOP;
|
| 3742 |
|
|
ELSE
|
| 3743 |
|
|
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
|
| 3744 |
|
|
END IF;
|
| 3745 |
|
|
END IF;
|
| 3746 |
|
|
-- Async clear
|
| 3747 |
|
|
IF (mem_invalidate'EVENT) THEN
|
| 3748 |
|
|
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
|
| 3749 |
|
|
mem <= mem_x;
|
| 3750 |
|
|
END IF;
|
| 3751 |
|
|
END IF;
|
| 3752 |
|
|
IF (mem_invalidate_loc'EVENT) THEN
|
| 3753 |
|
|
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
|
| 3754 |
|
|
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
|
| 3755 |
|
|
END IF;
|
| 3756 |
|
|
IF (read_latch_invalidate'EVENT) THEN
|
| 3757 |
|
|
IF (read_latch_invalidate(primary)) THEN
|
| 3758 |
|
|
read_latch.prime <= row_x;
|
| 3759 |
|
|
END IF;
|
| 3760 |
|
|
IF (read_latch_invalidate(secondary)) THEN
|
| 3761 |
|
|
read_latch.sec <= col_x;
|
| 3762 |
|
|
END IF;
|
| 3763 |
|
|
END IF;
|
| 3764 |
|
|
|
| 3765 |
|
|
END PROCESS mem_rw;
|
| 3766 |
|
|
|
| 3767 |
|
|
-- Same port feed through
|
| 3768 |
|
|
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
|
| 3769 |
|
|
ftpgen_a : stratixiii_ram_pulse_generator
|
| 3770 |
|
|
PORT MAP (
|
| 3771 |
|
|
clk => clk_a_in,
|
| 3772 |
|
|
ena => ftpgen_a_clkena,
|
| 3773 |
|
|
pulse => read_pulse_feedthru(primary_port_is_a)
|
| 3774 |
|
|
);
|
| 3775 |
|
|
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
|
| 3776 |
|
|
|
| 3777 |
|
|
ftpgen_b : stratixiii_ram_pulse_generator
|
| 3778 |
|
|
PORT MAP (
|
| 3779 |
|
|
clk => clk_b_in,
|
| 3780 |
|
|
ena => ftpgen_b_clkena,
|
| 3781 |
|
|
pulse => read_pulse_feedthru(primary_port_is_b)
|
| 3782 |
|
|
);
|
| 3783 |
|
|
|
| 3784 |
|
|
|
| 3785 |
|
|
|
| 3786 |
|
|
|
| 3787 |
|
|
|
| 3788 |
|
|
-- Asynch clear events
|
| 3789 |
|
|
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
|
| 3790 |
|
|
BEGIN
|
| 3791 |
|
|
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
|
| 3792 |
|
|
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
|
| 3793 |
|
|
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
|
| 3794 |
|
|
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
|
| 3795 |
|
|
ELSIF (re_a_reg = '1') THEN
|
| 3796 |
|
|
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
|
| 3797 |
|
|
END IF;
|
| 3798 |
|
|
END IF;
|
| 3799 |
|
|
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
|
| 3800 |
|
|
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
|
| 3801 |
|
|
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
|
| 3802 |
|
|
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
|
| 3803 |
|
|
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
|
| 3804 |
|
|
END IF;
|
| 3805 |
|
|
END IF;
|
| 3806 |
|
|
END PROCESS clear_a;
|
| 3807 |
|
|
|
| 3808 |
|
|
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
|
| 3809 |
|
|
BEGIN
|
| 3810 |
|
|
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
|
| 3811 |
|
|
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
|
| 3812 |
|
|
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
|
| 3813 |
|
|
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
|
| 3814 |
|
|
ELSIF ((mode_is_dp OR mode_is_bdp) AND re_b_reg = '1') THEN
|
| 3815 |
|
|
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
|
| 3816 |
|
|
END IF;
|
| 3817 |
|
|
END IF;
|
| 3818 |
|
|
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
|
| 3819 |
|
|
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
|
| 3820 |
|
|
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
|
| 3821 |
|
|
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
|
| 3822 |
|
|
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
|
| 3823 |
|
|
END IF;
|
| 3824 |
|
|
END IF;
|
| 3825 |
|
|
END PROCESS clear_b;
|
| 3826 |
|
|
-- Clear mux registers (Latch Clear)
|
| 3827 |
|
|
-- Port A output register clear
|
| 3828 |
|
|
dataout_a_clr_reg_in(0) <= dataout_a_clr;
|
| 3829 |
|
|
aclr_a_mux_register : stratixiii_ram_register
|
| 3830 |
|
|
GENERIC MAP ( width => 1 )
|
| 3831 |
|
|
PORT MAP (
|
| 3832 |
|
|
d => dataout_a_clr_reg_in,
|
| 3833 |
|
|
clk => clk_a_core,
|
| 3834 |
|
|
aclr => wire_gnd,
|
| 3835 |
|
|
devclrn => devclrn,
|
| 3836 |
|
|
devpor => devpor,
|
| 3837 |
|
|
stall => wire_gnd,
|
| 3838 |
|
|
ena => wire_vcc,
|
| 3839 |
|
|
q => dataout_a_clr_reg_out
|
| 3840 |
|
|
);
|
| 3841 |
|
|
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
|
| 3842 |
|
|
|
| 3843 |
|
|
-- Port B output register clear
|
| 3844 |
|
|
dataout_b_clr_reg_in(0) <= dataout_b_clr;
|
| 3845 |
|
|
aclr_b_mux_register : stratixiii_ram_register
|
| 3846 |
|
|
GENERIC MAP ( width => 1 )
|
| 3847 |
|
|
PORT MAP (
|
| 3848 |
|
|
d => dataout_b_clr_reg_in,
|
| 3849 |
|
|
clk => clk_b_core,
|
| 3850 |
|
|
aclr => wire_gnd,
|
| 3851 |
|
|
devclrn => devclrn,
|
| 3852 |
|
|
devpor => devpor,
|
| 3853 |
|
|
stall => wire_gnd,
|
| 3854 |
|
|
ena => wire_vcc,
|
| 3855 |
|
|
q => dataout_b_clr_reg_out
|
| 3856 |
|
|
);
|
| 3857 |
|
|
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
|
| 3858 |
|
|
|
| 3859 |
|
|
|
| 3860 |
|
|
|
| 3861 |
|
|
-- ------ Output registers
|
| 3862 |
|
|
|
| 3863 |
|
|
|
| 3864 |
|
|
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
|
| 3865 |
|
|
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
|
| 3866 |
|
|
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
|
| 3867 |
|
|
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
|
| 3868 |
|
|
|
| 3869 |
|
|
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
|
| 3870 |
|
|
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
|
| 3871 |
|
|
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
|
| 3872 |
|
|
|
| 3873 |
|
|
dataout_a_register : stratixiii_ram_register
|
| 3874 |
|
|
GENERIC MAP ( width => port_a_data_width )
|
| 3875 |
|
|
PORT MAP (
|
| 3876 |
|
|
d => dataout_a,
|
| 3877 |
|
|
clk => clk_a_out,
|
| 3878 |
|
|
aclr => dataout_a_clr,
|
| 3879 |
|
|
devclrn => devclrn,
|
| 3880 |
|
|
devpor => devpor,
|
| 3881 |
|
|
stall => wire_gnd,
|
| 3882 |
|
|
ena => clkena_a_out,
|
| 3883 |
|
|
q => dataout_a_reg
|
| 3884 |
|
|
);
|
| 3885 |
|
|
|
| 3886 |
|
|
dataout_b_register : stratixiii_ram_register
|
| 3887 |
|
|
GENERIC MAP ( width => port_b_data_width )
|
| 3888 |
|
|
PORT MAP (
|
| 3889 |
|
|
d => dataout_b,
|
| 3890 |
|
|
clk => clk_b_out,
|
| 3891 |
|
|
aclr => dataout_b_clr,
|
| 3892 |
|
|
devclrn => devclrn,
|
| 3893 |
|
|
devpor => devpor,
|
| 3894 |
|
|
stall => wire_gnd,
|
| 3895 |
|
|
ena => clkena_b_out,
|
| 3896 |
|
|
q => dataout_b_reg
|
| 3897 |
|
|
);
|
| 3898 |
|
|
|
| 3899 |
|
|
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
|
| 3900 |
|
|
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
|
| 3901 |
|
|
dataout_a;
|
| 3902 |
|
|
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
|
| 3903 |
|
|
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
|
| 3904 |
|
|
dataout_b;
|
| 3905 |
|
|
|
| 3906 |
|
|
eccstatus <= (OTHERS => '0');
|
| 3907 |
|
|
dftout <= (OTHERS => '0');
|
| 3908 |
|
|
|
| 3909 |
|
|
END block_arch;
|
| 3910 |
|
|
|
| 3911 |
|
|
|
| 3912 |
|
|
---------------------------------------------------------------------
|
| 3913 |
|
|
--
|
| 3914 |
|
|
-- Entity Name : stratixiii_ff
|
| 3915 |
|
|
--
|
| 3916 |
|
|
-- Description : Stratix III FF VHDL simulation model
|
| 3917 |
|
|
--
|
| 3918 |
|
|
--
|
| 3919 |
|
|
---------------------------------------------------------------------
|
| 3920 |
|
|
LIBRARY IEEE;
|
| 3921 |
|
|
use IEEE.std_logic_1164.all;
|
| 3922 |
|
|
use IEEE.VITAL_Timing.all;
|
| 3923 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 3924 |
|
|
use work.stratixiii_atom_pack.all;
|
| 3925 |
|
|
use work.stratixiii_and1;
|
| 3926 |
|
|
|
| 3927 |
|
|
entity stratixiii_ff is
|
| 3928 |
|
|
generic (
|
| 3929 |
|
|
power_up : string := "low";
|
| 3930 |
|
|
x_on_violation : string := "on";
|
| 3931 |
|
|
lpm_type : string := "stratixiii_ff";
|
| 3932 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3933 |
|
|
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3934 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3935 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3936 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3937 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3938 |
|
|
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3939 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3940 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3941 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 3942 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 3943 |
|
|
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 3944 |
|
|
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 3945 |
|
|
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
| 3946 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 3947 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 3948 |
|
|
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
| 3949 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
| 3950 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 3951 |
|
|
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
| 3952 |
|
|
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
| 3953 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 3954 |
|
|
TimingChecksOn: Boolean := True;
|
| 3955 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 3956 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 3957 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 3958 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 3959 |
|
|
InstancePath: STRING := "*"
|
| 3960 |
|
|
);
|
| 3961 |
|
|
|
| 3962 |
|
|
port (
|
| 3963 |
|
|
d : in std_logic := '0';
|
| 3964 |
|
|
clk : in std_logic := '0';
|
| 3965 |
|
|
clrn : in std_logic := '1';
|
| 3966 |
|
|
aload : in std_logic := '0';
|
| 3967 |
|
|
sclr : in std_logic := '0';
|
| 3968 |
|
|
sload : in std_logic := '0';
|
| 3969 |
|
|
ena : in std_logic := '1';
|
| 3970 |
|
|
asdata : in std_logic := '0';
|
| 3971 |
|
|
devclrn : in std_logic := '1';
|
| 3972 |
|
|
devpor : in std_logic := '1';
|
| 3973 |
|
|
q : out std_logic
|
| 3974 |
|
|
);
|
| 3975 |
|
|
attribute VITAL_LEVEL0 of stratixiii_ff : entity is TRUE;
|
| 3976 |
|
|
end stratixiii_ff;
|
| 3977 |
|
|
|
| 3978 |
|
|
architecture vital_lcell_ff of stratixiii_ff is
|
| 3979 |
|
|
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
|
| 3980 |
|
|
signal clk_ipd : std_logic;
|
| 3981 |
|
|
signal d_ipd : std_logic;
|
| 3982 |
|
|
signal d_dly : std_logic;
|
| 3983 |
|
|
signal asdata_ipd : std_logic;
|
| 3984 |
|
|
signal asdata_dly : std_logic;
|
| 3985 |
|
|
signal asdata_dly1 : std_logic;
|
| 3986 |
|
|
signal sclr_ipd : std_logic;
|
| 3987 |
|
|
signal sload_ipd : std_logic;
|
| 3988 |
|
|
signal clrn_ipd : std_logic;
|
| 3989 |
|
|
signal aload_ipd : std_logic;
|
| 3990 |
|
|
signal ena_ipd : std_logic;
|
| 3991 |
|
|
|
| 3992 |
|
|
component stratixiii_and1
|
| 3993 |
|
|
generic (XOn : Boolean := DefGlitchXOn;
|
| 3994 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 3995 |
|
|
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
|
| 3996 |
|
|
tipd_IN1 : VitalDelayType01 := DefPropDelay01
|
| 3997 |
|
|
);
|
| 3998 |
|
|
|
| 3999 |
|
|
port (Y : out STD_LOGIC;
|
| 4000 |
|
|
IN1 : in STD_LOGIC
|
| 4001 |
|
|
);
|
| 4002 |
|
|
end component;
|
| 4003 |
|
|
|
| 4004 |
|
|
begin
|
| 4005 |
|
|
|
| 4006 |
|
|
ddelaybuffer: stratixiii_and1
|
| 4007 |
|
|
port map(IN1 => d_ipd,
|
| 4008 |
|
|
Y => d_dly);
|
| 4009 |
|
|
|
| 4010 |
|
|
asdatadelaybuffer: stratixiii_and1
|
| 4011 |
|
|
port map(IN1 => asdata_ipd,
|
| 4012 |
|
|
Y => asdata_dly);
|
| 4013 |
|
|
|
| 4014 |
|
|
asdatadelaybuffer1: stratixiii_and1
|
| 4015 |
|
|
port map(IN1 => asdata_dly,
|
| 4016 |
|
|
Y => asdata_dly1);
|
| 4017 |
|
|
|
| 4018 |
|
|
|
| 4019 |
|
|
---------------------
|
| 4020 |
|
|
-- INPUT PATH DELAYs
|
| 4021 |
|
|
---------------------
|
| 4022 |
|
|
WireDelay : block
|
| 4023 |
|
|
begin
|
| 4024 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 4025 |
|
|
VitalWireDelay (d_ipd, d, tipd_d);
|
| 4026 |
|
|
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
|
| 4027 |
|
|
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
|
| 4028 |
|
|
VitalWireDelay (sload_ipd, sload, tipd_sload);
|
| 4029 |
|
|
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
|
| 4030 |
|
|
VitalWireDelay (aload_ipd, aload, tipd_aload);
|
| 4031 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 4032 |
|
|
end block;
|
| 4033 |
|
|
|
| 4034 |
|
|
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
|
| 4035 |
|
|
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
|
| 4036 |
|
|
ena_ipd, devclrn, devpor)
|
| 4037 |
|
|
|
| 4038 |
|
|
variable Tviol_d_clk : std_ulogic := '0';
|
| 4039 |
|
|
variable Tviol_asdata_clk : std_ulogic := '0';
|
| 4040 |
|
|
variable Tviol_sclr_clk : std_ulogic := '0';
|
| 4041 |
|
|
variable Tviol_sload_clk : std_ulogic := '0';
|
| 4042 |
|
|
variable Tviol_ena_clk : std_ulogic := '0';
|
| 4043 |
|
|
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 4044 |
|
|
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 4045 |
|
|
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 4046 |
|
|
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 4047 |
|
|
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 4048 |
|
|
variable q_VitalGlitchData : VitalGlitchDataType;
|
| 4049 |
|
|
|
| 4050 |
|
|
variable iq : std_logic := '0';
|
| 4051 |
|
|
variable idata: std_logic := '0';
|
| 4052 |
|
|
|
| 4053 |
|
|
-- variables for 'X' generation
|
| 4054 |
|
|
variable violation : std_logic := '0';
|
| 4055 |
|
|
|
| 4056 |
|
|
begin
|
| 4057 |
|
|
|
| 4058 |
|
|
if (now = 0 ns) then
|
| 4059 |
|
|
if (power_up = "low") then
|
| 4060 |
|
|
iq := '0';
|
| 4061 |
|
|
elsif (power_up = "high") then
|
| 4062 |
|
|
iq := '1';
|
| 4063 |
|
|
end if;
|
| 4064 |
|
|
end if;
|
| 4065 |
|
|
|
| 4066 |
|
|
------------------------
|
| 4067 |
|
|
-- Timing Check Section
|
| 4068 |
|
|
------------------------
|
| 4069 |
|
|
if (TimingChecksOn) then
|
| 4070 |
|
|
|
| 4071 |
|
|
VitalSetupHoldCheck (
|
| 4072 |
|
|
Violation => Tviol_d_clk,
|
| 4073 |
|
|
TimingData => TimingData_d_clk,
|
| 4074 |
|
|
TestSignal => d,
|
| 4075 |
|
|
TestSignalName => "DATAIN",
|
| 4076 |
|
|
RefSignal => clk_ipd,
|
| 4077 |
|
|
RefSignalName => "CLK",
|
| 4078 |
|
|
SetupHigh => tsetup_d_clk_noedge_posedge,
|
| 4079 |
|
|
SetupLow => tsetup_d_clk_noedge_posedge,
|
| 4080 |
|
|
HoldHigh => thold_d_clk_noedge_posedge,
|
| 4081 |
|
|
HoldLow => thold_d_clk_noedge_posedge,
|
| 4082 |
|
|
CheckEnabled => TO_X01((NOT clrn_ipd) OR
|
| 4083 |
|
|
(sload_ipd) OR
|
| 4084 |
|
|
(sclr_ipd) OR
|
| 4085 |
|
|
(NOT devpor) OR
|
| 4086 |
|
|
(NOT devclrn) OR
|
| 4087 |
|
|
(NOT ena_ipd)) /= '1',
|
| 4088 |
|
|
RefTransition => '/',
|
| 4089 |
|
|
HeaderMsg => InstancePath & "/LCELL_FF",
|
| 4090 |
|
|
XOn => XOnChecks,
|
| 4091 |
|
|
MsgOn => MsgOnChecks );
|
| 4092 |
|
|
|
| 4093 |
|
|
VitalSetupHoldCheck (
|
| 4094 |
|
|
Violation => Tviol_asdata_clk,
|
| 4095 |
|
|
TimingData => TimingData_asdata_clk,
|
| 4096 |
|
|
TestSignal => asdata_ipd,
|
| 4097 |
|
|
TestSignalName => "ASDATA",
|
| 4098 |
|
|
RefSignal => clk_ipd,
|
| 4099 |
|
|
RefSignalName => "CLK",
|
| 4100 |
|
|
SetupHigh => tsetup_asdata_clk_noedge_posedge,
|
| 4101 |
|
|
SetupLow => tsetup_asdata_clk_noedge_posedge,
|
| 4102 |
|
|
HoldHigh => thold_asdata_clk_noedge_posedge,
|
| 4103 |
|
|
HoldLow => thold_asdata_clk_noedge_posedge,
|
| 4104 |
|
|
CheckEnabled => TO_X01((NOT clrn_ipd) OR
|
| 4105 |
|
|
(NOT sload_ipd) OR
|
| 4106 |
|
|
(NOT devpor) OR
|
| 4107 |
|
|
(NOT devclrn) OR
|
| 4108 |
|
|
(NOT ena_ipd)) /= '1',
|
| 4109 |
|
|
RefTransition => '/',
|
| 4110 |
|
|
HeaderMsg => InstancePath & "/LCELL_FF",
|
| 4111 |
|
|
XOn => XOnChecks,
|
| 4112 |
|
|
MsgOn => MsgOnChecks );
|
| 4113 |
|
|
|
| 4114 |
|
|
VitalSetupHoldCheck (
|
| 4115 |
|
|
Violation => Tviol_sclr_clk,
|
| 4116 |
|
|
TimingData => TimingData_sclr_clk,
|
| 4117 |
|
|
TestSignal => sclr_ipd,
|
| 4118 |
|
|
TestSignalName => "SCLR",
|
| 4119 |
|
|
RefSignal => clk_ipd,
|
| 4120 |
|
|
RefSignalName => "CLK",
|
| 4121 |
|
|
SetupHigh => tsetup_sclr_clk_noedge_posedge,
|
| 4122 |
|
|
SetupLow => tsetup_sclr_clk_noedge_posedge,
|
| 4123 |
|
|
HoldHigh => thold_sclr_clk_noedge_posedge,
|
| 4124 |
|
|
HoldLow => thold_sclr_clk_noedge_posedge,
|
| 4125 |
|
|
CheckEnabled => TO_X01((NOT clrn_ipd) OR
|
| 4126 |
|
|
(NOT devpor) OR
|
| 4127 |
|
|
(NOT devclrn) OR
|
| 4128 |
|
|
(NOT ena_ipd)) /= '1',
|
| 4129 |
|
|
RefTransition => '/',
|
| 4130 |
|
|
HeaderMsg => InstancePath & "/LCELL_FF",
|
| 4131 |
|
|
XOn => XOnChecks,
|
| 4132 |
|
|
MsgOn => MsgOnChecks );
|
| 4133 |
|
|
|
| 4134 |
|
|
VitalSetupHoldCheck (
|
| 4135 |
|
|
Violation => Tviol_sload_clk,
|
| 4136 |
|
|
TimingData => TimingData_sload_clk,
|
| 4137 |
|
|
TestSignal => sload_ipd,
|
| 4138 |
|
|
TestSignalName => "SLOAD",
|
| 4139 |
|
|
RefSignal => clk_ipd,
|
| 4140 |
|
|
RefSignalName => "CLK",
|
| 4141 |
|
|
SetupHigh => tsetup_sload_clk_noedge_posedge,
|
| 4142 |
|
|
SetupLow => tsetup_sload_clk_noedge_posedge,
|
| 4143 |
|
|
HoldHigh => thold_sload_clk_noedge_posedge,
|
| 4144 |
|
|
HoldLow => thold_sload_clk_noedge_posedge,
|
| 4145 |
|
|
CheckEnabled => TO_X01((NOT clrn_ipd) OR
|
| 4146 |
|
|
(NOT devpor) OR
|
| 4147 |
|
|
(NOT devclrn) OR
|
| 4148 |
|
|
(NOT ena_ipd)) /= '1',
|
| 4149 |
|
|
RefTransition => '/',
|
| 4150 |
|
|
HeaderMsg => InstancePath & "/LCELL_FF",
|
| 4151 |
|
|
XOn => XOnChecks,
|
| 4152 |
|
|
MsgOn => MsgOnChecks );
|
| 4153 |
|
|
|
| 4154 |
|
|
VitalSetupHoldCheck (
|
| 4155 |
|
|
Violation => Tviol_ena_clk,
|
| 4156 |
|
|
TimingData => TimingData_ena_clk,
|
| 4157 |
|
|
TestSignal => ena_ipd,
|
| 4158 |
|
|
TestSignalName => "ENA",
|
| 4159 |
|
|
RefSignal => clk_ipd,
|
| 4160 |
|
|
RefSignalName => "CLK",
|
| 4161 |
|
|
SetupHigh => tsetup_ena_clk_noedge_posedge,
|
| 4162 |
|
|
SetupLow => tsetup_ena_clk_noedge_posedge,
|
| 4163 |
|
|
HoldHigh => thold_ena_clk_noedge_posedge,
|
| 4164 |
|
|
HoldLow => thold_ena_clk_noedge_posedge,
|
| 4165 |
|
|
CheckEnabled => TO_X01((NOT clrn_ipd) OR
|
| 4166 |
|
|
(NOT devpor) OR
|
| 4167 |
|
|
(NOT devclrn) ) /= '1',
|
| 4168 |
|
|
RefTransition => '/',
|
| 4169 |
|
|
HeaderMsg => InstancePath & "/LCELL_FF",
|
| 4170 |
|
|
XOn => XOnChecks,
|
| 4171 |
|
|
MsgOn => MsgOnChecks );
|
| 4172 |
|
|
|
| 4173 |
|
|
end if;
|
| 4174 |
|
|
|
| 4175 |
|
|
violation := Tviol_d_clk or Tviol_asdata_clk or
|
| 4176 |
|
|
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
|
| 4177 |
|
|
|
| 4178 |
|
|
|
| 4179 |
|
|
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '1')) then
|
| 4180 |
|
|
iq := '0';
|
| 4181 |
|
|
elsif (aload_ipd = '1') then
|
| 4182 |
|
|
iq := asdata_dly1;
|
| 4183 |
|
|
elsif (violation = 'X' and x_on_violation = "on") then
|
| 4184 |
|
|
iq := 'X';
|
| 4185 |
|
|
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
|
| 4186 |
|
|
if (ena_ipd = '1') then
|
| 4187 |
|
|
if (sclr_ipd = '1') then
|
| 4188 |
|
|
iq := '0';
|
| 4189 |
|
|
elsif (sload_ipd = '1') then
|
| 4190 |
|
|
iq := asdata_dly1;
|
| 4191 |
|
|
else
|
| 4192 |
|
|
iq := d_dly;
|
| 4193 |
|
|
end if;
|
| 4194 |
|
|
end if;
|
| 4195 |
|
|
end if;
|
| 4196 |
|
|
|
| 4197 |
|
|
----------------------
|
| 4198 |
|
|
-- Path Delay Section
|
| 4199 |
|
|
----------------------
|
| 4200 |
|
|
VitalPathDelay01 (
|
| 4201 |
|
|
OutSignal => q,
|
| 4202 |
|
|
OutSignalName => "Q",
|
| 4203 |
|
|
OutTemp => iq,
|
| 4204 |
|
|
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
|
| 4205 |
|
|
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
|
| 4206 |
|
|
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
|
| 4207 |
|
|
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
|
| 4208 |
|
|
GlitchData => q_VitalGlitchData,
|
| 4209 |
|
|
Mode => DefGlitchMode,
|
| 4210 |
|
|
XOn => XOn,
|
| 4211 |
|
|
MsgOn => MsgOn );
|
| 4212 |
|
|
|
| 4213 |
|
|
end process;
|
| 4214 |
|
|
|
| 4215 |
|
|
end vital_lcell_ff;
|
| 4216 |
|
|
|
| 4217 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 4218 |
|
|
--
|
| 4219 |
|
|
-- VHDL Simulation Model for Stratix III CLKSELECT Atom
|
| 4220 |
|
|
--
|
| 4221 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 4222 |
|
|
|
| 4223 |
|
|
--
|
| 4224 |
|
|
--
|
| 4225 |
|
|
-- STRATIXIII_CLKSELECT Model
|
| 4226 |
|
|
--
|
| 4227 |
|
|
--
|
| 4228 |
|
|
|
| 4229 |
|
|
LIBRARY IEEE;
|
| 4230 |
|
|
use IEEE.std_logic_1164.all;
|
| 4231 |
|
|
use IEEE.VITAL_Timing.all;
|
| 4232 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 4233 |
|
|
use work.stratixiii_atom_pack.all;
|
| 4234 |
|
|
|
| 4235 |
|
|
entity stratixiii_clkselect is
|
| 4236 |
|
|
generic (
|
| 4237 |
|
|
lpm_type : STRING := "stratixiii_clkselect";
|
| 4238 |
|
|
TimingChecksOn : Boolean := True;
|
| 4239 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 4240 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 4241 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 4242 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 4243 |
|
|
InstancePath : STRING := "*";
|
| 4244 |
|
|
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
| 4245 |
|
|
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
|
| 4246 |
|
|
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
| 4247 |
|
|
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
|
| 4248 |
|
|
);
|
| 4249 |
|
|
port (
|
| 4250 |
|
|
inclk : in std_logic_vector(3 downto 0) := "0000";
|
| 4251 |
|
|
clkselect : in std_logic_vector(1 downto 0) := "00";
|
| 4252 |
|
|
outclk : out std_logic
|
| 4253 |
|
|
);
|
| 4254 |
|
|
attribute VITAL_LEVEL0 of stratixiii_clkselect : entity is TRUE;
|
| 4255 |
|
|
end stratixiii_clkselect;
|
| 4256 |
|
|
|
| 4257 |
|
|
architecture vital_clkselect of stratixiii_clkselect is
|
| 4258 |
|
|
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
|
| 4259 |
|
|
|
| 4260 |
|
|
signal inclk_ipd : std_logic_vector(3 downto 0);
|
| 4261 |
|
|
signal clkselect_ipd : std_logic_vector(1 downto 0);
|
| 4262 |
|
|
signal clkmux_out : std_logic;
|
| 4263 |
|
|
begin
|
| 4264 |
|
|
|
| 4265 |
|
|
---------------------
|
| 4266 |
|
|
-- INPUT PATH DELAYs
|
| 4267 |
|
|
---------------------
|
| 4268 |
|
|
WireDelay : block
|
| 4269 |
|
|
begin
|
| 4270 |
|
|
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
|
| 4271 |
|
|
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
|
| 4272 |
|
|
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
|
| 4273 |
|
|
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
|
| 4274 |
|
|
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
|
| 4275 |
|
|
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
|
| 4276 |
|
|
end block;
|
| 4277 |
|
|
|
| 4278 |
|
|
process(inclk_ipd, clkselect_ipd)
|
| 4279 |
|
|
variable outclk_VitalGlitchData : VitalGlitchDataType;
|
| 4280 |
|
|
variable tmp : std_logic;
|
| 4281 |
|
|
begin
|
| 4282 |
|
|
if (clkselect_ipd = "11") then
|
| 4283 |
|
|
tmp := inclk_ipd(3);
|
| 4284 |
|
|
elsif (clkselect_ipd = "10") then
|
| 4285 |
|
|
tmp := inclk_ipd(2);
|
| 4286 |
|
|
elsif (clkselect_ipd = "01") then
|
| 4287 |
|
|
tmp := inclk_ipd(1);
|
| 4288 |
|
|
else
|
| 4289 |
|
|
tmp := inclk_ipd(0);
|
| 4290 |
|
|
end if;
|
| 4291 |
|
|
clkmux_out <= tmp;
|
| 4292 |
|
|
|
| 4293 |
|
|
----------------------
|
| 4294 |
|
|
-- Path Delay Section
|
| 4295 |
|
|
----------------------
|
| 4296 |
|
|
|
| 4297 |
|
|
VitalPathDelay01
|
| 4298 |
|
|
(
|
| 4299 |
|
|
OutSignal => outclk,
|
| 4300 |
|
|
OutSignalName => "OUTCLOCK",
|
| 4301 |
|
|
OutTemp => clkmux_out,
|
| 4302 |
|
|
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
|
| 4303 |
|
|
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
|
| 4304 |
|
|
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
|
| 4305 |
|
|
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
|
| 4306 |
|
|
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
|
| 4307 |
|
|
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
|
| 4308 |
|
|
GlitchData => outclk_VitalGlitchData,
|
| 4309 |
|
|
Mode => DefGlitchMode,
|
| 4310 |
|
|
XOn => XOn,
|
| 4311 |
|
|
MsgOn => MsgOn
|
| 4312 |
|
|
);
|
| 4313 |
|
|
|
| 4314 |
|
|
end process;
|
| 4315 |
|
|
|
| 4316 |
|
|
end vital_clkselect;
|
| 4317 |
|
|
|
| 4318 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 4319 |
|
|
--
|
| 4320 |
|
|
-- stratixiii_and2 Model
|
| 4321 |
|
|
-- Description : Simulation model for a simple two input AND gate.
|
| 4322 |
|
|
--
|
| 4323 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 4324 |
|
|
|
| 4325 |
|
|
LIBRARY IEEE;
|
| 4326 |
|
|
use IEEE.STD_LOGIC_1164.all;
|
| 4327 |
|
|
use IEEE.VITAL_Timing.all;
|
| 4328 |
|
|
use work.stratixiii_atom_pack.all;
|
| 4329 |
|
|
|
| 4330 |
|
|
-- entity declaration --
|
| 4331 |
|
|
entity stratixiii_and2 is
|
| 4332 |
|
|
generic(
|
| 4333 |
|
|
TimingChecksOn: Boolean := True;
|
| 4334 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 4335 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 4336 |
|
|
InstancePath: STRING := "*";
|
| 4337 |
|
|
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
|
| 4338 |
|
|
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
|
| 4339 |
|
|
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
|
| 4340 |
|
|
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
|
| 4341 |
|
|
|
| 4342 |
|
|
port(
|
| 4343 |
|
|
Y : out STD_LOGIC;
|
| 4344 |
|
|
IN1 : in STD_LOGIC;
|
| 4345 |
|
|
IN2 : in STD_LOGIC);
|
| 4346 |
|
|
attribute VITAL_LEVEL0 of stratixiii_and2 : entity is TRUE;
|
| 4347 |
|
|
end stratixiii_and2;
|
| 4348 |
|
|
|
| 4349 |
|
|
-- architecture body --
|
| 4350 |
|
|
|
| 4351 |
|
|
architecture AltVITAL of stratixiii_and2 is
|
| 4352 |
|
|
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
|
| 4353 |
|
|
|
| 4354 |
|
|
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
|
| 4355 |
|
|
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
|
| 4356 |
|
|
|
| 4357 |
|
|
begin
|
| 4358 |
|
|
|
| 4359 |
|
|
---------------------
|
| 4360 |
|
|
-- INPUT PATH DELAYs
|
| 4361 |
|
|
---------------------
|
| 4362 |
|
|
WireDelay : block
|
| 4363 |
|
|
begin
|
| 4364 |
|
|
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
|
| 4365 |
|
|
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
|
| 4366 |
|
|
end block;
|
| 4367 |
|
|
--------------------
|
| 4368 |
|
|
-- BEHAVIOR SECTION
|
| 4369 |
|
|
--------------------
|
| 4370 |
|
|
VITALBehavior : process (IN1_ipd, IN2_ipd)
|
| 4371 |
|
|
|
| 4372 |
|
|
|
| 4373 |
|
|
-- functionality results
|
| 4374 |
|
|
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
|
| 4375 |
|
|
ALIAS Y_zd : STD_ULOGIC is Results(1);
|
| 4376 |
|
|
|
| 4377 |
|
|
-- output glitch detection variables
|
| 4378 |
|
|
VARIABLE Y_GlitchData : VitalGlitchDataType;
|
| 4379 |
|
|
|
| 4380 |
|
|
begin
|
| 4381 |
|
|
|
| 4382 |
|
|
-------------------------
|
| 4383 |
|
|
-- Functionality Section
|
| 4384 |
|
|
-------------------------
|
| 4385 |
|
|
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
|
| 4386 |
|
|
|
| 4387 |
|
|
----------------------
|
| 4388 |
|
|
-- Path Delay Section
|
| 4389 |
|
|
----------------------
|
| 4390 |
|
|
VitalPathDelay01 (
|
| 4391 |
|
|
OutSignal => Y,
|
| 4392 |
|
|
OutSignalName => "Y",
|
| 4393 |
|
|
OutTemp => Y_zd,
|
| 4394 |
|
|
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
|
| 4395 |
|
|
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
|
| 4396 |
|
|
GlitchData => Y_GlitchData,
|
| 4397 |
|
|
Mode => DefGlitchMode,
|
| 4398 |
|
|
XOn => XOn,
|
| 4399 |
|
|
MsgOn => MsgOn );
|
| 4400 |
|
|
|
| 4401 |
|
|
end process;
|
| 4402 |
|
|
end AltVITAL;
|
| 4403 |
|
|
|
| 4404 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 4405 |
|
|
--
|
| 4406 |
|
|
-- Entity Name : stratixiii_ena_reg
|
| 4407 |
|
|
--
|
| 4408 |
|
|
-- Description : Simulation model for a simple DFF.
|
| 4409 |
|
|
-- This is used for the gated clock generation
|
| 4410 |
|
|
-- Powers upto 1.
|
| 4411 |
|
|
--
|
| 4412 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 4413 |
|
|
|
| 4414 |
|
|
LIBRARY IEEE;
|
| 4415 |
|
|
USE IEEE.std_logic_1164.all;
|
| 4416 |
|
|
use IEEE.VITAL_Timing.all;
|
| 4417 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 4418 |
|
|
use work.stratixiii_atom_pack.all;
|
| 4419 |
|
|
|
| 4420 |
|
|
ENTITY stratixiii_ena_reg is
|
| 4421 |
|
|
generic (
|
| 4422 |
|
|
TimingChecksOn : Boolean := True;
|
| 4423 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 4424 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 4425 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 4426 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 4427 |
|
|
InstancePath : STRING := "*";
|
| 4428 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 4429 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 4430 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 4431 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 4432 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01
|
| 4433 |
|
|
);
|
| 4434 |
|
|
PORT (
|
| 4435 |
|
|
clk : in std_logic;
|
| 4436 |
|
|
ena : in std_logic := '1';
|
| 4437 |
|
|
d : in std_logic;
|
| 4438 |
|
|
clrn : in std_logic := '1';
|
| 4439 |
|
|
prn : in std_logic := '1';
|
| 4440 |
|
|
q : out std_logic
|
| 4441 |
|
|
);
|
| 4442 |
|
|
attribute VITAL_LEVEL0 of stratixiii_ena_reg : entity is TRUE;
|
| 4443 |
|
|
end stratixiii_ena_reg;
|
| 4444 |
|
|
|
| 4445 |
|
|
ARCHITECTURE behave of stratixiii_ena_reg is
|
| 4446 |
|
|
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
|
| 4447 |
|
|
signal d_ipd : std_logic;
|
| 4448 |
|
|
signal clk_ipd : std_logic;
|
| 4449 |
|
|
begin
|
| 4450 |
|
|
|
| 4451 |
|
|
---------------------
|
| 4452 |
|
|
-- INPUT PATH DELAYs
|
| 4453 |
|
|
---------------------
|
| 4454 |
|
|
WireDelay : block
|
| 4455 |
|
|
begin
|
| 4456 |
|
|
VitalWireDelay (d_ipd, d, tipd_d);
|
| 4457 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 4458 |
|
|
end block;
|
| 4459 |
|
|
|
| 4460 |
|
|
VITALtiming : process (clk_ipd, prn, clrn)
|
| 4461 |
|
|
variable Tviol_d_clk : std_ulogic := '0';
|
| 4462 |
|
|
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 4463 |
|
|
variable q_VitalGlitchData : VitalGlitchDataType;
|
| 4464 |
|
|
variable q_reg : std_logic := '1';
|
| 4465 |
|
|
begin
|
| 4466 |
|
|
|
| 4467 |
|
|
------------------------
|
| 4468 |
|
|
-- Timing Check Section
|
| 4469 |
|
|
------------------------
|
| 4470 |
|
|
if (TimingChecksOn) then
|
| 4471 |
|
|
|
| 4472 |
|
|
VitalSetupHoldCheck (
|
| 4473 |
|
|
Violation => Tviol_d_clk,
|
| 4474 |
|
|
TimingData => TimingData_d_clk,
|
| 4475 |
|
|
TestSignal => d,
|
| 4476 |
|
|
TestSignalName => "D",
|
| 4477 |
|
|
RefSignal => clk_ipd,
|
| 4478 |
|
|
RefSignalName => "CLK",
|
| 4479 |
|
|
SetupHigh => tsetup_d_clk_noedge_posedge,
|
| 4480 |
|
|
SetupLow => tsetup_d_clk_noedge_posedge,
|
| 4481 |
|
|
HoldHigh => thold_d_clk_noedge_posedge,
|
| 4482 |
|
|
HoldLow => thold_d_clk_noedge_posedge,
|
| 4483 |
|
|
CheckEnabled => TO_X01((clrn) OR
|
| 4484 |
|
|
(NOT ena)) /= '1',
|
| 4485 |
|
|
RefTransition => '/',
|
| 4486 |
|
|
HeaderMsg => InstancePath & "/stratixiii_ena_reg",
|
| 4487 |
|
|
XOn => XOnChecks,
|
| 4488 |
|
|
MsgOn => MsgOnChecks );
|
| 4489 |
|
|
|
| 4490 |
|
|
end if;
|
| 4491 |
|
|
|
| 4492 |
|
|
if (prn = '0') then
|
| 4493 |
|
|
q_reg := '1';
|
| 4494 |
|
|
elsif (clrn = '0') then
|
| 4495 |
|
|
q_reg := '0';
|
| 4496 |
|
|
elsif (clk_ipd'event and clk_ipd = '1' and (ena = '1')) then
|
| 4497 |
|
|
q_reg := d_ipd;
|
| 4498 |
|
|
end if;
|
| 4499 |
|
|
|
| 4500 |
|
|
----------------------
|
| 4501 |
|
|
-- Path Delay Section
|
| 4502 |
|
|
----------------------
|
| 4503 |
|
|
VitalPathDelay01 (
|
| 4504 |
|
|
OutSignal => q,
|
| 4505 |
|
|
OutSignalName => "Q",
|
| 4506 |
|
|
OutTemp => q_reg,
|
| 4507 |
|
|
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
|
| 4508 |
|
|
GlitchData => q_VitalGlitchData,
|
| 4509 |
|
|
Mode => DefGlitchMode,
|
| 4510 |
|
|
XOn => XOn,
|
| 4511 |
|
|
MsgOn => MsgOn );
|
| 4512 |
|
|
|
| 4513 |
|
|
end process;
|
| 4514 |
|
|
|
| 4515 |
|
|
end behave;
|
| 4516 |
|
|
|
| 4517 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 4518 |
|
|
--
|
| 4519 |
|
|
-- VHDL Simulation Model for Cyclone II CLKCTRL Atom
|
| 4520 |
|
|
--
|
| 4521 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 4522 |
|
|
|
| 4523 |
|
|
--
|
| 4524 |
|
|
--
|
| 4525 |
|
|
-- CYCLONEII_CLKCTRL Model
|
| 4526 |
|
|
--
|
| 4527 |
|
|
--
|
| 4528 |
|
|
LIBRARY IEEE;
|
| 4529 |
|
|
use IEEE.std_logic_1164.all;
|
| 4530 |
|
|
use IEEE.VITAL_Timing.all;
|
| 4531 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 4532 |
|
|
use work.stratixiii_atom_pack.all;
|
| 4533 |
|
|
use work.stratixiii_ena_reg;
|
| 4534 |
|
|
use work.stratixiii_and2;
|
| 4535 |
|
|
|
| 4536 |
|
|
entity stratixiii_clkena is
|
| 4537 |
|
|
generic (
|
| 4538 |
|
|
clock_type : STRING := "Auto";
|
| 4539 |
|
|
lpm_type : STRING := "stratixiii_clkena";
|
| 4540 |
|
|
ena_register_mode : STRING := "Falling Edge";
|
| 4541 |
|
|
TimingChecksOn : Boolean := True;
|
| 4542 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 4543 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 4544 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 4545 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 4546 |
|
|
InstancePath : STRING := "*";
|
| 4547 |
|
|
tipd_inclk : VitalDelayType01 := DefPropDelay01;
|
| 4548 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01
|
| 4549 |
|
|
);
|
| 4550 |
|
|
port (
|
| 4551 |
|
|
inclk : in std_logic := '0';
|
| 4552 |
|
|
ena : in std_logic := '1';
|
| 4553 |
|
|
devclrn : in std_logic := '1';
|
| 4554 |
|
|
devpor : in std_logic := '1';
|
| 4555 |
|
|
enaout : out std_logic;
|
| 4556 |
|
|
outclk : out std_logic
|
| 4557 |
|
|
);
|
| 4558 |
|
|
attribute VITAL_LEVEL0 of stratixiii_clkena : entity is TRUE;
|
| 4559 |
|
|
end stratixiii_clkena;
|
| 4560 |
|
|
|
| 4561 |
|
|
architecture vital_clkena of stratixiii_clkena is
|
| 4562 |
|
|
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
|
| 4563 |
|
|
|
| 4564 |
|
|
component stratixiii_and2
|
| 4565 |
|
|
generic(
|
| 4566 |
|
|
TimingChecksOn: Boolean := True;
|
| 4567 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 4568 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 4569 |
|
|
InstancePath: STRING := "*";
|
| 4570 |
|
|
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
|
| 4571 |
|
|
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
|
| 4572 |
|
|
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
|
| 4573 |
|
|
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
|
| 4574 |
|
|
|
| 4575 |
|
|
port(
|
| 4576 |
|
|
Y : out STD_LOGIC;
|
| 4577 |
|
|
IN1 : in STD_LOGIC;
|
| 4578 |
|
|
IN2 : in STD_LOGIC);
|
| 4579 |
|
|
end component;
|
| 4580 |
|
|
|
| 4581 |
|
|
component stratixiii_ena_reg
|
| 4582 |
|
|
generic (
|
| 4583 |
|
|
TimingChecksOn : Boolean := True;
|
| 4584 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 4585 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 4586 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 4587 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 4588 |
|
|
InstancePath : STRING := "*";
|
| 4589 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 4590 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 4591 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 4592 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 4593 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01
|
| 4594 |
|
|
);
|
| 4595 |
|
|
PORT (
|
| 4596 |
|
|
clk : in std_logic;
|
| 4597 |
|
|
ena : in std_logic := '1';
|
| 4598 |
|
|
d : in std_logic;
|
| 4599 |
|
|
clrn : in std_logic := '1';
|
| 4600 |
|
|
prn : in std_logic := '1';
|
| 4601 |
|
|
q : out std_logic
|
| 4602 |
|
|
);
|
| 4603 |
|
|
end component;
|
| 4604 |
|
|
|
| 4605 |
|
|
signal inclk_ipd : std_logic;
|
| 4606 |
|
|
signal inclk_inv : std_logic;
|
| 4607 |
|
|
signal ena_ipd : std_logic;
|
| 4608 |
|
|
signal cereg_clr : std_logic;
|
| 4609 |
|
|
signal cereg1_out : std_logic;
|
| 4610 |
|
|
signal cereg2_out : std_logic;
|
| 4611 |
|
|
signal ena_out : std_logic;
|
| 4612 |
|
|
signal vcc : std_logic := '1';
|
| 4613 |
|
|
begin
|
| 4614 |
|
|
|
| 4615 |
|
|
---------------------
|
| 4616 |
|
|
-- INPUT PATH DELAYs
|
| 4617 |
|
|
---------------------
|
| 4618 |
|
|
WireDelay : block
|
| 4619 |
|
|
begin
|
| 4620 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 4621 |
|
|
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
|
| 4622 |
|
|
end block;
|
| 4623 |
|
|
|
| 4624 |
|
|
inclk_inv <= NOT inclk_ipd;
|
| 4625 |
|
|
|
| 4626 |
|
|
extena_reg1 : stratixiii_ena_reg
|
| 4627 |
|
|
port map (
|
| 4628 |
|
|
clk => inclk_inv,
|
| 4629 |
|
|
ena => vcc,
|
| 4630 |
|
|
d => ena_ipd,
|
| 4631 |
|
|
clrn => vcc,
|
| 4632 |
|
|
prn => devpor,
|
| 4633 |
|
|
q => cereg1_out
|
| 4634 |
|
|
);
|
| 4635 |
|
|
|
| 4636 |
|
|
extena_reg2 : stratixiii_ena_reg
|
| 4637 |
|
|
port map (
|
| 4638 |
|
|
clk => inclk_inv,
|
| 4639 |
|
|
ena => vcc,
|
| 4640 |
|
|
d => cereg1_out,
|
| 4641 |
|
|
clrn => vcc,
|
| 4642 |
|
|
prn => devpor,
|
| 4643 |
|
|
q => cereg2_out
|
| 4644 |
|
|
);
|
| 4645 |
|
|
|
| 4646 |
|
|
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
|
| 4647 |
|
|
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
|
| 4648 |
|
|
|
| 4649 |
|
|
outclk_and : stratixiii_and2
|
| 4650 |
|
|
port map (
|
| 4651 |
|
|
IN1 => inclk_ipd,
|
| 4652 |
|
|
IN2 => ena_out,
|
| 4653 |
|
|
Y => outclk
|
| 4654 |
|
|
);
|
| 4655 |
|
|
|
| 4656 |
|
|
enaout_and : stratixiii_and2
|
| 4657 |
|
|
port map (
|
| 4658 |
|
|
IN1 => vcc,
|
| 4659 |
|
|
IN2 => ena_out,
|
| 4660 |
|
|
Y => enaout
|
| 4661 |
|
|
);
|
| 4662 |
|
|
|
| 4663 |
|
|
|
| 4664 |
|
|
end vital_clkena;
|
| 4665 |
|
|
|
| 4666 |
|
|
|
| 4667 |
|
|
|
| 4668 |
|
|
----------------------------------------------------------------------------
|
| 4669 |
|
|
-- Module Name : stratixiii_mlab_cell_pulse_generator
|
| 4670 |
|
|
-- Description : Generate pulse to initiate memory read/write operations
|
| 4671 |
|
|
----------------------------------------------------------------------------
|
| 4672 |
|
|
|
| 4673 |
|
|
LIBRARY IEEE;
|
| 4674 |
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
| 4675 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 4676 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 4677 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 4678 |
|
|
|
| 4679 |
|
|
ENTITY stratixiii_mlab_cell_pulse_generator IS
|
| 4680 |
|
|
GENERIC (
|
| 4681 |
|
|
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
|
| 4682 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 4683 |
|
|
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
|
| 4684 |
|
|
);
|
| 4685 |
|
|
PORT (
|
| 4686 |
|
|
clk,ena : IN STD_LOGIC;
|
| 4687 |
|
|
pulse,cycle : OUT STD_LOGIC
|
| 4688 |
|
|
);
|
| 4689 |
|
|
ATTRIBUTE VITAL_Level0 OF stratixiii_mlab_cell_pulse_generator:ENTITY IS TRUE;
|
| 4690 |
|
|
END stratixiii_mlab_cell_pulse_generator;
|
| 4691 |
|
|
|
| 4692 |
|
|
ARCHITECTURE pgen_arch OF stratixiii_mlab_cell_pulse_generator IS
|
| 4693 |
|
|
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
|
| 4694 |
|
|
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
|
| 4695 |
|
|
SIGNAL state : STD_LOGIC;
|
| 4696 |
|
|
BEGIN
|
| 4697 |
|
|
|
| 4698 |
|
|
WireDelay : BLOCK
|
| 4699 |
|
|
BEGIN
|
| 4700 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 4701 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 4702 |
|
|
END BLOCK;
|
| 4703 |
|
|
|
| 4704 |
|
|
PROCESS (clk_ipd,state)
|
| 4705 |
|
|
BEGIN
|
| 4706 |
|
|
IF (state = '1' AND state'EVENT) THEN
|
| 4707 |
|
|
state <= '0';
|
| 4708 |
|
|
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
|
| 4709 |
|
|
state <= '1';
|
| 4710 |
|
|
END IF;
|
| 4711 |
|
|
END PROCESS;
|
| 4712 |
|
|
|
| 4713 |
|
|
PathDelay : PROCESS
|
| 4714 |
|
|
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
|
| 4715 |
|
|
BEGIN
|
| 4716 |
|
|
WAIT UNTIL state'EVENT;
|
| 4717 |
|
|
VitalPathDelay01 (
|
| 4718 |
|
|
OutSignal => pulse,
|
| 4719 |
|
|
OutSignalName => "pulse",
|
| 4720 |
|
|
OutTemp => state,
|
| 4721 |
|
|
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
|
| 4722 |
|
|
GlitchData => pulse_VitalGlitchData,
|
| 4723 |
|
|
Mode => DefGlitchMode,
|
| 4724 |
|
|
XOn => DefXOnChecks,
|
| 4725 |
|
|
MsgOn => DefMsgOnChecks
|
| 4726 |
|
|
);
|
| 4727 |
|
|
END PROCESS;
|
| 4728 |
|
|
|
| 4729 |
|
|
cycle <= clk_ipd;
|
| 4730 |
|
|
|
| 4731 |
|
|
END pgen_arch;
|
| 4732 |
|
|
|
| 4733 |
|
|
LIBRARY IEEE;
|
| 4734 |
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
| 4735 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 4736 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 4737 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 4738 |
|
|
USE work.stratixiii_mlab_cell_pulse_generator;
|
| 4739 |
|
|
|
| 4740 |
|
|
ENTITY stratixiii_mlab_cell IS
|
| 4741 |
|
|
GENERIC (
|
| 4742 |
|
|
-- -------- GLOBAL PARAMETERS ---------
|
| 4743 |
|
|
logical_ram_name : STRING := "lutram";
|
| 4744 |
|
|
init_file : STRING := "UNUSED";
|
| 4745 |
|
|
data_interleave_offset_in_bits : INTEGER := 1;
|
| 4746 |
|
|
logical_ram_depth : INTEGER := 0;
|
| 4747 |
|
|
logical_ram_width : INTEGER := 0;
|
| 4748 |
|
|
first_address : INTEGER := 0;
|
| 4749 |
|
|
last_address : INTEGER := 0;
|
| 4750 |
|
|
first_bit_number : INTEGER := 0;
|
| 4751 |
|
|
data_width : INTEGER := 1;
|
| 4752 |
|
|
address_width : INTEGER := 1;
|
| 4753 |
|
|
byte_enable_mask_width : INTEGER := 1;
|
| 4754 |
|
|
byte_size : INTEGER := 1;
|
| 4755 |
|
|
lpm_type : string := "stratixiii_mlab_cell";
|
| 4756 |
|
|
lpm_hint : string := "true";
|
| 4757 |
|
|
mixed_port_feed_through_mode : string := "dont_care";
|
| 4758 |
|
|
mem_init0 : BIT_VECTOR := X"0";
|
| 4759 |
|
|
-- --------- VITAL PARAMETERS --------
|
| 4760 |
|
|
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
|
| 4761 |
|
|
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
|
| 4762 |
|
|
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
|
| 4763 |
|
|
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
|
| 4764 |
|
|
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
|
| 4765 |
|
|
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 4766 |
|
|
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 4767 |
|
|
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 4768 |
|
|
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 4769 |
|
|
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
|
| 4770 |
|
|
|
| 4771 |
|
|
);
|
| 4772 |
|
|
-- -------- PORT DECLARATIONS ---------
|
| 4773 |
|
|
PORT (
|
| 4774 |
|
|
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
|
| 4775 |
|
|
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
|
| 4776 |
|
|
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
|
| 4777 |
|
|
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
|
| 4778 |
|
|
clk0 : IN STD_LOGIC := '0';
|
| 4779 |
|
|
ena0 : IN STD_LOGIC := '1';
|
| 4780 |
|
|
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
|
| 4781 |
|
|
);
|
| 4782 |
|
|
|
| 4783 |
|
|
END stratixiii_mlab_cell;
|
| 4784 |
|
|
|
| 4785 |
|
|
ARCHITECTURE block_arch OF stratixiii_mlab_cell IS
|
| 4786 |
|
|
COMPONENT stratixiii_mlab_cell_pulse_generator
|
| 4787 |
|
|
PORT (
|
| 4788 |
|
|
clk : IN STD_LOGIC;
|
| 4789 |
|
|
ena : IN STD_LOGIC;
|
| 4790 |
|
|
pulse : OUT STD_LOGIC;
|
| 4791 |
|
|
cycle : OUT STD_LOGIC
|
| 4792 |
|
|
);
|
| 4793 |
|
|
END COMPONENT;
|
| 4794 |
|
|
|
| 4795 |
|
|
CONSTANT port_byte_size : INTEGER := data_width / byte_enable_mask_width;
|
| 4796 |
|
|
|
| 4797 |
|
|
-- -------- internal signals ---------
|
| 4798 |
|
|
|
| 4799 |
|
|
-- Write address
|
| 4800 |
|
|
SIGNAL write_address : INTEGER := 0;
|
| 4801 |
|
|
SIGNAL read_address : INTEGER := 0;
|
| 4802 |
|
|
-- pulses
|
| 4803 |
|
|
SIGNAL write_pulse, write_cycle, write_clock : STD_LOGIC;
|
| 4804 |
|
|
|
| 4805 |
|
|
-- memory core
|
| 4806 |
|
|
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
|
| 4807 |
|
|
TYPE mem_type IS ARRAY ((2 ** address_width) - 1 DOWNTO 0) OF mem_word_type;
|
| 4808 |
|
|
SIGNAL mem : mem_type;
|
| 4809 |
|
|
SIGNAL init_mem : BOOLEAN := FALSE;
|
| 4810 |
|
|
|
| 4811 |
|
|
|
| 4812 |
|
|
-- byte enable
|
| 4813 |
|
|
TYPE mask_type IS (normal,inverse);
|
| 4814 |
|
|
TYPE mask_write IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
|
| 4815 |
|
|
|
| 4816 |
|
|
SIGNAL mask_vector : mask_write := (
|
| 4817 |
|
|
normal => (OTHERS => '0'),
|
| 4818 |
|
|
inverse => (OTHERS => 'X')
|
| 4819 |
|
|
);
|
| 4820 |
|
|
-- output
|
| 4821 |
|
|
|
| 4822 |
|
|
FUNCTION get_mask(
|
| 4823 |
|
|
b_ena : IN STD_LOGIC_VECTOR;
|
| 4824 |
|
|
CONSTANT b_ena_width ,byte_size: INTEGER
|
| 4825 |
|
|
) RETURN mask_write IS
|
| 4826 |
|
|
|
| 4827 |
|
|
VARIABLE l : INTEGER;
|
| 4828 |
|
|
VARIABLE mask : mask_write := (normal => (OTHERS => '0'),inverse => (OTHERS => 'X'));
|
| 4829 |
|
|
BEGIN
|
| 4830 |
|
|
FOR l in 0 TO b_ena_width - 1 LOOP
|
| 4831 |
|
|
IF (b_ena(l) = '0') THEN
|
| 4832 |
|
|
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
|
| 4833 |
|
|
mask(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
|
| 4834 |
|
|
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
|
| 4835 |
|
|
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
|
| 4836 |
|
|
END IF;
|
| 4837 |
|
|
END LOOP;
|
| 4838 |
|
|
RETURN mask;
|
| 4839 |
|
|
END get_mask;
|
| 4840 |
|
|
|
| 4841 |
|
|
SIGNAL clk0_ipd : STD_LOGIC;
|
| 4842 |
|
|
SIGNAL ena0_ipd : STD_LOGIC;
|
| 4843 |
|
|
SIGNAL portaaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
|
| 4844 |
|
|
SIGNAL portbaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
|
| 4845 |
|
|
SIGNAL portabyteenamasks_ipd : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
|
| 4846 |
|
|
SIGNAL ena0_reg : STD_LOGIC := '0';
|
| 4847 |
|
|
|
| 4848 |
|
|
BEGIN
|
| 4849 |
|
|
-- interconnect delays
|
| 4850 |
|
|
WireDelay : BLOCK
|
| 4851 |
|
|
BEGIN
|
| 4852 |
|
|
loopbits_ad : FOR i in portaaddr'RANGE GENERATE
|
| 4853 |
|
|
VitalWireDelay (portaaddr_ipd(i), portaaddr(i), tipd_portaaddr(i));
|
| 4854 |
|
|
VitalWireDelay (portbaddr_ipd(i), portbaddr(i), tipd_portbaddr(i));
|
| 4855 |
|
|
END GENERATE;
|
| 4856 |
|
|
loopbits_be : FOR j in portabyteenamasks'RANGE GENERATE
|
| 4857 |
|
|
VitalWireDelay (portabyteenamasks_ipd(j), portabyteenamasks(j), tipd_portabyteenamasks(j));
|
| 4858 |
|
|
END GENERATE;
|
| 4859 |
|
|
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
|
| 4860 |
|
|
VitalWireDelay (ena0_ipd, ena0, tipd_ena0);
|
| 4861 |
|
|
END BLOCK;
|
| 4862 |
|
|
|
| 4863 |
|
|
-- setup/hold checks
|
| 4864 |
|
|
setup_hold_checks: PROCESS (ena0_reg,portaaddr_ipd,portabyteenamasks_ipd)
|
| 4865 |
|
|
VARIABLE Tviol_clk_enable : STD_ULOGIC := '0';
|
| 4866 |
|
|
VARIABLE Tviol_clk_address : STD_ULOGIC := '0';
|
| 4867 |
|
|
VARIABLE Tviol_clk_bemasks : STD_ULOGIC := '0';
|
| 4868 |
|
|
VARIABLE TimingData_clk_enable : VitalTimingDataType := VitalTimingDataInit;
|
| 4869 |
|
|
VARIABLE TimingData_clk_address : VitalTimingDataType := VitalTimingDataInit;
|
| 4870 |
|
|
VARIABLE TimingData_clk_bemasks : VitalTimingDataType := VitalTimingDataInit;
|
| 4871 |
|
|
BEGIN
|
| 4872 |
|
|
-- Timing checks
|
| 4873 |
|
|
|
| 4874 |
|
|
VitalSetupHoldCheck (
|
| 4875 |
|
|
Violation => Tviol_clk_address,
|
| 4876 |
|
|
TimingData => TimingData_clk_address,
|
| 4877 |
|
|
TestSignal => portaaddr_ipd,
|
| 4878 |
|
|
TestSignalName => "portaaddr",
|
| 4879 |
|
|
RefSignal => clk0_ipd,
|
| 4880 |
|
|
RefSignalName => "clk0",
|
| 4881 |
|
|
SetupHigh => tsetup_portaaddr_clk0_noedge_negedge,
|
| 4882 |
|
|
SetupLow => tsetup_portaaddr_clk0_noedge_negedge,
|
| 4883 |
|
|
HoldHigh => thold_portaaddr_clk0_noedge_negedge,
|
| 4884 |
|
|
HoldLow => thold_portaaddr_clk0_noedge_negedge,
|
| 4885 |
|
|
CheckEnabled => (ena0_reg = '1'),
|
| 4886 |
|
|
|
| 4887 |
|
|
RefTransition => '\',
|
| 4888 |
|
|
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
|
| 4889 |
|
|
XOn => DefXOnChecks,
|
| 4890 |
|
|
MsgOn => DefMsgOnChecks );
|
| 4891 |
|
|
|
| 4892 |
|
|
VitalSetupHoldCheck (
|
| 4893 |
|
|
Violation => Tviol_clk_bemasks,
|
| 4894 |
|
|
TimingData => TimingData_clk_bemasks,
|
| 4895 |
|
|
TestSignal => portabyteenamasks_ipd,
|
| 4896 |
|
|
TestSignalName => "portabyteenamasks",
|
| 4897 |
|
|
RefSignal => clk0_ipd,
|
| 4898 |
|
|
RefSignalName => "clk0",
|
| 4899 |
|
|
SetupHigh => tsetup_portabyteenamasks_clk0_noedge_negedge,
|
| 4900 |
|
|
SetupLow => tsetup_portabyteenamasks_clk0_noedge_negedge,
|
| 4901 |
|
|
HoldHigh => thold_portabyteenamasks_clk0_noedge_negedge,
|
| 4902 |
|
|
HoldLow => thold_portabyteenamasks_clk0_noedge_negedge,
|
| 4903 |
|
|
CheckEnabled => (ena0_reg = '1'),
|
| 4904 |
|
|
|
| 4905 |
|
|
RefTransition => '\',
|
| 4906 |
|
|
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
|
| 4907 |
|
|
XOn => DefXOnChecks,
|
| 4908 |
|
|
MsgOn => DefMsgOnChecks );
|
| 4909 |
|
|
|
| 4910 |
|
|
END PROCESS setup_hold_checks;
|
| 4911 |
|
|
|
| 4912 |
|
|
-- latch CE signal
|
| 4913 |
|
|
PROCESS (clk0_ipd)
|
| 4914 |
|
|
BEGIN
|
| 4915 |
|
|
IF (clk0_ipd'EVENT AND clk0_ipd = '1') THEN
|
| 4916 |
|
|
ena0_reg <= ena0_ipd;
|
| 4917 |
|
|
END IF;
|
| 4918 |
|
|
END PROCESS;
|
| 4919 |
|
|
|
| 4920 |
|
|
-- output path delay
|
| 4921 |
|
|
PROCESS (portbaddr_ipd)
|
| 4922 |
|
|
VARIABLE CQDelay : TIME := 0 ns;
|
| 4923 |
|
|
BEGIN
|
| 4924 |
|
|
CQDelay := SelectDelay(
|
| 4925 |
|
|
( 1 => ( portbaddr_ipd'LAST_EVENT, tpd_portbaddr_portbdataout, TRUE ) )
|
| 4926 |
|
|
);
|
| 4927 |
|
|
read_address <= TRANSPORT alt_conv_integer(portbaddr_ipd) AFTER CQDelay;
|
| 4928 |
|
|
END PROCESS;
|
| 4929 |
|
|
|
| 4930 |
|
|
-- memory initialization
|
| 4931 |
|
|
init_mem <= TRUE;
|
| 4932 |
|
|
write_clock <= NOT clk0_ipd;
|
| 4933 |
|
|
write_address <= alt_conv_integer(portaaddr_ipd);
|
| 4934 |
|
|
|
| 4935 |
|
|
-- Write pulse generation (neg edge)
|
| 4936 |
|
|
wpgen_a : stratixiii_mlab_cell_pulse_generator
|
| 4937 |
|
|
PORT MAP (
|
| 4938 |
|
|
clk => write_clock,
|
| 4939 |
|
|
ena => ena0_reg,
|
| 4940 |
|
|
pulse => write_pulse,
|
| 4941 |
|
|
cycle => write_cycle
|
| 4942 |
|
|
);
|
| 4943 |
|
|
|
| 4944 |
|
|
-- Create internal masks for byte enable processing
|
| 4945 |
|
|
mask_create : PROCESS (portabyteenamasks_ipd)
|
| 4946 |
|
|
VARIABLE mask : mask_write;
|
| 4947 |
|
|
BEGIN
|
| 4948 |
|
|
IF (portabyteenamasks_ipd'EVENT) THEN
|
| 4949 |
|
|
mask := get_mask(portabyteenamasks_ipd,byte_enable_mask_width,port_byte_size);
|
| 4950 |
|
|
mask_vector <= mask;
|
| 4951 |
|
|
END IF;
|
| 4952 |
|
|
END PROCESS mask_create;
|
| 4953 |
|
|
|
| 4954 |
|
|
|
| 4955 |
|
|
mem_rw : PROCESS (init_mem, write_pulse)
|
| 4956 |
|
|
-- mem init
|
| 4957 |
|
|
VARIABLE addr_range_init,index : INTEGER;
|
| 4958 |
|
|
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
|
| 4959 |
|
|
VARIABLE mem_val : mem_type;
|
| 4960 |
|
|
-- read/write
|
| 4961 |
|
|
VARIABLE mem_data_p : mem_word_type;
|
| 4962 |
|
|
BEGIN
|
| 4963 |
|
|
-- Memory initialization
|
| 4964 |
|
|
IF (init_mem'EVENT) THEN
|
| 4965 |
|
|
-- Initialize output to 0
|
| 4966 |
|
|
mem_val := (OTHERS => (OTHERS => '0'));
|
| 4967 |
|
|
IF (init_file /= "UNUSED" AND init_file /= "unused") THEN
|
| 4968 |
|
|
addr_range_init := last_address - first_address + 1;
|
| 4969 |
|
|
mem_init_std := to_stdlogicvector(mem_init0)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
|
| 4970 |
|
|
FOR row IN 0 TO addr_range_init - 1 LOOP
|
| 4971 |
|
|
index := row * data_width;
|
| 4972 |
|
|
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
|
| 4973 |
|
|
END LOOP;
|
| 4974 |
|
|
END IF;
|
| 4975 |
|
|
mem <= mem_val;
|
| 4976 |
|
|
END IF;
|
| 4977 |
|
|
|
| 4978 |
|
|
-- Write stage 1 : X to memory
|
| 4979 |
|
|
-- Write stage 2 : actual data to memory
|
| 4980 |
|
|
IF (write_pulse'EVENT) THEN
|
| 4981 |
|
|
IF (write_pulse = '1') THEN
|
| 4982 |
|
|
mem_data_p := mem(write_address);
|
| 4983 |
|
|
FOR i IN 0 TO data_width - 1 LOOP
|
| 4984 |
|
|
mem_data_p(i) := mem_data_p(i) XOR mask_vector(inverse)(i);
|
| 4985 |
|
|
END LOOP;
|
| 4986 |
|
|
mem(write_address) <= mem_data_p;
|
| 4987 |
|
|
ELSIF (write_pulse = '0') THEN
|
| 4988 |
|
|
mem_data_p := mem(write_address);
|
| 4989 |
|
|
FOR i IN 0 TO data_width - 1 LOOP
|
| 4990 |
|
|
IF (mask_vector(normal)(i) = '0') THEN
|
| 4991 |
|
|
mem(write_address)(i) <= portadatain(i);
|
| 4992 |
|
|
mem_data_p(i) := portadatain(i);
|
| 4993 |
|
|
ELSIF (mask_vector(inverse)(i) = 'X') THEN
|
| 4994 |
|
|
mem(write_address)(i) <= 'X';
|
| 4995 |
|
|
mem_data_p(i) := 'X';
|
| 4996 |
|
|
END IF;
|
| 4997 |
|
|
END LOOP;
|
| 4998 |
|
|
END IF;
|
| 4999 |
|
|
END IF;
|
| 5000 |
|
|
|
| 5001 |
|
|
|
| 5002 |
|
|
END PROCESS mem_rw;
|
| 5003 |
|
|
|
| 5004 |
|
|
-- Continuous read
|
| 5005 |
|
|
portbdataout <= mem(read_address);
|
| 5006 |
|
|
|
| 5007 |
|
|
END block_arch;
|
| 5008 |
|
|
|
| 5009 |
|
|
|
| 5010 |
|
|
---------------------------------------------------------------------
|
| 5011 |
|
|
--
|
| 5012 |
|
|
-- Entity Name : stratixiii_io_ibuf
|
| 5013 |
|
|
--
|
| 5014 |
|
|
-- Description : Stratix III IO Ibuf VHDL simulation model
|
| 5015 |
|
|
--
|
| 5016 |
|
|
--
|
| 5017 |
|
|
---------------------------------------------------------------------
|
| 5018 |
|
|
|
| 5019 |
|
|
library IEEE;
|
| 5020 |
|
|
use IEEE.std_logic_1164.all;
|
| 5021 |
|
|
use IEEE.VITAL_Timing.all;
|
| 5022 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 5023 |
|
|
use work.stratixiii_atom_pack.all;
|
| 5024 |
|
|
|
| 5025 |
|
|
ENTITY stratixiii_io_ibuf IS
|
| 5026 |
|
|
GENERIC (
|
| 5027 |
|
|
tipd_i : VitalDelayType01 := DefPropDelay01;
|
| 5028 |
|
|
tipd_ibar : VitalDelayType01 := DefPropDelay01;
|
| 5029 |
|
|
tpd_i_o : VitalDelayType01 := DefPropDelay01;
|
| 5030 |
|
|
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
|
| 5031 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 5032 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 5033 |
|
|
differential_mode : string := "false";
|
| 5034 |
|
|
bus_hold : string := "false";
|
| 5035 |
|
|
simulate_z_as : string := "Z";
|
| 5036 |
|
|
lpm_type : string := "stratixiii_io_ibuf"
|
| 5037 |
|
|
);
|
| 5038 |
|
|
PORT (
|
| 5039 |
|
|
i : IN std_logic := '0';
|
| 5040 |
|
|
ibar : IN std_logic := '0';
|
| 5041 |
|
|
o : OUT std_logic
|
| 5042 |
|
|
);
|
| 5043 |
|
|
END stratixiii_io_ibuf;
|
| 5044 |
|
|
|
| 5045 |
|
|
ARCHITECTURE arch OF stratixiii_io_ibuf IS
|
| 5046 |
|
|
SIGNAL i_ipd : std_logic := '0';
|
| 5047 |
|
|
SIGNAL ibar_ipd : std_logic := '0';
|
| 5048 |
|
|
SIGNAL o_tmp : std_logic;
|
| 5049 |
|
|
SIGNAL out_tmp : std_logic;
|
| 5050 |
|
|
SIGNAL prev_value : std_logic := '0';
|
| 5051 |
|
|
BEGIN
|
| 5052 |
|
|
WireDelay : block
|
| 5053 |
|
|
begin
|
| 5054 |
|
|
VitalWireDelay (i_ipd, i, tipd_i);
|
| 5055 |
|
|
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
|
| 5056 |
|
|
end block;
|
| 5057 |
|
|
|
| 5058 |
|
|
PROCESS(i_ipd, ibar_ipd)
|
| 5059 |
|
|
BEGIN
|
| 5060 |
|
|
IF (differential_mode = "false") THEN
|
| 5061 |
|
|
IF (i_ipd = '1') THEN
|
| 5062 |
|
|
o_tmp <= '1';
|
| 5063 |
|
|
prev_value <= '1';
|
| 5064 |
|
|
ELSIF (i_ipd = '0') THEN
|
| 5065 |
|
|
o_tmp <= '0';
|
| 5066 |
|
|
prev_value <= '0';
|
| 5067 |
|
|
ELSE
|
| 5068 |
|
|
o_tmp <= i_ipd;
|
| 5069 |
|
|
END IF;
|
| 5070 |
|
|
ELSE
|
| 5071 |
|
|
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
|
| 5072 |
|
|
o_tmp <= '0';
|
| 5073 |
|
|
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
|
| 5074 |
|
|
o_tmp <= '1';
|
| 5075 |
|
|
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
|
| 5076 |
|
|
o_tmp <= 'X';
|
| 5077 |
|
|
ELSE
|
| 5078 |
|
|
o_tmp <= 'X';
|
| 5079 |
|
|
END IF;
|
| 5080 |
|
|
END IF;
|
| 5081 |
|
|
END PROCESS;
|
| 5082 |
|
|
|
| 5083 |
|
|
out_tmp <= prev_value when (bus_hold = "true") else
|
| 5084 |
|
|
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
|
| 5085 |
|
|
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
|
| 5086 |
|
|
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
|
| 5087 |
|
|
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
|
| 5088 |
|
|
o_tmp;
|
| 5089 |
|
|
----------------------
|
| 5090 |
|
|
-- Path Delay Section
|
| 5091 |
|
|
----------------------
|
| 5092 |
|
|
PROCESS( out_tmp)
|
| 5093 |
|
|
variable output_VitalGlitchData : VitalGlitchDataType;
|
| 5094 |
|
|
BEGIN
|
| 5095 |
|
|
VitalPathDelay01 (
|
| 5096 |
|
|
OutSignal => o,
|
| 5097 |
|
|
OutSignalName => "o",
|
| 5098 |
|
|
OutTemp => out_tmp,
|
| 5099 |
|
|
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
|
| 5100 |
|
|
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
|
| 5101 |
|
|
GlitchData => output_VitalGlitchData,
|
| 5102 |
|
|
Mode => DefGlitchMode,
|
| 5103 |
|
|
XOn => XOn,
|
| 5104 |
|
|
MsgOn => MsgOn
|
| 5105 |
|
|
);
|
| 5106 |
|
|
END PROCESS;
|
| 5107 |
|
|
END arch;
|
| 5108 |
|
|
|
| 5109 |
|
|
|
| 5110 |
|
|
|
| 5111 |
|
|
---------------------------------------------------------------------
|
| 5112 |
|
|
--
|
| 5113 |
|
|
-- Entity Name : stratixiii_io_obuf
|
| 5114 |
|
|
--
|
| 5115 |
|
|
-- Description : Stratix III IO Obuf VHDL simulation model
|
| 5116 |
|
|
--
|
| 5117 |
|
|
--
|
| 5118 |
|
|
---------------------------------------------------------------------
|
| 5119 |
|
|
|
| 5120 |
|
|
LIBRARY IEEE;
|
| 5121 |
|
|
use IEEE.std_logic_1164.all;
|
| 5122 |
|
|
use IEEE.std_logic_arith.all;
|
| 5123 |
|
|
use IEEE.VITAL_Timing.all;
|
| 5124 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 5125 |
|
|
use work.stratixiii_atom_pack.all;
|
| 5126 |
|
|
|
| 5127 |
|
|
ENTITY stratixiii_io_obuf IS
|
| 5128 |
|
|
GENERIC (
|
| 5129 |
|
|
tipd_i : VitalDelayType01 := DefPropDelay01;
|
| 5130 |
|
|
tipd_oe : VitalDelayType01 := DefPropDelay01;
|
| 5131 |
|
|
tpd_i_o : VitalDelayType01 := DefPropDelay01;
|
| 5132 |
|
|
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
|
| 5133 |
|
|
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
|
| 5134 |
|
|
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
|
| 5135 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 5136 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 5137 |
|
|
open_drain_output : string := "false";
|
| 5138 |
|
|
shift_series_termination_control : string := "false";
|
| 5139 |
|
|
bus_hold : string := "false";
|
| 5140 |
|
|
lpm_type : string := "stratixiii_io_obuf"
|
| 5141 |
|
|
);
|
| 5142 |
|
|
PORT (
|
| 5143 |
|
|
i : IN std_logic := '0';
|
| 5144 |
|
|
oe : IN std_logic := '1';
|
| 5145 |
|
|
dynamicterminationcontrol : IN std_logic := '0';
|
| 5146 |
|
|
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
|
| 5147 |
|
|
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
|
| 5148 |
|
|
devoe : IN std_logic := '1';
|
| 5149 |
|
|
o : OUT std_logic;
|
| 5150 |
|
|
obar : OUT std_logic
|
| 5151 |
|
|
);
|
| 5152 |
|
|
END stratixiii_io_obuf;
|
| 5153 |
|
|
|
| 5154 |
|
|
ARCHITECTURE arch OF stratixiii_io_obuf IS
|
| 5155 |
|
|
--INTERNAL Signals
|
| 5156 |
|
|
SIGNAL i_ipd : std_logic := '0';
|
| 5157 |
|
|
SIGNAL oe_ipd : std_logic := '0';
|
| 5158 |
|
|
SIGNAL out_tmp : std_logic := 'Z';
|
| 5159 |
|
|
SIGNAL out_tmp_bar : std_logic;
|
| 5160 |
|
|
SIGNAL prev_value : std_logic := '0';
|
| 5161 |
|
|
SIGNAL o_tmp : std_logic;
|
| 5162 |
|
|
SIGNAL obar_tmp : std_logic;
|
| 5163 |
|
|
SIGNAL o_tmp1 : std_logic;
|
| 5164 |
|
|
SIGNAL obar_tmp1 : std_logic;
|
| 5165 |
|
|
BEGIN
|
| 5166 |
|
|
|
| 5167 |
|
|
WireDelay : block
|
| 5168 |
|
|
begin
|
| 5169 |
|
|
VitalWireDelay (i_ipd, i, tipd_i);
|
| 5170 |
|
|
VitalWireDelay (oe_ipd, oe, tipd_oe);
|
| 5171 |
|
|
end block;
|
| 5172 |
|
|
PROCESS( i_ipd, oe_ipd)
|
| 5173 |
|
|
BEGIN
|
| 5174 |
|
|
IF (oe_ipd = '1') THEN
|
| 5175 |
|
|
IF (open_drain_output = "true") THEN
|
| 5176 |
|
|
IF (i_ipd = '0') THEN
|
| 5177 |
|
|
out_tmp <= '0';
|
| 5178 |
|
|
out_tmp_bar <= '1';
|
| 5179 |
|
|
prev_value <= '0';
|
| 5180 |
|
|
ELSE
|
| 5181 |
|
|
out_tmp <= 'Z';
|
| 5182 |
|
|
out_tmp_bar <= 'Z';
|
| 5183 |
|
|
END IF;
|
| 5184 |
|
|
ELSE
|
| 5185 |
|
|
IF (i_ipd = '0') THEN
|
| 5186 |
|
|
out_tmp <= '0';
|
| 5187 |
|
|
out_tmp_bar <= '1';
|
| 5188 |
|
|
prev_value <= '0';
|
| 5189 |
|
|
ELSE
|
| 5190 |
|
|
IF (i_ipd = '1') THEN
|
| 5191 |
|
|
out_tmp <= '1';
|
| 5192 |
|
|
out_tmp_bar <= '0';
|
| 5193 |
|
|
prev_value <= '1';
|
| 5194 |
|
|
ELSE
|
| 5195 |
|
|
out_tmp <= i_ipd;
|
| 5196 |
|
|
out_tmp_bar <= i_ipd;
|
| 5197 |
|
|
END IF;
|
| 5198 |
|
|
END IF;
|
| 5199 |
|
|
END IF;
|
| 5200 |
|
|
ELSE
|
| 5201 |
|
|
IF (oe_ipd = '0') THEN
|
| 5202 |
|
|
out_tmp <= 'Z';
|
| 5203 |
|
|
out_tmp_bar <= 'Z';
|
| 5204 |
|
|
ELSE
|
| 5205 |
|
|
out_tmp <= 'X';
|
| 5206 |
|
|
out_tmp_bar <= 'X';
|
| 5207 |
|
|
END IF;
|
| 5208 |
|
|
END IF;
|
| 5209 |
|
|
END PROCESS;
|
| 5210 |
|
|
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
|
| 5211 |
|
|
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
|
| 5212 |
|
|
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (shift_series_termination_control = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
|
| 5213 |
|
|
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (shift_series_termination_control = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
|
| 5214 |
|
|
---------------------
|
| 5215 |
|
|
-- Path Delay Section
|
| 5216 |
|
|
----------------------
|
| 5217 |
|
|
PROCESS( o_tmp,obar_tmp)
|
| 5218 |
|
|
variable o_VitalGlitchData : VitalGlitchDataType;
|
| 5219 |
|
|
variable obar_VitalGlitchData : VitalGlitchDataType;
|
| 5220 |
|
|
BEGIN
|
| 5221 |
|
|
VitalPathDelay01 (
|
| 5222 |
|
|
OutSignal => o,
|
| 5223 |
|
|
OutSignalName => "o",
|
| 5224 |
|
|
OutTemp => o_tmp,
|
| 5225 |
|
|
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
|
| 5226 |
|
|
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
|
| 5227 |
|
|
GlitchData => o_VitalGlitchData,
|
| 5228 |
|
|
Mode => DefGlitchMode,
|
| 5229 |
|
|
XOn => XOn,
|
| 5230 |
|
|
MsgOn => MsgOn
|
| 5231 |
|
|
);
|
| 5232 |
|
|
VitalPathDelay01 (
|
| 5233 |
|
|
OutSignal => obar,
|
| 5234 |
|
|
OutSignalName => "obar",
|
| 5235 |
|
|
OutTemp => obar_tmp,
|
| 5236 |
|
|
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
|
| 5237 |
|
|
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
|
| 5238 |
|
|
GlitchData => obar_VitalGlitchData,
|
| 5239 |
|
|
Mode => DefGlitchMode,
|
| 5240 |
|
|
XOn => XOn,
|
| 5241 |
|
|
MsgOn => MsgOn
|
| 5242 |
|
|
);
|
| 5243 |
|
|
END PROCESS;
|
| 5244 |
|
|
END arch;
|
| 5245 |
|
|
|
| 5246 |
|
|
-----------------------------------------------------------------------
|
| 5247 |
|
|
--
|
| 5248 |
|
|
-- Entity Name : stratixiii_ddio_in
|
| 5249 |
|
|
--
|
| 5250 |
|
|
-- Description : Stratix III DDIO_IN VHDL simulation model
|
| 5251 |
|
|
--
|
| 5252 |
|
|
--
|
| 5253 |
|
|
---------------------------------------------------------------------
|
| 5254 |
|
|
LIBRARY IEEE;
|
| 5255 |
|
|
LIBRARY altera;
|
| 5256 |
|
|
use IEEE.std_logic_1164.all;
|
| 5257 |
|
|
use IEEE.std_logic_arith.all;
|
| 5258 |
|
|
use IEEE.VITAL_Timing.all;
|
| 5259 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 5260 |
|
|
use altera.altera_primitives_components.all;
|
| 5261 |
|
|
use work.stratixiii_atom_pack.all;
|
| 5262 |
|
|
|
| 5263 |
|
|
|
| 5264 |
|
|
ENTITY stratixiii_ddio_in IS
|
| 5265 |
|
|
generic(
|
| 5266 |
|
|
tipd_datain : VitalDelayType01 := DefPropDelay01;
|
| 5267 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 5268 |
|
|
tipd_clkn : VitalDelayType01 := DefPropDelay01;
|
| 5269 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 5270 |
|
|
tipd_areset : VitalDelayType01 := DefPropDelay01;
|
| 5271 |
|
|
tipd_sreset : VitalDelayType01 := DefPropDelay01;
|
| 5272 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 5273 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 5274 |
|
|
power_up : string := "low";
|
| 5275 |
|
|
async_mode : string := "none";
|
| 5276 |
|
|
sync_mode : string := "none";
|
| 5277 |
|
|
use_clkn : string := "false";
|
| 5278 |
|
|
lpm_type : string := "stratixiii_ddio_in"
|
| 5279 |
|
|
);
|
| 5280 |
|
|
PORT (
|
| 5281 |
|
|
datain : IN std_logic := '0';
|
| 5282 |
|
|
clk : IN std_logic := '0';
|
| 5283 |
|
|
clkn : IN std_logic := '0';
|
| 5284 |
|
|
ena : IN std_logic := '1';
|
| 5285 |
|
|
areset : IN std_logic := '0';
|
| 5286 |
|
|
sreset : IN std_logic := '0';
|
| 5287 |
|
|
regoutlo : OUT std_logic;
|
| 5288 |
|
|
regouthi : OUT std_logic;
|
| 5289 |
|
|
dfflo : OUT std_logic;
|
| 5290 |
|
|
devclrn : IN std_logic := '1';
|
| 5291 |
|
|
devpor : IN std_logic := '1'
|
| 5292 |
|
|
);
|
| 5293 |
|
|
END stratixiii_ddio_in;
|
| 5294 |
|
|
|
| 5295 |
|
|
ARCHITECTURE arch OF stratixiii_ddio_in IS
|
| 5296 |
|
|
|
| 5297 |
|
|
component dffeas
|
| 5298 |
|
|
generic (
|
| 5299 |
|
|
power_up : string := "DONT_CARE";
|
| 5300 |
|
|
is_wysiwyg : string := "false";
|
| 5301 |
|
|
x_on_violation : string := "on";
|
| 5302 |
|
|
lpm_type : string := "DFFEAS";
|
| 5303 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5304 |
|
|
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5305 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5306 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5307 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5308 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5309 |
|
|
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5310 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5311 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5312 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5313 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 5314 |
|
|
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 5315 |
|
|
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 5316 |
|
|
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 5317 |
|
|
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
| 5318 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 5319 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 5320 |
|
|
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
| 5321 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
| 5322 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 5323 |
|
|
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
| 5324 |
|
|
tipd_prn : VitalDelayType01 := DefPropDelay01;
|
| 5325 |
|
|
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
| 5326 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 5327 |
|
|
TimingChecksOn: Boolean := True;
|
| 5328 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 5329 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 5330 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 5331 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 5332 |
|
|
InstancePath: STRING := "*"
|
| 5333 |
|
|
);
|
| 5334 |
|
|
|
| 5335 |
|
|
port (
|
| 5336 |
|
|
d : in std_logic := '0';
|
| 5337 |
|
|
clk : in std_logic := '0';
|
| 5338 |
|
|
ena : in std_logic := '1';
|
| 5339 |
|
|
clrn : in std_logic := '1';
|
| 5340 |
|
|
prn : in std_logic := '1';
|
| 5341 |
|
|
aload : in std_logic := '0';
|
| 5342 |
|
|
asdata : in std_logic := '1';
|
| 5343 |
|
|
sclr : in std_logic := '0';
|
| 5344 |
|
|
sload : in std_logic := '0';
|
| 5345 |
|
|
devclrn : in std_logic := '1';
|
| 5346 |
|
|
devpor : in std_logic := '1';
|
| 5347 |
|
|
q : out std_logic
|
| 5348 |
|
|
);
|
| 5349 |
|
|
end component;
|
| 5350 |
|
|
|
| 5351 |
|
|
--Internal Signals
|
| 5352 |
|
|
SIGNAL datain_ipd : std_logic := '0';
|
| 5353 |
|
|
SIGNAL clk_ipd : std_logic := '0';
|
| 5354 |
|
|
SIGNAL clkn_ipd : std_logic := '0';
|
| 5355 |
|
|
SIGNAL ena_ipd : std_logic := '0';
|
| 5356 |
|
|
SIGNAL areset_ipd : std_logic := '0';
|
| 5357 |
|
|
SIGNAL sreset_ipd : std_logic := '0';
|
| 5358 |
|
|
SIGNAL ddioreg_aclr : std_logic;
|
| 5359 |
|
|
SIGNAL ddioreg_prn : std_logic;
|
| 5360 |
|
|
SIGNAL ddioreg_adatasdata : std_logic;
|
| 5361 |
|
|
SIGNAL ddioreg_sclr : std_logic;
|
| 5362 |
|
|
SIGNAL ddioreg_sload : std_logic;
|
| 5363 |
|
|
SIGNAL ddioreg_clk : std_logic;
|
| 5364 |
|
|
SIGNAL dfflo_tmp : std_logic;
|
| 5365 |
|
|
SIGNAL regout_tmp_hi : std_logic;
|
| 5366 |
|
|
SIGNAL regout_tmp_lo : std_logic;
|
| 5367 |
|
|
SIGNAL regouthi_tmp : std_logic;
|
| 5368 |
|
|
SIGNAL regoutlo_tmp : std_logic;
|
| 5369 |
|
|
|
| 5370 |
|
|
|
| 5371 |
|
|
BEGIN
|
| 5372 |
|
|
|
| 5373 |
|
|
WireDelay : block
|
| 5374 |
|
|
begin
|
| 5375 |
|
|
VitalWireDelay (datain_ipd, datain, tipd_datain);
|
| 5376 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 5377 |
|
|
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
|
| 5378 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 5379 |
|
|
VitalWireDelay (areset_ipd, areset, tipd_areset);
|
| 5380 |
|
|
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
|
| 5381 |
|
|
end block;
|
| 5382 |
|
|
|
| 5383 |
|
|
|
| 5384 |
|
|
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
|
| 5385 |
|
|
|
| 5386 |
|
|
--Decode the control values for the DDIO registers
|
| 5387 |
|
|
PROCESS
|
| 5388 |
|
|
BEGIN
|
| 5389 |
|
|
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
|
| 5390 |
|
|
IF (async_mode = "clear") THEN
|
| 5391 |
|
|
ddioreg_aclr <= NOT areset_ipd;
|
| 5392 |
|
|
ddioreg_prn <= '1';
|
| 5393 |
|
|
ELSIF (async_mode = "preset") THEN
|
| 5394 |
|
|
ddioreg_aclr <= '1';
|
| 5395 |
|
|
ddioreg_prn <= NOT areset_ipd;
|
| 5396 |
|
|
ELSE
|
| 5397 |
|
|
ddioreg_aclr <= '1';
|
| 5398 |
|
|
ddioreg_prn <= '1';
|
| 5399 |
|
|
END IF;
|
| 5400 |
|
|
|
| 5401 |
|
|
IF (sync_mode = "clear") THEN
|
| 5402 |
|
|
ddioreg_adatasdata <= '0';
|
| 5403 |
|
|
ddioreg_sclr <= sreset_ipd;
|
| 5404 |
|
|
ddioreg_sload <= '0';
|
| 5405 |
|
|
ELSIF (sync_mode = "preset") THEN
|
| 5406 |
|
|
ddioreg_adatasdata <= '1';
|
| 5407 |
|
|
ddioreg_sclr <= '0';
|
| 5408 |
|
|
ddioreg_sload <= sreset_ipd;
|
| 5409 |
|
|
ELSE
|
| 5410 |
|
|
ddioreg_adatasdata <= '0';
|
| 5411 |
|
|
ddioreg_sclr <= '0';
|
| 5412 |
|
|
ddioreg_sload <= '0';
|
| 5413 |
|
|
END IF;
|
| 5414 |
|
|
END PROCESS;
|
| 5415 |
|
|
|
| 5416 |
|
|
--DDIO High Register
|
| 5417 |
|
|
ddioreg_hi : dffeas
|
| 5418 |
|
|
GENERIC MAP (
|
| 5419 |
|
|
power_up => power_up
|
| 5420 |
|
|
)
|
| 5421 |
|
|
PORT MAP (
|
| 5422 |
|
|
d => datain_ipd,
|
| 5423 |
|
|
clk => clk_ipd,
|
| 5424 |
|
|
clrn => ddioreg_aclr,
|
| 5425 |
|
|
prn => ddioreg_prn,
|
| 5426 |
|
|
sclr => ddioreg_sclr,
|
| 5427 |
|
|
sload => ddioreg_sload,
|
| 5428 |
|
|
asdata => ddioreg_adatasdata,
|
| 5429 |
|
|
ena => ena_ipd,
|
| 5430 |
|
|
q => regout_tmp_hi,
|
| 5431 |
|
|
devpor => devpor,
|
| 5432 |
|
|
devclrn => devclrn
|
| 5433 |
|
|
);
|
| 5434 |
|
|
|
| 5435 |
|
|
--DDIO Low Register
|
| 5436 |
|
|
ddioreg_lo : dffeas
|
| 5437 |
|
|
GENERIC MAP (
|
| 5438 |
|
|
power_up => power_up
|
| 5439 |
|
|
)
|
| 5440 |
|
|
PORT MAP (
|
| 5441 |
|
|
d => datain_ipd,
|
| 5442 |
|
|
clk => ddioreg_clk,
|
| 5443 |
|
|
clrn => ddioreg_aclr,
|
| 5444 |
|
|
prn => ddioreg_prn,
|
| 5445 |
|
|
sclr => ddioreg_sclr,
|
| 5446 |
|
|
sload => ddioreg_sload,
|
| 5447 |
|
|
asdata => ddioreg_adatasdata,
|
| 5448 |
|
|
ena => ena_ipd,
|
| 5449 |
|
|
q => dfflo_tmp,
|
| 5450 |
|
|
devpor => devpor,
|
| 5451 |
|
|
devclrn => devclrn
|
| 5452 |
|
|
);
|
| 5453 |
|
|
|
| 5454 |
|
|
ddioreg_lo1 : dffeas
|
| 5455 |
|
|
GENERIC MAP (
|
| 5456 |
|
|
power_up => power_up
|
| 5457 |
|
|
)
|
| 5458 |
|
|
PORT MAP (
|
| 5459 |
|
|
d => dfflo_tmp,
|
| 5460 |
|
|
clk => clk_ipd,
|
| 5461 |
|
|
clrn => ddioreg_aclr,
|
| 5462 |
|
|
prn => ddioreg_prn,
|
| 5463 |
|
|
sclr => ddioreg_sclr,
|
| 5464 |
|
|
sload => ddioreg_sload,
|
| 5465 |
|
|
asdata => ddioreg_adatasdata,
|
| 5466 |
|
|
ena => ena_ipd,
|
| 5467 |
|
|
q => regout_tmp_lo,
|
| 5468 |
|
|
devpor => devpor,
|
| 5469 |
|
|
devclrn => devclrn
|
| 5470 |
|
|
);
|
| 5471 |
|
|
|
| 5472 |
|
|
regouthi <= regout_tmp_hi ;
|
| 5473 |
|
|
regoutlo <= regout_tmp_lo ;
|
| 5474 |
|
|
dfflo <= dfflo_tmp ;
|
| 5475 |
|
|
END arch;
|
| 5476 |
|
|
|
| 5477 |
|
|
---------------------------------------------------------------------
|
| 5478 |
|
|
--
|
| 5479 |
|
|
-- Entity Name : stratixiii_ddio_oe
|
| 5480 |
|
|
--
|
| 5481 |
|
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-- Description : Stratix III DDIO_OE VHDL simulation model
|
| 5482 |
|
|
--
|
| 5483 |
|
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--
|
| 5484 |
|
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---------------------------------------------------------------------
|
| 5485 |
|
|
|
| 5486 |
|
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LIBRARY IEEE;
|
| 5487 |
|
|
LIBRARY altera;
|
| 5488 |
|
|
use IEEE.std_logic_1164.all;
|
| 5489 |
|
|
use IEEE.std_logic_arith.all;
|
| 5490 |
|
|
use IEEE.VITAL_Timing.all;
|
| 5491 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 5492 |
|
|
use altera.altera_primitives_components.all;
|
| 5493 |
|
|
use work.stratixiii_atom_pack.all;
|
| 5494 |
|
|
|
| 5495 |
|
|
|
| 5496 |
|
|
|
| 5497 |
|
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ENTITY stratixiii_ddio_oe IS
|
| 5498 |
|
|
generic(
|
| 5499 |
|
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tipd_oe : VitalDelayType01 := DefPropDelay01;
|
| 5500 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 5501 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 5502 |
|
|
tipd_areset : VitalDelayType01 := DefPropDelay01;
|
| 5503 |
|
|
tipd_sreset : VitalDelayType01 := DefPropDelay01;
|
| 5504 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 5505 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 5506 |
|
|
power_up : string := "low";
|
| 5507 |
|
|
async_mode : string := "none";
|
| 5508 |
|
|
sync_mode : string := "none";
|
| 5509 |
|
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lpm_type : string := "stratixiii_ddio_oe"
|
| 5510 |
|
|
);
|
| 5511 |
|
|
|
| 5512 |
|
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PORT (
|
| 5513 |
|
|
oe : IN std_logic := '1';
|
| 5514 |
|
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clk : IN std_logic := '0';
|
| 5515 |
|
|
ena : IN std_logic := '1';
|
| 5516 |
|
|
areset : IN std_logic := '0';
|
| 5517 |
|
|
sreset : IN std_logic := '0';
|
| 5518 |
|
|
dataout : OUT std_logic;
|
| 5519 |
|
|
dfflo : OUT std_logic;
|
| 5520 |
|
|
dffhi : OUT std_logic;
|
| 5521 |
|
|
devclrn : IN std_logic := '1';
|
| 5522 |
|
|
devpor : IN std_logic := '1'
|
| 5523 |
|
|
);
|
| 5524 |
|
|
END stratixiii_ddio_oe;
|
| 5525 |
|
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|
| 5526 |
|
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ARCHITECTURE arch OF stratixiii_ddio_oe IS
|
| 5527 |
|
|
|
| 5528 |
|
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component stratixiii_mux21
|
| 5529 |
|
|
generic(
|
| 5530 |
|
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TimingChecksOn: Boolean := True;
|
| 5531 |
|
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MsgOn: Boolean := DefGlitchMsgOn;
|
| 5532 |
|
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XOn: Boolean := DefGlitchXOn;
|
| 5533 |
|
|
InstancePath: STRING := "*";
|
| 5534 |
|
|
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
|
| 5535 |
|
|
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
|
| 5536 |
|
|
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
|
| 5537 |
|
|
tipd_A : VitalDelayType01 := DefPropDelay01;
|
| 5538 |
|
|
tipd_B : VitalDelayType01 := DefPropDelay01;
|
| 5539 |
|
|
tipd_S : VitalDelayType01 := DefPropDelay01
|
| 5540 |
|
|
);
|
| 5541 |
|
|
port (
|
| 5542 |
|
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A : in std_logic := '0';
|
| 5543 |
|
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B : in std_logic := '0';
|
| 5544 |
|
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S : in std_logic := '0';
|
| 5545 |
|
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MO : out std_logic
|
| 5546 |
|
|
);
|
| 5547 |
|
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end component;
|
| 5548 |
|
|
|
| 5549 |
|
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component dffeas
|
| 5550 |
|
|
generic (
|
| 5551 |
|
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power_up : string := "DONT_CARE";
|
| 5552 |
|
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is_wysiwyg : string := "false";
|
| 5553 |
|
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x_on_violation : string := "on";
|
| 5554 |
|
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lpm_type : string := "DFFEAS";
|
| 5555 |
|
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tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5556 |
|
|
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5557 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5558 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5559 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5560 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5561 |
|
|
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5562 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5563 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5564 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5565 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 5566 |
|
|
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 5567 |
|
|
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 5568 |
|
|
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 5569 |
|
|
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
| 5570 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 5571 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 5572 |
|
|
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
| 5573 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
| 5574 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 5575 |
|
|
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
| 5576 |
|
|
tipd_prn : VitalDelayType01 := DefPropDelay01;
|
| 5577 |
|
|
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
| 5578 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 5579 |
|
|
TimingChecksOn: Boolean := True;
|
| 5580 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 5581 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 5582 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 5583 |
|
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XOnChecks: Boolean := DefXOnChecks;
|
| 5584 |
|
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InstancePath: STRING := "*"
|
| 5585 |
|
|
);
|
| 5586 |
|
|
|
| 5587 |
|
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port (
|
| 5588 |
|
|
d : in std_logic := '0';
|
| 5589 |
|
|
clk : in std_logic := '0';
|
| 5590 |
|
|
ena : in std_logic := '1';
|
| 5591 |
|
|
clrn : in std_logic := '1';
|
| 5592 |
|
|
prn : in std_logic := '1';
|
| 5593 |
|
|
aload : in std_logic := '0';
|
| 5594 |
|
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asdata : in std_logic := '1';
|
| 5595 |
|
|
sclr : in std_logic := '0';
|
| 5596 |
|
|
sload : in std_logic := '0';
|
| 5597 |
|
|
devclrn : in std_logic := '1';
|
| 5598 |
|
|
devpor : in std_logic := '1';
|
| 5599 |
|
|
q : out std_logic
|
| 5600 |
|
|
);
|
| 5601 |
|
|
end component;
|
| 5602 |
|
|
|
| 5603 |
|
|
--Internal Signals
|
| 5604 |
|
|
SIGNAL oe_ipd : std_logic := '0';
|
| 5605 |
|
|
SIGNAL clk_ipd : std_logic := '0';
|
| 5606 |
|
|
SIGNAL ena_ipd : std_logic := '0';
|
| 5607 |
|
|
SIGNAL areset_ipd : std_logic := '0';
|
| 5608 |
|
|
SIGNAL sreset_ipd : std_logic := '0';
|
| 5609 |
|
|
SIGNAL ddioreg_aclr : std_logic;
|
| 5610 |
|
|
SIGNAL ddioreg_prn : std_logic;
|
| 5611 |
|
|
SIGNAL ddioreg_adatasdata : std_logic;
|
| 5612 |
|
|
SIGNAL ddioreg_sclr : std_logic;
|
| 5613 |
|
|
SIGNAL ddioreg_sload : std_logic;
|
| 5614 |
|
|
SIGNAL dfflo_tmp : std_logic;
|
| 5615 |
|
|
SIGNAL dffhi_tmp : std_logic;
|
| 5616 |
|
|
signal nclk : std_logic;
|
| 5617 |
|
|
signal dataout_tmp : std_logic;
|
| 5618 |
|
|
|
| 5619 |
|
|
BEGIN
|
| 5620 |
|
|
|
| 5621 |
|
|
WireDelay : block
|
| 5622 |
|
|
begin
|
| 5623 |
|
|
VitalWireDelay (oe_ipd, oe, tipd_oe);
|
| 5624 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 5625 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 5626 |
|
|
VitalWireDelay (areset_ipd, areset, tipd_areset);
|
| 5627 |
|
|
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
|
| 5628 |
|
|
end block;
|
| 5629 |
|
|
|
| 5630 |
|
|
nclk <= NOT clk_ipd;
|
| 5631 |
|
|
PROCESS
|
| 5632 |
|
|
BEGIN
|
| 5633 |
|
|
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
|
| 5634 |
|
|
IF (async_mode = "clear") THEN
|
| 5635 |
|
|
ddioreg_aclr <= NOT areset_ipd;
|
| 5636 |
|
|
ddioreg_prn <= '1';
|
| 5637 |
|
|
ELSIF (async_mode = "preset") THEN
|
| 5638 |
|
|
ddioreg_aclr <= '1';
|
| 5639 |
|
|
ddioreg_prn <= NOT areset_ipd;
|
| 5640 |
|
|
ELSE
|
| 5641 |
|
|
ddioreg_aclr <= '1';
|
| 5642 |
|
|
ddioreg_prn <= '1';
|
| 5643 |
|
|
END IF;
|
| 5644 |
|
|
|
| 5645 |
|
|
IF (sync_mode = "clear") THEN
|
| 5646 |
|
|
ddioreg_adatasdata <= '0';
|
| 5647 |
|
|
ddioreg_sclr <= sreset_ipd;
|
| 5648 |
|
|
ddioreg_sload <= '0';
|
| 5649 |
|
|
ELSIF (sync_mode = "preset") THEN
|
| 5650 |
|
|
ddioreg_adatasdata <= '1';
|
| 5651 |
|
|
ddioreg_sclr <= '0';
|
| 5652 |
|
|
ddioreg_sload <= sreset_ipd;
|
| 5653 |
|
|
ELSE
|
| 5654 |
|
|
ddioreg_adatasdata <= '0';
|
| 5655 |
|
|
ddioreg_sclr <= '0';
|
| 5656 |
|
|
ddioreg_sload <= '0';
|
| 5657 |
|
|
END IF;
|
| 5658 |
|
|
END PROCESS;
|
| 5659 |
|
|
|
| 5660 |
|
|
ddioreg_hi : dffeas
|
| 5661 |
|
|
GENERIC MAP (
|
| 5662 |
|
|
power_up => power_up
|
| 5663 |
|
|
)
|
| 5664 |
|
|
PORT MAP (
|
| 5665 |
|
|
d => oe_ipd,
|
| 5666 |
|
|
clk => clk_ipd,
|
| 5667 |
|
|
clrn => ddioreg_aclr,
|
| 5668 |
|
|
prn => ddioreg_prn,
|
| 5669 |
|
|
sclr => ddioreg_sclr,
|
| 5670 |
|
|
sload => ddioreg_sload,
|
| 5671 |
|
|
asdata => ddioreg_adatasdata,
|
| 5672 |
|
|
ena => ena_ipd,
|
| 5673 |
|
|
q => dffhi_tmp,
|
| 5674 |
|
|
devpor => devpor,
|
| 5675 |
|
|
devclrn => devclrn
|
| 5676 |
|
|
);
|
| 5677 |
|
|
|
| 5678 |
|
|
|
| 5679 |
|
|
--DDIO Low Register
|
| 5680 |
|
|
ddioreg_lo : dffeas
|
| 5681 |
|
|
GENERIC MAP (
|
| 5682 |
|
|
power_up => power_up
|
| 5683 |
|
|
)
|
| 5684 |
|
|
PORT MAP (
|
| 5685 |
|
|
d => dffhi_tmp,
|
| 5686 |
|
|
clk => nclk,
|
| 5687 |
|
|
clrn => ddioreg_aclr,
|
| 5688 |
|
|
prn => ddioreg_prn,
|
| 5689 |
|
|
sclr => ddioreg_sclr,
|
| 5690 |
|
|
sload => ddioreg_sload,
|
| 5691 |
|
|
asdata => ddioreg_adatasdata,
|
| 5692 |
|
|
ena => ena_ipd,
|
| 5693 |
|
|
q => dfflo_tmp,
|
| 5694 |
|
|
devpor => devpor,
|
| 5695 |
|
|
devclrn => devclrn
|
| 5696 |
|
|
);
|
| 5697 |
|
|
|
| 5698 |
|
|
--registered output
|
| 5699 |
|
|
or_gate : stratixiii_mux21
|
| 5700 |
|
|
port map (
|
| 5701 |
|
|
A => dffhi_tmp,
|
| 5702 |
|
|
B => dfflo_tmp,
|
| 5703 |
|
|
S => dfflo_tmp,
|
| 5704 |
|
|
MO => dataout
|
| 5705 |
|
|
);
|
| 5706 |
|
|
|
| 5707 |
|
|
dfflo <= dfflo_tmp ;
|
| 5708 |
|
|
dffhi <= dffhi_tmp ;
|
| 5709 |
|
|
|
| 5710 |
|
|
END arch;
|
| 5711 |
|
|
|
| 5712 |
|
|
---------------------------------------------------------------------
|
| 5713 |
|
|
--
|
| 5714 |
|
|
-- Entity Name : stratixiii_ddio_out
|
| 5715 |
|
|
--
|
| 5716 |
|
|
-- Description : Stratix III DDIO_OUT VHDL simulation model
|
| 5717 |
|
|
--
|
| 5718 |
|
|
--
|
| 5719 |
|
|
---------------------------------------------------------------------
|
| 5720 |
|
|
|
| 5721 |
|
|
LIBRARY IEEE;
|
| 5722 |
|
|
LIBRARY altera;
|
| 5723 |
|
|
use IEEE.std_logic_1164.all;
|
| 5724 |
|
|
use IEEE.std_logic_arith.all;
|
| 5725 |
|
|
use IEEE.VITAL_Timing.all;
|
| 5726 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 5727 |
|
|
use altera.altera_primitives_components.all;
|
| 5728 |
|
|
use work.stratixiii_atom_pack.all;
|
| 5729 |
|
|
|
| 5730 |
|
|
ENTITY stratixiii_ddio_out IS
|
| 5731 |
|
|
generic(
|
| 5732 |
|
|
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
|
| 5733 |
|
|
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
|
| 5734 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 5735 |
|
|
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
|
| 5736 |
|
|
tipd_clklo : VitalDelayType01 := DefPropDelay01;
|
| 5737 |
|
|
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
|
| 5738 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 5739 |
|
|
tipd_areset : VitalDelayType01 := DefPropDelay01;
|
| 5740 |
|
|
tipd_sreset : VitalDelayType01 := DefPropDelay01;
|
| 5741 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 5742 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 5743 |
|
|
power_up : string := "low";
|
| 5744 |
|
|
async_mode : string := "none";
|
| 5745 |
|
|
sync_mode : string := "none";
|
| 5746 |
|
|
half_rate_mode : string := "false";
|
| 5747 |
|
|
use_new_clocking_model : string := "false";
|
| 5748 |
|
|
lpm_type : string := "stratixiii_ddio_out"
|
| 5749 |
|
|
);
|
| 5750 |
|
|
PORT (
|
| 5751 |
|
|
datainlo : IN std_logic := '0';
|
| 5752 |
|
|
datainhi : IN std_logic := '0';
|
| 5753 |
|
|
clk : IN std_logic := '0';
|
| 5754 |
|
|
clkhi : IN std_logic := '0';
|
| 5755 |
|
|
clklo : IN std_logic := '0';
|
| 5756 |
|
|
muxsel : IN std_logic := '0';
|
| 5757 |
|
|
ena : IN std_logic := '1';
|
| 5758 |
|
|
areset : IN std_logic := '0';
|
| 5759 |
|
|
sreset : IN std_logic := '0';
|
| 5760 |
|
|
dataout : OUT std_logic;
|
| 5761 |
|
|
dfflo : OUT std_logic;
|
| 5762 |
|
|
dffhi : OUT std_logic ;
|
| 5763 |
|
|
devclrn : IN std_logic := '1';
|
| 5764 |
|
|
devpor : IN std_logic := '1'
|
| 5765 |
|
|
);
|
| 5766 |
|
|
END stratixiii_ddio_out;
|
| 5767 |
|
|
|
| 5768 |
|
|
ARCHITECTURE arch OF stratixiii_ddio_out IS
|
| 5769 |
|
|
|
| 5770 |
|
|
component stratixiii_mux21
|
| 5771 |
|
|
generic(
|
| 5772 |
|
|
TimingChecksOn: Boolean := True;
|
| 5773 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 5774 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 5775 |
|
|
InstancePath: STRING := "*";
|
| 5776 |
|
|
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
|
| 5777 |
|
|
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
|
| 5778 |
|
|
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
|
| 5779 |
|
|
tipd_A : VitalDelayType01 := DefPropDelay01;
|
| 5780 |
|
|
tipd_B : VitalDelayType01 := DefPropDelay01;
|
| 5781 |
|
|
tipd_S : VitalDelayType01 := DefPropDelay01
|
| 5782 |
|
|
);
|
| 5783 |
|
|
port (
|
| 5784 |
|
|
A : in std_logic := '0';
|
| 5785 |
|
|
B : in std_logic := '0';
|
| 5786 |
|
|
S : in std_logic := '0';
|
| 5787 |
|
|
MO : out std_logic
|
| 5788 |
|
|
);
|
| 5789 |
|
|
end component;
|
| 5790 |
|
|
|
| 5791 |
|
|
component dffeas
|
| 5792 |
|
|
generic (
|
| 5793 |
|
|
power_up : string := "DONT_CARE";
|
| 5794 |
|
|
is_wysiwyg : string := "false";
|
| 5795 |
|
|
x_on_violation : string := "on";
|
| 5796 |
|
|
lpm_type : string := "DFFEAS";
|
| 5797 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5798 |
|
|
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5799 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5800 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5801 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5802 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5803 |
|
|
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5804 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5805 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5806 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 5807 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 5808 |
|
|
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 5809 |
|
|
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 5810 |
|
|
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 5811 |
|
|
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
| 5812 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 5813 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 5814 |
|
|
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
| 5815 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
| 5816 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 5817 |
|
|
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
| 5818 |
|
|
tipd_prn : VitalDelayType01 := DefPropDelay01;
|
| 5819 |
|
|
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
| 5820 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 5821 |
|
|
TimingChecksOn: Boolean := True;
|
| 5822 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 5823 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 5824 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 5825 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 5826 |
|
|
InstancePath: STRING := "*"
|
| 5827 |
|
|
);
|
| 5828 |
|
|
|
| 5829 |
|
|
port (
|
| 5830 |
|
|
d : in std_logic := '0';
|
| 5831 |
|
|
clk : in std_logic := '0';
|
| 5832 |
|
|
ena : in std_logic := '1';
|
| 5833 |
|
|
clrn : in std_logic := '1';
|
| 5834 |
|
|
prn : in std_logic := '1';
|
| 5835 |
|
|
aload : in std_logic := '0';
|
| 5836 |
|
|
asdata : in std_logic := '1';
|
| 5837 |
|
|
sclr : in std_logic := '0';
|
| 5838 |
|
|
sload : in std_logic := '0';
|
| 5839 |
|
|
devclrn : in std_logic := '1';
|
| 5840 |
|
|
devpor : in std_logic := '1';
|
| 5841 |
|
|
q : out std_logic
|
| 5842 |
|
|
);
|
| 5843 |
|
|
end component;
|
| 5844 |
|
|
|
| 5845 |
|
|
--Internal Signals
|
| 5846 |
|
|
SIGNAL datainlo_ipd : std_logic := '0';
|
| 5847 |
|
|
SIGNAL datainhi_ipd : std_logic := '0';
|
| 5848 |
|
|
SIGNAL clk_ipd : std_logic := '0';
|
| 5849 |
|
|
SIGNAL clkhi_ipd : std_logic := '0';
|
| 5850 |
|
|
SIGNAL clklo_ipd : std_logic := '0';
|
| 5851 |
|
|
SIGNAL muxsel_ipd : std_logic := '0';
|
| 5852 |
|
|
SIGNAL ena_ipd : std_logic := '0';
|
| 5853 |
|
|
SIGNAL areset_ipd : std_logic := '0';
|
| 5854 |
|
|
SIGNAL sreset_ipd : std_logic := '0';
|
| 5855 |
|
|
SIGNAL ddioreg_aclr : std_logic;
|
| 5856 |
|
|
SIGNAL ddioreg_prn : std_logic;
|
| 5857 |
|
|
SIGNAL ddioreg_adatasdata : std_logic;
|
| 5858 |
|
|
SIGNAL ddioreg_sclr : std_logic;
|
| 5859 |
|
|
SIGNAL ddioreg_sload : std_logic;
|
| 5860 |
|
|
SIGNAL dfflo_tmp : std_logic;
|
| 5861 |
|
|
SIGNAL dffhi_tmp : std_logic;
|
| 5862 |
|
|
SIGNAL dataout_tmp : std_logic;
|
| 5863 |
|
|
Signal mux_sel : std_logic;
|
| 5864 |
|
|
Signal mux_hi : std_logic;
|
| 5865 |
|
|
Signal dffhi1_tmp : std_logic;
|
| 5866 |
|
|
Signal sel_mux_hi_in : std_logic;
|
| 5867 |
|
|
signal nclk : std_logic;
|
| 5868 |
|
|
signal clk1 : std_logic;
|
| 5869 |
|
|
signal clk_hi : std_logic;
|
| 5870 |
|
|
signal clk_lo : std_logic;
|
| 5871 |
|
|
signal clk_hr : std_logic;
|
| 5872 |
|
|
|
| 5873 |
|
|
signal muxsel1 : std_logic;
|
| 5874 |
|
|
signal muxsel2: std_logic;
|
| 5875 |
|
|
signal clk2 : std_logic;
|
| 5876 |
|
|
signal muxsel_tmp: std_logic;
|
| 5877 |
|
|
signal sel_mux_lo_in : std_logic;
|
| 5878 |
|
|
signal datainlo_tmp : std_logic;
|
| 5879 |
|
|
signal datainhi_tmp : std_logic;
|
| 5880 |
|
|
|
| 5881 |
|
|
BEGIN
|
| 5882 |
|
|
|
| 5883 |
|
|
WireDelay : block
|
| 5884 |
|
|
begin
|
| 5885 |
|
|
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
|
| 5886 |
|
|
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
|
| 5887 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 5888 |
|
|
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
|
| 5889 |
|
|
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
|
| 5890 |
|
|
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
|
| 5891 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 5892 |
|
|
VitalWireDelay (areset_ipd, areset, tipd_areset);
|
| 5893 |
|
|
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
|
| 5894 |
|
|
end block;
|
| 5895 |
|
|
nclk <= NOT clk_ipd;
|
| 5896 |
|
|
PROCESS
|
| 5897 |
|
|
BEGIN
|
| 5898 |
|
|
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
|
| 5899 |
|
|
IF (async_mode = "clear") THEN
|
| 5900 |
|
|
ddioreg_aclr <= NOT areset_ipd;
|
| 5901 |
|
|
ddioreg_prn <= '1';
|
| 5902 |
|
|
ELSIF (async_mode = "preset") THEN
|
| 5903 |
|
|
ddioreg_aclr <= '1';
|
| 5904 |
|
|
ddioreg_prn <= NOT areset_ipd;
|
| 5905 |
|
|
ELSE
|
| 5906 |
|
|
ddioreg_aclr <= '1';
|
| 5907 |
|
|
ddioreg_prn <= '1';
|
| 5908 |
|
|
END IF;
|
| 5909 |
|
|
|
| 5910 |
|
|
IF (sync_mode = "clear") THEN
|
| 5911 |
|
|
ddioreg_adatasdata <= '0';
|
| 5912 |
|
|
ddioreg_sclr <= sreset_ipd;
|
| 5913 |
|
|
ddioreg_sload <= '0';
|
| 5914 |
|
|
ELSIF (sync_mode = "preset") THEN
|
| 5915 |
|
|
ddioreg_adatasdata <= '1';
|
| 5916 |
|
|
ddioreg_sclr <= '0';
|
| 5917 |
|
|
ddioreg_sload <= sreset_ipd;
|
| 5918 |
|
|
ELSE
|
| 5919 |
|
|
ddioreg_adatasdata <= '0';
|
| 5920 |
|
|
ddioreg_sclr <= '0';
|
| 5921 |
|
|
ddioreg_sload <= '0';
|
| 5922 |
|
|
END IF;
|
| 5923 |
|
|
END PROCESS;
|
| 5924 |
|
|
|
| 5925 |
|
|
process(clk_ipd)
|
| 5926 |
|
|
begin
|
| 5927 |
|
|
clk1 <= clk_ipd;
|
| 5928 |
|
|
end process;
|
| 5929 |
|
|
|
| 5930 |
|
|
process(muxsel_ipd)
|
| 5931 |
|
|
begin
|
| 5932 |
|
|
muxsel1 <= muxsel_ipd;
|
| 5933 |
|
|
end process;
|
| 5934 |
|
|
|
| 5935 |
|
|
--DDIO HIGH Register
|
| 5936 |
|
|
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
|
| 5937 |
|
|
datainhi_tmp <= datainhi;
|
| 5938 |
|
|
ddioreg_hi : dffeas
|
| 5939 |
|
|
GENERIC MAP (
|
| 5940 |
|
|
power_up => power_up
|
| 5941 |
|
|
)
|
| 5942 |
|
|
PORT MAP (
|
| 5943 |
|
|
d => datainhi_tmp,
|
| 5944 |
|
|
clk => clk_hi,
|
| 5945 |
|
|
clrn => ddioreg_aclr,
|
| 5946 |
|
|
prn => ddioreg_prn,
|
| 5947 |
|
|
sclr => ddioreg_sclr,
|
| 5948 |
|
|
sload => ddioreg_sload,
|
| 5949 |
|
|
asdata => ddioreg_adatasdata,
|
| 5950 |
|
|
ena => ena_ipd,
|
| 5951 |
|
|
q => dffhi_tmp,
|
| 5952 |
|
|
devpor => devpor,
|
| 5953 |
|
|
devclrn => devclrn
|
| 5954 |
|
|
);
|
| 5955 |
|
|
|
| 5956 |
|
|
--DDIO Low Register
|
| 5957 |
|
|
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
|
| 5958 |
|
|
datainlo_tmp <= datainlo;
|
| 5959 |
|
|
ddioreg_lo : dffeas
|
| 5960 |
|
|
GENERIC MAP (
|
| 5961 |
|
|
power_up => power_up
|
| 5962 |
|
|
)
|
| 5963 |
|
|
PORT MAP (
|
| 5964 |
|
|
d => datainlo_tmp,
|
| 5965 |
|
|
clk => clk_lo,
|
| 5966 |
|
|
clrn => ddioreg_aclr,
|
| 5967 |
|
|
prn => ddioreg_prn,
|
| 5968 |
|
|
sclr => ddioreg_sclr,
|
| 5969 |
|
|
sload => ddioreg_sload,
|
| 5970 |
|
|
asdata => ddioreg_adatasdata,
|
| 5971 |
|
|
ena => ena_ipd,
|
| 5972 |
|
|
q => dfflo_tmp,
|
| 5973 |
|
|
devpor => devpor,
|
| 5974 |
|
|
devclrn => devclrn
|
| 5975 |
|
|
);
|
| 5976 |
|
|
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
|
| 5977 |
|
|
ddioreg_hi1 : dffeas
|
| 5978 |
|
|
GENERIC MAP (
|
| 5979 |
|
|
power_up => power_up
|
| 5980 |
|
|
)
|
| 5981 |
|
|
PORT MAP (
|
| 5982 |
|
|
d => dffhi_tmp,
|
| 5983 |
|
|
clk => clk_hr,
|
| 5984 |
|
|
clrn => ddioreg_aclr,
|
| 5985 |
|
|
prn => ddioreg_prn,
|
| 5986 |
|
|
sclr => ddioreg_sclr,
|
| 5987 |
|
|
sload => ddioreg_sload,
|
| 5988 |
|
|
asdata => ddioreg_adatasdata,
|
| 5989 |
|
|
ena => ena_ipd,
|
| 5990 |
|
|
q => dffhi1_tmp,
|
| 5991 |
|
|
devpor => devpor,
|
| 5992 |
|
|
devclrn => devclrn
|
| 5993 |
|
|
);
|
| 5994 |
|
|
|
| 5995 |
|
|
|
| 5996 |
|
|
|
| 5997 |
|
|
muxsel2 <= muxsel1;
|
| 5998 |
|
|
clk2 <= clk1;
|
| 5999 |
|
|
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
|
| 6000 |
|
|
muxsel_tmp <= mux_sel;
|
| 6001 |
|
|
sel_mux_lo_in <= dfflo_tmp;
|
| 6002 |
|
|
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
|
| 6003 |
|
|
|
| 6004 |
|
|
sel_mux : stratixiii_mux21
|
| 6005 |
|
|
port map (
|
| 6006 |
|
|
A => sel_mux_lo_in,
|
| 6007 |
|
|
B => sel_mux_hi_in,
|
| 6008 |
|
|
S => muxsel_tmp,
|
| 6009 |
|
|
MO => dataout
|
| 6010 |
|
|
);
|
| 6011 |
|
|
|
| 6012 |
|
|
dfflo <= dfflo_tmp;
|
| 6013 |
|
|
dffhi <= dffhi_tmp;
|
| 6014 |
|
|
|
| 6015 |
|
|
END arch;
|
| 6016 |
|
|
|
| 6017 |
|
|
-- --------------------------------------------------------------------
|
| 6018 |
|
|
-- Module Name: stratixiii_rt_sm
|
| 6019 |
|
|
-- Description: Parallel Termination State Machine
|
| 6020 |
|
|
-- --------------------------------------------------------------------
|
| 6021 |
|
|
|
| 6022 |
|
|
LIBRARY IEEE;
|
| 6023 |
|
|
USE IEEE.std_logic_1164.ALL;
|
| 6024 |
|
|
use IEEE.std_logic_arith.all;
|
| 6025 |
|
|
use IEEE.std_logic_unsigned.all;
|
| 6026 |
|
|
|
| 6027 |
|
|
ENTITY stratixiii_rt_sm IS
|
| 6028 |
|
|
PORT (
|
| 6029 |
|
|
rup : IN std_logic;
|
| 6030 |
|
|
rdn : IN std_logic;
|
| 6031 |
|
|
clk : IN std_logic;
|
| 6032 |
|
|
clken : IN std_logic;
|
| 6033 |
|
|
clr : IN std_logic;
|
| 6034 |
|
|
rtena : IN std_logic;
|
| 6035 |
|
|
rscaldone : IN std_logic;
|
| 6036 |
|
|
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
|
| 6037 |
|
|
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
|
| 6038 |
|
|
caldone : OUT std_logic;
|
| 6039 |
|
|
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
|
| 6040 |
|
|
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0));
|
| 6041 |
|
|
END stratixiii_rt_sm;
|
| 6042 |
|
|
|
| 6043 |
|
|
ARCHITECTURE stratixiii_rt_sm_rtl OF stratixiii_rt_sm IS
|
| 6044 |
|
|
|
| 6045 |
|
|
|
| 6046 |
|
|
CONSTANT STRATIXIII_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000";
|
| 6047 |
|
|
CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001";
|
| 6048 |
|
|
CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010";
|
| 6049 |
|
|
CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011";
|
| 6050 |
|
|
CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100";
|
| 6051 |
|
|
CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101";
|
| 6052 |
|
|
CONSTANT STRATIXIII_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000";
|
| 6053 |
|
|
CONSTANT STRATIXIII_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001";
|
| 6054 |
|
|
CONSTANT STRATIXIII_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010";
|
| 6055 |
|
|
CONSTANT STRATIXIII_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011";
|
| 6056 |
|
|
CONSTANT STRATIXIII_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100";
|
| 6057 |
|
|
CONSTANT STRATIXIII_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101";
|
| 6058 |
|
|
CONSTANT STRATIXIII_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001";
|
| 6059 |
|
|
CONSTANT STRATIXIII_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111";
|
| 6060 |
|
|
-- interface
|
| 6061 |
|
|
SIGNAL nclr : std_logic := '1'; -- for synthesis
|
| 6062 |
|
|
SIGNAL rtcalclk : std_logic;
|
| 6063 |
|
|
SIGNAL caldone_sig : std_logic := '0';
|
| 6064 |
|
|
-- sm
|
| 6065 |
|
|
SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000";
|
| 6066 |
|
|
SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000";
|
| 6067 |
|
|
SIGNAL sel_rup_vref_h_d : std_logic := '0';
|
| 6068 |
|
|
SIGNAL sel_rup_vref_h : std_logic := '0';
|
| 6069 |
|
|
SIGNAL sel_rup_vref_m_d : std_logic := '1';
|
| 6070 |
|
|
SIGNAL sel_rup_vref_m : std_logic := '1';
|
| 6071 |
|
|
SIGNAL sel_rup_vref_l_d : std_logic := '0';
|
| 6072 |
|
|
SIGNAL sel_rup_vref_l : std_logic := '0';
|
| 6073 |
|
|
SIGNAL sel_rdn_vref_h_d : std_logic := '0';
|
| 6074 |
|
|
SIGNAL sel_rdn_vref_h : std_logic := '0';
|
| 6075 |
|
|
SIGNAL sel_rdn_vref_m_d : std_logic := '1';
|
| 6076 |
|
|
SIGNAL sel_rdn_vref_m : std_logic := '1';
|
| 6077 |
|
|
SIGNAL sel_rdn_vref_l_d : std_logic := '0';
|
| 6078 |
|
|
SIGNAL sel_rdn_vref_l : std_logic := '0';
|
| 6079 |
|
|
SIGNAL switch_region_d : std_logic := '0';
|
| 6080 |
|
|
SIGNAL switch_region : std_logic := '0';
|
| 6081 |
|
|
SIGNAL cmpup : std_logic := '0';
|
| 6082 |
|
|
SIGNAL cmpdn : std_logic := '0';
|
| 6083 |
|
|
SIGNAL rt_sm_done_d : std_logic := '0';
|
| 6084 |
|
|
SIGNAL rt_sm_done : std_logic := '0';
|
| 6085 |
|
|
-- cnt
|
| 6086 |
|
|
SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
|
| 6087 |
|
|
SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000";
|
| 6088 |
|
|
SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
|
| 6089 |
|
|
SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000";
|
| 6090 |
|
|
SIGNAL p_cnt_sub_d : std_logic := '0';
|
| 6091 |
|
|
SIGNAL p_cnt_sub : std_logic := '0';
|
| 6092 |
|
|
SIGNAL n_cnt_sub_d : std_logic := '0';
|
| 6093 |
|
|
SIGNAL n_cnt_sub : std_logic := '0';
|
| 6094 |
|
|
|
| 6095 |
|
|
BEGIN
|
| 6096 |
|
|
-- primary output - MSB is sign bit
|
| 6097 |
|
|
rtoffsetp <= p_cnt_sub & p_cnt ;
|
| 6098 |
|
|
rtoffsetn <= n_cnt_sub & n_cnt ;
|
| 6099 |
|
|
caldone <= caldone_sig;
|
| 6100 |
|
|
caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1';
|
| 6101 |
|
|
|
| 6102 |
|
|
sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ;
|
| 6103 |
|
|
sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ;
|
| 6104 |
|
|
|
| 6105 |
|
|
-- input interface
|
| 6106 |
|
|
nclr <= NOT clr ;
|
| 6107 |
|
|
rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ;
|
| 6108 |
|
|
|
| 6109 |
|
|
-- latch registers - rising on everything except cmpup and cmpdn
|
| 6110 |
|
|
-- cmpup/dn
|
| 6111 |
|
|
|
| 6112 |
|
|
PROCESS
|
| 6113 |
|
|
BEGIN
|
| 6114 |
|
|
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0');
|
| 6115 |
|
|
IF (nclr = '0') THEN
|
| 6116 |
|
|
cmpup <= '0';
|
| 6117 |
|
|
cmpdn <= '0';
|
| 6118 |
|
|
ELSE
|
| 6119 |
|
|
cmpup <= rup;
|
| 6120 |
|
|
cmpdn <= rdn;
|
| 6121 |
|
|
END IF;
|
| 6122 |
|
|
END PROCESS;
|
| 6123 |
|
|
|
| 6124 |
|
|
-- other regisers
|
| 6125 |
|
|
|
| 6126 |
|
|
PROCESS
|
| 6127 |
|
|
BEGIN
|
| 6128 |
|
|
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1');
|
| 6129 |
|
|
IF (clr = '1') THEN
|
| 6130 |
|
|
current_state <= STRATIXIII_RTOCT_WAIT;
|
| 6131 |
|
|
switch_region <= '0';
|
| 6132 |
|
|
rt_sm_done <= '0';
|
| 6133 |
|
|
p_cnt <= "000";
|
| 6134 |
|
|
p_cnt_sub <= '0';
|
| 6135 |
|
|
n_cnt <= "000";
|
| 6136 |
|
|
n_cnt_sub <= '0';
|
| 6137 |
|
|
sel_rup_vref_h <= '0';
|
| 6138 |
|
|
sel_rup_vref_m <= '1';
|
| 6139 |
|
|
sel_rup_vref_l <= '0';
|
| 6140 |
|
|
sel_rdn_vref_h <= '0';
|
| 6141 |
|
|
sel_rdn_vref_m <= '1';
|
| 6142 |
|
|
sel_rdn_vref_l <= '0';
|
| 6143 |
|
|
ELSE
|
| 6144 |
|
|
current_state <= next_state;
|
| 6145 |
|
|
switch_region <= switch_region_d;
|
| 6146 |
|
|
rt_sm_done <= rt_sm_done_d;
|
| 6147 |
|
|
p_cnt <= p_cnt_d;
|
| 6148 |
|
|
p_cnt_sub <= p_cnt_sub_d;
|
| 6149 |
|
|
n_cnt <= n_cnt_d;
|
| 6150 |
|
|
n_cnt_sub <= n_cnt_sub_d;
|
| 6151 |
|
|
sel_rup_vref_h <= sel_rup_vref_h_d;
|
| 6152 |
|
|
sel_rup_vref_m <= sel_rup_vref_m_d;
|
| 6153 |
|
|
sel_rup_vref_l <= sel_rup_vref_l_d;
|
| 6154 |
|
|
sel_rdn_vref_h <= sel_rdn_vref_h_d;
|
| 6155 |
|
|
sel_rdn_vref_m <= sel_rdn_vref_m_d;
|
| 6156 |
|
|
sel_rdn_vref_l <= sel_rdn_vref_l_d;
|
| 6157 |
|
|
END IF;
|
| 6158 |
|
|
END PROCESS;
|
| 6159 |
|
|
|
| 6160 |
|
|
-- state machine
|
| 6161 |
|
|
|
| 6162 |
|
|
PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region)
|
| 6163 |
|
|
variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0);
|
| 6164 |
|
|
variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic;
|
| 6165 |
|
|
BEGIN
|
| 6166 |
|
|
p_cnt_d_var := p_cnt;
|
| 6167 |
|
|
n_cnt_d_var := n_cnt;
|
| 6168 |
|
|
p_cnt_sub_d_var := '0';
|
| 6169 |
|
|
n_cnt_sub_d_var := '0';
|
| 6170 |
|
|
CASE current_state IS
|
| 6171 |
|
|
WHEN STRATIXIII_RTOCT_WAIT =>
|
| 6172 |
|
|
IF (rtena = '0') THEN
|
| 6173 |
|
|
next_state <= STRATIXIII_RTOCT_WAIT;
|
| 6174 |
|
|
ELSE
|
| 6175 |
|
|
next_state <= RUP_VREF_M_RDN_VER_M;
|
| 6176 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6177 |
|
|
sel_rup_vref_m_d <= '1';
|
| 6178 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6179 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6180 |
|
|
sel_rdn_vref_m_d <= '1';
|
| 6181 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6182 |
|
|
END IF;
|
| 6183 |
|
|
WHEN RUP_VREF_M_RDN_VER_M =>
|
| 6184 |
|
|
IF (cmpup = '0' AND cmpdn = '0') THEN
|
| 6185 |
|
|
next_state <= RUP_VREF_L_RDN_VER_L;
|
| 6186 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6187 |
|
|
sel_rup_vref_m_d <= '0';
|
| 6188 |
|
|
sel_rup_vref_l_d <= '1';
|
| 6189 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6190 |
|
|
sel_rdn_vref_m_d <= '0';
|
| 6191 |
|
|
sel_rdn_vref_l_d <= '1';
|
| 6192 |
|
|
ELSE
|
| 6193 |
|
|
IF (cmpup = '1' AND cmpdn = '1') THEN
|
| 6194 |
|
|
next_state <= RUP_VREF_H_RDN_VER_H;
|
| 6195 |
|
|
sel_rup_vref_h_d <= '1';
|
| 6196 |
|
|
sel_rup_vref_m_d <= '0';
|
| 6197 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6198 |
|
|
sel_rdn_vref_h_d <= '1';
|
| 6199 |
|
|
sel_rdn_vref_m_d <= '0';
|
| 6200 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6201 |
|
|
ELSE
|
| 6202 |
|
|
IF (cmpup = '1' AND cmpdn = '0') THEN
|
| 6203 |
|
|
next_state <= STRATIXIII_RTOCT_INC_PN;
|
| 6204 |
|
|
p_cnt_d_var := p_cnt_d_var + 1;
|
| 6205 |
|
|
p_cnt_sub_d_var := '0';
|
| 6206 |
|
|
n_cnt_d_var := n_cnt_d_var + 1;
|
| 6207 |
|
|
n_cnt_sub_d_var := '0';
|
| 6208 |
|
|
ELSE
|
| 6209 |
|
|
IF (cmpup = '0' AND cmpdn = '1') THEN
|
| 6210 |
|
|
next_state <= STRATIXIII_RTOCT_DEC_PN;
|
| 6211 |
|
|
p_cnt_d_var := p_cnt_d_var + 1;
|
| 6212 |
|
|
p_cnt_sub_d_var := '1';
|
| 6213 |
|
|
n_cnt_d_var := n_cnt_d_var + 1;
|
| 6214 |
|
|
n_cnt_sub_d_var := '1';
|
| 6215 |
|
|
END IF;
|
| 6216 |
|
|
END IF;
|
| 6217 |
|
|
END IF;
|
| 6218 |
|
|
END IF;
|
| 6219 |
|
|
WHEN RUP_VREF_L_RDN_VER_L =>
|
| 6220 |
|
|
IF (cmpup = '1' AND cmpdn = '1') THEN
|
| 6221 |
|
|
next_state <= STRATIXIII_RTOCT_DONE;
|
| 6222 |
|
|
ELSE
|
| 6223 |
|
|
IF (cmpup = '0') THEN
|
| 6224 |
|
|
next_state <= STRATIXIII_RTOCT_DEC_N;
|
| 6225 |
|
|
n_cnt_d_var := n_cnt_d_var + 1;
|
| 6226 |
|
|
n_cnt_sub_d_var := '1';
|
| 6227 |
|
|
ELSE
|
| 6228 |
|
|
IF (cmpup = '1' AND cmpdn = '0') THEN
|
| 6229 |
|
|
next_state <= STRATIXIII_RTOCT_INC_P;
|
| 6230 |
|
|
p_cnt_d_var := p_cnt_d_var + 1;
|
| 6231 |
|
|
p_cnt_sub_d_var := '0';
|
| 6232 |
|
|
END IF;
|
| 6233 |
|
|
END IF;
|
| 6234 |
|
|
END IF;
|
| 6235 |
|
|
WHEN RUP_VREF_H_RDN_VER_H =>
|
| 6236 |
|
|
IF (cmpup = '0' AND cmpdn = '0') THEN
|
| 6237 |
|
|
next_state <= STRATIXIII_RTOCT_DONE;
|
| 6238 |
|
|
ELSE
|
| 6239 |
|
|
IF (cmpup = '1') THEN
|
| 6240 |
|
|
next_state <= STRATIXIII_RTOCT_INC_N;
|
| 6241 |
|
|
n_cnt_d_var := n_cnt_d_var + 1;
|
| 6242 |
|
|
n_cnt_sub_d_var := '0';
|
| 6243 |
|
|
ELSE
|
| 6244 |
|
|
IF (cmpup = '0' AND cmpdn = '1') THEN
|
| 6245 |
|
|
next_state <= STRATIXIII_RTOCT_DEC_P;
|
| 6246 |
|
|
p_cnt_d_var := p_cnt_d_var + 1;
|
| 6247 |
|
|
p_cnt_sub_d_var := '1';
|
| 6248 |
|
|
END IF;
|
| 6249 |
|
|
END IF;
|
| 6250 |
|
|
END IF;
|
| 6251 |
|
|
WHEN RUP_VREF_L_RDN_VER_H =>
|
| 6252 |
|
|
IF (cmpup = '1' AND cmpdn = '0') THEN
|
| 6253 |
|
|
next_state <= STRATIXIII_RTOCT_DONE;
|
| 6254 |
|
|
ELSE
|
| 6255 |
|
|
IF (cmpup = '1' AND switch_region = '1') THEN
|
| 6256 |
|
|
next_state <= STRATIXIII_RTOCT_DEC_P;
|
| 6257 |
|
|
p_cnt_d_var := p_cnt_d_var + 1;
|
| 6258 |
|
|
p_cnt_sub_d_var := '1';
|
| 6259 |
|
|
ELSE
|
| 6260 |
|
|
IF (cmpup = '0' AND switch_region = '1') THEN
|
| 6261 |
|
|
next_state <= STRATIXIII_RTOCT_DEC_N;
|
| 6262 |
|
|
n_cnt_d_var := n_cnt_d_var + 1;
|
| 6263 |
|
|
n_cnt_sub_d_var := '1';
|
| 6264 |
|
|
ELSE
|
| 6265 |
|
|
IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN
|
| 6266 |
|
|
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
|
| 6267 |
|
|
switch_region_d <= '1';
|
| 6268 |
|
|
END IF;
|
| 6269 |
|
|
END IF;
|
| 6270 |
|
|
END IF;
|
| 6271 |
|
|
END IF;
|
| 6272 |
|
|
WHEN RUP_VREF_H_RDN_VER_L =>
|
| 6273 |
|
|
IF (cmpup = '0' AND cmpdn = '1') THEN
|
| 6274 |
|
|
next_state <= STRATIXIII_RTOCT_DONE;
|
| 6275 |
|
|
ELSE
|
| 6276 |
|
|
IF (cmpup = '1' AND switch_region = '1') THEN
|
| 6277 |
|
|
next_state <= STRATIXIII_RTOCT_INC_N;
|
| 6278 |
|
|
n_cnt_d_var := n_cnt_d_var + 1;
|
| 6279 |
|
|
n_cnt_sub_d_var := '0';
|
| 6280 |
|
|
ELSE
|
| 6281 |
|
|
IF (cmpup = '0' AND switch_region = '1') THEN
|
| 6282 |
|
|
next_state <= STRATIXIII_RTOCT_INC_P;
|
| 6283 |
|
|
p_cnt_d_var := p_cnt_d_var + 1;
|
| 6284 |
|
|
p_cnt_sub_d_var := '0';
|
| 6285 |
|
|
ELSE
|
| 6286 |
|
|
IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN
|
| 6287 |
|
|
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
|
| 6288 |
|
|
switch_region_d <= '1';
|
| 6289 |
|
|
END IF;
|
| 6290 |
|
|
END IF;
|
| 6291 |
|
|
END IF;
|
| 6292 |
|
|
END IF;
|
| 6293 |
|
|
WHEN STRATIXIII_RTOCT_INC_PN =>
|
| 6294 |
|
|
IF (cmpup = '1' AND cmpdn = '0') THEN
|
| 6295 |
|
|
next_state <= STRATIXIII_RTOCT_INC_PN;
|
| 6296 |
|
|
p_cnt_d_var := p_cnt_d_var + 1;
|
| 6297 |
|
|
p_cnt_sub_d_var := '0';
|
| 6298 |
|
|
n_cnt_d_var := n_cnt_d_var + 1;
|
| 6299 |
|
|
n_cnt_sub_d_var := '0';
|
| 6300 |
|
|
ELSE
|
| 6301 |
|
|
IF (cmpup = '0' AND cmpdn = '0') THEN
|
| 6302 |
|
|
next_state <= RUP_VREF_L_RDN_VER_L;
|
| 6303 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6304 |
|
|
sel_rup_vref_m_d <= '0';
|
| 6305 |
|
|
sel_rup_vref_l_d <= '1';
|
| 6306 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6307 |
|
|
sel_rdn_vref_m_d <= '0';
|
| 6308 |
|
|
sel_rdn_vref_l_d <= '1';
|
| 6309 |
|
|
ELSE
|
| 6310 |
|
|
IF (cmpup = '1' AND cmpdn = '1') THEN
|
| 6311 |
|
|
next_state <= RUP_VREF_H_RDN_VER_H;
|
| 6312 |
|
|
sel_rup_vref_h_d <= '1';
|
| 6313 |
|
|
sel_rup_vref_m_d <= '0';
|
| 6314 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6315 |
|
|
sel_rdn_vref_h_d <= '1';
|
| 6316 |
|
|
sel_rdn_vref_m_d <= '0';
|
| 6317 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6318 |
|
|
ELSE
|
| 6319 |
|
|
IF (cmpup = '0' AND cmpdn = '1') THEN
|
| 6320 |
|
|
next_state <= RUP_VREF_L_RDN_VER_H;
|
| 6321 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6322 |
|
|
sel_rup_vref_m_d <= '0';
|
| 6323 |
|
|
sel_rup_vref_l_d <= '1';
|
| 6324 |
|
|
sel_rdn_vref_h_d <= '1';
|
| 6325 |
|
|
sel_rdn_vref_m_d <= '0';
|
| 6326 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6327 |
|
|
END IF;
|
| 6328 |
|
|
END IF;
|
| 6329 |
|
|
END IF;
|
| 6330 |
|
|
END IF;
|
| 6331 |
|
|
WHEN STRATIXIII_RTOCT_DEC_PN =>
|
| 6332 |
|
|
IF (cmpup = '0' AND cmpdn = '1') THEN
|
| 6333 |
|
|
next_state <= STRATIXIII_RTOCT_DEC_PN;
|
| 6334 |
|
|
p_cnt_d_var := p_cnt_d_var + 1;
|
| 6335 |
|
|
p_cnt_sub_d_var := '1';
|
| 6336 |
|
|
n_cnt_d_var := n_cnt_d_var + 1;
|
| 6337 |
|
|
n_cnt_sub_d_var := '1';
|
| 6338 |
|
|
ELSE
|
| 6339 |
|
|
IF (cmpup = '0' AND cmpdn = '0') THEN
|
| 6340 |
|
|
next_state <= RUP_VREF_L_RDN_VER_L;
|
| 6341 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6342 |
|
|
sel_rup_vref_m_d <= '0';
|
| 6343 |
|
|
sel_rup_vref_l_d <= '1';
|
| 6344 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6345 |
|
|
sel_rdn_vref_m_d <= '0';
|
| 6346 |
|
|
sel_rdn_vref_l_d <= '1';
|
| 6347 |
|
|
ELSE
|
| 6348 |
|
|
IF (cmpup = '1' AND cmpdn = '1') THEN
|
| 6349 |
|
|
next_state <= RUP_VREF_H_RDN_VER_H;
|
| 6350 |
|
|
sel_rup_vref_h_d <= '1';
|
| 6351 |
|
|
sel_rup_vref_m_d <= '0';
|
| 6352 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6353 |
|
|
sel_rdn_vref_h_d <= '1';
|
| 6354 |
|
|
sel_rdn_vref_m_d <= '0';
|
| 6355 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6356 |
|
|
ELSE
|
| 6357 |
|
|
IF (cmpup = '1' AND cmpdn = '0') THEN
|
| 6358 |
|
|
next_state <= RUP_VREF_H_RDN_VER_L;
|
| 6359 |
|
|
sel_rup_vref_h_d <= '1';
|
| 6360 |
|
|
sel_rup_vref_m_d <= '0';
|
| 6361 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6362 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6363 |
|
|
sel_rdn_vref_m_d <= '0';
|
| 6364 |
|
|
sel_rdn_vref_l_d <= '1';
|
| 6365 |
|
|
END IF;
|
| 6366 |
|
|
END IF;
|
| 6367 |
|
|
END IF;
|
| 6368 |
|
|
END IF;
|
| 6369 |
|
|
----------------- same action begin
|
| 6370 |
|
|
WHEN STRATIXIII_RTOCT_INC_P =>
|
| 6371 |
|
|
IF (switch_region = '1') THEN
|
| 6372 |
|
|
next_state <= STRATIXIII_RTOCT_DONE;
|
| 6373 |
|
|
ELSE
|
| 6374 |
|
|
IF (switch_region = '0') THEN
|
| 6375 |
|
|
next_state <= RUP_VREF_M_RDN_VER_M;
|
| 6376 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6377 |
|
|
sel_rup_vref_m_d <= '1';
|
| 6378 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6379 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6380 |
|
|
sel_rdn_vref_m_d <= '1';
|
| 6381 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6382 |
|
|
END IF;
|
| 6383 |
|
|
END IF;
|
| 6384 |
|
|
WHEN STRATIXIII_RTOCT_DEC_P =>
|
| 6385 |
|
|
IF (switch_region = '1') THEN
|
| 6386 |
|
|
next_state <= STRATIXIII_RTOCT_DONE;
|
| 6387 |
|
|
ELSE
|
| 6388 |
|
|
IF (switch_region = '0') THEN
|
| 6389 |
|
|
next_state <= RUP_VREF_M_RDN_VER_M;
|
| 6390 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6391 |
|
|
sel_rup_vref_m_d <= '1';
|
| 6392 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6393 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6394 |
|
|
sel_rdn_vref_m_d <= '1';
|
| 6395 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6396 |
|
|
END IF;
|
| 6397 |
|
|
END IF;
|
| 6398 |
|
|
WHEN STRATIXIII_RTOCT_INC_N =>
|
| 6399 |
|
|
IF (switch_region = '1') THEN
|
| 6400 |
|
|
next_state <= STRATIXIII_RTOCT_DONE;
|
| 6401 |
|
|
ELSE
|
| 6402 |
|
|
IF (switch_region = '0') THEN
|
| 6403 |
|
|
next_state <= RUP_VREF_M_RDN_VER_M;
|
| 6404 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6405 |
|
|
sel_rup_vref_m_d <= '1';
|
| 6406 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6407 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6408 |
|
|
sel_rdn_vref_m_d <= '1';
|
| 6409 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6410 |
|
|
END IF;
|
| 6411 |
|
|
END IF;
|
| 6412 |
|
|
WHEN STRATIXIII_RTOCT_DEC_N =>
|
| 6413 |
|
|
IF (switch_region = '1') THEN
|
| 6414 |
|
|
next_state <= STRATIXIII_RTOCT_DONE;
|
| 6415 |
|
|
ELSE
|
| 6416 |
|
|
IF (switch_region = '0') THEN
|
| 6417 |
|
|
next_state <= RUP_VREF_M_RDN_VER_M;
|
| 6418 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6419 |
|
|
sel_rup_vref_m_d <= '1';
|
| 6420 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6421 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6422 |
|
|
sel_rdn_vref_m_d <= '1';
|
| 6423 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6424 |
|
|
END IF;
|
| 6425 |
|
|
END IF;
|
| 6426 |
|
|
----------------- same action end
|
| 6427 |
|
|
WHEN STRATIXIII_RTOCT_SWITCH_REG =>
|
| 6428 |
|
|
next_state <= RUP_VREF_M_RDN_VER_M;
|
| 6429 |
|
|
sel_rup_vref_h_d <= '0';
|
| 6430 |
|
|
sel_rup_vref_m_d <= '1';
|
| 6431 |
|
|
sel_rup_vref_l_d <= '0';
|
| 6432 |
|
|
sel_rdn_vref_h_d <= '0';
|
| 6433 |
|
|
sel_rdn_vref_m_d <= '1';
|
| 6434 |
|
|
sel_rdn_vref_l_d <= '0';
|
| 6435 |
|
|
WHEN STRATIXIII_RTOCT_DONE =>
|
| 6436 |
|
|
next_state <= STRATIXIII_RTOCT_DONE;
|
| 6437 |
|
|
rt_sm_done_d <= '1';
|
| 6438 |
|
|
WHEN OTHERS =>
|
| 6439 |
|
|
next_state <= STRATIXIII_RTOCT_WAIT;
|
| 6440 |
|
|
|
| 6441 |
|
|
END CASE;
|
| 6442 |
|
|
-- case(current_state)
|
| 6443 |
|
|
|
| 6444 |
|
|
-- schedule the outputs
|
| 6445 |
|
|
p_cnt_d <= p_cnt_d_var;
|
| 6446 |
|
|
n_cnt_d <= n_cnt_d_var;
|
| 6447 |
|
|
p_cnt_sub_d <= p_cnt_sub_d_var;
|
| 6448 |
|
|
n_cnt_sub_d <= n_cnt_sub_d_var;
|
| 6449 |
|
|
|
| 6450 |
|
|
END PROCESS;
|
| 6451 |
|
|
|
| 6452 |
|
|
END stratixiii_rt_sm_rtl;
|
| 6453 |
|
|
|
| 6454 |
|
|
-------------------------------------------------------------------------------
|
| 6455 |
|
|
-- Module Name: stratixiii_termination_aux_clock_div
|
| 6456 |
|
|
-- Description: auxilary clock divider module
|
| 6457 |
|
|
-------------------------------------------------------------------------------
|
| 6458 |
|
|
|
| 6459 |
|
|
LIBRARY IEEE;
|
| 6460 |
|
|
USE IEEE.std_logic_1164.ALL;
|
| 6461 |
|
|
|
| 6462 |
|
|
ENTITY stratixiii_termination_aux_clock_div IS
|
| 6463 |
|
|
GENERIC (
|
| 6464 |
|
|
clk_divide_by : INTEGER := 1;
|
| 6465 |
|
|
extra_latency : INTEGER := 0
|
| 6466 |
|
|
);
|
| 6467 |
|
|
PORT (
|
| 6468 |
|
|
clk : IN STD_LOGIC;
|
| 6469 |
|
|
reset : IN STD_LOGIC := '0';
|
| 6470 |
|
|
clkout : OUT STD_LOGIC
|
| 6471 |
|
|
);
|
| 6472 |
|
|
END stratixiii_termination_aux_clock_div;
|
| 6473 |
|
|
|
| 6474 |
|
|
ARCHITECTURE oct_clock_div_arch OF stratixiii_termination_aux_clock_div IS
|
| 6475 |
|
|
SIGNAL clk_edges : INTEGER := -1;
|
| 6476 |
|
|
SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0)
|
| 6477 |
|
|
:= (OTHERS => '0');
|
| 6478 |
|
|
|
| 6479 |
|
|
BEGIN
|
| 6480 |
|
|
PROCESS(clk,reset)
|
| 6481 |
|
|
VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0');
|
| 6482 |
|
|
VARIABLE m : INTEGER := 0;
|
| 6483 |
|
|
VARIABLE running_clk_edge : INTEGER := -1;
|
| 6484 |
|
|
BEGIN
|
| 6485 |
|
|
running_clk_edge := clk_edges;
|
| 6486 |
|
|
IF (reset = '1') THEN
|
| 6487 |
|
|
clk_edges <= -1;
|
| 6488 |
|
|
m := 0;
|
| 6489 |
|
|
div_n := (OTHERS => '0');
|
| 6490 |
|
|
ELSE
|
| 6491 |
|
|
IF (clk'EVENT) THEN
|
| 6492 |
|
|
IF (running_clk_edge = -1) THEN
|
| 6493 |
|
|
m := 0;
|
| 6494 |
|
|
div_n(0) := clk;
|
| 6495 |
|
|
IF (clk = '1') THEN running_clk_edge := 0; END IF;
|
| 6496 |
|
|
ELSIF (running_clk_edge mod clk_divide_by = 0) THEN
|
| 6497 |
|
|
div_n(0) := NOT div_n(0);
|
| 6498 |
|
|
END IF;
|
| 6499 |
|
|
IF (running_clk_edge >= 0 OR clk = '1') THEN
|
| 6500 |
|
|
clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by);
|
| 6501 |
|
|
END IF;
|
| 6502 |
|
|
END IF;
|
| 6503 |
|
|
|
| 6504 |
|
|
END IF;
|
| 6505 |
|
|
m := 0;
|
| 6506 |
|
|
div_n_register(m) <= div_n(m);
|
| 6507 |
|
|
WHILE (m < 2 * extra_latency) LOOP
|
| 6508 |
|
|
div_n_register(m+1) <= div_n_register(m);
|
| 6509 |
|
|
m := m + 1;
|
| 6510 |
|
|
END LOOP;
|
| 6511 |
|
|
|
| 6512 |
|
|
END PROCESS;
|
| 6513 |
|
|
clkout <= div_n_register(2 * extra_latency);
|
| 6514 |
|
|
|
| 6515 |
|
|
END oct_clock_div_arch;
|
| 6516 |
|
|
|
| 6517 |
|
|
-------------------------------------------------------------------------------
|
| 6518 |
|
|
--
|
| 6519 |
|
|
-- Module Name : stratixiii_termination
|
| 6520 |
|
|
--
|
| 6521 |
|
|
-- Description : Stratix III Termination Atom
|
| 6522 |
|
|
-- Verilog simulation model
|
| 6523 |
|
|
--
|
| 6524 |
|
|
-------------------------------------------------------------------------------
|
| 6525 |
|
|
|
| 6526 |
|
|
LIBRARY IEEE;
|
| 6527 |
|
|
USE IEEE.std_logic_1164.ALL;
|
| 6528 |
|
|
use IEEE.std_logic_arith.all;
|
| 6529 |
|
|
use IEEE.std_logic_unsigned.all;
|
| 6530 |
|
|
USE IEEE.VITAL_Timing.ALL;
|
| 6531 |
|
|
USE IEEE.VITAL_Primitives.ALL;
|
| 6532 |
|
|
use work.stratixiii_atom_pack.all;
|
| 6533 |
|
|
|
| 6534 |
|
|
USE WORK.stratixiii_termination_aux_clock_div;
|
| 6535 |
|
|
USE WORK.stratixiii_rt_sm;
|
| 6536 |
|
|
|
| 6537 |
|
|
ENTITY stratixiii_termination IS
|
| 6538 |
|
|
GENERIC (
|
| 6539 |
|
|
runtime_control : STRING := "false";
|
| 6540 |
|
|
allow_serial_data_from_core : STRING := "false";
|
| 6541 |
|
|
power_down : STRING := "true";
|
| 6542 |
|
|
enable_parallel_termination : STRING := "false";
|
| 6543 |
|
|
test_mode : STRING := "false";
|
| 6544 |
|
|
enable_calclk_divider : STRING := "false"; -- replaced by below
|
| 6545 |
|
|
clock_divider_enable : STRING := "false";
|
| 6546 |
|
|
enable_pwrupmode_enser_for_usrmode : STRING := "false";
|
| 6547 |
|
|
bypass_enser_logic : STRING := "false";
|
| 6548 |
|
|
bypass_rt_calclk : STRING := "false";
|
| 6549 |
|
|
enable_rt_scan_mode : STRING := "false";
|
| 6550 |
|
|
enable_loopback : STRING := "false";
|
| 6551 |
|
|
|
| 6552 |
|
|
force_rtcalen_for_pllbiasen : STRING := "false";
|
| 6553 |
|
|
enable_rt_sm_loopback : STRING := "false";
|
| 6554 |
|
|
select_vrefl_values : integer := 0;
|
| 6555 |
|
|
select_vrefh_values : integer := 0;
|
| 6556 |
|
|
divide_intosc_by : integer := 2;
|
| 6557 |
|
|
use_usrmode_clear_for_configmode : STRING := "false";
|
| 6558 |
|
|
|
| 6559 |
|
|
tipd_rup : VitalDelayType01 := DefpropDelay01;
|
| 6560 |
|
|
tipd_rdn : VitalDelayType01 := DefpropDelay01;
|
| 6561 |
|
|
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
|
| 6562 |
|
|
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
|
| 6563 |
|
|
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
|
| 6564 |
|
|
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
|
| 6565 |
|
|
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
|
| 6566 |
|
|
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
|
| 6567 |
|
|
lpm_type : STRING := "stratixiii_termination");
|
| 6568 |
|
|
PORT (
|
| 6569 |
|
|
rup : IN std_logic := '0';
|
| 6570 |
|
|
rdn : IN std_logic := '0';
|
| 6571 |
|
|
terminationclock : IN std_logic := '0';
|
| 6572 |
|
|
terminationclear : IN std_logic := '0';
|
| 6573 |
|
|
terminationenable : IN std_logic := '1';
|
| 6574 |
|
|
serializerenable : IN std_logic := '0';
|
| 6575 |
|
|
terminationcontrolin : IN std_logic := '0';
|
| 6576 |
|
|
scanin : IN std_logic := '0';
|
| 6577 |
|
|
scanen : IN std_logic := '0';
|
| 6578 |
|
|
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
|
| 6579 |
|
|
devclrn : IN std_logic := '1';
|
| 6580 |
|
|
devpor : IN std_logic := '1';
|
| 6581 |
|
|
incrup : OUT std_logic;
|
| 6582 |
|
|
incrdn : OUT std_logic;
|
| 6583 |
|
|
serializerenableout : OUT std_logic;
|
| 6584 |
|
|
terminationcontrol : OUT std_logic;
|
| 6585 |
|
|
terminationcontrolprobe : OUT std_logic;
|
| 6586 |
|
|
scanout : OUT std_logic;
|
| 6587 |
|
|
shiftregisterprobe : OUT std_logic);
|
| 6588 |
|
|
END stratixiii_termination;
|
| 6589 |
|
|
|
| 6590 |
|
|
ARCHITECTURE stratixiii_oct_arch OF stratixiii_termination IS
|
| 6591 |
|
|
|
| 6592 |
|
|
COMPONENT stratixiii_termination_aux_clock_div
|
| 6593 |
|
|
GENERIC (
|
| 6594 |
|
|
clk_divide_by : INTEGER := 1;
|
| 6595 |
|
|
extra_latency : INTEGER := 0
|
| 6596 |
|
|
);
|
| 6597 |
|
|
PORT (
|
| 6598 |
|
|
clk : IN STD_LOGIC;
|
| 6599 |
|
|
reset : IN STD_LOGIC := '0';
|
| 6600 |
|
|
clkout : OUT STD_LOGIC
|
| 6601 |
|
|
);
|
| 6602 |
|
|
END COMPONENT;
|
| 6603 |
|
|
|
| 6604 |
|
|
COMPONENT stratixiii_rt_sm
|
| 6605 |
|
|
PORT (
|
| 6606 |
|
|
rup : IN std_logic;
|
| 6607 |
|
|
rdn : IN std_logic;
|
| 6608 |
|
|
clk : IN std_logic;
|
| 6609 |
|
|
clken : IN std_logic;
|
| 6610 |
|
|
clr : IN std_logic;
|
| 6611 |
|
|
rtena : IN std_logic;
|
| 6612 |
|
|
rscaldone : IN std_logic;
|
| 6613 |
|
|
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
|
| 6614 |
|
|
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
|
| 6615 |
|
|
caldone : OUT std_logic;
|
| 6616 |
|
|
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
|
| 6617 |
|
|
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)
|
| 6618 |
|
|
);
|
| 6619 |
|
|
END COMPONENT;
|
| 6620 |
|
|
|
| 6621 |
|
|
-- HW outputs
|
| 6622 |
|
|
SIGNAL compout_rup_core : std_logic;
|
| 6623 |
|
|
SIGNAL compout_rdn_core : std_logic;
|
| 6624 |
|
|
SIGNAL ser_data_io : std_logic;
|
| 6625 |
|
|
SIGNAL ser_data_core : std_logic;
|
| 6626 |
|
|
-- HW inputs
|
| 6627 |
|
|
SIGNAL usr_clk : std_logic;
|
| 6628 |
|
|
SIGNAL cal_clk : std_logic;
|
| 6629 |
|
|
SIGNAL rscal_clk : std_logic;
|
| 6630 |
|
|
SIGNAL cal_clken : std_logic;
|
| 6631 |
|
|
SIGNAL cal_nclr : std_logic;
|
| 6632 |
|
|
-- legality check on enser
|
| 6633 |
|
|
SIGNAL enser_checked : std_logic := '0';
|
| 6634 |
|
|
-- Shift Register
|
| 6635 |
|
|
SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
|
| 6636 |
|
|
SIGNAL sreg_bit_out_tmp0 : std_logic := '0';
|
| 6637 |
|
|
SIGNAL sreg_vshift_bit_tmp : std_logic := '0';
|
| 6638 |
|
|
SIGNAL sreg_vshift_bit_out : std_logic := '0';
|
| 6639 |
|
|
SIGNAL sreg_rscaldone_prev : std_logic := '0';
|
| 6640 |
|
|
SIGNAL sreg_rscaldone_prev1 : std_logic := '0';
|
| 6641 |
|
|
SIGNAL sregn_rscaldone_out : std_logic := '0';
|
| 6642 |
|
|
SIGNAL sreg_bit6_prev : std_logic := '1';
|
| 6643 |
|
|
-- nreg before SA-ADC
|
| 6644 |
|
|
SIGNAL regn_rup_in : std_logic;
|
| 6645 |
|
|
SIGNAL regn_rdn_in : std_logic;
|
| 6646 |
|
|
SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
|
| 6647 |
|
|
SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
|
| 6648 |
|
|
-- SA-ADC
|
| 6649 |
|
|
SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS
|
| 6650 |
|
|
SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS
|
| 6651 |
|
|
SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0);
|
| 6652 |
|
|
SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0);
|
| 6653 |
|
|
-- ENSER
|
| 6654 |
|
|
SIGNAL enser_out : std_logic;
|
| 6655 |
|
|
SIGNAL enser_gen_out : std_logic;
|
| 6656 |
|
|
SIGNAL enser_cnt : INTEGER := 0;
|
| 6657 |
|
|
-- RT State Machine
|
| 6658 |
|
|
SIGNAL rtsm_rup_in : std_logic;
|
| 6659 |
|
|
SIGNAL rtsm_rdn_in : std_logic;
|
| 6660 |
|
|
SIGNAL rtsm_rtena_in : std_logic;
|
| 6661 |
|
|
SIGNAL rtsm_rscaldone_in : std_logic;
|
| 6662 |
|
|
SIGNAL rtsm_caldone_out : std_logic;
|
| 6663 |
|
|
SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
|
| 6664 |
|
|
SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
|
| 6665 |
|
|
SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
|
| 6666 |
|
|
SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
|
| 6667 |
|
|
-- RT Adder/Sub
|
| 6668 |
|
|
SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
|
| 6669 |
|
|
SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
|
| 6670 |
|
|
SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
|
| 6671 |
|
|
SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
|
| 6672 |
|
|
SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0);
|
| 6673 |
|
|
SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0);
|
| 6674 |
|
|
SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
|
| 6675 |
|
|
SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
|
| 6676 |
|
|
-- P2S
|
| 6677 |
|
|
SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
|
| 6678 |
|
|
SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
|
| 6679 |
|
|
SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0);
|
| 6680 |
|
|
SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0);
|
| 6681 |
|
|
SIGNAL p2s_enser_in : std_logic;
|
| 6682 |
|
|
SIGNAL p2s_clk_in : std_logic;
|
| 6683 |
|
|
SIGNAL p2s_ser_data_out : std_logic;
|
| 6684 |
|
|
SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
|
| 6685 |
|
|
SIGNAL p2s_serial_reg : std_logic := '0';
|
| 6686 |
|
|
SIGNAL p2s_index : integer := 27;
|
| 6687 |
|
|
|
| 6688 |
|
|
-- used to set SA outputs
|
| 6689 |
|
|
SIGNAL temp_xhdl10 : std_logic;
|
| 6690 |
|
|
SIGNAL temp_xhdl12 : std_logic;
|
| 6691 |
|
|
SIGNAL temp_xhdl14 : std_logic;
|
| 6692 |
|
|
SIGNAL temp_xhdl16 : std_logic;
|
| 6693 |
|
|
SIGNAL temp_xhdl18 : std_logic;
|
| 6694 |
|
|
SIGNAL temp_xhdl20 : std_logic;
|
| 6695 |
|
|
SIGNAL temp_xhdl22 : std_logic;
|
| 6696 |
|
|
SIGNAL temp_xhdl24 : std_logic;
|
| 6697 |
|
|
SIGNAL temp_xhdl26 : std_logic;
|
| 6698 |
|
|
SIGNAL temp_xhdl28 : std_logic;
|
| 6699 |
|
|
SIGNAL temp_xhdl30 : std_logic;
|
| 6700 |
|
|
SIGNAL temp_xhdl32 : std_logic;
|
| 6701 |
|
|
SIGNAL temp_xhdl34 : std_logic;
|
| 6702 |
|
|
SIGNAL temp_xhdl36 : std_logic;
|
| 6703 |
|
|
|
| 6704 |
|
|
SIGNAL MY_GND : std_logic := '0';
|
| 6705 |
|
|
|
| 6706 |
|
|
-- timing
|
| 6707 |
|
|
SIGNAL rup_ipd : std_logic;
|
| 6708 |
|
|
SIGNAL rdn_ipd : std_logic;
|
| 6709 |
|
|
SIGNAL terminationclock_ipd : std_logic;
|
| 6710 |
|
|
SIGNAL terminationclear_ipd : std_logic;
|
| 6711 |
|
|
SIGNAL terminationenable_ipd : std_logic;
|
| 6712 |
|
|
SIGNAL serializerenable_ipd : std_logic;
|
| 6713 |
|
|
SIGNAL terminationcontrolin_ipd : std_logic;
|
| 6714 |
|
|
SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0);
|
| 6715 |
|
|
|
| 6716 |
|
|
BEGIN
|
| 6717 |
|
|
-- primary outputs
|
| 6718 |
|
|
incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core;
|
| 6719 |
|
|
incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core;
|
| 6720 |
|
|
terminationcontrol <= ser_data_io;
|
| 6721 |
|
|
terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core;
|
| 6722 |
|
|
shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out;
|
| 6723 |
|
|
serializerenableout <= serializerenable;
|
| 6724 |
|
|
|
| 6725 |
|
|
compout_rup_core <= rup ;
|
| 6726 |
|
|
compout_rdn_core <= rdn ;
|
| 6727 |
|
|
ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out;
|
| 6728 |
|
|
ser_data_core <= p2s_ser_data_out ;
|
| 6729 |
|
|
|
| 6730 |
|
|
-- primary inputs
|
| 6731 |
|
|
usr_clk <= terminationclock ;
|
| 6732 |
|
|
cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0';
|
| 6733 |
|
|
cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0';
|
| 6734 |
|
|
|
| 6735 |
|
|
-- divide by 100 clock
|
| 6736 |
|
|
m_gen_calclk : stratixiii_termination_aux_clock_div
|
| 6737 |
|
|
GENERIC MAP (
|
| 6738 |
|
|
clk_divide_by => 100,
|
| 6739 |
|
|
extra_latency => 0)
|
| 6740 |
|
|
PORT MAP (
|
| 6741 |
|
|
clk => usr_clk,
|
| 6742 |
|
|
reset => MY_GND,
|
| 6743 |
|
|
clkout => cal_clk);
|
| 6744 |
|
|
|
| 6745 |
|
|
rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ;
|
| 6746 |
|
|
|
| 6747 |
|
|
-- legality check on enser
|
| 6748 |
|
|
|
| 6749 |
|
|
PROCESS
|
| 6750 |
|
|
BEGIN
|
| 6751 |
|
|
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
|
| 6752 |
|
|
IF (serializerenable = '1' AND cal_clken = '0') THEN
|
| 6753 |
|
|
IF (otherserializerenable(0) = '1' OR
|
| 6754 |
|
|
otherserializerenable(1) = '1' OR
|
| 6755 |
|
|
otherserializerenable(2) = '1' OR
|
| 6756 |
|
|
otherserializerenable(3) = '1' OR
|
| 6757 |
|
|
otherserializerenable(4) = '1' OR
|
| 6758 |
|
|
otherserializerenable(5) = '1' OR
|
| 6759 |
|
|
otherserializerenable(6) = '1' OR
|
| 6760 |
|
|
otherserializerenable(7) = '1' OR
|
| 6761 |
|
|
otherserializerenable(8) = '1') THEN
|
| 6762 |
|
|
IF (enser_checked = '0') THEN
|
| 6763 |
|
|
assert false
|
| 6764 |
|
|
report "serializizerable and some bits of otherserializerenable are asserted at data transfer time"
|
| 6765 |
|
|
severity warning;
|
| 6766 |
|
|
enser_checked <= '1';
|
| 6767 |
|
|
END IF;
|
| 6768 |
|
|
ELSE
|
| 6769 |
|
|
enser_checked <= '0'; -- for another check
|
| 6770 |
|
|
END IF;
|
| 6771 |
|
|
ELSE
|
| 6772 |
|
|
enser_checked <= '0'; -- for another check
|
| 6773 |
|
|
END IF;
|
| 6774 |
|
|
END PROCESS;
|
| 6775 |
|
|
|
| 6776 |
|
|
-- SHIFT regiter
|
| 6777 |
|
|
|
| 6778 |
|
|
PROCESS
|
| 6779 |
|
|
BEGIN
|
| 6780 |
|
|
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
|
| 6781 |
|
|
IF (cal_nclr = '1') THEN
|
| 6782 |
|
|
sreg_bit6_prev <= '1';
|
| 6783 |
|
|
sreg_bit_out <= "0000000";
|
| 6784 |
|
|
sreg_vshift_bit_out <= '0';
|
| 6785 |
|
|
sreg_vshift_bit_tmp <= '0';
|
| 6786 |
|
|
sreg_bit_out_tmp0 <= '0';
|
| 6787 |
|
|
sreg_rscaldone_prev <= '0';
|
| 6788 |
|
|
sreg_rscaldone_prev1 <= '0';
|
| 6789 |
|
|
ELSE
|
| 6790 |
|
|
IF (cal_clken = '1') THEN
|
| 6791 |
|
|
sreg_bit_out(6) <= sreg_bit6_prev;
|
| 6792 |
|
|
sreg_bit_out(5) <= sreg_bit_out(6);
|
| 6793 |
|
|
sreg_bit_out(4) <= sreg_bit_out(5);
|
| 6794 |
|
|
sreg_bit_out(3) <= sreg_bit_out(4);
|
| 6795 |
|
|
sreg_bit_out(2) <= sreg_bit_out(3);
|
| 6796 |
|
|
sreg_bit_out(1) <= sreg_bit_out(2);
|
| 6797 |
|
|
sreg_bit_out_tmp0 <= sreg_bit_out(1);
|
| 6798 |
|
|
sreg_vshift_bit_tmp <= sreg_bit_out_tmp0;
|
| 6799 |
|
|
sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp;
|
| 6800 |
|
|
sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp;
|
| 6801 |
|
|
sreg_bit6_prev <= '0';
|
| 6802 |
|
|
END IF;
|
| 6803 |
|
|
END IF;
|
| 6804 |
|
|
|
| 6805 |
|
|
-- might falling outside of 10 cycles
|
| 6806 |
|
|
IF (sreg_vshift_bit_tmp = '1') THEN
|
| 6807 |
|
|
sreg_rscaldone_prev <= '1';
|
| 6808 |
|
|
END IF;
|
| 6809 |
|
|
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
|
| 6810 |
|
|
|
| 6811 |
|
|
END PROCESS;
|
| 6812 |
|
|
|
| 6813 |
|
|
PROCESS
|
| 6814 |
|
|
BEGIN
|
| 6815 |
|
|
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1');
|
| 6816 |
|
|
IF (cal_nclr = '1') THEN
|
| 6817 |
|
|
sregn_rscaldone_out <= '0';
|
| 6818 |
|
|
ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles
|
| 6819 |
|
|
IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN
|
| 6820 |
|
|
sregn_rscaldone_out <= '1';
|
| 6821 |
|
|
END IF;
|
| 6822 |
|
|
END IF;
|
| 6823 |
|
|
END PROCESS;
|
| 6824 |
|
|
|
| 6825 |
|
|
-- nreg and SA-ADC:
|
| 6826 |
|
|
--
|
| 6827 |
|
|
-- RDN_vol < ref_voltage < RUP_voltage
|
| 6828 |
|
|
-- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
|
| 6829 |
|
|
-- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
|
| 6830 |
|
|
-- RDN=GND so voltage compare out for RDN = 0
|
| 6831 |
|
|
regn_rup_in <= rup ;
|
| 6832 |
|
|
regn_rdn_in <= rdn ;
|
| 6833 |
|
|
|
| 6834 |
|
|
PROCESS
|
| 6835 |
|
|
BEGIN
|
| 6836 |
|
|
WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0');
|
| 6837 |
|
|
IF (cal_nclr = '1') THEN
|
| 6838 |
|
|
regn_compout_rup <= "0000000";
|
| 6839 |
|
|
regn_compout_rdn <= "0000000";
|
| 6840 |
|
|
ELSE
|
| 6841 |
|
|
-- rup
|
| 6842 |
|
|
IF (sreg_bit_out(0) = '1') THEN
|
| 6843 |
|
|
regn_compout_rup(0) <= regn_rup_in;
|
| 6844 |
|
|
END IF;
|
| 6845 |
|
|
IF (sreg_bit_out(1) = '1') THEN
|
| 6846 |
|
|
regn_compout_rup(1) <= regn_rup_in;
|
| 6847 |
|
|
END IF;
|
| 6848 |
|
|
IF (sreg_bit_out(2) = '1') THEN
|
| 6849 |
|
|
regn_compout_rup(2) <= regn_rup_in;
|
| 6850 |
|
|
END IF;
|
| 6851 |
|
|
IF (sreg_bit_out(3) = '1') THEN
|
| 6852 |
|
|
regn_compout_rup(3) <= regn_rup_in;
|
| 6853 |
|
|
END IF;
|
| 6854 |
|
|
IF (sreg_bit_out(4) = '1') THEN
|
| 6855 |
|
|
regn_compout_rup(4) <= regn_rup_in;
|
| 6856 |
|
|
END IF;
|
| 6857 |
|
|
IF (sreg_bit_out(5) = '1') THEN
|
| 6858 |
|
|
regn_compout_rup(5) <= regn_rup_in;
|
| 6859 |
|
|
END IF;
|
| 6860 |
|
|
IF (sreg_bit_out(6) = '1') THEN
|
| 6861 |
|
|
regn_compout_rup(6) <= regn_rup_in;
|
| 6862 |
|
|
END IF;
|
| 6863 |
|
|
-- rdn
|
| 6864 |
|
|
IF (sreg_bit_out(0) = '1') THEN
|
| 6865 |
|
|
regn_compout_rdn(0) <= regn_rdn_in;
|
| 6866 |
|
|
END IF;
|
| 6867 |
|
|
IF (sreg_bit_out(1) = '1') THEN
|
| 6868 |
|
|
regn_compout_rdn(1) <= regn_rdn_in;
|
| 6869 |
|
|
END IF;
|
| 6870 |
|
|
IF (sreg_bit_out(2) = '1') THEN
|
| 6871 |
|
|
regn_compout_rdn(2) <= regn_rdn_in;
|
| 6872 |
|
|
END IF;
|
| 6873 |
|
|
IF (sreg_bit_out(3) = '1') THEN
|
| 6874 |
|
|
regn_compout_rdn(3) <= regn_rdn_in;
|
| 6875 |
|
|
END IF;
|
| 6876 |
|
|
IF (sreg_bit_out(4) = '1') THEN
|
| 6877 |
|
|
regn_compout_rdn(4) <= regn_rdn_in;
|
| 6878 |
|
|
END IF;
|
| 6879 |
|
|
IF (sreg_bit_out(5) = '1') THEN
|
| 6880 |
|
|
regn_compout_rdn(5) <= regn_rdn_in;
|
| 6881 |
|
|
END IF;
|
| 6882 |
|
|
IF (sreg_bit_out(6) = '1') THEN
|
| 6883 |
|
|
regn_compout_rdn(6) <= regn_rdn_in;
|
| 6884 |
|
|
END IF;
|
| 6885 |
|
|
END IF;
|
| 6886 |
|
|
END PROCESS;
|
| 6887 |
|
|
|
| 6888 |
|
|
sa_octcaln_in <= sreg_bit_out ;
|
| 6889 |
|
|
sa_octcalp_in <= sreg_bit_out ;
|
| 6890 |
|
|
|
| 6891 |
|
|
|
| 6892 |
|
|
-- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
|
| 6893 |
|
|
temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0);
|
| 6894 |
|
|
sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10;
|
| 6895 |
|
|
temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1);
|
| 6896 |
|
|
sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12;
|
| 6897 |
|
|
temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2);
|
| 6898 |
|
|
sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14;
|
| 6899 |
|
|
temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3);
|
| 6900 |
|
|
sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16;
|
| 6901 |
|
|
temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4);
|
| 6902 |
|
|
sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18;
|
| 6903 |
|
|
temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5);
|
| 6904 |
|
|
sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20;
|
| 6905 |
|
|
temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6);
|
| 6906 |
|
|
sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22;
|
| 6907 |
|
|
temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0);
|
| 6908 |
|
|
sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24;
|
| 6909 |
|
|
temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1);
|
| 6910 |
|
|
sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26;
|
| 6911 |
|
|
temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2);
|
| 6912 |
|
|
sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28;
|
| 6913 |
|
|
temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3);
|
| 6914 |
|
|
sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30;
|
| 6915 |
|
|
temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4);
|
| 6916 |
|
|
sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32;
|
| 6917 |
|
|
temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5);
|
| 6918 |
|
|
sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34;
|
| 6919 |
|
|
temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6);
|
| 6920 |
|
|
sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36;
|
| 6921 |
|
|
|
| 6922 |
|
|
-- ENSER
|
| 6923 |
|
|
enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out;
|
| 6924 |
|
|
enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0';
|
| 6925 |
|
|
|
| 6926 |
|
|
PROCESS
|
| 6927 |
|
|
BEGIN
|
| 6928 |
|
|
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1');
|
| 6929 |
|
|
IF (sregn_rscaldone_out = '0') THEN
|
| 6930 |
|
|
enser_cnt <= 0;
|
| 6931 |
|
|
ELSE
|
| 6932 |
|
|
IF (enser_cnt < 63) THEN
|
| 6933 |
|
|
enser_cnt <= enser_cnt + 1;
|
| 6934 |
|
|
END IF;
|
| 6935 |
|
|
END IF;
|
| 6936 |
|
|
END PROCESS;
|
| 6937 |
|
|
|
| 6938 |
|
|
-- RT SM
|
| 6939 |
|
|
rtsm_rup_in <= rup ;
|
| 6940 |
|
|
rtsm_rdn_in <= rdn ;
|
| 6941 |
|
|
rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0';
|
| 6942 |
|
|
rtsm_rscaldone_in <= sregn_rscaldone_out ;
|
| 6943 |
|
|
|
| 6944 |
|
|
m_rt_sm : stratixiii_rt_sm
|
| 6945 |
|
|
PORT MAP (
|
| 6946 |
|
|
rup => rtsm_rup_in,
|
| 6947 |
|
|
rdn => rtsm_rdn_in,
|
| 6948 |
|
|
clk => cal_clk,
|
| 6949 |
|
|
clken => cal_clken,
|
| 6950 |
|
|
clr => cal_nclr,
|
| 6951 |
|
|
rtena => rtsm_rtena_in,
|
| 6952 |
|
|
rscaldone => rtsm_rscaldone_in,
|
| 6953 |
|
|
rtoffsetp => rtsm_rtoffsetp_out,
|
| 6954 |
|
|
rtoffsetn => rtsm_rtoffsetn_out,
|
| 6955 |
|
|
caldone => rtsm_caldone_out,
|
| 6956 |
|
|
sel_rup_vref => rtsm_sel_rup_vref_out,
|
| 6957 |
|
|
sel_rdn_vref => rtsm_sel_rdn_vref_out
|
| 6958 |
|
|
);
|
| 6959 |
|
|
|
| 6960 |
|
|
-- RT Adder/Sub
|
| 6961 |
|
|
rtas_rs_rpcdp_in <= sa_octcalp_out ;
|
| 6962 |
|
|
rtas_rs_rpcdn_in <= sa_octcaln_out ;
|
| 6963 |
|
|
rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0);
|
| 6964 |
|
|
rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0);
|
| 6965 |
|
|
|
| 6966 |
|
|
rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ;
|
| 6967 |
|
|
rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ;
|
| 6968 |
|
|
|
| 6969 |
|
|
|
| 6970 |
|
|
rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE
|
| 6971 |
|
|
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
|
| 6972 |
|
|
rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE
|
| 6973 |
|
|
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
|
| 6974 |
|
|
|
| 6975 |
|
|
-- P2S
|
| 6976 |
|
|
p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ;
|
| 6977 |
|
|
p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ;
|
| 6978 |
|
|
p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out;
|
| 6979 |
|
|
p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out;
|
| 6980 |
|
|
|
| 6981 |
|
|
p2s_enser_in <= enser_out ;
|
| 6982 |
|
|
p2s_clk_in <= usr_clk ;
|
| 6983 |
|
|
p2s_ser_data_out <= p2s_serial_reg ;
|
| 6984 |
|
|
|
| 6985 |
|
|
-- load - clken
|
| 6986 |
|
|
PROCESS
|
| 6987 |
|
|
BEGIN
|
| 6988 |
|
|
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
|
| 6989 |
|
|
IF (cal_nclr = '1') THEN
|
| 6990 |
|
|
p2s_parallel_reg <= "0000000000000000000000000000";
|
| 6991 |
|
|
ELSE
|
| 6992 |
|
|
IF (cal_clken = '1') THEN
|
| 6993 |
|
|
p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in;
|
| 6994 |
|
|
END IF;
|
| 6995 |
|
|
END IF;
|
| 6996 |
|
|
END PROCESS;
|
| 6997 |
|
|
|
| 6998 |
|
|
-- shift - enser
|
| 6999 |
|
|
PROCESS
|
| 7000 |
|
|
BEGIN
|
| 7001 |
|
|
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
|
| 7002 |
|
|
IF (cal_nclr = '1') THEN
|
| 7003 |
|
|
p2s_serial_reg <= '0';
|
| 7004 |
|
|
p2s_index <= 27;
|
| 7005 |
|
|
ELSE
|
| 7006 |
|
|
IF (p2s_enser_in = '1' AND cal_clken = '0') THEN
|
| 7007 |
|
|
p2s_serial_reg <= p2s_parallel_reg(p2s_index);
|
| 7008 |
|
|
IF (p2s_index > 0) THEN
|
| 7009 |
|
|
p2s_index <= p2s_index - 1;
|
| 7010 |
|
|
END IF;
|
| 7011 |
|
|
END IF;
|
| 7012 |
|
|
END IF;
|
| 7013 |
|
|
END PROCESS;
|
| 7014 |
|
|
|
| 7015 |
|
|
|
| 7016 |
|
|
--------------------
|
| 7017 |
|
|
-- INPUT PATH DELAYS
|
| 7018 |
|
|
--------------------
|
| 7019 |
|
|
WireDelay : block
|
| 7020 |
|
|
begin
|
| 7021 |
|
|
VitalWireDelay (rup_ipd, rup, tipd_rup);
|
| 7022 |
|
|
VitalWireDelay (rdn_ipd, rdn, tipd_rdn);
|
| 7023 |
|
|
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
|
| 7024 |
|
|
VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear);
|
| 7025 |
|
|
VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable);
|
| 7026 |
|
|
VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable);
|
| 7027 |
|
|
VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin);
|
| 7028 |
|
|
VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0));
|
| 7029 |
|
|
|
| 7030 |
|
|
VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1));
|
| 7031 |
|
|
VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2));
|
| 7032 |
|
|
VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3));
|
| 7033 |
|
|
VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4));
|
| 7034 |
|
|
VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5));
|
| 7035 |
|
|
VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6));
|
| 7036 |
|
|
VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7));
|
| 7037 |
|
|
VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8));
|
| 7038 |
|
|
end block;
|
| 7039 |
|
|
|
| 7040 |
|
|
END stratixiii_oct_arch;
|
| 7041 |
|
|
|
| 7042 |
|
|
-------------------------------------------------------------------------------
|
| 7043 |
|
|
--
|
| 7044 |
|
|
-- Module Name : stratixiii_termination_logic
|
| 7045 |
|
|
--
|
| 7046 |
|
|
-- Description : Stratix III Termination Logic Atom
|
| 7047 |
|
|
-- Verilog simulation model
|
| 7048 |
|
|
--
|
| 7049 |
|
|
-------------------------------------------------------------------------------
|
| 7050 |
|
|
LIBRARY IEEE;
|
| 7051 |
|
|
USE IEEE.std_logic_1164.ALL;
|
| 7052 |
|
|
USE IEEE.VITAL_Timing.ALL;
|
| 7053 |
|
|
USE IEEE.VITAL_Primitives.ALL;
|
| 7054 |
|
|
use work.stratixiii_atom_pack.all;
|
| 7055 |
|
|
|
| 7056 |
|
|
ENTITY stratixiii_termination_logic IS
|
| 7057 |
|
|
GENERIC (
|
| 7058 |
|
|
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
|
| 7059 |
|
|
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
|
| 7060 |
|
|
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
|
| 7061 |
|
|
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
|
| 7062 |
|
|
test_mode : string := "false";
|
| 7063 |
|
|
lpm_type : string := "stratixiii_termination_logic");
|
| 7064 |
|
|
PORT (
|
| 7065 |
|
|
serialloadenable : IN std_logic := '0';
|
| 7066 |
|
|
terminationclock : IN std_logic := '0';
|
| 7067 |
|
|
parallelloadenable : IN std_logic := '0';
|
| 7068 |
|
|
terminationdata : IN std_logic := '0';
|
| 7069 |
|
|
devclrn : IN std_logic := '1';
|
| 7070 |
|
|
devpor : IN std_logic := '1';
|
| 7071 |
|
|
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
|
| 7072 |
|
|
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
|
| 7073 |
|
|
END stratixiii_termination_logic;
|
| 7074 |
|
|
|
| 7075 |
|
|
ARCHITECTURE stratixiii_oct_logic_arch OF stratixiii_termination_logic IS
|
| 7076 |
|
|
|
| 7077 |
|
|
CONSTANT xhdl_timescale : time := 1 ps;
|
| 7078 |
|
|
|
| 7079 |
|
|
|
| 7080 |
|
|
SIGNAL usr_clk : std_logic;
|
| 7081 |
|
|
SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
|
| 7082 |
|
|
SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
|
| 7083 |
|
|
SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
|
| 7084 |
|
|
SIGNAL shift_index : integer := 27;
|
| 7085 |
|
|
|
| 7086 |
|
|
-- timing
|
| 7087 |
|
|
SIGNAL serialloadenable_ipd : std_logic;
|
| 7088 |
|
|
SIGNAL terminationclock_ipd : std_logic;
|
| 7089 |
|
|
SIGNAL parallelloadenable_ipd : std_logic;
|
| 7090 |
|
|
SIGNAL terminationdata_ipd : std_logic;
|
| 7091 |
|
|
|
| 7092 |
|
|
BEGIN
|
| 7093 |
|
|
seriesterminationcontrol <= rs_reg;
|
| 7094 |
|
|
parallelterminationcontrol <= rt_reg;
|
| 7095 |
|
|
usr_clk <= terminationclock AFTER 11 * xhdl_timescale;
|
| 7096 |
|
|
|
| 7097 |
|
|
PROCESS
|
| 7098 |
|
|
BEGIN
|
| 7099 |
|
|
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
|
| 7100 |
|
|
IF (serialloadenable = '0') THEN
|
| 7101 |
|
|
shift_index <= 27;
|
| 7102 |
|
|
ELSE
|
| 7103 |
|
|
hold_reg(shift_index) <= terminationdata;
|
| 7104 |
|
|
IF (shift_index > 0) THEN
|
| 7105 |
|
|
shift_index <= shift_index - 1;
|
| 7106 |
|
|
END IF;
|
| 7107 |
|
|
END IF;
|
| 7108 |
|
|
END PROCESS;
|
| 7109 |
|
|
|
| 7110 |
|
|
PROCESS
|
| 7111 |
|
|
BEGIN
|
| 7112 |
|
|
WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1');
|
| 7113 |
|
|
IF (parallelloadenable = '1') THEN
|
| 7114 |
|
|
rs_reg <= hold_reg(27 DOWNTO 14);
|
| 7115 |
|
|
rt_reg <= hold_reg(13 DOWNTO 0);
|
| 7116 |
|
|
END IF;
|
| 7117 |
|
|
END PROCESS;
|
| 7118 |
|
|
|
| 7119 |
|
|
--------------------
|
| 7120 |
|
|
-- INPUT PATH DELAYS
|
| 7121 |
|
|
--------------------
|
| 7122 |
|
|
WireDelay : block
|
| 7123 |
|
|
begin
|
| 7124 |
|
|
VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable);
|
| 7125 |
|
|
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
|
| 7126 |
|
|
VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable);
|
| 7127 |
|
|
VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata);
|
| 7128 |
|
|
end block;
|
| 7129 |
|
|
|
| 7130 |
|
|
END stratixiii_oct_logic_arch;
|
| 7131 |
|
|
-------------------------------------------------------------------------------
|
| 7132 |
|
|
-- utilities common for ddr
|
| 7133 |
|
|
-------------------------------------------------------------------------------
|
| 7134 |
|
|
|
| 7135 |
|
|
library IEEE;
|
| 7136 |
|
|
use IEEE.std_logic_1164.all;
|
| 7137 |
|
|
package stratixiii_atom_ddr_pack is
|
| 7138 |
|
|
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
|
| 7139 |
|
|
end stratixiii_atom_ddr_pack;
|
| 7140 |
|
|
|
| 7141 |
|
|
library IEEE;
|
| 7142 |
|
|
use IEEE.std_logic_1164.all;
|
| 7143 |
|
|
|
| 7144 |
|
|
package body stratixiii_atom_ddr_pack is
|
| 7145 |
|
|
|
| 7146 |
|
|
-- truncate input integer to get 6 LSB bits
|
| 7147 |
|
|
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
|
| 7148 |
|
|
variable tmp_int, i : integer;
|
| 7149 |
|
|
variable tmp_bit : integer;
|
| 7150 |
|
|
variable result : std_logic_vector(5 downto 0) := "000000";
|
| 7151 |
|
|
begin
|
| 7152 |
|
|
tmp_int := in_int;
|
| 7153 |
|
|
for i in 0 to 5 loop
|
| 7154 |
|
|
tmp_bit := tmp_int MOD 2;
|
| 7155 |
|
|
if (tmp_bit = 1) then
|
| 7156 |
|
|
result(i) := '1';
|
| 7157 |
|
|
else
|
| 7158 |
|
|
result(i) := '0';
|
| 7159 |
|
|
end if;
|
| 7160 |
|
|
tmp_int := tmp_int/2;
|
| 7161 |
|
|
end loop;
|
| 7162 |
|
|
return result;
|
| 7163 |
|
|
end dll_unsigned2bin;
|
| 7164 |
|
|
|
| 7165 |
|
|
end stratixiii_atom_ddr_pack;
|
| 7166 |
|
|
|
| 7167 |
|
|
-------------------------------------------------------------------------------
|
| 7168 |
|
|
-- auxilary module for ddr
|
| 7169 |
|
|
-------------------------------------------------------------------------------
|
| 7170 |
|
|
library IEEE;
|
| 7171 |
|
|
use IEEE.std_logic_1164.all;
|
| 7172 |
|
|
|
| 7173 |
|
|
ENTITY stratixiii_dll_gray_encoder IS
|
| 7174 |
|
|
GENERIC ( width : integer := 6 );
|
| 7175 |
|
|
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 7176 |
|
|
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
|
| 7177 |
|
|
);
|
| 7178 |
|
|
END stratixiii_dll_gray_encoder;
|
| 7179 |
|
|
|
| 7180 |
|
|
ARCHITECTURE stratixiii_dll_gray_encoder_arch OF stratixiii_dll_gray_encoder IS
|
| 7181 |
|
|
|
| 7182 |
|
|
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 7183 |
|
|
BEGIN
|
| 7184 |
|
|
gout <= greg;
|
| 7185 |
|
|
PROCESS(mbin)
|
| 7186 |
|
|
VARIABLE i : INTEGER := 0;
|
| 7187 |
|
|
BEGIN
|
| 7188 |
|
|
greg(width-1) <= mbin(width-1);
|
| 7189 |
|
|
IF (width > 1) THEN
|
| 7190 |
|
|
i := width - 2;
|
| 7191 |
|
|
WHILE (i >= 0) LOOP
|
| 7192 |
|
|
greg(i) <= mbin(i+1) XOR mbin(i);
|
| 7193 |
|
|
i := i - 1;
|
| 7194 |
|
|
END LOOP;
|
| 7195 |
|
|
END IF;
|
| 7196 |
|
|
END PROCESS;
|
| 7197 |
|
|
|
| 7198 |
|
|
END stratixiii_dll_gray_encoder_arch;
|
| 7199 |
|
|
|
| 7200 |
|
|
-------------------------------------------------------------------------------
|
| 7201 |
|
|
-- auxilary module for ddr
|
| 7202 |
|
|
-------------------------------------------------------------------------------
|
| 7203 |
|
|
library IEEE;
|
| 7204 |
|
|
use IEEE.std_logic_1164.all;
|
| 7205 |
|
|
|
| 7206 |
|
|
ENTITY stratixiii_dll_gray_decoder IS
|
| 7207 |
|
|
GENERIC ( width : integer := 6 );
|
| 7208 |
|
|
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 7209 |
|
|
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
|
| 7210 |
|
|
);
|
| 7211 |
|
|
END stratixiii_dll_gray_decoder;
|
| 7212 |
|
|
|
| 7213 |
|
|
ARCHITECTURE stratixiii_dll_gray_decoder_arch OF stratixiii_dll_gray_decoder IS
|
| 7214 |
|
|
|
| 7215 |
|
|
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 7216 |
|
|
BEGIN
|
| 7217 |
|
|
bout <= breg;
|
| 7218 |
|
|
PROCESS(gin)
|
| 7219 |
|
|
VARIABLE i : INTEGER := 0;
|
| 7220 |
|
|
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 7221 |
|
|
BEGIN
|
| 7222 |
|
|
bvar(width-1) := gin(width-1);
|
| 7223 |
|
|
IF (width > 1) THEN
|
| 7224 |
|
|
i := width - 2;
|
| 7225 |
|
|
WHILE (i >= 0) LOOP
|
| 7226 |
|
|
bvar(i) := bvar(i+1) XOR gin(i);
|
| 7227 |
|
|
i := i - 1;
|
| 7228 |
|
|
END LOOP;
|
| 7229 |
|
|
END IF;
|
| 7230 |
|
|
breg <= bvar;
|
| 7231 |
|
|
END PROCESS;
|
| 7232 |
|
|
|
| 7233 |
|
|
END stratixiii_dll_gray_decoder_arch;
|
| 7234 |
|
|
|
| 7235 |
|
|
-------------------------------------------------------------------------------
|
| 7236 |
|
|
-- Module Name: stratixiii_ddr_delay_chain_s
|
| 7237 |
|
|
-- Description: auxilary module - delay chain-setting
|
| 7238 |
|
|
-------------------------------------------------------------------------------
|
| 7239 |
|
|
|
| 7240 |
|
|
Library ieee;
|
| 7241 |
|
|
use ieee.std_logic_1164.all;
|
| 7242 |
|
|
use work.stratixiii_atom_pack.all;
|
| 7243 |
|
|
use work.stratixiii_dll_gray_decoder;
|
| 7244 |
|
|
|
| 7245 |
|
|
ENTITY stratixiii_ddr_delay_chain_s IS
|
| 7246 |
|
|
GENERIC (
|
| 7247 |
|
|
use_phasectrlin : string := "true";
|
| 7248 |
|
|
phase_setting : integer := 0;
|
| 7249 |
|
|
delay_buffer_mode : string := "high";
|
| 7250 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 7251 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 7252 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 7253 |
|
|
phasectrlin_limit : integer := 7
|
| 7254 |
|
|
);
|
| 7255 |
|
|
PORT (
|
| 7256 |
|
|
clk : IN std_logic := '0';
|
| 7257 |
|
|
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
|
| 7258 |
|
|
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
|
| 7259 |
|
|
delayed_clkout : OUT std_logic
|
| 7260 |
|
|
);
|
| 7261 |
|
|
END stratixiii_ddr_delay_chain_s;
|
| 7262 |
|
|
|
| 7263 |
|
|
ARCHITECTURE stratixiii_ddr_delay_chain_s_arch OF stratixiii_ddr_delay_chain_s IS
|
| 7264 |
|
|
|
| 7265 |
|
|
COMPONENT stratixiii_dll_gray_decoder
|
| 7266 |
|
|
GENERIC ( width : integer := 6 );
|
| 7267 |
|
|
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 7268 |
|
|
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
|
| 7269 |
|
|
);
|
| 7270 |
|
|
END COMPONENT;
|
| 7271 |
|
|
|
| 7272 |
|
|
SIGNAL clk_delay : INTEGER := 0;
|
| 7273 |
|
|
SIGNAL delayed_clk : STD_LOGIC := '0';
|
| 7274 |
|
|
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
|
| 7275 |
|
|
|
| 7276 |
|
|
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
|
| 7277 |
|
|
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
|
| 7278 |
|
|
|
| 7279 |
|
|
BEGIN
|
| 7280 |
|
|
|
| 7281 |
|
|
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
|
| 7282 |
|
|
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
|
| 7283 |
|
|
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
|
| 7284 |
|
|
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
|
| 7285 |
|
|
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
|
| 7286 |
|
|
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
|
| 7287 |
|
|
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
|
| 7288 |
|
|
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
|
| 7289 |
|
|
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
|
| 7290 |
|
|
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
|
| 7291 |
|
|
|
| 7292 |
|
|
-- decoder
|
| 7293 |
|
|
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
|
| 7294 |
|
|
GENERIC MAP (width => 6)
|
| 7295 |
|
|
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
|
| 7296 |
|
|
|
| 7297 |
|
|
PROCESS(delayctrl_bin, phasectrlin_in)
|
| 7298 |
|
|
variable sim_intrinsic_delay : INTEGER := 0;
|
| 7299 |
|
|
variable acell_delay : INTEGER := 0;
|
| 7300 |
|
|
variable delay_chain_len : INTEGER := 0;
|
| 7301 |
|
|
BEGIN
|
| 7302 |
|
|
IF (delay_buffer_mode = "low") THEN
|
| 7303 |
|
|
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
|
| 7304 |
|
|
ELSE
|
| 7305 |
|
|
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
|
| 7306 |
|
|
END IF;
|
| 7307 |
|
|
|
| 7308 |
|
|
-- cell
|
| 7309 |
|
|
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
|
| 7310 |
|
|
-- no of cells
|
| 7311 |
|
|
IF (use_phasectrlin = "false") THEN
|
| 7312 |
|
|
delay_chain_len := phase_setting;
|
| 7313 |
|
|
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
|
| 7314 |
|
|
delay_chain_len := 0;
|
| 7315 |
|
|
ELSE
|
| 7316 |
|
|
delay_chain_len := alt_conv_integer(phasectrlin_in);
|
| 7317 |
|
|
END IF;
|
| 7318 |
|
|
-- total delay - added extra 1 ps for resolving racing
|
| 7319 |
|
|
clk_delay <= delay_chain_len * acell_delay + 1;
|
| 7320 |
|
|
|
| 7321 |
|
|
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
|
| 7322 |
|
|
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
|
| 7323 |
|
|
END IF;
|
| 7324 |
|
|
|
| 7325 |
|
|
END PROCESS; -- generating delays
|
| 7326 |
|
|
|
| 7327 |
|
|
delayed_clk <= transport clk after (clk_delay * 1 ps);
|
| 7328 |
|
|
delayed_clkout <= delayed_clk;
|
| 7329 |
|
|
|
| 7330 |
|
|
END stratixiii_ddr_delay_chain_s_arch;
|
| 7331 |
|
|
|
| 7332 |
|
|
-------------------------------------------------------------------------------
|
| 7333 |
|
|
-- based on dffeas
|
| 7334 |
|
|
-------------------------------------------------------------------------------
|
| 7335 |
|
|
|
| 7336 |
|
|
Library ieee;
|
| 7337 |
|
|
use ieee.std_logic_1164.all;
|
| 7338 |
|
|
use IEEE.VITAL_Timing.all;
|
| 7339 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 7340 |
|
|
use work.stratixiii_atom_pack.all;
|
| 7341 |
|
|
|
| 7342 |
|
|
entity stratixiii_ddr_io_reg is
|
| 7343 |
|
|
generic(
|
| 7344 |
|
|
power_up : string := "DONT_CARE";
|
| 7345 |
|
|
is_wysiwyg : string := "false";
|
| 7346 |
|
|
x_on_violation : string := "on";
|
| 7347 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7348 |
|
|
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7349 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7350 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7351 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7352 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7353 |
|
|
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7354 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7355 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7356 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7357 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 7358 |
|
|
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 7359 |
|
|
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 7360 |
|
|
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 7361 |
|
|
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
| 7362 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 7363 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 7364 |
|
|
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
| 7365 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
| 7366 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 7367 |
|
|
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
| 7368 |
|
|
tipd_prn : VitalDelayType01 := DefPropDelay01;
|
| 7369 |
|
|
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
| 7370 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 7371 |
|
|
TimingChecksOn: Boolean := True;
|
| 7372 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 7373 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 7374 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 7375 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 7376 |
|
|
InstancePath: STRING := "*"
|
| 7377 |
|
|
);
|
| 7378 |
|
|
|
| 7379 |
|
|
port(
|
| 7380 |
|
|
d : in std_logic := '0';
|
| 7381 |
|
|
clk : in std_logic := '0';
|
| 7382 |
|
|
ena : in std_logic := '1';
|
| 7383 |
|
|
clrn : in std_logic := '1';
|
| 7384 |
|
|
prn : in std_logic := '1';
|
| 7385 |
|
|
aload : in std_logic := '0';
|
| 7386 |
|
|
asdata : in std_logic := '1';
|
| 7387 |
|
|
sclr : in std_logic := '0';
|
| 7388 |
|
|
sload : in std_logic := '0';
|
| 7389 |
|
|
devclrn : in std_logic := '1';
|
| 7390 |
|
|
devpor : in std_logic := '1';
|
| 7391 |
|
|
q : out std_logic
|
| 7392 |
|
|
);
|
| 7393 |
|
|
attribute VITAL_LEVEL0 of stratixiii_ddr_io_reg : entity is TRUE;
|
| 7394 |
|
|
end stratixiii_ddr_io_reg;
|
| 7395 |
|
|
|
| 7396 |
|
|
|
| 7397 |
|
|
architecture vital_stratixiii_ddr_io_reg of stratixiii_ddr_io_reg is
|
| 7398 |
|
|
attribute VITAL_LEVEL0 of vital_stratixiii_ddr_io_reg : architecture is TRUE;
|
| 7399 |
|
|
signal clk_ipd : std_logic;
|
| 7400 |
|
|
signal d_ipd : std_logic;
|
| 7401 |
|
|
signal d_dly : std_logic;
|
| 7402 |
|
|
signal asdata_ipd : std_logic;
|
| 7403 |
|
|
signal asdata_dly : std_logic;
|
| 7404 |
|
|
signal asdata_dly1 : std_logic;
|
| 7405 |
|
|
signal sclr_ipd : std_logic;
|
| 7406 |
|
|
signal sload_ipd : std_logic;
|
| 7407 |
|
|
signal clrn_ipd : std_logic;
|
| 7408 |
|
|
signal prn_ipd : std_logic;
|
| 7409 |
|
|
signal aload_ipd : std_logic;
|
| 7410 |
|
|
signal ena_ipd : std_logic;
|
| 7411 |
|
|
|
| 7412 |
|
|
begin
|
| 7413 |
|
|
|
| 7414 |
|
|
d_dly <= d_ipd;
|
| 7415 |
|
|
asdata_dly <= asdata_ipd;
|
| 7416 |
|
|
asdata_dly1 <= asdata_dly;
|
| 7417 |
|
|
|
| 7418 |
|
|
|
| 7419 |
|
|
---------------------
|
| 7420 |
|
|
-- INPUT PATH DELAYs
|
| 7421 |
|
|
---------------------
|
| 7422 |
|
|
WireDelay : block
|
| 7423 |
|
|
begin
|
| 7424 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 7425 |
|
|
VitalWireDelay (d_ipd, d, tipd_d);
|
| 7426 |
|
|
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
|
| 7427 |
|
|
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
|
| 7428 |
|
|
VitalWireDelay (sload_ipd, sload, tipd_sload);
|
| 7429 |
|
|
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
|
| 7430 |
|
|
VitalWireDelay (prn_ipd, prn, tipd_prn);
|
| 7431 |
|
|
VitalWireDelay (aload_ipd, aload, tipd_aload);
|
| 7432 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 7433 |
|
|
end block;
|
| 7434 |
|
|
|
| 7435 |
|
|
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
|
| 7436 |
|
|
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
|
| 7437 |
|
|
ena_ipd, devclrn, devpor)
|
| 7438 |
|
|
|
| 7439 |
|
|
variable Tviol_d_clk : std_ulogic := '0';
|
| 7440 |
|
|
variable Tviol_asdata_clk : std_ulogic := '0';
|
| 7441 |
|
|
variable Tviol_sclr_clk : std_ulogic := '0';
|
| 7442 |
|
|
variable Tviol_sload_clk : std_ulogic := '0';
|
| 7443 |
|
|
variable Tviol_ena_clk : std_ulogic := '0';
|
| 7444 |
|
|
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 7445 |
|
|
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 7446 |
|
|
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 7447 |
|
|
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 7448 |
|
|
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 7449 |
|
|
variable q_VitalGlitchData : VitalGlitchDataType;
|
| 7450 |
|
|
|
| 7451 |
|
|
variable iq : std_logic := '0';
|
| 7452 |
|
|
variable idata: std_logic := '0';
|
| 7453 |
|
|
|
| 7454 |
|
|
-- variables for 'X' generation
|
| 7455 |
|
|
variable violation : std_logic := '0';
|
| 7456 |
|
|
|
| 7457 |
|
|
begin
|
| 7458 |
|
|
|
| 7459 |
|
|
if (now = 0 ns) then
|
| 7460 |
|
|
if ((power_up = "low") or (power_up = "DONT_CARE")) then
|
| 7461 |
|
|
iq := '0';
|
| 7462 |
|
|
elsif (power_up = "high") then
|
| 7463 |
|
|
iq := '1';
|
| 7464 |
|
|
else
|
| 7465 |
|
|
iq := '0';
|
| 7466 |
|
|
end if;
|
| 7467 |
|
|
end if;
|
| 7468 |
|
|
|
| 7469 |
|
|
------------------------
|
| 7470 |
|
|
-- Timing Check Section
|
| 7471 |
|
|
------------------------
|
| 7472 |
|
|
if (TimingChecksOn) then
|
| 7473 |
|
|
|
| 7474 |
|
|
VitalSetupHoldCheck (
|
| 7475 |
|
|
Violation => Tviol_d_clk,
|
| 7476 |
|
|
TimingData => TimingData_d_clk,
|
| 7477 |
|
|
TestSignal => d,
|
| 7478 |
|
|
TestSignalName => "DATAIN",
|
| 7479 |
|
|
RefSignal => clk_ipd,
|
| 7480 |
|
|
RefSignalName => "CLK",
|
| 7481 |
|
|
SetupHigh => tsetup_d_clk_noedge_posedge,
|
| 7482 |
|
|
SetupLow => tsetup_d_clk_noedge_posedge,
|
| 7483 |
|
|
HoldHigh => thold_d_clk_noedge_posedge,
|
| 7484 |
|
|
HoldLow => thold_d_clk_noedge_posedge,
|
| 7485 |
|
|
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
|
| 7486 |
|
|
(NOT prn_ipd) OR
|
| 7487 |
|
|
(sload_ipd) OR
|
| 7488 |
|
|
(sclr_ipd) OR
|
| 7489 |
|
|
(NOT devpor) OR
|
| 7490 |
|
|
(NOT devclrn) OR
|
| 7491 |
|
|
(NOT ena_ipd)) /= '1',
|
| 7492 |
|
|
RefTransition => '/',
|
| 7493 |
|
|
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
|
| 7494 |
|
|
XOn => XOnChecks,
|
| 7495 |
|
|
MsgOn => MsgOnChecks );
|
| 7496 |
|
|
|
| 7497 |
|
|
VitalSetupHoldCheck (
|
| 7498 |
|
|
Violation => Tviol_asdata_clk,
|
| 7499 |
|
|
TimingData => TimingData_asdata_clk,
|
| 7500 |
|
|
TestSignal => asdata_ipd,
|
| 7501 |
|
|
TestSignalName => "ASDATA",
|
| 7502 |
|
|
RefSignal => clk_ipd,
|
| 7503 |
|
|
RefSignalName => "CLK",
|
| 7504 |
|
|
SetupHigh => tsetup_asdata_clk_noedge_posedge,
|
| 7505 |
|
|
SetupLow => tsetup_asdata_clk_noedge_posedge,
|
| 7506 |
|
|
HoldHigh => thold_asdata_clk_noedge_posedge,
|
| 7507 |
|
|
HoldLow => thold_asdata_clk_noedge_posedge,
|
| 7508 |
|
|
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
|
| 7509 |
|
|
(NOT prn_ipd) OR
|
| 7510 |
|
|
(NOT sload_ipd) OR
|
| 7511 |
|
|
(NOT devpor) OR
|
| 7512 |
|
|
(NOT devclrn) OR
|
| 7513 |
|
|
(NOT ena_ipd)) /= '1',
|
| 7514 |
|
|
RefTransition => '/',
|
| 7515 |
|
|
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
|
| 7516 |
|
|
XOn => XOnChecks,
|
| 7517 |
|
|
MsgOn => MsgOnChecks );
|
| 7518 |
|
|
|
| 7519 |
|
|
VitalSetupHoldCheck (
|
| 7520 |
|
|
Violation => Tviol_sclr_clk,
|
| 7521 |
|
|
TimingData => TimingData_sclr_clk,
|
| 7522 |
|
|
TestSignal => sclr_ipd,
|
| 7523 |
|
|
TestSignalName => "SCLR",
|
| 7524 |
|
|
RefSignal => clk_ipd,
|
| 7525 |
|
|
RefSignalName => "CLK",
|
| 7526 |
|
|
SetupHigh => tsetup_sclr_clk_noedge_posedge,
|
| 7527 |
|
|
SetupLow => tsetup_sclr_clk_noedge_posedge,
|
| 7528 |
|
|
HoldHigh => thold_sclr_clk_noedge_posedge,
|
| 7529 |
|
|
HoldLow => thold_sclr_clk_noedge_posedge,
|
| 7530 |
|
|
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
|
| 7531 |
|
|
(NOT prn_ipd) OR
|
| 7532 |
|
|
(NOT devpor) OR
|
| 7533 |
|
|
(NOT devclrn) OR
|
| 7534 |
|
|
(NOT ena_ipd)) /= '1',
|
| 7535 |
|
|
RefTransition => '/',
|
| 7536 |
|
|
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
|
| 7537 |
|
|
XOn => XOnChecks,
|
| 7538 |
|
|
MsgOn => MsgOnChecks );
|
| 7539 |
|
|
|
| 7540 |
|
|
VitalSetupHoldCheck (
|
| 7541 |
|
|
Violation => Tviol_sload_clk,
|
| 7542 |
|
|
TimingData => TimingData_sload_clk,
|
| 7543 |
|
|
TestSignal => sload_ipd,
|
| 7544 |
|
|
TestSignalName => "SLOAD",
|
| 7545 |
|
|
RefSignal => clk_ipd,
|
| 7546 |
|
|
RefSignalName => "CLK",
|
| 7547 |
|
|
SetupHigh => tsetup_sload_clk_noedge_posedge,
|
| 7548 |
|
|
SetupLow => tsetup_sload_clk_noedge_posedge,
|
| 7549 |
|
|
HoldHigh => thold_sload_clk_noedge_posedge,
|
| 7550 |
|
|
HoldLow => thold_sload_clk_noedge_posedge,
|
| 7551 |
|
|
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
|
| 7552 |
|
|
(NOT prn_ipd) OR
|
| 7553 |
|
|
(NOT devpor) OR
|
| 7554 |
|
|
(NOT devclrn) OR
|
| 7555 |
|
|
(NOT ena_ipd)) /= '1',
|
| 7556 |
|
|
RefTransition => '/',
|
| 7557 |
|
|
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
|
| 7558 |
|
|
XOn => XOnChecks,
|
| 7559 |
|
|
MsgOn => MsgOnChecks );
|
| 7560 |
|
|
|
| 7561 |
|
|
VitalSetupHoldCheck (
|
| 7562 |
|
|
Violation => Tviol_ena_clk,
|
| 7563 |
|
|
TimingData => TimingData_ena_clk,
|
| 7564 |
|
|
TestSignal => ena_ipd,
|
| 7565 |
|
|
TestSignalName => "ENA",
|
| 7566 |
|
|
RefSignal => clk_ipd,
|
| 7567 |
|
|
RefSignalName => "CLK",
|
| 7568 |
|
|
SetupHigh => tsetup_ena_clk_noedge_posedge,
|
| 7569 |
|
|
SetupLow => tsetup_ena_clk_noedge_posedge,
|
| 7570 |
|
|
HoldHigh => thold_ena_clk_noedge_posedge,
|
| 7571 |
|
|
HoldLow => thold_ena_clk_noedge_posedge,
|
| 7572 |
|
|
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
|
| 7573 |
|
|
(NOT prn_ipd) OR
|
| 7574 |
|
|
(NOT devpor) OR
|
| 7575 |
|
|
(NOT devclrn) ) /= '1',
|
| 7576 |
|
|
RefTransition => '/',
|
| 7577 |
|
|
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
|
| 7578 |
|
|
XOn => XOnChecks,
|
| 7579 |
|
|
MsgOn => MsgOnChecks );
|
| 7580 |
|
|
end if;
|
| 7581 |
|
|
|
| 7582 |
|
|
violation := Tviol_d_clk or Tviol_asdata_clk or
|
| 7583 |
|
|
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
|
| 7584 |
|
|
|
| 7585 |
|
|
|
| 7586 |
|
|
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
|
| 7587 |
|
|
iq := '0';
|
| 7588 |
|
|
elsif (prn_ipd = '0') then
|
| 7589 |
|
|
iq := '1';
|
| 7590 |
|
|
elsif (aload_ipd = '1') then
|
| 7591 |
|
|
iq := asdata_dly1;
|
| 7592 |
|
|
elsif (violation = 'X' and x_on_violation = "on") then
|
| 7593 |
|
|
iq := 'X';
|
| 7594 |
|
|
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
|
| 7595 |
|
|
if (ena_ipd = '1') then
|
| 7596 |
|
|
if (sclr_ipd = '1') then
|
| 7597 |
|
|
iq := '0';
|
| 7598 |
|
|
elsif (sload_ipd = '1') then
|
| 7599 |
|
|
iq := asdata_dly1;
|
| 7600 |
|
|
else
|
| 7601 |
|
|
iq := d_dly;
|
| 7602 |
|
|
end if;
|
| 7603 |
|
|
end if;
|
| 7604 |
|
|
end if;
|
| 7605 |
|
|
|
| 7606 |
|
|
----------------------
|
| 7607 |
|
|
-- Path Delay Section
|
| 7608 |
|
|
----------------------
|
| 7609 |
|
|
VitalPathDelay01 (
|
| 7610 |
|
|
OutSignal => q,
|
| 7611 |
|
|
OutSignalName => "Q",
|
| 7612 |
|
|
OutTemp => iq,
|
| 7613 |
|
|
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
|
| 7614 |
|
|
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
|
| 7615 |
|
|
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
|
| 7616 |
|
|
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
|
| 7617 |
|
|
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
|
| 7618 |
|
|
GlitchData => q_VitalGlitchData,
|
| 7619 |
|
|
Mode => DefGlitchMode,
|
| 7620 |
|
|
XOn => XOn,
|
| 7621 |
|
|
MsgOn => MsgOn );
|
| 7622 |
|
|
|
| 7623 |
|
|
end process;
|
| 7624 |
|
|
|
| 7625 |
|
|
end vital_stratixiii_ddr_io_reg;
|
| 7626 |
|
|
|
| 7627 |
|
|
-------------------------------------------------------------------------------
|
| 7628 |
|
|
--
|
| 7629 |
|
|
-- Entity Name : stratixiii_dll
|
| 7630 |
|
|
--
|
| 7631 |
|
|
-------------------------------------------------------------------------------
|
| 7632 |
|
|
|
| 7633 |
|
|
library IEEE;
|
| 7634 |
|
|
use IEEE.std_logic_1164.all;
|
| 7635 |
|
|
--use IEEE.std_logic_arith.all;
|
| 7636 |
|
|
--use IEEE.std_logic_unsigned.all;
|
| 7637 |
|
|
use IEEE.VITAL_Timing.all;
|
| 7638 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 7639 |
|
|
use work.stratixiii_atom_pack.all;
|
| 7640 |
|
|
use work.stratixiii_pllpack.all;
|
| 7641 |
|
|
use work.stratixiii_atom_ddr_pack.all;
|
| 7642 |
|
|
use work.stratixiii_dll_gray_encoder;
|
| 7643 |
|
|
library grlib;
|
| 7644 |
|
|
use grlib.stdlib.all;
|
| 7645 |
|
|
|
| 7646 |
|
|
ENTITY stratixiii_dll is
|
| 7647 |
|
|
GENERIC (
|
| 7648 |
|
|
input_frequency : string := "0 ps";
|
| 7649 |
|
|
delay_buffer_mode : string := "low";
|
| 7650 |
|
|
delay_chain_length : integer := 12;
|
| 7651 |
|
|
delayctrlout_mode : string := "normal";
|
| 7652 |
|
|
jitter_reduction : string := "false";
|
| 7653 |
|
|
use_upndnin : string := "false";
|
| 7654 |
|
|
use_upndninclkena : string := "false";
|
| 7655 |
|
|
dual_phase_comparators : string := "true";
|
| 7656 |
|
|
sim_valid_lock : integer := 16;
|
| 7657 |
|
|
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
|
| 7658 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 7659 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 7660 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 7661 |
|
|
static_delay_ctrl : integer := 0;
|
| 7662 |
|
|
lpm_type : string := "stratixiii_dll";
|
| 7663 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 7664 |
|
|
tipd_aload : VitalDelayType01 := DefpropDelay01;
|
| 7665 |
|
|
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
|
| 7666 |
|
|
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
|
| 7667 |
|
|
TimingChecksOn : Boolean := True;
|
| 7668 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 7669 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 7670 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 7671 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 7672 |
|
|
InstancePath : String := "*";
|
| 7673 |
|
|
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7674 |
|
|
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7675 |
|
|
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7676 |
|
|
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 7677 |
|
|
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 7678 |
|
|
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
|
| 7679 |
|
|
);
|
| 7680 |
|
|
|
| 7681 |
|
|
PORT ( clk : IN std_logic := '0';
|
| 7682 |
|
|
aload : IN std_logic := '0';
|
| 7683 |
|
|
upndnin : IN std_logic := '1';
|
| 7684 |
|
|
upndninclkena : IN std_logic := '1';
|
| 7685 |
|
|
devclrn : IN std_logic := '1';
|
| 7686 |
|
|
devpor : IN std_logic := '0';
|
| 7687 |
|
|
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
|
| 7688 |
|
|
dqsupdate : OUT std_logic;
|
| 7689 |
|
|
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
|
| 7690 |
|
|
offsetdelayctrlclkout : OUT std_logic;
|
| 7691 |
|
|
upndnout : OUT std_logic
|
| 7692 |
|
|
);
|
| 7693 |
|
|
|
| 7694 |
|
|
END stratixiii_dll;
|
| 7695 |
|
|
|
| 7696 |
|
|
|
| 7697 |
|
|
ARCHITECTURE vital_stratixiiidll of stratixiii_dll is
|
| 7698 |
|
|
|
| 7699 |
|
|
COMPONENT stratixiii_dll_gray_encoder
|
| 7700 |
|
|
GENERIC ( width : integer := 6 );
|
| 7701 |
|
|
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 7702 |
|
|
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
|
| 7703 |
|
|
);
|
| 7704 |
|
|
END COMPONENT;
|
| 7705 |
|
|
|
| 7706 |
|
|
signal clk_in : std_logic := '0';
|
| 7707 |
|
|
signal aload_in_buf : std_logic := '0';
|
| 7708 |
|
|
signal upndn_in : std_logic := '0';
|
| 7709 |
|
|
signal upndninclkena_in : std_logic := '1';
|
| 7710 |
|
|
signal addnsub_in : std_logic := '0';
|
| 7711 |
|
|
|
| 7712 |
|
|
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
|
| 7713 |
|
|
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
|
| 7714 |
|
|
signal upndn_out : std_logic := '0';
|
| 7715 |
|
|
signal dqsupdate_out : std_logic := '0';
|
| 7716 |
|
|
|
| 7717 |
|
|
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
|
| 7718 |
|
|
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
|
| 7719 |
|
|
signal para_static_delay_ctrl : integer := 0;
|
| 7720 |
|
|
signal para_jitter_reduction : std_logic := '0';
|
| 7721 |
|
|
signal para_use_upndnin : std_logic := '0';
|
| 7722 |
|
|
signal para_use_upndninclkena : std_logic := '1';
|
| 7723 |
|
|
|
| 7724 |
|
|
-- INTERNAL NETS AND VARIABLES
|
| 7725 |
|
|
|
| 7726 |
|
|
-- for functionality - by modules
|
| 7727 |
|
|
signal sim_buffer_intrinsic_delay : INTEGER := 0;
|
| 7728 |
|
|
|
| 7729 |
|
|
-- two reg on the de-assertion of dll
|
| 7730 |
|
|
SIGNAL aload_in : std_logic := '0';
|
| 7731 |
|
|
SIGNAL aload_reg1 : std_logic := '1';
|
| 7732 |
|
|
SIGNAL aload_reg2 : std_logic := '1';
|
| 7733 |
|
|
|
| 7734 |
|
|
-- delay and offset control out resolver
|
| 7735 |
|
|
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 7736 |
|
|
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 7737 |
|
|
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 7738 |
|
|
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 7739 |
|
|
signal dr_clk8_in : std_logic := '0';
|
| 7740 |
|
|
signal dr_aload_in : std_logic := '0';
|
| 7741 |
|
|
|
| 7742 |
|
|
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 7743 |
|
|
|
| 7744 |
|
|
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 7745 |
|
|
|
| 7746 |
|
|
|
| 7747 |
|
|
-- delay chain setting counter
|
| 7748 |
|
|
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 7749 |
|
|
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 7750 |
|
|
signal dc_dllcount_out : integer := 0;
|
| 7751 |
|
|
|
| 7752 |
|
|
signal dc_dqsupdate_out : std_logic := '0';
|
| 7753 |
|
|
signal dc_upndn_in : std_logic := '1';
|
| 7754 |
|
|
signal dc_aload_in : std_logic := '0';
|
| 7755 |
|
|
signal dc_upndnclkena_in : std_logic := '1';
|
| 7756 |
|
|
signal dc_clk8_in : std_logic := '0';
|
| 7757 |
|
|
signal dc_clk1_in : std_logic := '0';
|
| 7758 |
|
|
signal dc_dlltolock_in : std_logic := '0';
|
| 7759 |
|
|
|
| 7760 |
|
|
signal dc_reg_dllcount : integer := 0;
|
| 7761 |
|
|
signal dc_reg_dlltolock_pulse : std_logic := '0';
|
| 7762 |
|
|
|
| 7763 |
|
|
-- jitter reduction counter
|
| 7764 |
|
|
signal jc_upndn_out : std_logic := '0';
|
| 7765 |
|
|
signal jc_upndnclkena_out : std_logic := '1';
|
| 7766 |
|
|
signal jc_clk8_in : std_logic := '0';
|
| 7767 |
|
|
signal jc_upndn_in : std_logic := '1';
|
| 7768 |
|
|
signal jc_aload_in : std_logic := '0';
|
| 7769 |
|
|
signal jc_clkena_in : std_logic := '1'; -- new in stratixiii
|
| 7770 |
|
|
|
| 7771 |
|
|
signal jc_count : integer := 8;
|
| 7772 |
|
|
signal jc_reg_upndn : std_logic := '0';
|
| 7773 |
|
|
signal jc_reg_upndnclkena : std_logic := '0';
|
| 7774 |
|
|
|
| 7775 |
|
|
-- phase comparator
|
| 7776 |
|
|
signal pc_lock : std_logic := '0'; -- new in stratixiii
|
| 7777 |
|
|
signal pc_upndn_out : std_logic := '1';
|
| 7778 |
|
|
signal pc_dllcount_in : integer := 0;
|
| 7779 |
|
|
signal pc_clk1_in : std_logic := '0';
|
| 7780 |
|
|
signal pc_clk8_in : std_logic := '0';
|
| 7781 |
|
|
signal pc_aload_in : std_logic := '0';
|
| 7782 |
|
|
|
| 7783 |
|
|
signal pc_reg_upndn : std_logic := '1';
|
| 7784 |
|
|
signal pc_delay : integer := 0;
|
| 7785 |
|
|
signal pc_lock_reg : std_logic := '0'; -- new in stratixiii
|
| 7786 |
|
|
signal pc_comp_range : integer := 0; -- new in stratixiii
|
| 7787 |
|
|
|
| 7788 |
|
|
-- clock generator
|
| 7789 |
|
|
signal cg_clk_in : std_logic := '0';
|
| 7790 |
|
|
signal cg_aload_in : std_logic := '0';
|
| 7791 |
|
|
signal cg_clk1_out : std_logic := '0';
|
| 7792 |
|
|
|
| 7793 |
|
|
signal cg_clk8a_out : std_logic := '0';
|
| 7794 |
|
|
signal cg_clk8b_out : std_logic := '0';
|
| 7795 |
|
|
|
| 7796 |
|
|
-- por: 000
|
| 7797 |
|
|
signal cg_reg_1 : std_logic := '0';
|
| 7798 |
|
|
signal cg_rega_2 : std_logic := '0';
|
| 7799 |
|
|
signal cg_rega_3 : std_logic := '0';
|
| 7800 |
|
|
|
| 7801 |
|
|
-- por: 010
|
| 7802 |
|
|
signal cg_regb_2 : std_logic := '1';
|
| 7803 |
|
|
signal cg_regb_3 : std_logic := '0';
|
| 7804 |
|
|
|
| 7805 |
|
|
-- for violation checks
|
| 7806 |
|
|
signal dll_to_lock : std_logic := '0';
|
| 7807 |
|
|
signal input_period : integer := 10000;
|
| 7808 |
|
|
signal clk_in_last_value : std_logic := 'X';
|
| 7809 |
|
|
|
| 7810 |
|
|
|
| 7811 |
|
|
begin
|
| 7812 |
|
|
-- paramters
|
| 7813 |
|
|
input_period <= dqs_str2int(input_frequency);
|
| 7814 |
|
|
para_static_delay_ctrl <= static_delay_ctrl;
|
| 7815 |
|
|
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
|
| 7816 |
|
|
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
|
| 7817 |
|
|
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
|
| 7818 |
|
|
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
|
| 7819 |
|
|
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
|
| 7820 |
|
|
|
| 7821 |
|
|
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
|
| 7822 |
|
|
sim_high_buffer_intrinsic_delay;
|
| 7823 |
|
|
|
| 7824 |
|
|
-- violation check block
|
| 7825 |
|
|
process (clk_in)
|
| 7826 |
|
|
|
| 7827 |
|
|
variable got_first_rising_edge : std_logic := '0';
|
| 7828 |
|
|
variable got_first_falling_edge : std_logic := '0';
|
| 7829 |
|
|
|
| 7830 |
|
|
variable per_violation : std_logic := '0';
|
| 7831 |
|
|
variable duty_violation : std_logic := '0';
|
| 7832 |
|
|
variable sent_per_violation : std_logic := '0';
|
| 7833 |
|
|
variable sent_duty_violation : std_logic := '0';
|
| 7834 |
|
|
|
| 7835 |
|
|
variable clk_in_last_rising_edge : time := 0 ps;
|
| 7836 |
|
|
variable clk_in_last_falling_edge : time := 0 ps;
|
| 7837 |
|
|
|
| 7838 |
|
|
variable input_period_ps : time := 10000 ps;
|
| 7839 |
|
|
variable duty_cycle : time := 5000 ps;
|
| 7840 |
|
|
variable clk_in_period : time := 10000 ps;
|
| 7841 |
|
|
variable clk_in_duty_cycle : time := 5000 ps;
|
| 7842 |
|
|
variable clk_per_tolerance : time := 2 ps;
|
| 7843 |
|
|
variable half_cycles_to_lock : integer := 1;
|
| 7844 |
|
|
|
| 7845 |
|
|
variable init : boolean := true;
|
| 7846 |
|
|
|
| 7847 |
|
|
begin
|
| 7848 |
|
|
if (init) then
|
| 7849 |
|
|
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
|
| 7850 |
|
|
if (input_period_ps = 0 ps) then
|
| 7851 |
|
|
assert false report "Need to specify ps scale in simulation command" severity error;
|
| 7852 |
|
|
end if;
|
| 7853 |
|
|
|
| 7854 |
|
|
duty_cycle := input_period_ps/2;
|
| 7855 |
|
|
clk_per_tolerance := 2 ps;
|
| 7856 |
|
|
half_cycles_to_lock := 0;
|
| 7857 |
|
|
init := false;
|
| 7858 |
|
|
end if;
|
| 7859 |
|
|
|
| 7860 |
|
|
if (clk_in'event and clk_in = '1') then -- rising edge
|
| 7861 |
|
|
if (got_first_rising_edge = '0') then
|
| 7862 |
|
|
got_first_rising_edge := '1';
|
| 7863 |
|
|
else -- subsequent rising
|
| 7864 |
|
|
-- check for clock period and duty cycle violation
|
| 7865 |
|
|
clk_in_period := now - clk_in_last_rising_edge;
|
| 7866 |
|
|
clk_in_duty_cycle := now - clk_in_last_falling_edge;
|
| 7867 |
|
|
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
|
| 7868 |
|
|
per_violation := '1';
|
| 7869 |
|
|
if (sent_per_violation /= '1') then
|
| 7870 |
|
|
sent_per_violation := '1';
|
| 7871 |
|
|
assert false report "Input clock frequency violation." severity warning;
|
| 7872 |
|
|
end if;
|
| 7873 |
|
|
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
|
| 7874 |
|
|
duty_violation := '1';
|
| 7875 |
|
|
if (sent_duty_violation /= '1') then
|
| 7876 |
|
|
sent_duty_violation := '1';
|
| 7877 |
|
|
assert false report "Input clock duty cycle violation." severity warning;
|
| 7878 |
|
|
end if;
|
| 7879 |
|
|
else
|
| 7880 |
|
|
if (per_violation = '1') then
|
| 7881 |
|
|
sent_per_violation := '0';
|
| 7882 |
|
|
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
|
| 7883 |
|
|
end if;
|
| 7884 |
|
|
per_violation := '0';
|
| 7885 |
|
|
duty_violation := '0';
|
| 7886 |
|
|
end if;
|
| 7887 |
|
|
end if;
|
| 7888 |
|
|
|
| 7889 |
|
|
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
|
| 7890 |
|
|
half_cycles_to_lock := half_cycles_to_lock + 1;
|
| 7891 |
|
|
if (half_cycles_to_lock >= sim_valid_lock) then
|
| 7892 |
|
|
dll_to_lock <= '1';
|
| 7893 |
|
|
assert false report "DLL to lock to incoming clock" severity note;
|
| 7894 |
|
|
end if;
|
| 7895 |
|
|
end if;
|
| 7896 |
|
|
clk_in_last_rising_edge := now;
|
| 7897 |
|
|
elsif (clk_in'event and clk_in = '0') then -- falling edge
|
| 7898 |
|
|
got_first_falling_edge := '1';
|
| 7899 |
|
|
if (got_first_rising_edge = '1') then
|
| 7900 |
|
|
-- duty cycle check
|
| 7901 |
|
|
clk_in_duty_cycle := now - clk_in_last_rising_edge;
|
| 7902 |
|
|
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
|
| 7903 |
|
|
duty_violation := '1';
|
| 7904 |
|
|
if (sent_duty_violation /= '1') then
|
| 7905 |
|
|
sent_duty_violation := '1';
|
| 7906 |
|
|
assert false report "Input clock duty cycle violation." severity warning;
|
| 7907 |
|
|
end if;
|
| 7908 |
|
|
else
|
| 7909 |
|
|
duty_violation := '0';
|
| 7910 |
|
|
end if;
|
| 7911 |
|
|
|
| 7912 |
|
|
if (dll_to_lock = '0' and duty_violation = '0') then
|
| 7913 |
|
|
half_cycles_to_lock := half_cycles_to_lock + 1;
|
| 7914 |
|
|
end if;
|
| 7915 |
|
|
end if;
|
| 7916 |
|
|
clk_in_last_falling_edge := now;
|
| 7917 |
|
|
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
|
| 7918 |
|
|
-- switches from 1, 0 to X
|
| 7919 |
|
|
half_cycles_to_lock := 0;
|
| 7920 |
|
|
got_first_rising_edge := '0';
|
| 7921 |
|
|
got_first_falling_edge := '0';
|
| 7922 |
|
|
if (dll_to_lock = '1') then
|
| 7923 |
|
|
dll_to_lock <= '0';
|
| 7924 |
|
|
assert false report "Illegal value detected on input clock. DLL will lose lock." severity error;
|
| 7925 |
|
|
else
|
| 7926 |
|
|
assert false report "Illegal value detected on input clock." severity error;
|
| 7927 |
|
|
end if;
|
| 7928 |
|
|
end if;
|
| 7929 |
|
|
|
| 7930 |
|
|
clk_in_last_value <= clk_in;
|
| 7931 |
|
|
|
| 7932 |
|
|
end process ; -- violation check
|
| 7933 |
|
|
|
| 7934 |
|
|
|
| 7935 |
|
|
-- outputs
|
| 7936 |
|
|
delayctrl_out <= dr_delayctrl_out;
|
| 7937 |
|
|
offsetdelayctrl_out <= dr_offsetctrl_out;
|
| 7938 |
|
|
offsetdelayctrlclkout <= dr_clk8_in;
|
| 7939 |
|
|
dqsupdate_out <= cg_clk8a_out;
|
| 7940 |
|
|
upndn_out <= pc_upndn_out;
|
| 7941 |
|
|
|
| 7942 |
|
|
-- two registers on aload path --------------------------------------------
|
| 7943 |
|
|
aload_in <= (aload_in_buf OR aload_reg2);
|
| 7944 |
|
|
|
| 7945 |
|
|
process(clk_in)
|
| 7946 |
|
|
begin
|
| 7947 |
|
|
if (clk_in = '0' and clk_in'event) then
|
| 7948 |
|
|
aload_reg2 <= aload_reg1;
|
| 7949 |
|
|
aload_reg1 <= aload_in_buf;
|
| 7950 |
|
|
end if;
|
| 7951 |
|
|
end process;
|
| 7952 |
|
|
|
| 7953 |
|
|
-- Delay and offset ctrl out resolver -------------------------------------
|
| 7954 |
|
|
-------- convert calculations into integer
|
| 7955 |
|
|
|
| 7956 |
|
|
-- inputs
|
| 7957 |
|
|
dr_clk8_in <= not cg_clk8b_out;
|
| 7958 |
|
|
dr_dllcount_in <= dc_dllcount_out_gray;
|
| 7959 |
|
|
dr_aload_in <= aload_in;
|
| 7960 |
|
|
|
| 7961 |
|
|
mdll_count_enc : stratixiii_dll_gray_encoder
|
| 7962 |
|
|
GENERIC MAP (width => 6)
|
| 7963 |
|
|
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
|
| 7964 |
|
|
|
| 7965 |
|
|
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
|
| 7966 |
|
|
|
| 7967 |
|
|
-- outputs
|
| 7968 |
|
|
dr_delayctrl_out <= dr_reg_dllcount;
|
| 7969 |
|
|
dr_offsetctrl_out <= dr_delayctrl_int;
|
| 7970 |
|
|
|
| 7971 |
|
|
-- assumed para_static_delay_ctrl is gray-coded
|
| 7972 |
|
|
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
|
| 7973 |
|
|
|
| 7974 |
|
|
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
|
| 7975 |
|
|
dr_dllcount_in;
|
| 7976 |
|
|
|
| 7977 |
|
|
|
| 7978 |
|
|
-- model
|
| 7979 |
|
|
process(dr_clk8_in, dr_aload_in)
|
| 7980 |
|
|
begin
|
| 7981 |
|
|
if (dr_aload_in = '1' and dr_aload_in'event) then
|
| 7982 |
|
|
dr_reg_dllcount <= "000000";
|
| 7983 |
|
|
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
|
| 7984 |
|
|
dr_reg_dllcount <= dr_delayctrl_int;
|
| 7985 |
|
|
end if;
|
| 7986 |
|
|
end process;
|
| 7987 |
|
|
|
| 7988 |
|
|
|
| 7989 |
|
|
-- Delay Setting Control Counter ------------------------------------------
|
| 7990 |
|
|
|
| 7991 |
|
|
--inputs
|
| 7992 |
|
|
dc_dlltolock_in <= dll_to_lock;
|
| 7993 |
|
|
dc_aload_in <= aload_in;
|
| 7994 |
|
|
dc_clk1_in <= cg_clk1_out;
|
| 7995 |
|
|
dc_clk8_in <= not cg_clk8b_out;
|
| 7996 |
|
|
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
|
| 7997 |
|
|
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
|
| 7998 |
|
|
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
|
| 7999 |
|
|
'1';
|
| 8000 |
|
|
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
|
| 8001 |
|
|
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
|
| 8002 |
|
|
pc_upndn_out;
|
| 8003 |
|
|
|
| 8004 |
|
|
-- outputs
|
| 8005 |
|
|
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
|
| 8006 |
|
|
|
| 8007 |
|
|
-- dll counter logic
|
| 8008 |
|
|
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
|
| 8009 |
|
|
variable dc_var_dllcount : integer := 64;
|
| 8010 |
|
|
variable init : boolean := true;
|
| 8011 |
|
|
begin
|
| 8012 |
|
|
if (init) then
|
| 8013 |
|
|
if (delay_buffer_mode = "low") then
|
| 8014 |
|
|
dc_var_dllcount := 32;
|
| 8015 |
|
|
else
|
| 8016 |
|
|
dc_var_dllcount := 16;
|
| 8017 |
|
|
end if;
|
| 8018 |
|
|
init := false;
|
| 8019 |
|
|
end if;
|
| 8020 |
|
|
|
| 8021 |
|
|
if (dc_aload_in = '1' and dc_aload_in'event) then
|
| 8022 |
|
|
if (delay_buffer_mode = "low") then
|
| 8023 |
|
|
dc_var_dllcount := 32;
|
| 8024 |
|
|
else
|
| 8025 |
|
|
dc_var_dllcount := 16;
|
| 8026 |
|
|
end if;
|
| 8027 |
|
|
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
|
| 8028 |
|
|
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
|
| 8029 |
|
|
dc_var_dllcount := sim_valid_lockcount;
|
| 8030 |
|
|
dc_reg_dlltolock_pulse <= '1';
|
| 8031 |
|
|
elsif (dc_aload_in /= '1' and
|
| 8032 |
|
|
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
|
| 8033 |
|
|
if (dc_upndn_in = '1') then
|
| 8034 |
|
|
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
|
| 8035 |
|
|
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
|
| 8036 |
|
|
dc_var_dllcount := dc_var_dllcount + 1;
|
| 8037 |
|
|
end if;
|
| 8038 |
|
|
elsif (dc_upndn_in = '0') then
|
| 8039 |
|
|
if (dc_var_dllcount > 0) then
|
| 8040 |
|
|
dc_var_dllcount := dc_var_dllcount - 1;
|
| 8041 |
|
|
end if;
|
| 8042 |
|
|
end if;
|
| 8043 |
|
|
end if; -- rising clock
|
| 8044 |
|
|
|
| 8045 |
|
|
-- schedule signal dc_reg_dllcount
|
| 8046 |
|
|
dc_reg_dllcount <= dc_var_dllcount;
|
| 8047 |
|
|
end process;
|
| 8048 |
|
|
|
| 8049 |
|
|
-- Jitter reduction counter -----------------------------------------------
|
| 8050 |
|
|
|
| 8051 |
|
|
-- inputs
|
| 8052 |
|
|
jc_clk8_in <= not cg_clk8b_out;
|
| 8053 |
|
|
jc_upndn_in <= pc_upndn_out;
|
| 8054 |
|
|
jc_aload_in <= aload_in;
|
| 8055 |
|
|
|
| 8056 |
|
|
-- new in stratixiii
|
| 8057 |
|
|
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
|
| 8058 |
|
|
|
| 8059 |
|
|
-- outputs
|
| 8060 |
|
|
jc_upndn_out <= jc_reg_upndn;
|
| 8061 |
|
|
jc_upndnclkena_out <= jc_reg_upndnclkena;
|
| 8062 |
|
|
|
| 8063 |
|
|
-- Model
|
| 8064 |
|
|
process (jc_clk8_in, jc_aload_in)
|
| 8065 |
|
|
begin
|
| 8066 |
|
|
if (jc_aload_in = '1' and jc_aload_in'event) then
|
| 8067 |
|
|
jc_count <= 8;
|
| 8068 |
|
|
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
|
| 8069 |
|
|
if (jc_clkena_in = '1') then
|
| 8070 |
|
|
if (jc_count = 12) then
|
| 8071 |
|
|
jc_reg_upndn <= '1';
|
| 8072 |
|
|
jc_reg_upndnclkena <= '1';
|
| 8073 |
|
|
jc_count <= 8;
|
| 8074 |
|
|
elsif (jc_count = 4) then
|
| 8075 |
|
|
jc_reg_upndn <= '0';
|
| 8076 |
|
|
jc_reg_upndnclkena <= '1';
|
| 8077 |
|
|
jc_count <= 8;
|
| 8078 |
|
|
else -- increment/decrement counter
|
| 8079 |
|
|
jc_reg_upndnclkena <= '0';
|
| 8080 |
|
|
if (jc_upndn_in = '1') then
|
| 8081 |
|
|
jc_count <= jc_count + 1;
|
| 8082 |
|
|
elsif (jc_upndn_in = '0') then
|
| 8083 |
|
|
jc_count <= jc_count - 1;
|
| 8084 |
|
|
end if;
|
| 8085 |
|
|
end if;
|
| 8086 |
|
|
else -- not clkena
|
| 8087 |
|
|
jc_reg_upndnclkena <= '0';
|
| 8088 |
|
|
end if;
|
| 8089 |
|
|
end if;
|
| 8090 |
|
|
end process;
|
| 8091 |
|
|
|
| 8092 |
|
|
-- Phase comparator -------------------------------------------------------
|
| 8093 |
|
|
|
| 8094 |
|
|
-- inputs
|
| 8095 |
|
|
pc_clk1_in <= cg_clk1_out;
|
| 8096 |
|
|
pc_clk8_in <= cg_clk8b_out; -- positive
|
| 8097 |
|
|
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
|
| 8098 |
|
|
pc_aload_in <= aload_in;
|
| 8099 |
|
|
|
| 8100 |
|
|
-- outputs
|
| 8101 |
|
|
pc_upndn_out <= pc_reg_upndn;
|
| 8102 |
|
|
pc_lock <= pc_lock_reg;
|
| 8103 |
|
|
|
| 8104 |
|
|
-- parameter used
|
| 8105 |
|
|
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
|
| 8106 |
|
|
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
|
| 8107 |
|
|
|
| 8108 |
|
|
-- Model
|
| 8109 |
|
|
process (pc_clk8_in, pc_aload_in)
|
| 8110 |
|
|
variable pc_var_delay : integer := 0;
|
| 8111 |
|
|
begin
|
| 8112 |
|
|
if (pc_aload_in = '1' and pc_aload_in'event) then
|
| 8113 |
|
|
pc_var_delay := 0;
|
| 8114 |
|
|
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
|
| 8115 |
|
|
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
|
| 8116 |
|
|
pc_delay <= pc_var_delay;
|
| 8117 |
|
|
|
| 8118 |
|
|
if (dual_phase_comparators = "false") then
|
| 8119 |
|
|
if (pc_var_delay > input_period) then
|
| 8120 |
|
|
pc_reg_upndn <= '0';
|
| 8121 |
|
|
else
|
| 8122 |
|
|
pc_reg_upndn <= '1';
|
| 8123 |
|
|
end if;
|
| 8124 |
|
|
else -- use dual phase
|
| 8125 |
|
|
if (pc_var_delay < (input_period - pc_comp_range/2)) then
|
| 8126 |
|
|
pc_reg_upndn <= '1';
|
| 8127 |
|
|
pc_lock_reg <= '0';
|
| 8128 |
|
|
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
|
| 8129 |
|
|
pc_reg_upndn <= '0';
|
| 8130 |
|
|
pc_lock_reg <= '1';
|
| 8131 |
|
|
else
|
| 8132 |
|
|
pc_reg_upndn <= '0';
|
| 8133 |
|
|
pc_lock_reg <= '0';
|
| 8134 |
|
|
end if;
|
| 8135 |
|
|
end if;
|
| 8136 |
|
|
end if;
|
| 8137 |
|
|
end process;
|
| 8138 |
|
|
|
| 8139 |
|
|
-- Clock Generator -------------------------------------------------------
|
| 8140 |
|
|
|
| 8141 |
|
|
-- inputs
|
| 8142 |
|
|
cg_clk_in <= clk_in;
|
| 8143 |
|
|
cg_aload_in <= aload_in;
|
| 8144 |
|
|
|
| 8145 |
|
|
-- outputs
|
| 8146 |
|
|
cg_clk8a_out <= cg_rega_3;
|
| 8147 |
|
|
cg_clk8b_out <= cg_regb_3;
|
| 8148 |
|
|
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
|
| 8149 |
|
|
|
| 8150 |
|
|
-- Model
|
| 8151 |
|
|
process(cg_clk1_out, cg_aload_in)
|
| 8152 |
|
|
begin
|
| 8153 |
|
|
if (cg_aload_in = '1' and cg_aload_in'event) then
|
| 8154 |
|
|
cg_reg_1 <= '0';
|
| 8155 |
|
|
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
|
| 8156 |
|
|
cg_reg_1 <= not cg_reg_1;
|
| 8157 |
|
|
end if;
|
| 8158 |
|
|
end process;
|
| 8159 |
|
|
|
| 8160 |
|
|
process(cg_reg_1, cg_aload_in)
|
| 8161 |
|
|
begin
|
| 8162 |
|
|
if (cg_aload_in = '1' and cg_aload_in'event) then
|
| 8163 |
|
|
cg_rega_2 <= '0';
|
| 8164 |
|
|
cg_regb_2 <= '1';
|
| 8165 |
|
|
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
|
| 8166 |
|
|
cg_rega_2 <= not cg_rega_2;
|
| 8167 |
|
|
cg_regb_2 <= not cg_regb_2;
|
| 8168 |
|
|
end if;
|
| 8169 |
|
|
end process;
|
| 8170 |
|
|
|
| 8171 |
|
|
process (cg_rega_2, cg_aload_in)
|
| 8172 |
|
|
begin
|
| 8173 |
|
|
if (cg_aload_in = '1' and cg_aload_in'event) then
|
| 8174 |
|
|
cg_rega_3 <= '0';
|
| 8175 |
|
|
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
|
| 8176 |
|
|
cg_rega_3 <= not cg_rega_3;
|
| 8177 |
|
|
end if;
|
| 8178 |
|
|
end process;
|
| 8179 |
|
|
|
| 8180 |
|
|
process (cg_regb_2, cg_aload_in)
|
| 8181 |
|
|
begin
|
| 8182 |
|
|
if (cg_aload_in = '1' and cg_aload_in'event) then
|
| 8183 |
|
|
cg_regb_3 <= '0';
|
| 8184 |
|
|
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
|
| 8185 |
|
|
cg_regb_3 <= not cg_regb_3;
|
| 8186 |
|
|
end if;
|
| 8187 |
|
|
end process;
|
| 8188 |
|
|
|
| 8189 |
|
|
--------------------
|
| 8190 |
|
|
-- INPUT PATH DELAYS
|
| 8191 |
|
|
--------------------
|
| 8192 |
|
|
WireDelay : block
|
| 8193 |
|
|
begin
|
| 8194 |
|
|
VitalWireDelay (clk_in, clk, tipd_clk);
|
| 8195 |
|
|
VitalWireDelay (aload_in_buf, aload, tipd_aload);
|
| 8196 |
|
|
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
|
| 8197 |
|
|
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
|
| 8198 |
|
|
end block;
|
| 8199 |
|
|
|
| 8200 |
|
|
------------------------
|
| 8201 |
|
|
-- Timing Check Section
|
| 8202 |
|
|
------------------------
|
| 8203 |
|
|
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
|
| 8204 |
|
|
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
|
| 8205 |
|
|
|
| 8206 |
|
|
variable Tviol_upndnin_clk : std_ulogic := '0';
|
| 8207 |
|
|
variable Tviol_upndninclkena_clk : std_ulogic := '0';
|
| 8208 |
|
|
|
| 8209 |
|
|
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 8210 |
|
|
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 8211 |
|
|
|
| 8212 |
|
|
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
|
| 8213 |
|
|
variable upndnout_VitalGlitchData : VitalGlitchDataType;
|
| 8214 |
|
|
|
| 8215 |
|
|
begin
|
| 8216 |
|
|
|
| 8217 |
|
|
if (TimingChecksOn) then
|
| 8218 |
|
|
|
| 8219 |
|
|
|
| 8220 |
|
|
VitalSetupHoldCheck (
|
| 8221 |
|
|
Violation => Tviol_upndnin_clk,
|
| 8222 |
|
|
TimingData => TimingData_upndnin_clk,
|
| 8223 |
|
|
TestSignal => upndn_in,
|
| 8224 |
|
|
TestSignalName => "UPNDNIN",
|
| 8225 |
|
|
RefSignal => clk_in,
|
| 8226 |
|
|
RefSignalName => "CLK",
|
| 8227 |
|
|
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
|
| 8228 |
|
|
SetupLow => tsetup_upndnin_clk_noedge_posedge,
|
| 8229 |
|
|
HoldHigh => thold_upndnin_clk_noedge_posedge,
|
| 8230 |
|
|
HoldLow => thold_upndnin_clk_noedge_posedge,
|
| 8231 |
|
|
RefTransition => '/',
|
| 8232 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
|
| 8233 |
|
|
XOn => XOn,
|
| 8234 |
|
|
MsgOn => MsgOnChecks );
|
| 8235 |
|
|
|
| 8236 |
|
|
VitalSetupHoldCheck (
|
| 8237 |
|
|
Violation => Tviol_upndninclkena_clk,
|
| 8238 |
|
|
TimingData => TimingData_upndninclkena_clk,
|
| 8239 |
|
|
TestSignal => upndninclkena_in,
|
| 8240 |
|
|
TestSignalName => "UPNDNINCLKENA",
|
| 8241 |
|
|
RefSignal => clk_in,
|
| 8242 |
|
|
RefSignalName => "CLK",
|
| 8243 |
|
|
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
|
| 8244 |
|
|
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
|
| 8245 |
|
|
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
|
| 8246 |
|
|
HoldLow => thold_upndninclkena_clk_noedge_posedge,
|
| 8247 |
|
|
RefTransition => '/',
|
| 8248 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
|
| 8249 |
|
|
XOn => XOn,
|
| 8250 |
|
|
MsgOn => MsgOnChecks );
|
| 8251 |
|
|
|
| 8252 |
|
|
end if;
|
| 8253 |
|
|
|
| 8254 |
|
|
----------------------
|
| 8255 |
|
|
-- Path Delay Section
|
| 8256 |
|
|
----------------------
|
| 8257 |
|
|
|
| 8258 |
|
|
offsetdelayctrlout <= offsetdelayctrl_out;
|
| 8259 |
|
|
dqsupdate <= dqsupdate_out;
|
| 8260 |
|
|
|
| 8261 |
|
|
VitalPathDelay01 (
|
| 8262 |
|
|
OutSignal => upndnout,
|
| 8263 |
|
|
OutSignalName => "UPNDNOUT",
|
| 8264 |
|
|
OutTemp => upndn_out,
|
| 8265 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
|
| 8266 |
|
|
GlitchData => upndnout_VitalGlitchData,
|
| 8267 |
|
|
Mode => DefGlitchMode,
|
| 8268 |
|
|
XOn => XOn,
|
| 8269 |
|
|
MsgOn => MsgOn );
|
| 8270 |
|
|
|
| 8271 |
|
|
VitalPathDelay01 (
|
| 8272 |
|
|
OutSignal => delayctrlout(0),
|
| 8273 |
|
|
OutSignalName => "DELAYCTRLOUT",
|
| 8274 |
|
|
OutTemp => delayctrl_out(0),
|
| 8275 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
|
| 8276 |
|
|
GlitchData => delayctrlout_VitalGlitchDataArray(0),
|
| 8277 |
|
|
Mode => DefGlitchMode,
|
| 8278 |
|
|
XOn => XOn,
|
| 8279 |
|
|
MsgOn => MsgOn );
|
| 8280 |
|
|
|
| 8281 |
|
|
VitalPathDelay01 (
|
| 8282 |
|
|
OutSignal => delayctrlout(1),
|
| 8283 |
|
|
OutSignalName => "DELAYCTRLOUT",
|
| 8284 |
|
|
OutTemp => delayctrl_out(1),
|
| 8285 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
|
| 8286 |
|
|
GlitchData => delayctrlout_VitalGlitchDataArray(1),
|
| 8287 |
|
|
Mode => DefGlitchMode,
|
| 8288 |
|
|
XOn => XOn,
|
| 8289 |
|
|
MsgOn => MsgOn );
|
| 8290 |
|
|
|
| 8291 |
|
|
VitalPathDelay01 (
|
| 8292 |
|
|
OutSignal => delayctrlout(2),
|
| 8293 |
|
|
OutSignalName => "DELAYCTRLOUT",
|
| 8294 |
|
|
OutTemp => delayctrl_out(2),
|
| 8295 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
|
| 8296 |
|
|
GlitchData => delayctrlout_VitalGlitchDataArray(2),
|
| 8297 |
|
|
Mode => DefGlitchMode,
|
| 8298 |
|
|
XOn => XOn,
|
| 8299 |
|
|
MsgOn => MsgOn );
|
| 8300 |
|
|
|
| 8301 |
|
|
VitalPathDelay01 (
|
| 8302 |
|
|
OutSignal => delayctrlout(3),
|
| 8303 |
|
|
OutSignalName => "DELAYCTRLOUT",
|
| 8304 |
|
|
OutTemp => delayctrl_out(3),
|
| 8305 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
|
| 8306 |
|
|
GlitchData => delayctrlout_VitalGlitchDataArray(3),
|
| 8307 |
|
|
Mode => DefGlitchMode,
|
| 8308 |
|
|
XOn => XOn,
|
| 8309 |
|
|
MsgOn => MsgOn );
|
| 8310 |
|
|
|
| 8311 |
|
|
VitalPathDelay01 (
|
| 8312 |
|
|
OutSignal => delayctrlout(4),
|
| 8313 |
|
|
OutSignalName => "DELAYCTRLOUT",
|
| 8314 |
|
|
OutTemp => delayctrl_out(4),
|
| 8315 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
|
| 8316 |
|
|
GlitchData => delayctrlout_VitalGlitchDataArray(4),
|
| 8317 |
|
|
Mode => DefGlitchMode,
|
| 8318 |
|
|
XOn => XOn,
|
| 8319 |
|
|
MsgOn => MsgOn );
|
| 8320 |
|
|
|
| 8321 |
|
|
VitalPathDelay01 (
|
| 8322 |
|
|
OutSignal => delayctrlout(5),
|
| 8323 |
|
|
OutSignalName => "DELAYCTRLOUT",
|
| 8324 |
|
|
OutTemp => delayctrl_out(5),
|
| 8325 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
|
| 8326 |
|
|
GlitchData => delayctrlout_VitalGlitchDataArray(5),
|
| 8327 |
|
|
Mode => DefGlitchMode,
|
| 8328 |
|
|
XOn => XOn,
|
| 8329 |
|
|
MsgOn => MsgOn );
|
| 8330 |
|
|
|
| 8331 |
|
|
end process; -- vital timing
|
| 8332 |
|
|
|
| 8333 |
|
|
end vital_stratixiiidll;
|
| 8334 |
|
|
|
| 8335 |
|
|
-------------------------------------------------------------------------------
|
| 8336 |
|
|
--
|
| 8337 |
|
|
-- Entity Name : stratixiii_dll_offset_ctrl
|
| 8338 |
|
|
--
|
| 8339 |
|
|
-------------------------------------------------------------------------------
|
| 8340 |
|
|
|
| 8341 |
|
|
library IEEE;
|
| 8342 |
|
|
use IEEE.std_logic_1164.all;
|
| 8343 |
|
|
--use IEEE.std_logic_arith.all;
|
| 8344 |
|
|
--use IEEE.std_logic_unsigned.all;
|
| 8345 |
|
|
use IEEE.VITAL_Timing.all;
|
| 8346 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 8347 |
|
|
use work.stratixiii_atom_pack.all;
|
| 8348 |
|
|
USE work.stratixiii_pllpack.all;
|
| 8349 |
|
|
use work.stratixiii_atom_ddr_pack.all;
|
| 8350 |
|
|
use work.stratixiii_dll_gray_encoder;
|
| 8351 |
|
|
use work.stratixiii_dll_gray_decoder;
|
| 8352 |
|
|
library grlib;
|
| 8353 |
|
|
use grlib.stdlib.all;
|
| 8354 |
|
|
|
| 8355 |
|
|
ENTITY stratixiii_dll_offset_ctrl is
|
| 8356 |
|
|
GENERIC (
|
| 8357 |
|
|
use_offset : string := "false";
|
| 8358 |
|
|
static_offset : string := "0";
|
| 8359 |
|
|
delay_buffer_mode : string := "low";
|
| 8360 |
|
|
lpm_type : string := "stratixiii_dll_offset_ctrl";
|
| 8361 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 8362 |
|
|
tipd_aload : VitalDelayType01 := DefpropDelay01;
|
| 8363 |
|
|
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
| 8364 |
|
|
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
| 8365 |
|
|
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
|
| 8366 |
|
|
TimingChecksOn : Boolean := True;
|
| 8367 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 8368 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 8369 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 8370 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 8371 |
|
|
InstancePath : String := "*";
|
| 8372 |
|
|
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
|
| 8373 |
|
|
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
|
| 8374 |
|
|
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 8375 |
|
|
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 8376 |
|
|
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
|
| 8377 |
|
|
);
|
| 8378 |
|
|
|
| 8379 |
|
|
PORT ( clk : IN std_logic := '0';
|
| 8380 |
|
|
aload : IN std_logic := '0';
|
| 8381 |
|
|
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
|
| 8382 |
|
|
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
|
| 8383 |
|
|
addnsub : IN std_logic := '1';
|
| 8384 |
|
|
devclrn : IN std_logic := '1';
|
| 8385 |
|
|
devpor : IN std_logic := '0';
|
| 8386 |
|
|
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
|
| 8387 |
|
|
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
|
| 8388 |
|
|
);
|
| 8389 |
|
|
|
| 8390 |
|
|
END stratixiii_dll_offset_ctrl;
|
| 8391 |
|
|
|
| 8392 |
|
|
|
| 8393 |
|
|
ARCHITECTURE vital_stratixiiioffset of stratixiii_dll_offset_ctrl is
|
| 8394 |
|
|
|
| 8395 |
|
|
COMPONENT stratixiii_dll_gray_encoder
|
| 8396 |
|
|
GENERIC ( width : integer := 6 );
|
| 8397 |
|
|
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 8398 |
|
|
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
|
| 8399 |
|
|
);
|
| 8400 |
|
|
END COMPONENT;
|
| 8401 |
|
|
|
| 8402 |
|
|
COMPONENT stratixiii_dll_gray_decoder
|
| 8403 |
|
|
GENERIC ( width : integer := 6 );
|
| 8404 |
|
|
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 8405 |
|
|
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
|
| 8406 |
|
|
);
|
| 8407 |
|
|
END COMPONENT;
|
| 8408 |
|
|
|
| 8409 |
|
|
signal clk_in : std_logic := '0';
|
| 8410 |
|
|
signal aload_in : std_logic := '0';
|
| 8411 |
|
|
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
|
| 8412 |
|
|
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
|
| 8413 |
|
|
signal addnsub_in : std_logic := '0';
|
| 8414 |
|
|
|
| 8415 |
|
|
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
|
| 8416 |
|
|
|
| 8417 |
|
|
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
|
| 8418 |
|
|
signal para_use_offset : std_logic := '0';
|
| 8419 |
|
|
signal para_static_offset : integer := 0;
|
| 8420 |
|
|
signal para_static_offset_pos : integer := 0;
|
| 8421 |
|
|
|
| 8422 |
|
|
-- INTERNAL NETS AND VARIABLES
|
| 8423 |
|
|
|
| 8424 |
|
|
-- for functionality - by modules
|
| 8425 |
|
|
|
| 8426 |
|
|
-- two reg on the de-assertion of aload
|
| 8427 |
|
|
SIGNAL aload_reg1 : std_logic := '1';
|
| 8428 |
|
|
SIGNAL aload_reg2 : std_logic := '1';
|
| 8429 |
|
|
|
| 8430 |
|
|
-- delay and offset control out resolver
|
| 8431 |
|
|
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8432 |
|
|
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8433 |
|
|
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8434 |
|
|
signal dr_addnsub_in : std_logic := '1';
|
| 8435 |
|
|
signal dr_clk8_in : std_logic := '0';
|
| 8436 |
|
|
signal dr_aload_in : std_logic := '0';
|
| 8437 |
|
|
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8438 |
|
|
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8439 |
|
|
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8440 |
|
|
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
|
| 8441 |
|
|
|
| 8442 |
|
|
-- docoder
|
| 8443 |
|
|
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8444 |
|
|
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8445 |
|
|
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
|
| 8446 |
|
|
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8447 |
|
|
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
|
| 8448 |
|
|
|
| 8449 |
|
|
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
|
| 8450 |
|
|
|
| 8451 |
|
|
begin
|
| 8452 |
|
|
-- paramters
|
| 8453 |
|
|
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
|
| 8454 |
|
|
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
|
| 8455 |
|
|
para_static_offset <= dqs_str2int(static_offset); -- signed int
|
| 8456 |
|
|
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
|
| 8457 |
|
|
|
| 8458 |
|
|
-- outputs
|
| 8459 |
|
|
offsetctrl_out <= dr_offsetctrl_out_gray;
|
| 8460 |
|
|
offsettestout <= dr_offsettest_out;
|
| 8461 |
|
|
|
| 8462 |
|
|
-- two registers on aload path --------------------------------------------
|
| 8463 |
|
|
-- it should be user clock to DLL, not the /8 clock of offsetctrl
|
| 8464 |
|
|
process(clk_in)
|
| 8465 |
|
|
begin
|
| 8466 |
|
|
if (clk_in = '0' and clk_in'event) then
|
| 8467 |
|
|
aload_reg2 <= aload_reg1;
|
| 8468 |
|
|
aload_reg1 <= aload_in;
|
| 8469 |
|
|
end if;
|
| 8470 |
|
|
end process;
|
| 8471 |
|
|
|
| 8472 |
|
|
-- Delay and offset ctrl out resolver -------------------------------------
|
| 8473 |
|
|
|
| 8474 |
|
|
-- inputs
|
| 8475 |
|
|
dr_clk8_in <= clk_in;
|
| 8476 |
|
|
dr_addnsub_in <= addnsub_in;
|
| 8477 |
|
|
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
|
| 8478 |
|
|
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
|
| 8479 |
|
|
dr_offset_in_gray <= offset_in;
|
| 8480 |
|
|
|
| 8481 |
|
|
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
|
| 8482 |
|
|
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
|
| 8483 |
|
|
|
| 8484 |
|
|
-- outputs
|
| 8485 |
|
|
dr_offsetctrl_out <= dr_reg_offset;
|
| 8486 |
|
|
moffsetctrl_out_enc : stratixiii_dll_gray_encoder
|
| 8487 |
|
|
GENERIC MAP (width => 6)
|
| 8488 |
|
|
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
|
| 8489 |
|
|
|
| 8490 |
|
|
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
|
| 8491 |
|
|
|
| 8492 |
|
|
-- model
|
| 8493 |
|
|
|
| 8494 |
|
|
-- decoders
|
| 8495 |
|
|
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
|
| 8496 |
|
|
GENERIC MAP (width => 6)
|
| 8497 |
|
|
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
|
| 8498 |
|
|
mdr_offset_in_dec : stratixiii_dll_gray_decoder
|
| 8499 |
|
|
GENERIC MAP (width => 6)
|
| 8500 |
|
|
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
|
| 8501 |
|
|
mpara_static_offset_dec : stratixiii_dll_gray_decoder
|
| 8502 |
|
|
GENERIC MAP (width => 6)
|
| 8503 |
|
|
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
|
| 8504 |
|
|
|
| 8505 |
|
|
-- get postive value of decoded offset for over/underflow check
|
| 8506 |
|
|
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
|
| 8507 |
|
|
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
|
| 8508 |
|
|
|
| 8509 |
|
|
-- generating dr_reg_offset
|
| 8510 |
|
|
process(dr_clk8_in, dr_aload_in)
|
| 8511 |
|
|
begin
|
| 8512 |
|
|
if (dr_aload_in = '1' and dr_aload_in'event) then
|
| 8513 |
|
|
dr_reg_offset <= "000000";
|
| 8514 |
|
|
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
|
| 8515 |
|
|
if (use_offset = "true") then
|
| 8516 |
|
|
if (dr_addnsub_in = '1') then
|
| 8517 |
|
|
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
|
| 8518 |
|
|
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
|
| 8519 |
|
|
else
|
| 8520 |
|
|
dr_reg_offset <= "111111";
|
| 8521 |
|
|
end if;
|
| 8522 |
|
|
elsif (dr_addnsub_in = '0') then
|
| 8523 |
|
|
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
|
| 8524 |
|
|
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
|
| 8525 |
|
|
else
|
| 8526 |
|
|
dr_reg_offset <= "000000";
|
| 8527 |
|
|
end if;
|
| 8528 |
|
|
end if;
|
| 8529 |
|
|
else
|
| 8530 |
|
|
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
|
| 8531 |
|
|
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
|
| 8532 |
|
|
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
|
| 8533 |
|
|
else
|
| 8534 |
|
|
dr_reg_offset <= "111111";
|
| 8535 |
|
|
end if;
|
| 8536 |
|
|
else
|
| 8537 |
|
|
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
|
| 8538 |
|
|
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
|
| 8539 |
|
|
else
|
| 8540 |
|
|
dr_reg_offset <= "000000";
|
| 8541 |
|
|
end if;
|
| 8542 |
|
|
end if;
|
| 8543 |
|
|
end if;
|
| 8544 |
|
|
end if; -- rising clock
|
| 8545 |
|
|
end process ; -- generating dr_reg_offset
|
| 8546 |
|
|
|
| 8547 |
|
|
--------------------
|
| 8548 |
|
|
-- INPUT PATH DELAYS
|
| 8549 |
|
|
--------------------
|
| 8550 |
|
|
WireDelay : block
|
| 8551 |
|
|
begin
|
| 8552 |
|
|
VitalWireDelay (clk_in, clk, tipd_clk);
|
| 8553 |
|
|
VitalWireDelay (aload_in, aload, tipd_aload);
|
| 8554 |
|
|
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
|
| 8555 |
|
|
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
|
| 8556 |
|
|
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
|
| 8557 |
|
|
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
|
| 8558 |
|
|
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
|
| 8559 |
|
|
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
|
| 8560 |
|
|
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
|
| 8561 |
|
|
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
|
| 8562 |
|
|
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
|
| 8563 |
|
|
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
|
| 8564 |
|
|
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
|
| 8565 |
|
|
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
|
| 8566 |
|
|
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
|
| 8567 |
|
|
end block;
|
| 8568 |
|
|
|
| 8569 |
|
|
------------------------
|
| 8570 |
|
|
-- Timing Check Section
|
| 8571 |
|
|
------------------------
|
| 8572 |
|
|
VITALtiming : process (clk_in, offset_in, addnsub_in,
|
| 8573 |
|
|
offsetctrl_out)
|
| 8574 |
|
|
|
| 8575 |
|
|
variable Tviol_offset_clk : std_ulogic := '0';
|
| 8576 |
|
|
variable Tviol_addnsub_clk : std_ulogic := '0';
|
| 8577 |
|
|
|
| 8578 |
|
|
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 8579 |
|
|
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 8580 |
|
|
|
| 8581 |
|
|
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
|
| 8582 |
|
|
|
| 8583 |
|
|
begin
|
| 8584 |
|
|
|
| 8585 |
|
|
if (TimingChecksOn) then
|
| 8586 |
|
|
|
| 8587 |
|
|
VitalSetupHoldCheck (
|
| 8588 |
|
|
Violation => Tviol_offset_clk,
|
| 8589 |
|
|
TimingData => TimingData_offset_clk,
|
| 8590 |
|
|
TestSignal => offset_in,
|
| 8591 |
|
|
TestSignalName => "OFFSET",
|
| 8592 |
|
|
RefSignal => clk_in,
|
| 8593 |
|
|
RefSignalName => "CLK",
|
| 8594 |
|
|
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
|
| 8595 |
|
|
SetupLow => tsetup_offset_clk_noedge_posedge(0),
|
| 8596 |
|
|
HoldHigh => thold_offset_clk_noedge_posedge(0),
|
| 8597 |
|
|
HoldLow => thold_offset_clk_noedge_posedge(0),
|
| 8598 |
|
|
RefTransition => '/',
|
| 8599 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
|
| 8600 |
|
|
XOn => XOn,
|
| 8601 |
|
|
MsgOn => MsgOnChecks );
|
| 8602 |
|
|
|
| 8603 |
|
|
VitalSetupHoldCheck (
|
| 8604 |
|
|
Violation => Tviol_addnsub_clk,
|
| 8605 |
|
|
TimingData => TimingData_addnsub_clk,
|
| 8606 |
|
|
TestSignal => addnsub_in,
|
| 8607 |
|
|
TestSignalName => "ADDNSUB",
|
| 8608 |
|
|
RefSignal => clk_in,
|
| 8609 |
|
|
RefSignalName => "CLK",
|
| 8610 |
|
|
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
|
| 8611 |
|
|
SetupLow => tsetup_addnsub_clk_noedge_posedge,
|
| 8612 |
|
|
HoldHigh => thold_addnsub_clk_noedge_posedge,
|
| 8613 |
|
|
HoldLow => thold_addnsub_clk_noedge_posedge,
|
| 8614 |
|
|
RefTransition => '/',
|
| 8615 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
|
| 8616 |
|
|
XOn => XOn,
|
| 8617 |
|
|
MsgOn => MsgOnChecks );
|
| 8618 |
|
|
end if;
|
| 8619 |
|
|
|
| 8620 |
|
|
----------------------
|
| 8621 |
|
|
-- Path Delay Section
|
| 8622 |
|
|
----------------------
|
| 8623 |
|
|
|
| 8624 |
|
|
VitalPathDelay01 (
|
| 8625 |
|
|
OutSignal => offsetctrlout(0),
|
| 8626 |
|
|
OutSignalName => "offsetctrlOUT",
|
| 8627 |
|
|
OutTemp => offsetctrl_out(0),
|
| 8628 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
|
| 8629 |
|
|
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
|
| 8630 |
|
|
Mode => DefGlitchMode,
|
| 8631 |
|
|
XOn => XOn,
|
| 8632 |
|
|
MsgOn => MsgOn );
|
| 8633 |
|
|
|
| 8634 |
|
|
VitalPathDelay01 (
|
| 8635 |
|
|
OutSignal => offsetctrlout(1),
|
| 8636 |
|
|
OutSignalName => "offsetctrlOUT",
|
| 8637 |
|
|
OutTemp => offsetctrl_out(1),
|
| 8638 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
|
| 8639 |
|
|
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
|
| 8640 |
|
|
Mode => DefGlitchMode,
|
| 8641 |
|
|
XOn => XOn,
|
| 8642 |
|
|
MsgOn => MsgOn );
|
| 8643 |
|
|
|
| 8644 |
|
|
VitalPathDelay01 (
|
| 8645 |
|
|
OutSignal => offsetctrlout(2),
|
| 8646 |
|
|
OutSignalName => "offsetctrlOUT",
|
| 8647 |
|
|
OutTemp => offsetctrl_out(2),
|
| 8648 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
|
| 8649 |
|
|
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
|
| 8650 |
|
|
Mode => DefGlitchMode,
|
| 8651 |
|
|
XOn => XOn,
|
| 8652 |
|
|
MsgOn => MsgOn );
|
| 8653 |
|
|
|
| 8654 |
|
|
VitalPathDelay01 (
|
| 8655 |
|
|
OutSignal => offsetctrlout(3),
|
| 8656 |
|
|
OutSignalName => "offsetctrlOUT",
|
| 8657 |
|
|
OutTemp => offsetctrl_out(3),
|
| 8658 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
|
| 8659 |
|
|
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
|
| 8660 |
|
|
Mode => DefGlitchMode,
|
| 8661 |
|
|
XOn => XOn,
|
| 8662 |
|
|
MsgOn => MsgOn );
|
| 8663 |
|
|
|
| 8664 |
|
|
VitalPathDelay01 (
|
| 8665 |
|
|
OutSignal => offsetctrlout(4),
|
| 8666 |
|
|
OutSignalName => "offsetctrlOUT",
|
| 8667 |
|
|
OutTemp => offsetctrl_out(4),
|
| 8668 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
|
| 8669 |
|
|
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
|
| 8670 |
|
|
Mode => DefGlitchMode,
|
| 8671 |
|
|
XOn => XOn,
|
| 8672 |
|
|
MsgOn => MsgOn );
|
| 8673 |
|
|
|
| 8674 |
|
|
VitalPathDelay01 (
|
| 8675 |
|
|
OutSignal => offsetctrlout(5),
|
| 8676 |
|
|
OutSignalName => "offsetctrlOUT",
|
| 8677 |
|
|
OutTemp => offsetctrl_out(5),
|
| 8678 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
|
| 8679 |
|
|
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
|
| 8680 |
|
|
Mode => DefGlitchMode,
|
| 8681 |
|
|
XOn => XOn,
|
| 8682 |
|
|
MsgOn => MsgOn );
|
| 8683 |
|
|
|
| 8684 |
|
|
|
| 8685 |
|
|
|
| 8686 |
|
|
end process; -- vital timing
|
| 8687 |
|
|
|
| 8688 |
|
|
|
| 8689 |
|
|
end vital_stratixiiioffset;
|
| 8690 |
|
|
|
| 8691 |
|
|
-------------------------------------------------------------------------------
|
| 8692 |
|
|
--
|
| 8693 |
|
|
-- Entity Name : stratixiii_dqs_delay_chain
|
| 8694 |
|
|
--
|
| 8695 |
|
|
-------------------------------------------------------------------------------
|
| 8696 |
|
|
|
| 8697 |
|
|
library IEEE;
|
| 8698 |
|
|
use IEEE.std_logic_1164.all;
|
| 8699 |
|
|
use IEEE.VITAL_Timing.all;
|
| 8700 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 8701 |
|
|
use work.stratixiii_atom_pack.all;
|
| 8702 |
|
|
use work.stratixiii_dll_gray_decoder;
|
| 8703 |
|
|
|
| 8704 |
|
|
ENTITY stratixiii_dqs_delay_chain IS
|
| 8705 |
|
|
GENERIC (
|
| 8706 |
|
|
dqs_input_frequency : string := "unused" ;
|
| 8707 |
|
|
use_phasectrlin : string := "false";
|
| 8708 |
|
|
phase_setting : integer := 0;
|
| 8709 |
|
|
delay_buffer_mode : string := "low";
|
| 8710 |
|
|
dqs_phase_shift : integer := 0;
|
| 8711 |
|
|
dqs_offsetctrl_enable : string := "false";
|
| 8712 |
|
|
dqs_ctrl_latches_enable : string := "false";
|
| 8713 |
|
|
-- DFT added in WYS 1.33
|
| 8714 |
|
|
test_enable : string := "false";
|
| 8715 |
|
|
test_select : integer := 0;
|
| 8716 |
|
|
-- SIM only
|
| 8717 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 8718 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 8719 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 8720 |
|
|
lpm_type : string := "stratixiii_dqs_delay_chain";
|
| 8721 |
|
|
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
|
| 8722 |
|
|
tipd_aload : VitalDelayType01 := DefpropDelay01;
|
| 8723 |
|
|
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
| 8724 |
|
|
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
| 8725 |
|
|
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
|
| 8726 |
|
|
tipd_phasectrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
| 8727 |
|
|
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
|
| 8728 |
|
|
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
|
| 8729 |
|
|
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
|
| 8730 |
|
|
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
|
| 8731 |
|
|
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
|
| 8732 |
|
|
TimingChecksOn : Boolean := True;
|
| 8733 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 8734 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 8735 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 8736 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 8737 |
|
|
InstancePath : String := "*"
|
| 8738 |
|
|
);
|
| 8739 |
|
|
|
| 8740 |
|
|
PORT (
|
| 8741 |
|
|
dqsin : IN std_logic := '0';
|
| 8742 |
|
|
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8743 |
|
|
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8744 |
|
|
dqsupdateen : IN std_logic := '1';
|
| 8745 |
|
|
phasectrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8746 |
|
|
devclrn : IN std_logic := '1';
|
| 8747 |
|
|
devpor : IN std_logic := '1';
|
| 8748 |
|
|
dqsbusout : OUT std_logic;
|
| 8749 |
|
|
dffin : OUT std_logic
|
| 8750 |
|
|
);
|
| 8751 |
|
|
|
| 8752 |
|
|
END;
|
| 8753 |
|
|
|
| 8754 |
|
|
ARCHITECTURE stratixiii_dqs_delay_chain_arch OF stratixiii_dqs_delay_chain IS
|
| 8755 |
|
|
|
| 8756 |
|
|
-- component section
|
| 8757 |
|
|
COMPONENT stratixiii_dll_gray_decoder
|
| 8758 |
|
|
GENERIC ( width : integer := 6 );
|
| 8759 |
|
|
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
|
| 8760 |
|
|
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
|
| 8761 |
|
|
);
|
| 8762 |
|
|
END COMPONENT;
|
| 8763 |
|
|
|
| 8764 |
|
|
-- signal section
|
| 8765 |
|
|
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8766 |
|
|
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8767 |
|
|
|
| 8768 |
|
|
-- offsetctrl after "dqs_offsetctrl_enable" mux
|
| 8769 |
|
|
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8770 |
|
|
|
| 8771 |
|
|
-- reged outputs of delay count
|
| 8772 |
|
|
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
|
| 8773 |
|
|
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
|
| 8774 |
|
|
|
| 8775 |
|
|
-- delay count after latch enable mux
|
| 8776 |
|
|
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8777 |
|
|
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8778 |
|
|
|
| 8779 |
|
|
-- timing outputs
|
| 8780 |
|
|
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
|
| 8781 |
|
|
SIGNAL dqs_delay : INTEGER := 0;
|
| 8782 |
|
|
|
| 8783 |
|
|
-- timing inputs
|
| 8784 |
|
|
SIGNAL dqsin_in : std_logic := '0';
|
| 8785 |
|
|
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8786 |
|
|
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8787 |
|
|
SIGNAL dqsupdateen_in : std_logic := '1';
|
| 8788 |
|
|
SIGNAL phasectrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 8789 |
|
|
|
| 8790 |
|
|
SIGNAL test_bus : std_logic_vector(12 downto 0);
|
| 8791 |
|
|
SIGNAL test_lpbk : std_logic;
|
| 8792 |
|
|
SIGNAL tmp_dqsin : std_logic;
|
| 8793 |
|
|
|
| 8794 |
|
|
BEGIN
|
| 8795 |
|
|
|
| 8796 |
|
|
PROCESS(dqsupdateen_in)
|
| 8797 |
|
|
BEGIN
|
| 8798 |
|
|
IF (dqsupdateen_in = '1') THEN
|
| 8799 |
|
|
delayctrl_reg <= delayctrlin_in;
|
| 8800 |
|
|
offsetctrl_reg <= offsetctrl_mux;
|
| 8801 |
|
|
END IF;
|
| 8802 |
|
|
END PROCESS;
|
| 8803 |
|
|
|
| 8804 |
|
|
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
|
| 8805 |
|
|
|
| 8806 |
|
|
-- mux after reg
|
| 8807 |
|
|
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
|
| 8808 |
|
|
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
|
| 8809 |
|
|
|
| 8810 |
|
|
mdelayctrlin_dec : stratixiii_dll_gray_decoder
|
| 8811 |
|
|
GENERIC MAP (width => 6)
|
| 8812 |
|
|
PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin);
|
| 8813 |
|
|
moffsetctrlin_dec : stratixiii_dll_gray_decoder
|
| 8814 |
|
|
GENERIC MAP (width => 6)
|
| 8815 |
|
|
PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin);
|
| 8816 |
|
|
|
| 8817 |
|
|
PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in)
|
| 8818 |
|
|
variable sim_intrinsic_delay : INTEGER := 0;
|
| 8819 |
|
|
variable acell_delay : INTEGER := 0;
|
| 8820 |
|
|
variable aoffsetcell_delay : INTEGER := 0;
|
| 8821 |
|
|
variable delay_chain_len : INTEGER := 0;
|
| 8822 |
|
|
BEGIN
|
| 8823 |
|
|
IF (delay_buffer_mode = "low") THEN
|
| 8824 |
|
|
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
|
| 8825 |
|
|
ELSE
|
| 8826 |
|
|
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
|
| 8827 |
|
|
END IF;
|
| 8828 |
|
|
|
| 8829 |
|
|
-- cell
|
| 8830 |
|
|
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
|
| 8831 |
|
|
IF (dqs_offsetctrl_enable = "true") THEN
|
| 8832 |
|
|
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(offsetctrl_bin)*sim_buffer_delay_increment;
|
| 8833 |
|
|
ELSE
|
| 8834 |
|
|
aoffsetcell_delay := acell_delay;
|
| 8835 |
|
|
END IF;
|
| 8836 |
|
|
-- no of cells
|
| 8837 |
|
|
IF (use_phasectrlin = "false") THEN
|
| 8838 |
|
|
delay_chain_len := phase_setting;
|
| 8839 |
|
|
ELSIF (phasectrlin_in(2) = '1') THEN
|
| 8840 |
|
|
delay_chain_len := 0;
|
| 8841 |
|
|
ELSE
|
| 8842 |
|
|
delay_chain_len := alt_conv_integer(phasectrlin_in) + 1;
|
| 8843 |
|
|
END IF;
|
| 8844 |
|
|
-- total delay
|
| 8845 |
|
|
IF (delay_chain_len = 0) THEN
|
| 8846 |
|
|
dqs_delay <= 0;
|
| 8847 |
|
|
ELSE
|
| 8848 |
|
|
dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
|
| 8849 |
|
|
END IF;
|
| 8850 |
|
|
|
| 8851 |
|
|
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
|
| 8852 |
|
|
assert false report "DELAYCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
|
| 8853 |
|
|
END IF;
|
| 8854 |
|
|
|
| 8855 |
|
|
END PROCESS; -- generating delays
|
| 8856 |
|
|
|
| 8857 |
|
|
-- test bus loopback
|
| 8858 |
|
|
test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux;
|
| 8859 |
|
|
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z';
|
| 8860 |
|
|
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in;
|
| 8861 |
|
|
|
| 8862 |
|
|
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
|
| 8863 |
|
|
|
| 8864 |
|
|
--------------------
|
| 8865 |
|
|
-- INPUT PATH DELAYS
|
| 8866 |
|
|
--------------------
|
| 8867 |
|
|
WireDelay : block
|
| 8868 |
|
|
begin
|
| 8869 |
|
|
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
|
| 8870 |
|
|
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
|
| 8871 |
|
|
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
|
| 8872 |
|
|
END GENERATE;
|
| 8873 |
|
|
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
|
| 8874 |
|
|
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
|
| 8875 |
|
|
END GENERATE;
|
| 8876 |
|
|
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
|
| 8877 |
|
|
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
|
| 8878 |
|
|
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
|
| 8879 |
|
|
END GENERATE;
|
| 8880 |
|
|
end block;
|
| 8881 |
|
|
|
| 8882 |
|
|
-----------------------------------
|
| 8883 |
|
|
-- Timing Check Section
|
| 8884 |
|
|
-----------------------------------
|
| 8885 |
|
|
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
|
| 8886 |
|
|
|
| 8887 |
|
|
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
|
| 8888 |
|
|
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
|
| 8889 |
|
|
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
|
| 8890 |
|
|
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
|
| 8891 |
|
|
|
| 8892 |
|
|
BEGIN
|
| 8893 |
|
|
IF (TimingChecksOn) THEN
|
| 8894 |
|
|
VitalSetupHoldCheck (
|
| 8895 |
|
|
Violation => Tviol_dqsupdateen_offsetctrlin,
|
| 8896 |
|
|
TimingData => TimingData_dqsupdateen_offsetctrlin,
|
| 8897 |
|
|
TestSignal => offsetctrlin_in,
|
| 8898 |
|
|
TestSignalName => "offsetctrlin",
|
| 8899 |
|
|
RefSignal => dqsupdateen_in,
|
| 8900 |
|
|
RefSignalName => "dqsupdateen",
|
| 8901 |
|
|
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
|
| 8902 |
|
|
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
|
| 8903 |
|
|
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
|
| 8904 |
|
|
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
|
| 8905 |
|
|
RefTransition => '/',
|
| 8906 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
|
| 8907 |
|
|
XOn => XOnChecks,
|
| 8908 |
|
|
MsgOn => MsgOnChecks
|
| 8909 |
|
|
);
|
| 8910 |
|
|
|
| 8911 |
|
|
VitalSetupHoldCheck (
|
| 8912 |
|
|
Violation => Tviol_dqsupdateen_delayctrlin,
|
| 8913 |
|
|
TimingData => TimingData_dqsupdateen_delayctrlin,
|
| 8914 |
|
|
TestSignal => delayctrlin_in,
|
| 8915 |
|
|
TestSignalName => "delayctrlin",
|
| 8916 |
|
|
RefSignal => dqsupdateen_in,
|
| 8917 |
|
|
RefSignalName => "dqsupdateen",
|
| 8918 |
|
|
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
|
| 8919 |
|
|
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
|
| 8920 |
|
|
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
|
| 8921 |
|
|
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
|
| 8922 |
|
|
RefTransition => '/',
|
| 8923 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
|
| 8924 |
|
|
XOn => XOnChecks,
|
| 8925 |
|
|
MsgOn => MsgOnChecks
|
| 8926 |
|
|
);
|
| 8927 |
|
|
|
| 8928 |
|
|
END IF;
|
| 8929 |
|
|
END PROCESS; -- timing check
|
| 8930 |
|
|
|
| 8931 |
|
|
--------------------------------------
|
| 8932 |
|
|
-- Path Delay Section
|
| 8933 |
|
|
--------------------------------------
|
| 8934 |
|
|
|
| 8935 |
|
|
VITAL_path_delays: PROCESS (tmp_dqsbusout)
|
| 8936 |
|
|
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
|
| 8937 |
|
|
BEGIN
|
| 8938 |
|
|
VitalPathDelay01 (
|
| 8939 |
|
|
OutSignal => dqsbusout,
|
| 8940 |
|
|
OutSignalName => "dqsbusout",
|
| 8941 |
|
|
OutTemp => tmp_dqsbusout,
|
| 8942 |
|
|
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
|
| 8943 |
|
|
GlitchData => dqsbusout_VitalGlitchData,
|
| 8944 |
|
|
Mode => DefGlitchMode,
|
| 8945 |
|
|
XOn => XOn,
|
| 8946 |
|
|
MsgOn => MsgOn );
|
| 8947 |
|
|
END PROCESS; -- Path Delays
|
| 8948 |
|
|
|
| 8949 |
|
|
END stratixiii_dqs_delay_chain_arch;
|
| 8950 |
|
|
|
| 8951 |
|
|
-------------------------------------------------------------------------------
|
| 8952 |
|
|
--
|
| 8953 |
|
|
-- Entity Name : stratixiii_dqs_enable
|
| 8954 |
|
|
--
|
| 8955 |
|
|
-------------------------------------------------------------------------------
|
| 8956 |
|
|
|
| 8957 |
|
|
library IEEE;
|
| 8958 |
|
|
use IEEE.std_logic_1164.all;
|
| 8959 |
|
|
use IEEE.VITAL_Timing.all;
|
| 8960 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 8961 |
|
|
use work.stratixiii_atom_pack.all;
|
| 8962 |
|
|
|
| 8963 |
|
|
ENTITY stratixiii_dqs_enable IS
|
| 8964 |
|
|
GENERIC (
|
| 8965 |
|
|
lpm_type : string := "stratixiii_dqs_enable";
|
| 8966 |
|
|
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
|
| 8967 |
|
|
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
|
| 8968 |
|
|
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
|
| 8969 |
|
|
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
|
| 8970 |
|
|
TimingChecksOn : Boolean := True;
|
| 8971 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 8972 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 8973 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 8974 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 8975 |
|
|
InstancePath : String := "*"
|
| 8976 |
|
|
);
|
| 8977 |
|
|
|
| 8978 |
|
|
PORT (
|
| 8979 |
|
|
dqsin : IN std_logic := '0';
|
| 8980 |
|
|
dqsenable : IN std_logic := '1';
|
| 8981 |
|
|
devclrn : IN std_logic := '1';
|
| 8982 |
|
|
devpor : IN std_logic := '1';
|
| 8983 |
|
|
dqsbusout : OUT std_logic
|
| 8984 |
|
|
);
|
| 8985 |
|
|
|
| 8986 |
|
|
END;
|
| 8987 |
|
|
|
| 8988 |
|
|
ARCHITECTURE stratixiii_dqs_enable_arch OF stratixiii_dqs_enable IS
|
| 8989 |
|
|
-- component section
|
| 8990 |
|
|
|
| 8991 |
|
|
-- signal section
|
| 8992 |
|
|
SIGNAL ena_reg : STD_LOGIC := '1';
|
| 8993 |
|
|
|
| 8994 |
|
|
-- timing output
|
| 8995 |
|
|
SIGNAL tmp_dqsbusout : std_logic := '0';
|
| 8996 |
|
|
|
| 8997 |
|
|
-- timing input
|
| 8998 |
|
|
SIGNAL dqsin_in : std_logic := '0';
|
| 8999 |
|
|
SIGNAL dqsenable_in : std_logic := '1';
|
| 9000 |
|
|
|
| 9001 |
|
|
|
| 9002 |
|
|
BEGIN
|
| 9003 |
|
|
tmp_dqsbusout <= ena_reg AND dqsin_in;
|
| 9004 |
|
|
PROCESS(tmp_dqsbusout, dqsenable_in)
|
| 9005 |
|
|
BEGIN
|
| 9006 |
|
|
IF (dqsenable_in = '1') THEN
|
| 9007 |
|
|
ena_reg <= '1';
|
| 9008 |
|
|
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
|
| 9009 |
|
|
ena_reg <= '0';
|
| 9010 |
|
|
END IF;
|
| 9011 |
|
|
END PROCESS;
|
| 9012 |
|
|
|
| 9013 |
|
|
--------------------
|
| 9014 |
|
|
-- INPUT PATH DELAYS
|
| 9015 |
|
|
--------------------
|
| 9016 |
|
|
WireDelay : block
|
| 9017 |
|
|
begin
|
| 9018 |
|
|
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
|
| 9019 |
|
|
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
|
| 9020 |
|
|
end block;
|
| 9021 |
|
|
|
| 9022 |
|
|
--------------------------------------
|
| 9023 |
|
|
-- Path Delay Section
|
| 9024 |
|
|
--------------------------------------
|
| 9025 |
|
|
|
| 9026 |
|
|
VITAL_path_delays: PROCESS (tmp_dqsbusout)
|
| 9027 |
|
|
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
|
| 9028 |
|
|
BEGIN
|
| 9029 |
|
|
VitalPathDelay01 (
|
| 9030 |
|
|
OutSignal => dqsbusout,
|
| 9031 |
|
|
OutSignalName => "dqsbusout",
|
| 9032 |
|
|
OutTemp => tmp_dqsbusout,
|
| 9033 |
|
|
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
|
| 9034 |
|
|
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
|
| 9035 |
|
|
GlitchData => dqsbusout_VitalGlitchData,
|
| 9036 |
|
|
Mode => DefGlitchMode,
|
| 9037 |
|
|
XOn => XOn,
|
| 9038 |
|
|
MsgOn => MsgOn );
|
| 9039 |
|
|
END PROCESS; -- Path Delays
|
| 9040 |
|
|
|
| 9041 |
|
|
END stratixiii_dqs_enable_arch;
|
| 9042 |
|
|
|
| 9043 |
|
|
-------------------------------------------------------------------------------
|
| 9044 |
|
|
--
|
| 9045 |
|
|
-- Entity Name : stratixiii_dqs_enable_ctrl
|
| 9046 |
|
|
--
|
| 9047 |
|
|
-------------------------------------------------------------------------------
|
| 9048 |
|
|
|
| 9049 |
|
|
library IEEE;
|
| 9050 |
|
|
use IEEE.std_logic_1164.all;
|
| 9051 |
|
|
use IEEE.std_logic_arith.all;
|
| 9052 |
|
|
use IEEE.std_logic_unsigned.all;
|
| 9053 |
|
|
use IEEE.VITAL_Timing.all;
|
| 9054 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 9055 |
|
|
use work.stratixiii_atom_pack.all;
|
| 9056 |
|
|
use work.stratixiii_ddr_io_reg;
|
| 9057 |
|
|
use work.stratixiii_ddr_delay_chain_s;
|
| 9058 |
|
|
|
| 9059 |
|
|
ENTITY stratixiii_dqs_enable_ctrl IS
|
| 9060 |
|
|
GENERIC (
|
| 9061 |
|
|
use_phasectrlin : string := "true";
|
| 9062 |
|
|
phase_setting : integer := 0;
|
| 9063 |
|
|
delay_buffer_mode : string := "high";
|
| 9064 |
|
|
level_dqs_enable : string := "false";
|
| 9065 |
|
|
delay_dqs_enable_by_half_cycle : string := "false";
|
| 9066 |
|
|
add_phase_transfer_reg : string := "false";
|
| 9067 |
|
|
invert_phase : string := "false";
|
| 9068 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 9069 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 9070 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 9071 |
|
|
lpm_type : string := "stratixiii_dqs_enable_ctrl";
|
| 9072 |
|
|
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
|
| 9073 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 9074 |
|
|
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
| 9075 |
|
|
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
| 9076 |
|
|
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
|
| 9077 |
|
|
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
|
| 9078 |
|
|
TimingChecksOn : Boolean := True;
|
| 9079 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 9080 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 9081 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 9082 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 9083 |
|
|
InstancePath : String := "*"
|
| 9084 |
|
|
);
|
| 9085 |
|
|
|
| 9086 |
|
|
PORT (
|
| 9087 |
|
|
dqsenablein : IN std_logic := '1';
|
| 9088 |
|
|
clk : IN std_logic := '0';
|
| 9089 |
|
|
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 9090 |
|
|
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
|
| 9091 |
|
|
enaphasetransferreg : IN std_logic := '0';
|
| 9092 |
|
|
phaseinvertctrl : IN std_logic := '0';
|
| 9093 |
|
|
devclrn : IN std_logic := '1';
|
| 9094 |
|
|
devpor : IN std_logic := '1';
|
| 9095 |
|
|
dqsenableout : OUT std_logic;
|
| 9096 |
|
|
dffin : OUT std_logic;
|
| 9097 |
|
|
dffextenddqsenable : OUT std_logic
|
| 9098 |
|
|
);
|
| 9099 |
|
|
|
| 9100 |
|
|
END;
|
| 9101 |
|
|
|
| 9102 |
|
|
ARCHITECTURE stratixiii_dqs_enable_ctrl_arch OF stratixiii_dqs_enable_ctrl IS
|
| 9103 |
|
|
-- component section
|
| 9104 |
|
|
COMPONENT stratixiii_ddr_delay_chain_s
|
| 9105 |
|
|
GENERIC (
|
| 9106 |
|
|
use_phasectrlin : string := "true";
|
| 9107 |
|
|
phase_setting : integer := 0;
|
| 9108 |
|
|
delay_buffer_mode : string := "high";
|
| 9109 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 9110 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 9111 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 9112 |
|
|
phasectrlin_limit : integer := 7
|
| 9113 |
|
|
);
|
| 9114 |
|
|
PORT (
|
| 9115 |
|
|
clk : IN std_logic := '0';
|
| 9116 |
|
|
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
|
| 9117 |
|
|
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
|
| 9118 |
|
|
delayed_clkout : OUT std_logic
|
| 9119 |
|
|
);
|
| 9120 |
|
|
END COMPONENT;
|
| 9121 |
|
|
|
| 9122 |
|
|
component stratixiii_ddr_io_reg
|
| 9123 |
|
|
generic (
|
| 9124 |
|
|
power_up : string := "DONT_CARE";
|
| 9125 |
|
|
is_wysiwyg : string := "false";
|
| 9126 |
|
|
x_on_violation : string := "on";
|
| 9127 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9128 |
|
|
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9129 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9130 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9131 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9132 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9133 |
|
|
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9134 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9135 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9136 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9137 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 9138 |
|
|
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 9139 |
|
|
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 9140 |
|
|
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
| 9141 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 9142 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 9143 |
|
|
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
| 9144 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
| 9145 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 9146 |
|
|
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
| 9147 |
|
|
tipd_prn : VitalDelayType01 := DefPropDelay01;
|
| 9148 |
|
|
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
| 9149 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 9150 |
|
|
TimingChecksOn: Boolean := True;
|
| 9151 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 9152 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 9153 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 9154 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 9155 |
|
|
InstancePath: STRING := "*"
|
| 9156 |
|
|
);
|
| 9157 |
|
|
|
| 9158 |
|
|
port (
|
| 9159 |
|
|
d : in std_logic := '0';
|
| 9160 |
|
|
clk : in std_logic := '0';
|
| 9161 |
|
|
ena : in std_logic := '1';
|
| 9162 |
|
|
clrn : in std_logic := '1';
|
| 9163 |
|
|
prn : in std_logic := '1';
|
| 9164 |
|
|
aload : in std_logic := '0';
|
| 9165 |
|
|
asdata : in std_logic := '0';
|
| 9166 |
|
|
sclr : in std_logic := '0';
|
| 9167 |
|
|
sload : in std_logic := '0';
|
| 9168 |
|
|
devclrn : in std_logic := '1';
|
| 9169 |
|
|
devpor : in std_logic := '1';
|
| 9170 |
|
|
q : out std_logic
|
| 9171 |
|
|
);
|
| 9172 |
|
|
end component;
|
| 9173 |
|
|
|
| 9174 |
|
|
|
| 9175 |
|
|
-- int signals
|
| 9176 |
|
|
SIGNAL phasectrl_clkout : std_logic := '0';
|
| 9177 |
|
|
SIGNAL delayed_clk : std_logic := '0';
|
| 9178 |
|
|
SIGNAL dqsenablein_reg_q : std_logic := '0';
|
| 9179 |
|
|
SIGNAL dqsenablein_level_ena : std_logic := '0';
|
| 9180 |
|
|
|
| 9181 |
|
|
-- transfer delay
|
| 9182 |
|
|
SIGNAL dqsenablein_reg_dly : std_logic := '0';
|
| 9183 |
|
|
SIGNAL phasetransferdelay_mux_out : std_logic := '0';
|
| 9184 |
|
|
|
| 9185 |
|
|
SIGNAL dqsenable_delayed_regp : std_logic := '0';
|
| 9186 |
|
|
SIGNAL dqsenable_delayed_regn : std_logic := '0';
|
| 9187 |
|
|
|
| 9188 |
|
|
SIGNAL m_vcc : std_logic := '1';
|
| 9189 |
|
|
SIGNAL m_gnd : std_logic := '0';
|
| 9190 |
|
|
|
| 9191 |
|
|
SIGNAL not_clk_in : std_logic := '1';
|
| 9192 |
|
|
SIGNAL not_delayed_clk : std_logic := '1';
|
| 9193 |
|
|
|
| 9194 |
|
|
-- timing output
|
| 9195 |
|
|
SIGNAL tmp_dqsenableout : std_logic := '1';
|
| 9196 |
|
|
|
| 9197 |
|
|
-- timing input
|
| 9198 |
|
|
SIGNAL dqsenablein_in : std_logic := '1';
|
| 9199 |
|
|
SIGNAL clk_in : std_logic := '0';
|
| 9200 |
|
|
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 9201 |
|
|
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
|
| 9202 |
|
|
SIGNAL enaphasetransferreg_in : std_logic := '0';
|
| 9203 |
|
|
SIGNAL phaseinvertctrl_in : std_logic := '0';
|
| 9204 |
|
|
|
| 9205 |
|
|
BEGIN
|
| 9206 |
|
|
|
| 9207 |
|
|
-- delay chain
|
| 9208 |
|
|
m_delay_chain : stratixiii_ddr_delay_chain_s
|
| 9209 |
|
|
GENERIC MAP (
|
| 9210 |
|
|
phase_setting => phase_setting,
|
| 9211 |
|
|
use_phasectrlin => use_phasectrlin,
|
| 9212 |
|
|
delay_buffer_mode => delay_buffer_mode,
|
| 9213 |
|
|
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
|
| 9214 |
|
|
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
|
| 9215 |
|
|
sim_buffer_delay_increment => sim_buffer_delay_increment
|
| 9216 |
|
|
)
|
| 9217 |
|
|
PORT MAP(
|
| 9218 |
|
|
clk => clk_in,
|
| 9219 |
|
|
delayctrlin => delayctrlin_in,
|
| 9220 |
|
|
phasectrlin => phasectrlin_in,
|
| 9221 |
|
|
delayed_clkout => phasectrl_clkout
|
| 9222 |
|
|
);
|
| 9223 |
|
|
|
| 9224 |
|
|
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
|
| 9225 |
|
|
phasectrl_clkout WHEN (invert_phase = "false") ELSE
|
| 9226 |
|
|
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
|
| 9227 |
|
|
phasectrl_clkout;
|
| 9228 |
|
|
|
| 9229 |
|
|
not_clk_in <= not clk_in;
|
| 9230 |
|
|
not_delayed_clk <= not delayed_clk;
|
| 9231 |
|
|
|
| 9232 |
|
|
dqsenablein_reg : stratixiii_ddr_io_reg
|
| 9233 |
|
|
PORT MAP(
|
| 9234 |
|
|
d => dqsenablein_in,
|
| 9235 |
|
|
clk => clk_in,
|
| 9236 |
|
|
ena => m_vcc,
|
| 9237 |
|
|
clrn => m_vcc,
|
| 9238 |
|
|
prn => m_vcc,
|
| 9239 |
|
|
aload => m_gnd,
|
| 9240 |
|
|
asdata => m_gnd,
|
| 9241 |
|
|
sclr => m_gnd,
|
| 9242 |
|
|
sload => m_gnd,
|
| 9243 |
|
|
devclrn => devclrn,
|
| 9244 |
|
|
devpor => devpor,
|
| 9245 |
|
|
q => dqsenablein_reg_q
|
| 9246 |
|
|
);
|
| 9247 |
|
|
|
| 9248 |
|
|
dqsenable_transfer_reg : stratixiii_ddr_io_reg
|
| 9249 |
|
|
PORT MAP (
|
| 9250 |
|
|
d => dqsenablein_reg_q,
|
| 9251 |
|
|
clk => not_clk_in,
|
| 9252 |
|
|
ena => m_vcc,
|
| 9253 |
|
|
clrn => m_vcc,
|
| 9254 |
|
|
prn => m_vcc,
|
| 9255 |
|
|
aload => m_gnd,
|
| 9256 |
|
|
asdata => m_gnd,
|
| 9257 |
|
|
sclr => m_gnd,
|
| 9258 |
|
|
sload => m_gnd,
|
| 9259 |
|
|
devclrn => devclrn,
|
| 9260 |
|
|
devpor => devpor,
|
| 9261 |
|
|
q => dqsenablein_reg_dly
|
| 9262 |
|
|
);
|
| 9263 |
|
|
|
| 9264 |
|
|
-- add phase transfer mux
|
| 9265 |
|
|
phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE
|
| 9266 |
|
|
dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE
|
| 9267 |
|
|
dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE
|
| 9268 |
|
|
dqsenablein_reg_q;
|
| 9269 |
|
|
|
| 9270 |
|
|
dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in;
|
| 9271 |
|
|
|
| 9272 |
|
|
dqsenableout_reg : stratixiii_ddr_io_reg
|
| 9273 |
|
|
PORT MAP(
|
| 9274 |
|
|
d => dqsenablein_level_ena,
|
| 9275 |
|
|
clk => delayed_clk,
|
| 9276 |
|
|
ena => m_vcc,
|
| 9277 |
|
|
clrn => m_vcc,
|
| 9278 |
|
|
prn => m_vcc,
|
| 9279 |
|
|
aload => m_gnd,
|
| 9280 |
|
|
asdata => m_gnd,
|
| 9281 |
|
|
sclr => m_gnd,
|
| 9282 |
|
|
sload => m_gnd,
|
| 9283 |
|
|
devclrn => devclrn,
|
| 9284 |
|
|
devpor => devpor,
|
| 9285 |
|
|
q => dqsenable_delayed_regp
|
| 9286 |
|
|
);
|
| 9287 |
|
|
|
| 9288 |
|
|
dqsenableout_extend_reg : stratixiii_ddr_io_reg
|
| 9289 |
|
|
PORT MAP(
|
| 9290 |
|
|
d => dqsenable_delayed_regp,
|
| 9291 |
|
|
clk => not_delayed_clk,
|
| 9292 |
|
|
ena => m_vcc,
|
| 9293 |
|
|
clrn => m_vcc,
|
| 9294 |
|
|
prn => m_vcc,
|
| 9295 |
|
|
aload => m_gnd,
|
| 9296 |
|
|
asdata => m_gnd,
|
| 9297 |
|
|
sclr => m_gnd,
|
| 9298 |
|
|
sload => m_gnd,
|
| 9299 |
|
|
devclrn => devclrn,
|
| 9300 |
|
|
devpor => devpor,
|
| 9301 |
|
|
q => dqsenable_delayed_regn
|
| 9302 |
|
|
);
|
| 9303 |
|
|
|
| 9304 |
|
|
tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE
|
| 9305 |
|
|
(dqsenable_delayed_regp AND dqsenable_delayed_regn);
|
| 9306 |
|
|
|
| 9307 |
|
|
dqsenableout <= tmp_dqsenableout;
|
| 9308 |
|
|
|
| 9309 |
|
|
|
| 9310 |
|
|
--------------------
|
| 9311 |
|
|
-- INPUT PATH DELAYS
|
| 9312 |
|
|
--------------------
|
| 9313 |
|
|
WireDelay : block
|
| 9314 |
|
|
begin
|
| 9315 |
|
|
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
|
| 9316 |
|
|
VitalWireDelay (clk_in, clk, tipd_clk);
|
| 9317 |
|
|
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
|
| 9318 |
|
|
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
|
| 9319 |
|
|
END GENERATE;
|
| 9320 |
|
|
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
|
| 9321 |
|
|
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
|
| 9322 |
|
|
END GENERATE;
|
| 9323 |
|
|
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
|
| 9324 |
|
|
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
|
| 9325 |
|
|
end block;
|
| 9326 |
|
|
|
| 9327 |
|
|
|
| 9328 |
|
|
END stratixiii_dqs_enable_ctrl_arch;
|
| 9329 |
|
|
|
| 9330 |
|
|
-------------------------------------------------------------------------------
|
| 9331 |
|
|
--
|
| 9332 |
|
|
-- Entity Name : stratixiii_delay_chain
|
| 9333 |
|
|
--
|
| 9334 |
|
|
-------------------------------------------------------------------------------
|
| 9335 |
|
|
|
| 9336 |
|
|
library IEEE;
|
| 9337 |
|
|
use IEEE.std_logic_1164.all;
|
| 9338 |
|
|
use IEEE.std_logic_arith.all;
|
| 9339 |
|
|
use IEEE.std_logic_unsigned.all;
|
| 9340 |
|
|
use IEEE.VITAL_Timing.all;
|
| 9341 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 9342 |
|
|
use work.stratixiii_atom_pack.all;
|
| 9343 |
|
|
|
| 9344 |
|
|
ENTITY stratixiii_delay_chain IS
|
| 9345 |
|
|
GENERIC (
|
| 9346 |
|
|
sim_delayctrlin_rising_delay_0 : integer := 0;
|
| 9347 |
|
|
sim_delayctrlin_rising_delay_1 : integer := 50;
|
| 9348 |
|
|
sim_delayctrlin_rising_delay_2 : integer := 100;
|
| 9349 |
|
|
sim_delayctrlin_rising_delay_3 : integer := 150;
|
| 9350 |
|
|
sim_delayctrlin_rising_delay_4 : integer := 200;
|
| 9351 |
|
|
sim_delayctrlin_rising_delay_5 : integer := 250;
|
| 9352 |
|
|
sim_delayctrlin_rising_delay_6 : integer := 300;
|
| 9353 |
|
|
sim_delayctrlin_rising_delay_7 : integer := 350;
|
| 9354 |
|
|
sim_delayctrlin_rising_delay_8 : integer := 400;
|
| 9355 |
|
|
sim_delayctrlin_rising_delay_9 : integer := 450;
|
| 9356 |
|
|
sim_delayctrlin_rising_delay_10 : integer := 500;
|
| 9357 |
|
|
sim_delayctrlin_rising_delay_11 : integer := 550;
|
| 9358 |
|
|
sim_delayctrlin_rising_delay_12 : integer := 600;
|
| 9359 |
|
|
sim_delayctrlin_rising_delay_13 : integer := 650;
|
| 9360 |
|
|
sim_delayctrlin_rising_delay_14 : integer := 700;
|
| 9361 |
|
|
sim_delayctrlin_rising_delay_15 : integer := 750;
|
| 9362 |
|
|
sim_delayctrlin_falling_delay_0 : integer := 0;
|
| 9363 |
|
|
sim_delayctrlin_falling_delay_1 : integer := 50;
|
| 9364 |
|
|
sim_delayctrlin_falling_delay_2 : integer := 100;
|
| 9365 |
|
|
sim_delayctrlin_falling_delay_3 : integer := 150;
|
| 9366 |
|
|
sim_delayctrlin_falling_delay_4 : integer := 200;
|
| 9367 |
|
|
sim_delayctrlin_falling_delay_5 : integer := 250;
|
| 9368 |
|
|
sim_delayctrlin_falling_delay_6 : integer := 300;
|
| 9369 |
|
|
sim_delayctrlin_falling_delay_7 : integer := 350;
|
| 9370 |
|
|
sim_delayctrlin_falling_delay_8 : integer := 400;
|
| 9371 |
|
|
sim_delayctrlin_falling_delay_9 : integer := 450;
|
| 9372 |
|
|
sim_delayctrlin_falling_delay_10 : integer := 500;
|
| 9373 |
|
|
sim_delayctrlin_falling_delay_11 : integer := 550;
|
| 9374 |
|
|
sim_delayctrlin_falling_delay_12 : integer := 600;
|
| 9375 |
|
|
sim_delayctrlin_falling_delay_13 : integer := 650;
|
| 9376 |
|
|
sim_delayctrlin_falling_delay_14 : integer := 700;
|
| 9377 |
|
|
sim_delayctrlin_falling_delay_15 : integer := 750;
|
| 9378 |
|
|
use_delayctrlin : string := "true";
|
| 9379 |
|
|
delay_setting : integer := 0;
|
| 9380 |
|
|
lpm_type : string := "stratixiii_delay_chain";
|
| 9381 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01;
|
| 9382 |
|
|
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
| 9383 |
|
|
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
|
| 9384 |
|
|
TimingChecksOn : Boolean := True;
|
| 9385 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 9386 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 9387 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 9388 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 9389 |
|
|
InstancePath : String := "*"
|
| 9390 |
|
|
);
|
| 9391 |
|
|
|
| 9392 |
|
|
PORT (
|
| 9393 |
|
|
datain : IN std_logic := '0';
|
| 9394 |
|
|
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
|
| 9395 |
|
|
devclrn : IN std_logic := '1';
|
| 9396 |
|
|
devpor : IN std_logic := '1';
|
| 9397 |
|
|
dataout : OUT std_logic
|
| 9398 |
|
|
);
|
| 9399 |
|
|
|
| 9400 |
|
|
END;
|
| 9401 |
|
|
|
| 9402 |
|
|
ARCHITECTURE stratixiii_delay_chain_arch OF stratixiii_delay_chain IS
|
| 9403 |
|
|
-- type def
|
| 9404 |
|
|
type delay_chain_int_vec is array (natural range <>) of integer;
|
| 9405 |
|
|
|
| 9406 |
|
|
-- component section
|
| 9407 |
|
|
|
| 9408 |
|
|
-- signal section
|
| 9409 |
|
|
SIGNAL rising_dly : INTEGER := 0;
|
| 9410 |
|
|
SIGNAL falling_dly : INTEGER := 0;
|
| 9411 |
|
|
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
|
| 9412 |
|
|
|
| 9413 |
|
|
-- timing inputs
|
| 9414 |
|
|
SIGNAL tmp_dataout : std_logic := '0';
|
| 9415 |
|
|
|
| 9416 |
|
|
-- timing inputs
|
| 9417 |
|
|
SIGNAL datain_in : std_logic := '0';
|
| 9418 |
|
|
|
| 9419 |
|
|
BEGIN
|
| 9420 |
|
|
-- filtering X/U etc.
|
| 9421 |
|
|
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
|
| 9422 |
|
|
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
|
| 9423 |
|
|
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
|
| 9424 |
|
|
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
|
| 9425 |
|
|
|
| 9426 |
|
|
-- generate dynamic delay table and dynamic delay
|
| 9427 |
|
|
process(delayctrlin_in)
|
| 9428 |
|
|
variable init : boolean := true;
|
| 9429 |
|
|
variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
|
| 9430 |
|
|
variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
|
| 9431 |
|
|
variable dly_setting : integer := 0;
|
| 9432 |
|
|
begin
|
| 9433 |
|
|
if (init) then
|
| 9434 |
|
|
dly_table_rising(0) := sim_delayctrlin_rising_delay_0;
|
| 9435 |
|
|
dly_table_rising(1) := sim_delayctrlin_rising_delay_1;
|
| 9436 |
|
|
dly_table_rising(2) := sim_delayctrlin_rising_delay_2;
|
| 9437 |
|
|
dly_table_rising(3) := sim_delayctrlin_rising_delay_3;
|
| 9438 |
|
|
dly_table_rising(4) := sim_delayctrlin_rising_delay_4;
|
| 9439 |
|
|
dly_table_rising(5) := sim_delayctrlin_rising_delay_5;
|
| 9440 |
|
|
dly_table_rising(6) := sim_delayctrlin_rising_delay_6;
|
| 9441 |
|
|
dly_table_rising(7) := sim_delayctrlin_rising_delay_7;
|
| 9442 |
|
|
dly_table_rising(8) := sim_delayctrlin_rising_delay_8;
|
| 9443 |
|
|
dly_table_rising(9) := sim_delayctrlin_rising_delay_9;
|
| 9444 |
|
|
dly_table_rising(10) := sim_delayctrlin_rising_delay_10;
|
| 9445 |
|
|
dly_table_rising(11) := sim_delayctrlin_rising_delay_11;
|
| 9446 |
|
|
dly_table_rising(12) := sim_delayctrlin_rising_delay_12;
|
| 9447 |
|
|
dly_table_rising(13) := sim_delayctrlin_rising_delay_13;
|
| 9448 |
|
|
dly_table_rising(14) := sim_delayctrlin_rising_delay_14;
|
| 9449 |
|
|
dly_table_rising(15) := sim_delayctrlin_rising_delay_15;
|
| 9450 |
|
|
|
| 9451 |
|
|
dly_table_falling(0) := sim_delayctrlin_falling_delay_0;
|
| 9452 |
|
|
dly_table_falling(1) := sim_delayctrlin_falling_delay_1;
|
| 9453 |
|
|
dly_table_falling(2) := sim_delayctrlin_falling_delay_2;
|
| 9454 |
|
|
dly_table_falling(3) := sim_delayctrlin_falling_delay_3;
|
| 9455 |
|
|
dly_table_falling(4) := sim_delayctrlin_falling_delay_4;
|
| 9456 |
|
|
dly_table_falling(5) := sim_delayctrlin_falling_delay_5;
|
| 9457 |
|
|
dly_table_falling(6) := sim_delayctrlin_falling_delay_6;
|
| 9458 |
|
|
dly_table_falling(7) := sim_delayctrlin_falling_delay_7;
|
| 9459 |
|
|
dly_table_falling(8) := sim_delayctrlin_falling_delay_8;
|
| 9460 |
|
|
dly_table_falling(9) := sim_delayctrlin_falling_delay_9;
|
| 9461 |
|
|
dly_table_falling(10) := sim_delayctrlin_falling_delay_10;
|
| 9462 |
|
|
dly_table_falling(11) := sim_delayctrlin_falling_delay_11;
|
| 9463 |
|
|
dly_table_falling(12) := sim_delayctrlin_falling_delay_12;
|
| 9464 |
|
|
dly_table_falling(13) := sim_delayctrlin_falling_delay_13;
|
| 9465 |
|
|
dly_table_falling(14) := sim_delayctrlin_falling_delay_14;
|
| 9466 |
|
|
dly_table_falling(15) := sim_delayctrlin_falling_delay_15;
|
| 9467 |
|
|
|
| 9468 |
|
|
init := false;
|
| 9469 |
|
|
end if;
|
| 9470 |
|
|
|
| 9471 |
|
|
IF (use_delayctrlin = "false") THEN
|
| 9472 |
|
|
dly_setting := delay_setting;
|
| 9473 |
|
|
ELSE
|
| 9474 |
|
|
dly_setting := alt_conv_integer(delayctrlin_in);
|
| 9475 |
|
|
END IF;
|
| 9476 |
|
|
|
| 9477 |
|
|
rising_dly <= dly_table_rising(dly_setting);
|
| 9478 |
|
|
falling_dly <= dly_table_falling(dly_setting);
|
| 9479 |
|
|
end process; -- generating dynamic delays
|
| 9480 |
|
|
|
| 9481 |
|
|
PROCESS(datain_in)
|
| 9482 |
|
|
BEGIN
|
| 9483 |
|
|
if (datain_in = '0') then
|
| 9484 |
|
|
tmp_dataout <= transport datain_in after (falling_dly * 1 ps);
|
| 9485 |
|
|
else
|
| 9486 |
|
|
tmp_dataout <= transport datain_in after (rising_dly * 1 ps);
|
| 9487 |
|
|
end if;
|
| 9488 |
|
|
END PROCESS;
|
| 9489 |
|
|
|
| 9490 |
|
|
----------------------------------
|
| 9491 |
|
|
-- Path Delay Section
|
| 9492 |
|
|
----------------------------------
|
| 9493 |
|
|
|
| 9494 |
|
|
VITAL: process(tmp_dataout)
|
| 9495 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 9496 |
|
|
begin
|
| 9497 |
|
|
VitalPathDelay01 (
|
| 9498 |
|
|
OutSignal => dataout,
|
| 9499 |
|
|
OutSignalName => "dataout",
|
| 9500 |
|
|
OutTemp => tmp_dataout,
|
| 9501 |
|
|
Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)),
|
| 9502 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 9503 |
|
|
Mode => DefGlitchMode,
|
| 9504 |
|
|
XOn => XOn,
|
| 9505 |
|
|
MsgOn => MsgOn );
|
| 9506 |
|
|
end process;
|
| 9507 |
|
|
|
| 9508 |
|
|
--------------------
|
| 9509 |
|
|
-- INPUT PATH DELAYS
|
| 9510 |
|
|
--------------------
|
| 9511 |
|
|
WireDelay : block
|
| 9512 |
|
|
begin
|
| 9513 |
|
|
VitalWireDelay (datain_in, datain, tipd_datain);
|
| 9514 |
|
|
end block;
|
| 9515 |
|
|
|
| 9516 |
|
|
END stratixiii_delay_chain_arch;
|
| 9517 |
|
|
|
| 9518 |
|
|
-------------------------------------------------------------------------------
|
| 9519 |
|
|
--
|
| 9520 |
|
|
-- Entity Name : stratixiii_io_clock_divider
|
| 9521 |
|
|
--
|
| 9522 |
|
|
-------------------------------------------------------------------------------
|
| 9523 |
|
|
|
| 9524 |
|
|
library IEEE;
|
| 9525 |
|
|
use IEEE.std_logic_1164.all;
|
| 9526 |
|
|
use IEEE.VITAL_Timing.all;
|
| 9527 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 9528 |
|
|
use work.stratixiii_atom_pack.all;
|
| 9529 |
|
|
use work.stratixiii_ddr_delay_chain_s;
|
| 9530 |
|
|
|
| 9531 |
|
|
ENTITY stratixiii_io_clock_divider IS
|
| 9532 |
|
|
GENERIC (
|
| 9533 |
|
|
use_phasectrlin : string := "true";
|
| 9534 |
|
|
phase_setting : integer := 0;
|
| 9535 |
|
|
delay_buffer_mode : string := "high";
|
| 9536 |
|
|
use_masterin : string := "false";
|
| 9537 |
|
|
invert_phase : string := "false";
|
| 9538 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 9539 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 9540 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 9541 |
|
|
lpm_type : string := "stratixiii_io_clock_divider";
|
| 9542 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 9543 |
|
|
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
|
| 9544 |
|
|
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
| 9545 |
|
|
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
| 9546 |
|
|
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
|
| 9547 |
|
|
tipd_masterin : VitalDelayType01 := DefpropDelay01;
|
| 9548 |
|
|
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
|
| 9549 |
|
|
TimingChecksOn : Boolean := True;
|
| 9550 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 9551 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 9552 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 9553 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 9554 |
|
|
InstancePath : String := "*"
|
| 9555 |
|
|
);
|
| 9556 |
|
|
|
| 9557 |
|
|
PORT (
|
| 9558 |
|
|
clk : IN std_logic := '0';
|
| 9559 |
|
|
phaseselect : IN std_logic := '0';
|
| 9560 |
|
|
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 9561 |
|
|
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
|
| 9562 |
|
|
phaseinvertctrl : IN std_logic := '0';
|
| 9563 |
|
|
masterin : IN std_logic := '0';
|
| 9564 |
|
|
devclrn : IN std_logic := '1';
|
| 9565 |
|
|
devpor : IN std_logic := '1';
|
| 9566 |
|
|
clkout : OUT std_logic;
|
| 9567 |
|
|
slaveout : OUT std_logic
|
| 9568 |
|
|
);
|
| 9569 |
|
|
|
| 9570 |
|
|
END;
|
| 9571 |
|
|
|
| 9572 |
|
|
ARCHITECTURE stratixiii_io_clock_divider_arch OF stratixiii_io_clock_divider IS
|
| 9573 |
|
|
-- component section
|
| 9574 |
|
|
COMPONENT stratixiii_ddr_delay_chain_s
|
| 9575 |
|
|
GENERIC (
|
| 9576 |
|
|
use_phasectrlin : string := "true";
|
| 9577 |
|
|
phase_setting : integer := 0;
|
| 9578 |
|
|
delay_buffer_mode : string := "high";
|
| 9579 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 9580 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 9581 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 9582 |
|
|
phasectrlin_limit : integer := 7
|
| 9583 |
|
|
);
|
| 9584 |
|
|
PORT (
|
| 9585 |
|
|
clk : IN std_logic := '0';
|
| 9586 |
|
|
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
|
| 9587 |
|
|
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
|
| 9588 |
|
|
delayed_clkout : OUT std_logic
|
| 9589 |
|
|
);
|
| 9590 |
|
|
END COMPONENT;
|
| 9591 |
|
|
|
| 9592 |
|
|
-- int signals
|
| 9593 |
|
|
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
|
| 9594 |
|
|
SIGNAL delayed_clk : STD_LOGIC := '0';
|
| 9595 |
|
|
SIGNAL divided_clk_in : STD_LOGIC := '0';
|
| 9596 |
|
|
SIGNAL divided_clk : STD_LOGIC := '0';
|
| 9597 |
|
|
|
| 9598 |
|
|
-- timing outputs
|
| 9599 |
|
|
SIGNAL tmp_clkout : STD_LOGIC := '0';
|
| 9600 |
|
|
|
| 9601 |
|
|
-- timing inputs
|
| 9602 |
|
|
SIGNAL clk_in : std_logic := '0';
|
| 9603 |
|
|
SIGNAL phaseselect_in : std_logic := '0';
|
| 9604 |
|
|
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 9605 |
|
|
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
|
| 9606 |
|
|
SIGNAL phaseinvertctrl_in : std_logic := '0';
|
| 9607 |
|
|
SIGNAL masterin_in : std_logic := '0';
|
| 9608 |
|
|
|
| 9609 |
|
|
BEGIN
|
| 9610 |
|
|
|
| 9611 |
|
|
-- delay chain
|
| 9612 |
|
|
m_delay_chain : stratixiii_ddr_delay_chain_s
|
| 9613 |
|
|
GENERIC MAP (
|
| 9614 |
|
|
phase_setting => phase_setting,
|
| 9615 |
|
|
use_phasectrlin => use_phasectrlin,
|
| 9616 |
|
|
delay_buffer_mode => delay_buffer_mode,
|
| 9617 |
|
|
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
|
| 9618 |
|
|
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
|
| 9619 |
|
|
sim_buffer_delay_increment => sim_buffer_delay_increment
|
| 9620 |
|
|
)
|
| 9621 |
|
|
PORT MAP(
|
| 9622 |
|
|
clk => clk_in,
|
| 9623 |
|
|
delayctrlin => delayctrlin_in,
|
| 9624 |
|
|
phasectrlin => phasectrlin_in,
|
| 9625 |
|
|
delayed_clkout => phasectrl_clkout
|
| 9626 |
|
|
);
|
| 9627 |
|
|
|
| 9628 |
|
|
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
|
| 9629 |
|
|
phasectrl_clkout WHEN (invert_phase = "false") ELSE
|
| 9630 |
|
|
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
|
| 9631 |
|
|
phasectrl_clkout;
|
| 9632 |
|
|
|
| 9633 |
|
|
divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk;
|
| 9634 |
|
|
|
| 9635 |
|
|
PROCESS (delayed_clk)
|
| 9636 |
|
|
BEGIN
|
| 9637 |
|
|
if (delayed_clk = '1') then
|
| 9638 |
|
|
divided_clk <= not divided_clk_in;
|
| 9639 |
|
|
end if;
|
| 9640 |
|
|
END PROCESS;
|
| 9641 |
|
|
|
| 9642 |
|
|
|
| 9643 |
|
|
tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk;
|
| 9644 |
|
|
|
| 9645 |
|
|
slaveout <= divided_clk;
|
| 9646 |
|
|
|
| 9647 |
|
|
----------------------------------
|
| 9648 |
|
|
-- Path Delay Section
|
| 9649 |
|
|
----------------------------------
|
| 9650 |
|
|
|
| 9651 |
|
|
VITAL: process(tmp_clkout)
|
| 9652 |
|
|
variable clkout_VitalGlitchData : VitalGlitchDataType;
|
| 9653 |
|
|
begin
|
| 9654 |
|
|
VitalPathDelay01 (
|
| 9655 |
|
|
OutSignal => clkout,
|
| 9656 |
|
|
OutSignalName => "clkout",
|
| 9657 |
|
|
OutTemp => tmp_clkout,
|
| 9658 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)),
|
| 9659 |
|
|
GlitchData => clkout_VitalGlitchData,
|
| 9660 |
|
|
Mode => DefGlitchMode,
|
| 9661 |
|
|
XOn => XOn,
|
| 9662 |
|
|
MsgOn => MsgOn );
|
| 9663 |
|
|
end process;
|
| 9664 |
|
|
|
| 9665 |
|
|
--------------------
|
| 9666 |
|
|
-- INPUT PATH DELAYS
|
| 9667 |
|
|
--------------------
|
| 9668 |
|
|
WireDelay : block
|
| 9669 |
|
|
begin
|
| 9670 |
|
|
VitalWireDelay (clk_in, clk, tipd_clk);
|
| 9671 |
|
|
VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect);
|
| 9672 |
|
|
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
|
| 9673 |
|
|
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
|
| 9674 |
|
|
END GENERATE;
|
| 9675 |
|
|
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
|
| 9676 |
|
|
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
|
| 9677 |
|
|
END GENERATE;
|
| 9678 |
|
|
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
|
| 9679 |
|
|
VitalWireDelay (masterin_in, masterin, tipd_masterin);
|
| 9680 |
|
|
end block;
|
| 9681 |
|
|
|
| 9682 |
|
|
END stratixiii_io_clock_divider_arch;
|
| 9683 |
|
|
|
| 9684 |
|
|
-------------------------------------------------------------------------------
|
| 9685 |
|
|
--
|
| 9686 |
|
|
-- Entity Name : stratixiii_output_phase_alignment
|
| 9687 |
|
|
--
|
| 9688 |
|
|
-------------------------------------------------------------------------------
|
| 9689 |
|
|
|
| 9690 |
|
|
library IEEE;
|
| 9691 |
|
|
use IEEE.std_logic_1164.all;
|
| 9692 |
|
|
use IEEE.std_logic_arith.all;
|
| 9693 |
|
|
use IEEE.std_logic_unsigned.all;
|
| 9694 |
|
|
use IEEE.VITAL_Timing.all;
|
| 9695 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 9696 |
|
|
use work.stratixiii_atom_pack.all;
|
| 9697 |
|
|
use work.stratixiii_ddr_io_reg;
|
| 9698 |
|
|
use work.stratixiii_ddr_delay_chain_s;
|
| 9699 |
|
|
|
| 9700 |
|
|
ENTITY stratixiii_output_phase_alignment IS
|
| 9701 |
|
|
GENERIC (
|
| 9702 |
|
|
operation_mode : string := "ddio_out";
|
| 9703 |
|
|
use_phasectrlin : string := "true";
|
| 9704 |
|
|
phase_setting : integer := 0;
|
| 9705 |
|
|
delay_buffer_mode : string := "high";
|
| 9706 |
|
|
power_up : string := "low";
|
| 9707 |
|
|
async_mode : string := "none";
|
| 9708 |
|
|
sync_mode : string := "none";
|
| 9709 |
|
|
add_output_cycle_delay : string := "false";
|
| 9710 |
|
|
use_delayed_clock : string := "false";
|
| 9711 |
|
|
add_phase_transfer_reg : string := "false";
|
| 9712 |
|
|
use_phasectrl_clock : string := "true";
|
| 9713 |
|
|
use_primary_clock : string := "true";
|
| 9714 |
|
|
invert_phase : string := "false";
|
| 9715 |
|
|
bypass_input_register : string := "false";
|
| 9716 |
|
|
phase_setting_for_delayed_clock : integer := 2;
|
| 9717 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 9718 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 9719 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 9720 |
|
|
lpm_type : string := "stratixiii_output_phase_alignment";
|
| 9721 |
|
|
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
|
| 9722 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 9723 |
|
|
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
| 9724 |
|
|
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
| 9725 |
|
|
tipd_areset : VitalDelayType01 := DefpropDelay01;
|
| 9726 |
|
|
tipd_sreset : VitalDelayType01 := DefpropDelay01;
|
| 9727 |
|
|
tipd_clkena : VitalDelayType01 := DefpropDelay01;
|
| 9728 |
|
|
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
|
| 9729 |
|
|
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
|
| 9730 |
|
|
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
|
| 9731 |
|
|
TimingChecksOn : Boolean := True;
|
| 9732 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 9733 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 9734 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 9735 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 9736 |
|
|
InstancePath : String := "*"
|
| 9737 |
|
|
);
|
| 9738 |
|
|
|
| 9739 |
|
|
PORT (
|
| 9740 |
|
|
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
|
| 9741 |
|
|
clk : IN std_logic := '0';
|
| 9742 |
|
|
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 9743 |
|
|
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
|
| 9744 |
|
|
areset : IN std_logic := '0';
|
| 9745 |
|
|
sreset : IN std_logic := '0';
|
| 9746 |
|
|
clkena : IN std_logic := '1';
|
| 9747 |
|
|
enaoutputcycledelay : IN std_logic := '0';
|
| 9748 |
|
|
enaphasetransferreg : IN std_logic := '0';
|
| 9749 |
|
|
phaseinvertctrl : IN std_logic := '0';
|
| 9750 |
|
|
devclrn : IN std_logic := '1';
|
| 9751 |
|
|
devpor : IN std_logic := '1';
|
| 9752 |
|
|
dataout : OUT std_logic;
|
| 9753 |
|
|
dffin : OUT std_logic_vector(1 downto 0);
|
| 9754 |
|
|
dff1t : OUT std_logic_vector(1 downto 0);
|
| 9755 |
|
|
dffddiodataout : OUT std_logic
|
| 9756 |
|
|
);
|
| 9757 |
|
|
|
| 9758 |
|
|
END;
|
| 9759 |
|
|
|
| 9760 |
|
|
ARCHITECTURE stratixiii_output_phase_alignment_arch OF stratixiii_output_phase_alignment IS
|
| 9761 |
|
|
-- component section
|
| 9762 |
|
|
COMPONENT stratixiii_ddr_delay_chain_s
|
| 9763 |
|
|
GENERIC (
|
| 9764 |
|
|
use_phasectrlin : string := "true";
|
| 9765 |
|
|
phase_setting : integer := 0;
|
| 9766 |
|
|
delay_buffer_mode : string := "high";
|
| 9767 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 9768 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 9769 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 9770 |
|
|
phasectrlin_limit : integer := 7
|
| 9771 |
|
|
);
|
| 9772 |
|
|
PORT (
|
| 9773 |
|
|
clk : IN std_logic := '0';
|
| 9774 |
|
|
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
|
| 9775 |
|
|
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
|
| 9776 |
|
|
delayed_clkout : OUT std_logic
|
| 9777 |
|
|
);
|
| 9778 |
|
|
END COMPONENT;
|
| 9779 |
|
|
|
| 9780 |
|
|
component stratixiii_ddr_io_reg
|
| 9781 |
|
|
generic (
|
| 9782 |
|
|
power_up : string := "DONT_CARE";
|
| 9783 |
|
|
is_wysiwyg : string := "false";
|
| 9784 |
|
|
x_on_violation : string := "on";
|
| 9785 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9786 |
|
|
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9787 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9788 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9789 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9790 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9791 |
|
|
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9792 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9793 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9794 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 9795 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 9796 |
|
|
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 9797 |
|
|
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 9798 |
|
|
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
| 9799 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 9800 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 9801 |
|
|
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
| 9802 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
| 9803 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 9804 |
|
|
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
| 9805 |
|
|
tipd_prn : VitalDelayType01 := DefPropDelay01;
|
| 9806 |
|
|
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
| 9807 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 9808 |
|
|
TimingChecksOn: Boolean := True;
|
| 9809 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 9810 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 9811 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 9812 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 9813 |
|
|
InstancePath: STRING := "*"
|
| 9814 |
|
|
);
|
| 9815 |
|
|
|
| 9816 |
|
|
port (
|
| 9817 |
|
|
d : in std_logic := '0';
|
| 9818 |
|
|
clk : in std_logic := '0';
|
| 9819 |
|
|
ena : in std_logic := '1';
|
| 9820 |
|
|
clrn : in std_logic := '1';
|
| 9821 |
|
|
prn : in std_logic := '1';
|
| 9822 |
|
|
aload : in std_logic := '0';
|
| 9823 |
|
|
asdata : in std_logic := '0';
|
| 9824 |
|
|
sclr : in std_logic := '0';
|
| 9825 |
|
|
sload : in std_logic := '0';
|
| 9826 |
|
|
devclrn : in std_logic := '1';
|
| 9827 |
|
|
devpor : in std_logic := '1';
|
| 9828 |
|
|
q : out std_logic
|
| 9829 |
|
|
);
|
| 9830 |
|
|
end component;
|
| 9831 |
|
|
|
| 9832 |
|
|
-- int signals on clock paths
|
| 9833 |
|
|
SIGNAL clk_in_delayed: STD_LOGIC := '0';
|
| 9834 |
|
|
SIGNAL clk_in_mux: STD_LOGIC := '0';
|
| 9835 |
|
|
SIGNAL phasectrl_clkout: STD_LOGIC := '0';
|
| 9836 |
|
|
SIGNAL phaseinvertctrl_out: STD_LOGIC := '0';
|
| 9837 |
|
|
|
| 9838 |
|
|
SIGNAL m_vcc: STD_LOGIC := '1';
|
| 9839 |
|
|
SIGNAL m_gnd: STD_LOGIC := '0';
|
| 9840 |
|
|
|
| 9841 |
|
|
-- IO registers
|
| 9842 |
|
|
-- common
|
| 9843 |
|
|
SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg
|
| 9844 |
|
|
SIGNAL sclr_in_r : STD_LOGIC := '0';
|
| 9845 |
|
|
SIGNAL sload_in_r : STD_LOGIC := '0';
|
| 9846 |
|
|
SIGNAL sclr_in : STD_LOGIC := '0';
|
| 9847 |
|
|
SIGNAL sload_in : STD_LOGIC := '0';
|
| 9848 |
|
|
SIGNAL adatasdata_in : STD_LOGIC := '0';
|
| 9849 |
|
|
SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers
|
| 9850 |
|
|
SIGNAL prn_in_r : STD_LOGIC := '1';
|
| 9851 |
|
|
|
| 9852 |
|
|
SIGNAL datain_q: STD_LOGIC := '0';
|
| 9853 |
|
|
SIGNAL ddio_datain_q: STD_LOGIC := '0';
|
| 9854 |
|
|
|
| 9855 |
|
|
SIGNAL cycledelay_q: STD_LOGIC := '0';
|
| 9856 |
|
|
SIGNAL ddio_cycledelay_q: STD_LOGIC := '0';
|
| 9857 |
|
|
|
| 9858 |
|
|
SIGNAL cycledelay_mux_out: STD_LOGIC := '0';
|
| 9859 |
|
|
SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0';
|
| 9860 |
|
|
|
| 9861 |
|
|
SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0';
|
| 9862 |
|
|
SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0';
|
| 9863 |
|
|
|
| 9864 |
|
|
SIGNAL not_clk_in_mux: STD_LOGIC := '0';
|
| 9865 |
|
|
|
| 9866 |
|
|
SIGNAL ddio_out_clk_mux: STD_LOGIC := '0';
|
| 9867 |
|
|
SIGNAL ddio_out_lo_q: STD_LOGIC := '0';
|
| 9868 |
|
|
SIGNAL ddio_out_hi_q: STD_LOGIC := '0';
|
| 9869 |
|
|
|
| 9870 |
|
|
-- transfer delay now by negative clk
|
| 9871 |
|
|
SIGNAL transfer_q: STD_LOGIC := '0';
|
| 9872 |
|
|
SIGNAL ddio_transfer_q: STD_LOGIC := '0';
|
| 9873 |
|
|
|
| 9874 |
|
|
SIGNAL dlyclk_clk: STD_LOGIC := '0';
|
| 9875 |
|
|
SIGNAL dlyclk_d: STD_LOGIC := '0';
|
| 9876 |
|
|
SIGNAL dlyclk_q: STD_LOGIC := '0';
|
| 9877 |
|
|
SIGNAL ddio_dlyclk_d: STD_LOGIC := '0';
|
| 9878 |
|
|
SIGNAL ddio_dlyclk_q: STD_LOGIC := '0';
|
| 9879 |
|
|
|
| 9880 |
|
|
SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared
|
| 9881 |
|
|
SIGNAL dlyclk_extended_q: STD_LOGIC := '0';
|
| 9882 |
|
|
SIGNAL dlyclk_extended_clk: STD_LOGIC := '0';
|
| 9883 |
|
|
|
| 9884 |
|
|
SIGNAL normal_dataout: STD_LOGIC := '0';
|
| 9885 |
|
|
SIGNAL extended_dataout: STD_LOGIC := '0';
|
| 9886 |
|
|
SIGNAL ddio_dataout: STD_LOGIC := '0';
|
| 9887 |
|
|
SIGNAL tmp_dataout: STD_LOGIC := '0';
|
| 9888 |
|
|
|
| 9889 |
|
|
|
| 9890 |
|
|
-- timing inputs
|
| 9891 |
|
|
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
|
| 9892 |
|
|
SIGNAL clk_in : std_logic := '0';
|
| 9893 |
|
|
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 9894 |
|
|
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
|
| 9895 |
|
|
SIGNAL areset_in : std_logic := '0';
|
| 9896 |
|
|
SIGNAL sreset_in : std_logic := '0';
|
| 9897 |
|
|
SIGNAL clkena_in : std_logic := '1';
|
| 9898 |
|
|
SIGNAL enaoutputcycledelay_in : std_logic := '0';
|
| 9899 |
|
|
SIGNAL enaphasetransferreg_in : std_logic := '0';
|
| 9900 |
|
|
SIGNAL phaseinvertctrl_in : std_logic := '0';
|
| 9901 |
|
|
|
| 9902 |
|
|
BEGIN
|
| 9903 |
|
|
|
| 9904 |
|
|
-- delay chain for clk_in delay
|
| 9905 |
|
|
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
|
| 9906 |
|
|
GENERIC MAP (
|
| 9907 |
|
|
phase_setting => phase_setting_for_delayed_clock,
|
| 9908 |
|
|
use_phasectrlin => "false",
|
| 9909 |
|
|
delay_buffer_mode => delay_buffer_mode,
|
| 9910 |
|
|
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
|
| 9911 |
|
|
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
|
| 9912 |
|
|
sim_buffer_delay_increment => sim_buffer_delay_increment
|
| 9913 |
|
|
)
|
| 9914 |
|
|
PORT MAP(
|
| 9915 |
|
|
clk => clk_in,
|
| 9916 |
|
|
delayctrlin => delayctrlin_in,
|
| 9917 |
|
|
phasectrlin => phasectrlin_in,
|
| 9918 |
|
|
delayed_clkout => clk_in_delayed
|
| 9919 |
|
|
);
|
| 9920 |
|
|
|
| 9921 |
|
|
-- clock source for datain and cycle delay registers
|
| 9922 |
|
|
clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in;
|
| 9923 |
|
|
|
| 9924 |
|
|
-- delay chain for phase control
|
| 9925 |
|
|
m_delay_chain : stratixiii_ddr_delay_chain_s
|
| 9926 |
|
|
GENERIC MAP (
|
| 9927 |
|
|
phase_setting => phase_setting,
|
| 9928 |
|
|
use_phasectrlin => use_phasectrlin,
|
| 9929 |
|
|
delay_buffer_mode => delay_buffer_mode,
|
| 9930 |
|
|
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
|
| 9931 |
|
|
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
|
| 9932 |
|
|
phasectrlin_limit => 10,
|
| 9933 |
|
|
sim_buffer_delay_increment => sim_buffer_delay_increment
|
| 9934 |
|
|
)
|
| 9935 |
|
|
PORT MAP(
|
| 9936 |
|
|
clk => clk_in,
|
| 9937 |
|
|
delayctrlin => delayctrlin_in,
|
| 9938 |
|
|
phasectrlin => phasectrlin_in,
|
| 9939 |
|
|
delayed_clkout => phasectrl_clkout
|
| 9940 |
|
|
);
|
| 9941 |
|
|
|
| 9942 |
|
|
-- primary outputs
|
| 9943 |
|
|
normal_dataout <= dlyclk_q;
|
| 9944 |
|
|
extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low
|
| 9945 |
|
|
ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q;
|
| 9946 |
|
|
tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE
|
| 9947 |
|
|
extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE
|
| 9948 |
|
|
normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE
|
| 9949 |
|
|
'Z';
|
| 9950 |
|
|
dataout <= tmp_dataout;
|
| 9951 |
|
|
|
| 9952 |
|
|
ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h
|
| 9953 |
|
|
ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l
|
| 9954 |
|
|
ddio_out_hi_q <= ddio_dlyclk_q;
|
| 9955 |
|
|
|
| 9956 |
|
|
-- resolve reset modes
|
| 9957 |
|
|
PROCESS(areset_in)
|
| 9958 |
|
|
BEGIN
|
| 9959 |
|
|
IF (async_mode = "clear") THEN
|
| 9960 |
|
|
clrn_in_r <= not areset_in;
|
| 9961 |
|
|
prn_in_r <= '1';
|
| 9962 |
|
|
ELSIF (async_mode = "preset") THEN
|
| 9963 |
|
|
prn_in_r <= not areset_in;
|
| 9964 |
|
|
clrn_in_r <= '1';
|
| 9965 |
|
|
END IF;
|
| 9966 |
|
|
END PROCESS;
|
| 9967 |
|
|
|
| 9968 |
|
|
PROCESS(sreset_in)
|
| 9969 |
|
|
BEGIN
|
| 9970 |
|
|
IF (sync_mode = "clear") THEN
|
| 9971 |
|
|
sclr_in_r <= sreset_in;
|
| 9972 |
|
|
adatasdata_in_r <= '0';
|
| 9973 |
|
|
sload_in_r <= '0';
|
| 9974 |
|
|
ELSIF (sync_mode = "preset") THEN
|
| 9975 |
|
|
sload_in_r <= sreset_in;
|
| 9976 |
|
|
adatasdata_in_r <= '1';
|
| 9977 |
|
|
sclr_in_r <= '0';
|
| 9978 |
|
|
END IF;
|
| 9979 |
|
|
END PROCESS;
|
| 9980 |
|
|
|
| 9981 |
|
|
|
| 9982 |
|
|
sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r;
|
| 9983 |
|
|
sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r;
|
| 9984 |
|
|
adatasdata_in <= adatasdata_in_r;
|
| 9985 |
|
|
dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in;
|
| 9986 |
|
|
|
| 9987 |
|
|
-- Datain Register
|
| 9988 |
|
|
datain_reg : stratixiii_ddr_io_reg
|
| 9989 |
|
|
GENERIC MAP (power_up => power_up)
|
| 9990 |
|
|
PORT MAP(
|
| 9991 |
|
|
d => datain_in(0),
|
| 9992 |
|
|
clk => clk_in_mux,
|
| 9993 |
|
|
ena => m_vcc,
|
| 9994 |
|
|
clrn => clrn_in_r,
|
| 9995 |
|
|
prn => prn_in_r,
|
| 9996 |
|
|
aload => m_gnd,
|
| 9997 |
|
|
asdata => adatasdata_in,
|
| 9998 |
|
|
sclr => m_gnd,
|
| 9999 |
|
|
sload => m_gnd,
|
| 10000 |
|
|
devclrn => devclrn,
|
| 10001 |
|
|
devpor => devpor,
|
| 10002 |
|
|
q => datain_q
|
| 10003 |
|
|
);
|
| 10004 |
|
|
|
| 10005 |
|
|
-- DDIO Datain Register
|
| 10006 |
|
|
ddio_datain_reg : stratixiii_ddr_io_reg
|
| 10007 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10008 |
|
|
PORT MAP(
|
| 10009 |
|
|
d => datain_in(1),
|
| 10010 |
|
|
clk => clk_in_mux,
|
| 10011 |
|
|
ena => m_vcc,
|
| 10012 |
|
|
clrn => clrn_in_r,
|
| 10013 |
|
|
prn => prn_in_r,
|
| 10014 |
|
|
aload => m_gnd,
|
| 10015 |
|
|
asdata => adatasdata_in,
|
| 10016 |
|
|
sclr => m_gnd,
|
| 10017 |
|
|
sload => m_gnd,
|
| 10018 |
|
|
devclrn => devclrn,
|
| 10019 |
|
|
devpor => devpor,
|
| 10020 |
|
|
q => ddio_datain_q
|
| 10021 |
|
|
);
|
| 10022 |
|
|
|
| 10023 |
|
|
-- Cycle Delay Register
|
| 10024 |
|
|
cycledelay_reg : stratixiii_ddr_io_reg
|
| 10025 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10026 |
|
|
PORT MAP(
|
| 10027 |
|
|
d => datain_q,
|
| 10028 |
|
|
clk => clk_in_mux,
|
| 10029 |
|
|
ena => m_vcc,
|
| 10030 |
|
|
clrn => clrn_in_r,
|
| 10031 |
|
|
prn => prn_in_r,
|
| 10032 |
|
|
aload => m_gnd,
|
| 10033 |
|
|
asdata => adatasdata_in,
|
| 10034 |
|
|
sclr => m_gnd,
|
| 10035 |
|
|
sload => m_gnd,
|
| 10036 |
|
|
devclrn => devclrn,
|
| 10037 |
|
|
devpor => devpor,
|
| 10038 |
|
|
q => cycledelay_q
|
| 10039 |
|
|
);
|
| 10040 |
|
|
|
| 10041 |
|
|
-- DDIO Cycle Delay Register
|
| 10042 |
|
|
ddio_cycledelay_reg : stratixiii_ddr_io_reg
|
| 10043 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10044 |
|
|
PORT MAP(
|
| 10045 |
|
|
d => ddio_datain_q,
|
| 10046 |
|
|
clk => clk_in_mux,
|
| 10047 |
|
|
ena => m_vcc,
|
| 10048 |
|
|
clrn => clrn_in_r,
|
| 10049 |
|
|
prn => prn_in_r,
|
| 10050 |
|
|
aload => m_gnd,
|
| 10051 |
|
|
asdata => adatasdata_in,
|
| 10052 |
|
|
sclr => m_gnd,
|
| 10053 |
|
|
sload => m_gnd,
|
| 10054 |
|
|
devclrn => devclrn,
|
| 10055 |
|
|
devpor => devpor,
|
| 10056 |
|
|
q => ddio_cycledelay_q
|
| 10057 |
|
|
);
|
| 10058 |
|
|
|
| 10059 |
|
|
-- enaoutputcycledelay data path mux
|
| 10060 |
|
|
cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
|
| 10061 |
|
|
datain_q WHEN (add_output_cycle_delay = "false") ELSE
|
| 10062 |
|
|
cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
|
| 10063 |
|
|
datain_q;
|
| 10064 |
|
|
|
| 10065 |
|
|
-- input register bypass mux
|
| 10066 |
|
|
bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out;
|
| 10067 |
|
|
|
| 10068 |
|
|
--assign #300 transfer_q = cycledelay_mux_out;
|
| 10069 |
|
|
-- transfer delay is implemented with negative register in rev1.26
|
| 10070 |
|
|
transferdelay_reg : stratixiii_ddr_io_reg
|
| 10071 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10072 |
|
|
PORT MAP(
|
| 10073 |
|
|
d => bypass_input_reg_mux_out,
|
| 10074 |
|
|
clk => not_clk_in_mux,
|
| 10075 |
|
|
ena => m_vcc,
|
| 10076 |
|
|
clrn => clrn_in_r,
|
| 10077 |
|
|
prn => prn_in_r,
|
| 10078 |
|
|
aload => m_gnd,
|
| 10079 |
|
|
asdata => adatasdata_in,
|
| 10080 |
|
|
sclr => sclr_in,
|
| 10081 |
|
|
sload => sload_in,
|
| 10082 |
|
|
devclrn => devclrn,
|
| 10083 |
|
|
devpor => devpor,
|
| 10084 |
|
|
q => transfer_q
|
| 10085 |
|
|
);
|
| 10086 |
|
|
|
| 10087 |
|
|
-- add phase transfer data path mux
|
| 10088 |
|
|
dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
|
| 10089 |
|
|
bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
|
| 10090 |
|
|
transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
|
| 10091 |
|
|
bypass_input_reg_mux_out;
|
| 10092 |
|
|
|
| 10093 |
|
|
-- clock mux for the output register
|
| 10094 |
|
|
phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
|
| 10095 |
|
|
phasectrl_clkout WHEN (invert_phase = "false") ELSE
|
| 10096 |
|
|
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE
|
| 10097 |
|
|
phasectrl_clkout;
|
| 10098 |
|
|
|
| 10099 |
|
|
dlyclk_clk <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux;
|
| 10100 |
|
|
|
| 10101 |
|
|
-- Output Register clocked by phasectrl_clk
|
| 10102 |
|
|
dlyclk_reg : stratixiii_ddr_io_reg
|
| 10103 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10104 |
|
|
PORT MAP(
|
| 10105 |
|
|
d => dlyclk_d,
|
| 10106 |
|
|
clk => dlyclk_clk,
|
| 10107 |
|
|
ena => dlyclk_clkena_in,
|
| 10108 |
|
|
clrn => clrn_in_r,
|
| 10109 |
|
|
prn => prn_in_r,
|
| 10110 |
|
|
aload => m_gnd,
|
| 10111 |
|
|
asdata => adatasdata_in,
|
| 10112 |
|
|
sclr => sclr_in,
|
| 10113 |
|
|
sload => sload_in,
|
| 10114 |
|
|
devclrn => devclrn,
|
| 10115 |
|
|
devpor => devpor,
|
| 10116 |
|
|
q => dlyclk_q
|
| 10117 |
|
|
);
|
| 10118 |
|
|
|
| 10119 |
|
|
-- enaoutputcycledelay data path mux
|
| 10120 |
|
|
ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
|
| 10121 |
|
|
ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE
|
| 10122 |
|
|
ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
|
| 10123 |
|
|
ddio_datain_q;
|
| 10124 |
|
|
|
| 10125 |
|
|
-- input register bypass mux
|
| 10126 |
|
|
ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out;
|
| 10127 |
|
|
|
| 10128 |
|
|
--assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
|
| 10129 |
|
|
-- transfer delay is implemented with negative register in rev1.26
|
| 10130 |
|
|
not_clk_in_mux <= not clk_in_mux;
|
| 10131 |
|
|
|
| 10132 |
|
|
ddio_transferdelay_reg : stratixiii_ddr_io_reg
|
| 10133 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10134 |
|
|
PORT MAP(
|
| 10135 |
|
|
d => ddio_bypass_input_reg_mux_out,
|
| 10136 |
|
|
clk => not_clk_in_mux,
|
| 10137 |
|
|
ena => m_vcc,
|
| 10138 |
|
|
clrn => clrn_in_r,
|
| 10139 |
|
|
prn => prn_in_r,
|
| 10140 |
|
|
aload => m_gnd,
|
| 10141 |
|
|
asdata => adatasdata_in,
|
| 10142 |
|
|
sclr => sclr_in,
|
| 10143 |
|
|
sload => sload_in,
|
| 10144 |
|
|
devclrn => devclrn,
|
| 10145 |
|
|
devpor => devpor,
|
| 10146 |
|
|
q => ddio_transfer_q
|
| 10147 |
|
|
);
|
| 10148 |
|
|
|
| 10149 |
|
|
-- add phase transfer data path mux
|
| 10150 |
|
|
ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
|
| 10151 |
|
|
ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
|
| 10152 |
|
|
ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
|
| 10153 |
|
|
ddio_bypass_input_reg_mux_out;
|
| 10154 |
|
|
|
| 10155 |
|
|
-- Output Register clocked by phasectrl_clk
|
| 10156 |
|
|
ddio_dlyclk_reg : stratixiii_ddr_io_reg
|
| 10157 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10158 |
|
|
PORT MAP(
|
| 10159 |
|
|
d => ddio_dlyclk_d,
|
| 10160 |
|
|
clk => dlyclk_clk,
|
| 10161 |
|
|
ena => dlyclk_clkena_in,
|
| 10162 |
|
|
clrn => clrn_in_r,
|
| 10163 |
|
|
prn => prn_in_r,
|
| 10164 |
|
|
aload => m_gnd,
|
| 10165 |
|
|
asdata => adatasdata_in,
|
| 10166 |
|
|
sclr => sclr_in,
|
| 10167 |
|
|
sload => sload_in,
|
| 10168 |
|
|
devclrn => devclrn,
|
| 10169 |
|
|
devpor => devpor,
|
| 10170 |
|
|
q => ddio_dlyclk_q
|
| 10171 |
|
|
);
|
| 10172 |
|
|
|
| 10173 |
|
|
-- Extension Register
|
| 10174 |
|
|
dlyclk_extended_clk <= not dlyclk_clk;
|
| 10175 |
|
|
|
| 10176 |
|
|
dlyclk_extended_reg : stratixiii_ddr_io_reg
|
| 10177 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10178 |
|
|
PORT MAP(
|
| 10179 |
|
|
d => dlyclk_q,
|
| 10180 |
|
|
clk => dlyclk_extended_clk,
|
| 10181 |
|
|
ena => dlyclk_clkena_in,
|
| 10182 |
|
|
clrn => clrn_in_r,
|
| 10183 |
|
|
prn => prn_in_r,
|
| 10184 |
|
|
aload => m_gnd,
|
| 10185 |
|
|
asdata => adatasdata_in,
|
| 10186 |
|
|
sclr => sclr_in,
|
| 10187 |
|
|
sload => sload_in,
|
| 10188 |
|
|
devclrn => devclrn,
|
| 10189 |
|
|
devpor => devpor,
|
| 10190 |
|
|
q => dlyclk_extended_q
|
| 10191 |
|
|
);
|
| 10192 |
|
|
|
| 10193 |
|
|
--------------------
|
| 10194 |
|
|
-- INPUT PATH DELAYS
|
| 10195 |
|
|
--------------------
|
| 10196 |
|
|
WireDelay : block
|
| 10197 |
|
|
begin
|
| 10198 |
|
|
loopbits_datain : FOR i in datain'RANGE GENERATE
|
| 10199 |
|
|
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
|
| 10200 |
|
|
END GENERATE;
|
| 10201 |
|
|
VitalWireDelay (clk_in, clk, tipd_clk);
|
| 10202 |
|
|
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
|
| 10203 |
|
|
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
|
| 10204 |
|
|
END GENERATE;
|
| 10205 |
|
|
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
|
| 10206 |
|
|
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
|
| 10207 |
|
|
END GENERATE;
|
| 10208 |
|
|
VitalWireDelay (areset_in, areset, tipd_areset);
|
| 10209 |
|
|
VitalWireDelay (sreset_in, sreset, tipd_sreset);
|
| 10210 |
|
|
VitalWireDelay (clkena_in, clkena, tipd_clkena);
|
| 10211 |
|
|
end block;
|
| 10212 |
|
|
|
| 10213 |
|
|
END stratixiii_output_phase_alignment_arch;
|
| 10214 |
|
|
|
| 10215 |
|
|
-------------------------------------------------------------------------------
|
| 10216 |
|
|
--
|
| 10217 |
|
|
-- Entity Name : stratixiii_input_phase_alignment
|
| 10218 |
|
|
--
|
| 10219 |
|
|
-------------------------------------------------------------------------------
|
| 10220 |
|
|
|
| 10221 |
|
|
library IEEE;
|
| 10222 |
|
|
use IEEE.std_logic_1164.all;
|
| 10223 |
|
|
use IEEE.VITAL_Timing.all;
|
| 10224 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 10225 |
|
|
use work.stratixiii_atom_pack.all;
|
| 10226 |
|
|
use work.stratixiii_ddr_io_reg;
|
| 10227 |
|
|
use work.stratixiii_ddr_delay_chain_s;
|
| 10228 |
|
|
|
| 10229 |
|
|
ENTITY stratixiii_input_phase_alignment IS
|
| 10230 |
|
|
GENERIC (
|
| 10231 |
|
|
use_phasectrlin : string := "true";
|
| 10232 |
|
|
phase_setting : integer := 0;
|
| 10233 |
|
|
delay_buffer_mode : string := "high";
|
| 10234 |
|
|
power_up : string := "low";
|
| 10235 |
|
|
async_mode : string := "none";
|
| 10236 |
|
|
add_input_cycle_delay : string := "false";
|
| 10237 |
|
|
bypass_output_register : string := "false";
|
| 10238 |
|
|
add_phase_transfer_reg : string := "false";
|
| 10239 |
|
|
invert_phase : string := "false";
|
| 10240 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 10241 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 10242 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 10243 |
|
|
lpm_type : string := "stratixiii_input_phase_alignment";
|
| 10244 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01;
|
| 10245 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 10246 |
|
|
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
| 10247 |
|
|
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
| 10248 |
|
|
tipd_areset : VitalDelayType01 := DefpropDelay01;
|
| 10249 |
|
|
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
|
| 10250 |
|
|
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
|
| 10251 |
|
|
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
|
| 10252 |
|
|
TimingChecksOn : Boolean := True;
|
| 10253 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 10254 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 10255 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 10256 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 10257 |
|
|
InstancePath : String := "*"
|
| 10258 |
|
|
);
|
| 10259 |
|
|
|
| 10260 |
|
|
PORT (
|
| 10261 |
|
|
datain : IN std_logic := '0';
|
| 10262 |
|
|
clk : IN std_logic := '0';
|
| 10263 |
|
|
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 10264 |
|
|
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
|
| 10265 |
|
|
areset : IN std_logic := '0';
|
| 10266 |
|
|
enainputcycledelay : IN std_logic := '0';
|
| 10267 |
|
|
enaphasetransferreg : IN std_logic := '0';
|
| 10268 |
|
|
phaseinvertctrl : IN std_logic := '0';
|
| 10269 |
|
|
devclrn : IN std_logic := '1';
|
| 10270 |
|
|
devpor : IN std_logic := '1';
|
| 10271 |
|
|
dataout : OUT std_logic;
|
| 10272 |
|
|
dffin : OUT std_logic;
|
| 10273 |
|
|
dff1t : OUT std_logic
|
| 10274 |
|
|
);
|
| 10275 |
|
|
|
| 10276 |
|
|
END;
|
| 10277 |
|
|
|
| 10278 |
|
|
ARCHITECTURE stratixiii_input_phase_alignment_arch OF stratixiii_input_phase_alignment IS
|
| 10279 |
|
|
-- component section
|
| 10280 |
|
|
COMPONENT stratixiii_ddr_delay_chain_s
|
| 10281 |
|
|
GENERIC (
|
| 10282 |
|
|
use_phasectrlin : string := "true";
|
| 10283 |
|
|
phase_setting : integer := 0;
|
| 10284 |
|
|
delay_buffer_mode : string := "high";
|
| 10285 |
|
|
sim_low_buffer_intrinsic_delay : integer := 350;
|
| 10286 |
|
|
sim_high_buffer_intrinsic_delay : integer := 175;
|
| 10287 |
|
|
sim_buffer_delay_increment : integer := 10;
|
| 10288 |
|
|
phasectrlin_limit : integer := 7
|
| 10289 |
|
|
);
|
| 10290 |
|
|
PORT (
|
| 10291 |
|
|
clk : IN std_logic := '0';
|
| 10292 |
|
|
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
|
| 10293 |
|
|
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
|
| 10294 |
|
|
delayed_clkout : OUT std_logic
|
| 10295 |
|
|
);
|
| 10296 |
|
|
END COMPONENT;
|
| 10297 |
|
|
|
| 10298 |
|
|
component stratixiii_ddr_io_reg
|
| 10299 |
|
|
generic (
|
| 10300 |
|
|
power_up : string := "DONT_CARE";
|
| 10301 |
|
|
is_wysiwyg : string := "false";
|
| 10302 |
|
|
x_on_violation : string := "on";
|
| 10303 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10304 |
|
|
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10305 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10306 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10307 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10308 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10309 |
|
|
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10310 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10311 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10312 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10313 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 10314 |
|
|
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 10315 |
|
|
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 10316 |
|
|
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
| 10317 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 10318 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 10319 |
|
|
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
| 10320 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
| 10321 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 10322 |
|
|
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
| 10323 |
|
|
tipd_prn : VitalDelayType01 := DefPropDelay01;
|
| 10324 |
|
|
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
| 10325 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 10326 |
|
|
TimingChecksOn: Boolean := True;
|
| 10327 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 10328 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 10329 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 10330 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 10331 |
|
|
InstancePath: STRING := "*"
|
| 10332 |
|
|
);
|
| 10333 |
|
|
|
| 10334 |
|
|
port (
|
| 10335 |
|
|
d : in std_logic := '0';
|
| 10336 |
|
|
clk : in std_logic := '0';
|
| 10337 |
|
|
ena : in std_logic := '1';
|
| 10338 |
|
|
clrn : in std_logic := '1';
|
| 10339 |
|
|
prn : in std_logic := '1';
|
| 10340 |
|
|
aload : in std_logic := '0';
|
| 10341 |
|
|
asdata : in std_logic := '0';
|
| 10342 |
|
|
sclr : in std_logic := '0';
|
| 10343 |
|
|
sload : in std_logic := '0';
|
| 10344 |
|
|
devclrn : in std_logic := '1';
|
| 10345 |
|
|
devpor : in std_logic := '1';
|
| 10346 |
|
|
q : out std_logic
|
| 10347 |
|
|
);
|
| 10348 |
|
|
end component;
|
| 10349 |
|
|
|
| 10350 |
|
|
-- int signals
|
| 10351 |
|
|
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
|
| 10352 |
|
|
SIGNAL delayed_clk : STD_LOGIC := '0';
|
| 10353 |
|
|
SIGNAL not_delayed_clk : STD_LOGIC := '1';
|
| 10354 |
|
|
|
| 10355 |
|
|
SIGNAL m_vcc: STD_LOGIC := '1';
|
| 10356 |
|
|
SIGNAL m_gnd: STD_LOGIC := '0';
|
| 10357 |
|
|
|
| 10358 |
|
|
-- IO registers
|
| 10359 |
|
|
-- common
|
| 10360 |
|
|
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
|
| 10361 |
|
|
SIGNAL aload_in_r : STD_LOGIC := '0';
|
| 10362 |
|
|
|
| 10363 |
|
|
SIGNAL datain_q : STD_LOGIC := '0';
|
| 10364 |
|
|
|
| 10365 |
|
|
SIGNAL cycledelay_q : STD_LOGIC := '0';
|
| 10366 |
|
|
SIGNAL cycledelay_mux_out : STD_LOGIC := '0';
|
| 10367 |
|
|
SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0';
|
| 10368 |
|
|
|
| 10369 |
|
|
SIGNAL dlyclk_d : STD_LOGIC := '0';
|
| 10370 |
|
|
SIGNAL dlyclk_q : STD_LOGIC := '0';
|
| 10371 |
|
|
|
| 10372 |
|
|
SIGNAL tmp_dataout : STD_LOGIC := '0';
|
| 10373 |
|
|
|
| 10374 |
|
|
-- timing inputs
|
| 10375 |
|
|
SIGNAL datain_in : std_logic := '0';
|
| 10376 |
|
|
SIGNAL clk_in : std_logic := '0';
|
| 10377 |
|
|
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
|
| 10378 |
|
|
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
|
| 10379 |
|
|
SIGNAL areset_in : std_logic := '0';
|
| 10380 |
|
|
SIGNAL enainputcycledelay_in : std_logic := '0';
|
| 10381 |
|
|
SIGNAL enaphasetransferreg_in : std_logic := '0';
|
| 10382 |
|
|
SIGNAL phaseinvertctrl_in : std_logic := '0';
|
| 10383 |
|
|
|
| 10384 |
|
|
BEGIN
|
| 10385 |
|
|
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
|
| 10386 |
|
|
GENERIC MAP (
|
| 10387 |
|
|
phase_setting => phase_setting,
|
| 10388 |
|
|
use_phasectrlin => use_phasectrlin,
|
| 10389 |
|
|
delay_buffer_mode => delay_buffer_mode,
|
| 10390 |
|
|
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
|
| 10391 |
|
|
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
|
| 10392 |
|
|
sim_buffer_delay_increment => sim_buffer_delay_increment
|
| 10393 |
|
|
)
|
| 10394 |
|
|
PORT MAP(
|
| 10395 |
|
|
clk => clk_in,
|
| 10396 |
|
|
delayctrlin => delayctrlin_in,
|
| 10397 |
|
|
phasectrlin => phasectrlin_in,
|
| 10398 |
|
|
delayed_clkout => phasectrl_clkout
|
| 10399 |
|
|
);
|
| 10400 |
|
|
|
| 10401 |
|
|
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
|
| 10402 |
|
|
phasectrl_clkout WHEN (invert_phase = "false") ELSE
|
| 10403 |
|
|
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
|
| 10404 |
|
|
phasectrl_clkout;
|
| 10405 |
|
|
|
| 10406 |
|
|
|
| 10407 |
|
|
-- primary output
|
| 10408 |
|
|
dataout <= tmp_dataout;
|
| 10409 |
|
|
tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q;
|
| 10410 |
|
|
|
| 10411 |
|
|
-- add phase transfer data path mux
|
| 10412 |
|
|
dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE
|
| 10413 |
|
|
cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
|
| 10414 |
|
|
cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE
|
| 10415 |
|
|
cycledelay_mux_out;
|
| 10416 |
|
|
|
| 10417 |
|
|
-- enaoutputcycledelay data path mux
|
| 10418 |
|
|
cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE
|
| 10419 |
|
|
datain_q WHEN (add_input_cycle_delay = "false") ELSE
|
| 10420 |
|
|
cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE
|
| 10421 |
|
|
datain_q;
|
| 10422 |
|
|
|
| 10423 |
|
|
-- resolve reset modes
|
| 10424 |
|
|
PROCESS (areset_in)
|
| 10425 |
|
|
BEGIN
|
| 10426 |
|
|
if (async_mode = "clear") then
|
| 10427 |
|
|
aload_in_r <= areset_in;
|
| 10428 |
|
|
adatasdata_in_r <= '0';
|
| 10429 |
|
|
elsif (async_mode = "preset") then
|
| 10430 |
|
|
aload_in_r <= areset_in;
|
| 10431 |
|
|
adatasdata_in_r <= '1';
|
| 10432 |
|
|
else -- async_mode = "none"
|
| 10433 |
|
|
adatasdata_in_r <= 'Z';
|
| 10434 |
|
|
end if;
|
| 10435 |
|
|
END PROCESS;
|
| 10436 |
|
|
|
| 10437 |
|
|
|
| 10438 |
|
|
-- Datain Register
|
| 10439 |
|
|
datain_reg : stratixiii_ddr_io_reg
|
| 10440 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10441 |
|
|
PORT MAP(
|
| 10442 |
|
|
d => datain_in,
|
| 10443 |
|
|
clk => delayed_clk,
|
| 10444 |
|
|
ena => m_vcc,
|
| 10445 |
|
|
clrn => m_vcc,
|
| 10446 |
|
|
prn => m_vcc,
|
| 10447 |
|
|
aload => aload_in_r,
|
| 10448 |
|
|
asdata => adatasdata_in_r,
|
| 10449 |
|
|
sclr => m_gnd,
|
| 10450 |
|
|
sload => m_gnd,
|
| 10451 |
|
|
devclrn => devclrn,
|
| 10452 |
|
|
devpor => devpor,
|
| 10453 |
|
|
q => datain_q
|
| 10454 |
|
|
);
|
| 10455 |
|
|
|
| 10456 |
|
|
-- Cycle Delay Register
|
| 10457 |
|
|
cycledelay_reg : stratixiii_ddr_io_reg
|
| 10458 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10459 |
|
|
PORT MAP(
|
| 10460 |
|
|
d => datain_q,
|
| 10461 |
|
|
clk => delayed_clk,
|
| 10462 |
|
|
ena => m_vcc,
|
| 10463 |
|
|
clrn => m_vcc,
|
| 10464 |
|
|
prn => m_vcc,
|
| 10465 |
|
|
aload => aload_in_r,
|
| 10466 |
|
|
asdata => adatasdata_in_r,
|
| 10467 |
|
|
sclr => m_gnd,
|
| 10468 |
|
|
sload => m_gnd,
|
| 10469 |
|
|
devclrn => devclrn,
|
| 10470 |
|
|
devpor => devpor,
|
| 10471 |
|
|
q => cycledelay_q
|
| 10472 |
|
|
);
|
| 10473 |
|
|
|
| 10474 |
|
|
-- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
|
| 10475 |
|
|
-- Transfer Register - clocked by negative edge
|
| 10476 |
|
|
not_delayed_clk <= not delayed_clk;
|
| 10477 |
|
|
|
| 10478 |
|
|
transfer_reg : stratixiii_ddr_io_reg
|
| 10479 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10480 |
|
|
PORT MAP(
|
| 10481 |
|
|
d => cycledelay_mux_out,
|
| 10482 |
|
|
clk => not_delayed_clk, -- ~delayed_clk
|
| 10483 |
|
|
ena => m_vcc,
|
| 10484 |
|
|
clrn => m_vcc,
|
| 10485 |
|
|
prn => m_vcc,
|
| 10486 |
|
|
aload => aload_in_r,
|
| 10487 |
|
|
asdata => adatasdata_in_r,
|
| 10488 |
|
|
sclr => m_gnd,
|
| 10489 |
|
|
sload => m_gnd,
|
| 10490 |
|
|
devclrn => devclrn,
|
| 10491 |
|
|
devpor => devpor,
|
| 10492 |
|
|
q => cycledelay_mux_out_dly
|
| 10493 |
|
|
);
|
| 10494 |
|
|
|
| 10495 |
|
|
|
| 10496 |
|
|
-- Register clocked by actually by clk_in
|
| 10497 |
|
|
dlyclk_reg : stratixiii_ddr_io_reg
|
| 10498 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10499 |
|
|
PORT MAP(
|
| 10500 |
|
|
d => dlyclk_d,
|
| 10501 |
|
|
clk => clk_in,
|
| 10502 |
|
|
ena => m_vcc,
|
| 10503 |
|
|
clrn => m_vcc,
|
| 10504 |
|
|
prn => m_vcc,
|
| 10505 |
|
|
aload => aload_in_r,
|
| 10506 |
|
|
asdata => adatasdata_in_r,
|
| 10507 |
|
|
sclr => m_gnd,
|
| 10508 |
|
|
sload => m_gnd,
|
| 10509 |
|
|
devclrn => devclrn,
|
| 10510 |
|
|
devpor => devpor,
|
| 10511 |
|
|
q => dlyclk_q
|
| 10512 |
|
|
);
|
| 10513 |
|
|
|
| 10514 |
|
|
--------------------
|
| 10515 |
|
|
-- INPUT PATH DELAYS
|
| 10516 |
|
|
--------------------
|
| 10517 |
|
|
WireDelay : block
|
| 10518 |
|
|
begin
|
| 10519 |
|
|
VitalWireDelay (datain_in, datain, tipd_datain);
|
| 10520 |
|
|
VitalWireDelay (clk_in, clk, tipd_clk);
|
| 10521 |
|
|
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
|
| 10522 |
|
|
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
|
| 10523 |
|
|
END GENERATE;
|
| 10524 |
|
|
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
|
| 10525 |
|
|
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
|
| 10526 |
|
|
END GENERATE;
|
| 10527 |
|
|
VitalWireDelay (areset_in, areset, tipd_areset);
|
| 10528 |
|
|
VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay);
|
| 10529 |
|
|
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
|
| 10530 |
|
|
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
|
| 10531 |
|
|
end block;
|
| 10532 |
|
|
|
| 10533 |
|
|
END stratixiii_input_phase_alignment_arch;
|
| 10534 |
|
|
|
| 10535 |
|
|
-------------------------------------------------------------------------------
|
| 10536 |
|
|
--
|
| 10537 |
|
|
-- Entity Name : stratixiii_half_rate_input
|
| 10538 |
|
|
--
|
| 10539 |
|
|
-------------------------------------------------------------------------------
|
| 10540 |
|
|
|
| 10541 |
|
|
library IEEE;
|
| 10542 |
|
|
use IEEE.std_logic_1164.all;
|
| 10543 |
|
|
use IEEE.std_logic_arith.all;
|
| 10544 |
|
|
use IEEE.std_logic_unsigned.all;
|
| 10545 |
|
|
use IEEE.VITAL_Timing.all;
|
| 10546 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 10547 |
|
|
use work.stratixiii_atom_pack.all;
|
| 10548 |
|
|
use work.stratixiii_ddr_io_reg;
|
| 10549 |
|
|
|
| 10550 |
|
|
ENTITY stratixiii_half_rate_input IS
|
| 10551 |
|
|
GENERIC (
|
| 10552 |
|
|
power_up : string := "low";
|
| 10553 |
|
|
async_mode : string := "none";
|
| 10554 |
|
|
use_dataoutbypass : string := "false";
|
| 10555 |
|
|
lpm_type : string := "stratixiii_half_rate_input";
|
| 10556 |
|
|
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
|
| 10557 |
|
|
tipd_directin : VitalDelayType01 := DefpropDelay01;
|
| 10558 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 10559 |
|
|
tipd_areset : VitalDelayType01 := DefpropDelay01;
|
| 10560 |
|
|
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
|
| 10561 |
|
|
TimingChecksOn : Boolean := True;
|
| 10562 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 10563 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 10564 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 10565 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 10566 |
|
|
InstancePath : String := "*"
|
| 10567 |
|
|
);
|
| 10568 |
|
|
|
| 10569 |
|
|
PORT (
|
| 10570 |
|
|
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
|
| 10571 |
|
|
directin : IN std_logic := '0';
|
| 10572 |
|
|
clk : IN std_logic := '0';
|
| 10573 |
|
|
areset : IN std_logic := '0';
|
| 10574 |
|
|
dataoutbypass: IN std_logic := '0';
|
| 10575 |
|
|
devclrn : IN std_logic := '1';
|
| 10576 |
|
|
devpor : IN std_logic := '1';
|
| 10577 |
|
|
dataout : OUT std_logic_vector(3 downto 0);
|
| 10578 |
|
|
dffin : OUT std_logic
|
| 10579 |
|
|
);
|
| 10580 |
|
|
|
| 10581 |
|
|
END;
|
| 10582 |
|
|
|
| 10583 |
|
|
ARCHITECTURE stratixiii_half_rate_input_arch OF stratixiii_half_rate_input IS
|
| 10584 |
|
|
-- component section
|
| 10585 |
|
|
component stratixiii_ddr_io_reg
|
| 10586 |
|
|
generic (
|
| 10587 |
|
|
power_up : string := "DONT_CARE";
|
| 10588 |
|
|
is_wysiwyg : string := "false";
|
| 10589 |
|
|
x_on_violation : string := "on";
|
| 10590 |
|
|
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10591 |
|
|
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10592 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10593 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10594 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10595 |
|
|
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10596 |
|
|
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10597 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10598 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10599 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10600 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 10601 |
|
|
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 10602 |
|
|
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 10603 |
|
|
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
| 10604 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 10605 |
|
|
tipd_d : VitalDelayType01 := DefPropDelay01;
|
| 10606 |
|
|
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
| 10607 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
| 10608 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 10609 |
|
|
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
| 10610 |
|
|
tipd_prn : VitalDelayType01 := DefPropDelay01;
|
| 10611 |
|
|
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
| 10612 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 10613 |
|
|
TimingChecksOn: Boolean := True;
|
| 10614 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 10615 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 10616 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 10617 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 10618 |
|
|
InstancePath: STRING := "*"
|
| 10619 |
|
|
);
|
| 10620 |
|
|
|
| 10621 |
|
|
port (
|
| 10622 |
|
|
d : in std_logic := '0';
|
| 10623 |
|
|
clk : in std_logic := '0';
|
| 10624 |
|
|
ena : in std_logic := '1';
|
| 10625 |
|
|
clrn : in std_logic := '1';
|
| 10626 |
|
|
prn : in std_logic := '1';
|
| 10627 |
|
|
aload : in std_logic := '0';
|
| 10628 |
|
|
asdata : in std_logic := '0';
|
| 10629 |
|
|
sclr : in std_logic := '0';
|
| 10630 |
|
|
sload : in std_logic := '0';
|
| 10631 |
|
|
devclrn : in std_logic := '1';
|
| 10632 |
|
|
devpor : in std_logic := '1';
|
| 10633 |
|
|
q : out std_logic
|
| 10634 |
|
|
);
|
| 10635 |
|
|
end component;
|
| 10636 |
|
|
|
| 10637 |
|
|
SIGNAL m_vcc: STD_LOGIC := '1';
|
| 10638 |
|
|
SIGNAL m_gnd: STD_LOGIC := '0';
|
| 10639 |
|
|
|
| 10640 |
|
|
-- IO SIGNAListers
|
| 10641 |
|
|
-- common
|
| 10642 |
|
|
SIGNAL neg_clk_in : STD_LOGIC := '0';
|
| 10643 |
|
|
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
|
| 10644 |
|
|
SIGNAL aload_in_r : STD_LOGIC := '0';
|
| 10645 |
|
|
|
| 10646 |
|
|
-- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
|
| 10647 |
|
|
-- high_bank = {3, 2} - output of SIGNALister datain at rising
|
| 10648 |
|
|
SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
|
| 10649 |
|
|
SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
|
| 10650 |
|
|
SIGNAL low_bank_low : STD_LOGIC := '0';
|
| 10651 |
|
|
SIGNAL low_bank_high : STD_LOGIC := '0';
|
| 10652 |
|
|
SIGNAL high_bank_low : STD_LOGIC := '0';
|
| 10653 |
|
|
SIGNAL high_bank_high: STD_LOGIC := '0';
|
| 10654 |
|
|
|
| 10655 |
|
|
SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
|
| 10656 |
|
|
SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
|
| 10657 |
|
|
|
| 10658 |
|
|
-- delayed version to ensure 1 latency as expected in functional sim
|
| 10659 |
|
|
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
|
| 10660 |
|
|
|
| 10661 |
|
|
-- timing inputs
|
| 10662 |
|
|
SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0');
|
| 10663 |
|
|
SIGNAL directin_in : std_logic := '0';
|
| 10664 |
|
|
SIGNAL clk_in : std_logic := '0';
|
| 10665 |
|
|
SIGNAL areset_in : std_logic := '0';
|
| 10666 |
|
|
SIGNAL dataoutbypass_in: std_logic := '0';
|
| 10667 |
|
|
|
| 10668 |
|
|
BEGIN
|
| 10669 |
|
|
-- primary input
|
| 10670 |
|
|
datain_in <= transport datain_ipd after 2 ps;
|
| 10671 |
|
|
|
| 10672 |
|
|
-- primary output
|
| 10673 |
|
|
dataout <= tmp_dataout;
|
| 10674 |
|
|
tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high;
|
| 10675 |
|
|
tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low;
|
| 10676 |
|
|
tmp_dataout(1) <= low_bank(1);
|
| 10677 |
|
|
tmp_dataout(0) <= low_bank(0);
|
| 10678 |
|
|
|
| 10679 |
|
|
low_bank <= low_bank_high & low_bank_low;
|
| 10680 |
|
|
high_bank <= high_bank_high & high_bank_low;
|
| 10681 |
|
|
|
| 10682 |
|
|
-- resolve reset modes
|
| 10683 |
|
|
PROCESS(areset_in)
|
| 10684 |
|
|
BEGIN
|
| 10685 |
|
|
if (async_mode = "clear") then
|
| 10686 |
|
|
aload_in_r <= areset_in;
|
| 10687 |
|
|
adatasdata_in_r <= '0';
|
| 10688 |
|
|
elsif (async_mode = "preset") then
|
| 10689 |
|
|
aload_in_r <= areset_in;
|
| 10690 |
|
|
adatasdata_in_r <= '1';
|
| 10691 |
|
|
else -- async_mode = "none"
|
| 10692 |
|
|
adatasdata_in_r <= 'Z';
|
| 10693 |
|
|
end if;
|
| 10694 |
|
|
END PROCESS;
|
| 10695 |
|
|
|
| 10696 |
|
|
neg_clk_in <= not clk_in;
|
| 10697 |
|
|
|
| 10698 |
|
|
-- datain_1 - H
|
| 10699 |
|
|
reg1_h : stratixiii_ddr_io_reg
|
| 10700 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10701 |
|
|
PORT MAP(
|
| 10702 |
|
|
d => datain_in(1),
|
| 10703 |
|
|
clk => clk_in,
|
| 10704 |
|
|
ena => m_vcc,
|
| 10705 |
|
|
clrn => m_vcc,
|
| 10706 |
|
|
prn => m_vcc,
|
| 10707 |
|
|
aload => aload_in_r,
|
| 10708 |
|
|
asdata => adatasdata_in_r,
|
| 10709 |
|
|
sclr => m_gnd,
|
| 10710 |
|
|
sload => m_gnd,
|
| 10711 |
|
|
devclrn => devclrn,
|
| 10712 |
|
|
devpor => devpor,
|
| 10713 |
|
|
q => high_bank_high
|
| 10714 |
|
|
);
|
| 10715 |
|
|
|
| 10716 |
|
|
-- datain_0 - H
|
| 10717 |
|
|
reg0_h : stratixiii_ddr_io_reg
|
| 10718 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10719 |
|
|
PORT MAP(
|
| 10720 |
|
|
d => datain_in(0),
|
| 10721 |
|
|
clk => clk_in,
|
| 10722 |
|
|
ena => m_vcc,
|
| 10723 |
|
|
clrn => m_vcc,
|
| 10724 |
|
|
prn => m_vcc,
|
| 10725 |
|
|
aload => aload_in_r,
|
| 10726 |
|
|
asdata => adatasdata_in_r,
|
| 10727 |
|
|
sclr => m_gnd,
|
| 10728 |
|
|
sload => m_gnd,
|
| 10729 |
|
|
devclrn => devclrn,
|
| 10730 |
|
|
devpor => devpor,
|
| 10731 |
|
|
q => high_bank_low
|
| 10732 |
|
|
);
|
| 10733 |
|
|
|
| 10734 |
|
|
-- datain_1 - L (n)
|
| 10735 |
|
|
reg1_l_n : stratixiii_ddr_io_reg
|
| 10736 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10737 |
|
|
PORT MAP(
|
| 10738 |
|
|
d => datain_in(1),
|
| 10739 |
|
|
clk => neg_clk_in,
|
| 10740 |
|
|
ena => m_vcc,
|
| 10741 |
|
|
clrn => m_vcc,
|
| 10742 |
|
|
prn => m_vcc,
|
| 10743 |
|
|
aload => aload_in_r,
|
| 10744 |
|
|
asdata => adatasdata_in_r,
|
| 10745 |
|
|
sclr => m_gnd,
|
| 10746 |
|
|
sload => m_gnd,
|
| 10747 |
|
|
devclrn => devclrn,
|
| 10748 |
|
|
devpor => devpor,
|
| 10749 |
|
|
q => dataout_reg_n(1)
|
| 10750 |
|
|
);
|
| 10751 |
|
|
|
| 10752 |
|
|
-- datain_1 - L
|
| 10753 |
|
|
reg1_l : stratixiii_ddr_io_reg
|
| 10754 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10755 |
|
|
PORT MAP(
|
| 10756 |
|
|
d => dataout_reg_n(1),
|
| 10757 |
|
|
clk => clk_in,
|
| 10758 |
|
|
ena => m_vcc,
|
| 10759 |
|
|
clrn => m_vcc,
|
| 10760 |
|
|
prn => m_vcc,
|
| 10761 |
|
|
aload => aload_in_r,
|
| 10762 |
|
|
asdata => adatasdata_in_r,
|
| 10763 |
|
|
sclr => m_gnd,
|
| 10764 |
|
|
sload => m_gnd,
|
| 10765 |
|
|
devclrn => devclrn,
|
| 10766 |
|
|
devpor => devpor,
|
| 10767 |
|
|
q => low_bank_high
|
| 10768 |
|
|
);
|
| 10769 |
|
|
|
| 10770 |
|
|
-- datain_0 - L (n)
|
| 10771 |
|
|
reg0_l_n : stratixiii_ddr_io_reg
|
| 10772 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10773 |
|
|
PORT MAP(
|
| 10774 |
|
|
d => datain_in(0),
|
| 10775 |
|
|
clk => neg_clk_in,
|
| 10776 |
|
|
ena => m_vcc,
|
| 10777 |
|
|
clrn => m_vcc,
|
| 10778 |
|
|
prn => m_vcc,
|
| 10779 |
|
|
aload => aload_in_r,
|
| 10780 |
|
|
asdata => adatasdata_in_r,
|
| 10781 |
|
|
sclr => m_gnd,
|
| 10782 |
|
|
sload => m_gnd,
|
| 10783 |
|
|
devclrn => devclrn,
|
| 10784 |
|
|
devpor => devpor,
|
| 10785 |
|
|
q => dataout_reg_n(0)
|
| 10786 |
|
|
);
|
| 10787 |
|
|
|
| 10788 |
|
|
-- datain_0 - L
|
| 10789 |
|
|
reg0_l : stratixiii_ddr_io_reg
|
| 10790 |
|
|
GENERIC MAP (power_up => power_up)
|
| 10791 |
|
|
PORT MAP(
|
| 10792 |
|
|
d => dataout_reg_n(0),
|
| 10793 |
|
|
clk => clk_in,
|
| 10794 |
|
|
ena => m_vcc,
|
| 10795 |
|
|
clrn => m_vcc,
|
| 10796 |
|
|
prn => m_vcc,
|
| 10797 |
|
|
aload => aload_in_r,
|
| 10798 |
|
|
asdata => adatasdata_in_r,
|
| 10799 |
|
|
sclr => m_gnd,
|
| 10800 |
|
|
sload => m_gnd,
|
| 10801 |
|
|
devclrn => devclrn,
|
| 10802 |
|
|
devpor => devpor,
|
| 10803 |
|
|
q => low_bank_low
|
| 10804 |
|
|
);
|
| 10805 |
|
|
|
| 10806 |
|
|
--------------------
|
| 10807 |
|
|
-- INPUT PATH DELAYS
|
| 10808 |
|
|
--------------------
|
| 10809 |
|
|
WireDelay : block
|
| 10810 |
|
|
begin
|
| 10811 |
|
|
loopbits_datain : FOR i in datain'RANGE GENERATE
|
| 10812 |
|
|
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
|
| 10813 |
|
|
END GENERATE;
|
| 10814 |
|
|
VitalWireDelay (directin_in, directin, tipd_directin);
|
| 10815 |
|
|
VitalWireDelay (clk_in, clk, tipd_clk);
|
| 10816 |
|
|
VitalWireDelay (areset_in, areset, tipd_areset);
|
| 10817 |
|
|
VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass);
|
| 10818 |
|
|
end block;
|
| 10819 |
|
|
|
| 10820 |
|
|
END stratixiii_half_rate_input_arch;
|
| 10821 |
|
|
|
| 10822 |
|
|
-------------------------------------------------------------------------------
|
| 10823 |
|
|
--
|
| 10824 |
|
|
-- Entity Name : stratixiii_io_config
|
| 10825 |
|
|
--
|
| 10826 |
|
|
-------------------------------------------------------------------------------
|
| 10827 |
|
|
|
| 10828 |
|
|
library IEEE;
|
| 10829 |
|
|
use IEEE.std_logic_1164.all;
|
| 10830 |
|
|
use IEEE.std_logic_arith.all;
|
| 10831 |
|
|
use IEEE.std_logic_unsigned.all;
|
| 10832 |
|
|
use IEEE.VITAL_Timing.all;
|
| 10833 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 10834 |
|
|
use work.stratixiii_atom_pack.all;
|
| 10835 |
|
|
|
| 10836 |
|
|
ENTITY stratixiii_io_config IS
|
| 10837 |
|
|
GENERIC (
|
| 10838 |
|
|
lpm_type : string := "stratixiii_io_config";
|
| 10839 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01;
|
| 10840 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 10841 |
|
|
tipd_ena : VitalDelayType01 := DefpropDelay01;
|
| 10842 |
|
|
tipd_update : VitalDelayType01 := DefpropDelay01;
|
| 10843 |
|
|
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10844 |
|
|
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 10845 |
|
|
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 10846 |
|
|
TimingChecksOn : Boolean := True;
|
| 10847 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 10848 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 10849 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 10850 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 10851 |
|
|
InstancePath : String := "*"
|
| 10852 |
|
|
);
|
| 10853 |
|
|
|
| 10854 |
|
|
PORT (
|
| 10855 |
|
|
datain : IN std_logic := '0';
|
| 10856 |
|
|
clk : IN std_logic := '0';
|
| 10857 |
|
|
ena : IN std_logic := '0';
|
| 10858 |
|
|
update : IN std_logic := '0';
|
| 10859 |
|
|
devclrn : IN std_logic := '1';
|
| 10860 |
|
|
devpor : IN std_logic := '1';
|
| 10861 |
|
|
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
|
| 10862 |
|
|
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
|
| 10863 |
|
|
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
|
| 10864 |
|
|
dataout : OUT std_logic
|
| 10865 |
|
|
);
|
| 10866 |
|
|
|
| 10867 |
|
|
END;
|
| 10868 |
|
|
|
| 10869 |
|
|
ARCHITECTURE stratixiii_io_config_arch OF stratixiii_io_config IS
|
| 10870 |
|
|
-- component section
|
| 10871 |
|
|
|
| 10872 |
|
|
SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
|
| 10873 |
|
|
SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
|
| 10874 |
|
|
SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0');
|
| 10875 |
|
|
|
| 10876 |
|
|
-- timing outputs
|
| 10877 |
|
|
SIGNAL tmp_dataout : std_logic := '0';
|
| 10878 |
|
|
|
| 10879 |
|
|
-- timing inputs
|
| 10880 |
|
|
SIGNAL datain_in : std_logic := '0';
|
| 10881 |
|
|
SIGNAL clk_in : std_logic := '0';
|
| 10882 |
|
|
SIGNAL ena_in : std_logic := '0';
|
| 10883 |
|
|
SIGNAL update_in : std_logic := '0';
|
| 10884 |
|
|
|
| 10885 |
|
|
BEGIN
|
| 10886 |
|
|
-- primary outputs
|
| 10887 |
|
|
tmp_dataout <= shift_reg(10);
|
| 10888 |
|
|
|
| 10889 |
|
|
-- bit order changed in wys revision 1.32
|
| 10890 |
|
|
outputdelaysetting1 <= tmp_output(3 DOWNTO 0);
|
| 10891 |
|
|
outputdelaysetting2 <= tmp_output(6 DOWNTO 4);
|
| 10892 |
|
|
padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7);
|
| 10893 |
|
|
-- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0);
|
| 10894 |
|
|
-- outputdelaysetting1 <= tmp_output(7 DOWNTO 4);
|
| 10895 |
|
|
-- outputdelaysetting2 <= tmp_output(10 DOWNTO 8);
|
| 10896 |
|
|
tmp_output <= output_reg;
|
| 10897 |
|
|
|
| 10898 |
|
|
|
| 10899 |
|
|
|
| 10900 |
|
|
PROCESS(clk_in)
|
| 10901 |
|
|
BEGIN
|
| 10902 |
|
|
if (clk_in = '1' AND ena_in = '1') then
|
| 10903 |
|
|
shift_reg(0) <= datain_in;
|
| 10904 |
|
|
shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0);
|
| 10905 |
|
|
end if;
|
| 10906 |
|
|
END PROCESS;
|
| 10907 |
|
|
|
| 10908 |
|
|
|
| 10909 |
|
|
PROCESS(clk_in)
|
| 10910 |
|
|
BEGIN
|
| 10911 |
|
|
if (clk_in = '1' AND update_in = '1') then
|
| 10912 |
|
|
output_reg <= shift_reg;
|
| 10913 |
|
|
end if;
|
| 10914 |
|
|
END PROCESS;
|
| 10915 |
|
|
|
| 10916 |
|
|
|
| 10917 |
|
|
--------------------
|
| 10918 |
|
|
-- INPUT PATH DELAYS
|
| 10919 |
|
|
--------------------
|
| 10920 |
|
|
WireDelay : block
|
| 10921 |
|
|
begin
|
| 10922 |
|
|
VitalWireDelay (datain_in, datain, tipd_datain);
|
| 10923 |
|
|
VitalWireDelay (clk_in, clk, tipd_clk);
|
| 10924 |
|
|
VitalWireDelay (ena_in, ena, tipd_ena);
|
| 10925 |
|
|
VitalWireDelay (update_in, update, tipd_update);
|
| 10926 |
|
|
end block;
|
| 10927 |
|
|
|
| 10928 |
|
|
-----------------------------------
|
| 10929 |
|
|
-- Timing Check Section
|
| 10930 |
|
|
-----------------------------------
|
| 10931 |
|
|
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
|
| 10932 |
|
|
|
| 10933 |
|
|
variable Tviol_clk_datain : std_ulogic := '0';
|
| 10934 |
|
|
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
|
| 10935 |
|
|
variable Tviol_clk_ena : std_ulogic := '0';
|
| 10936 |
|
|
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
|
| 10937 |
|
|
variable Tviol_clk_update : std_ulogic := '0';
|
| 10938 |
|
|
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
|
| 10939 |
|
|
|
| 10940 |
|
|
BEGIN
|
| 10941 |
|
|
IF (TimingChecksOn) THEN
|
| 10942 |
|
|
VitalSetupHoldCheck (
|
| 10943 |
|
|
Violation => Tviol_clk_datain,
|
| 10944 |
|
|
TimingData => TimingData_clk_datain,
|
| 10945 |
|
|
TestSignal => datain_in,
|
| 10946 |
|
|
TestSignalName => "Datain",
|
| 10947 |
|
|
RefSignal => clk_in,
|
| 10948 |
|
|
RefSignalName => "clk",
|
| 10949 |
|
|
SetupHigh => tsetup_datain_clk_noedge_posedge,
|
| 10950 |
|
|
SetupLow => tsetup_datain_clk_noedge_posedge,
|
| 10951 |
|
|
HoldHigh => thold_datain_clk_noedge_posedge,
|
| 10952 |
|
|
HoldLow => thold_datain_clk_noedge_posedge,
|
| 10953 |
|
|
RefTransition => '/',
|
| 10954 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
|
| 10955 |
|
|
XOn => XOnChecks,
|
| 10956 |
|
|
MsgOn => MsgOnChecks
|
| 10957 |
|
|
);
|
| 10958 |
|
|
|
| 10959 |
|
|
VitalSetupHoldCheck (
|
| 10960 |
|
|
Violation => Tviol_clk_ena,
|
| 10961 |
|
|
TimingData => TimingData_clk_ena,
|
| 10962 |
|
|
TestSignal => ena_in,
|
| 10963 |
|
|
TestSignalName => "Ena",
|
| 10964 |
|
|
RefSignal => clk_in,
|
| 10965 |
|
|
RefSignalName => "clk",
|
| 10966 |
|
|
SetupHigh => tsetup_datain_clk_noedge_posedge,
|
| 10967 |
|
|
SetupLow => tsetup_datain_clk_noedge_posedge,
|
| 10968 |
|
|
HoldHigh => thold_datain_clk_noedge_posedge,
|
| 10969 |
|
|
HoldLow => thold_datain_clk_noedge_posedge,
|
| 10970 |
|
|
RefTransition => '/',
|
| 10971 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
|
| 10972 |
|
|
XOn => XOnChecks,
|
| 10973 |
|
|
MsgOn => MsgOnChecks
|
| 10974 |
|
|
);
|
| 10975 |
|
|
|
| 10976 |
|
|
VitalSetupHoldCheck (
|
| 10977 |
|
|
Violation => Tviol_clk_update,
|
| 10978 |
|
|
TimingData => TimingData_clk_update,
|
| 10979 |
|
|
TestSignal => update_in,
|
| 10980 |
|
|
TestSignalName => "Update",
|
| 10981 |
|
|
RefSignal => clk_in,
|
| 10982 |
|
|
RefSignalName => "clk",
|
| 10983 |
|
|
SetupHigh => tsetup_datain_clk_noedge_posedge,
|
| 10984 |
|
|
SetupLow => tsetup_datain_clk_noedge_posedge,
|
| 10985 |
|
|
HoldHigh => thold_datain_clk_noedge_posedge,
|
| 10986 |
|
|
HoldLow => thold_datain_clk_noedge_posedge,
|
| 10987 |
|
|
RefTransition => '/',
|
| 10988 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
|
| 10989 |
|
|
XOn => XOnChecks,
|
| 10990 |
|
|
MsgOn => MsgOnChecks
|
| 10991 |
|
|
);
|
| 10992 |
|
|
|
| 10993 |
|
|
END IF;
|
| 10994 |
|
|
END PROCESS; -- timing check
|
| 10995 |
|
|
|
| 10996 |
|
|
--------------------------------------
|
| 10997 |
|
|
-- Path Delay Section
|
| 10998 |
|
|
--------------------------------------
|
| 10999 |
|
|
|
| 11000 |
|
|
VITAL_path_delays: PROCESS (tmp_dataout)
|
| 11001 |
|
|
|
| 11002 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 11003 |
|
|
|
| 11004 |
|
|
BEGIN
|
| 11005 |
|
|
VitalPathDelay01 (
|
| 11006 |
|
|
OutSignal => dataout,
|
| 11007 |
|
|
OutSignalName => "Dataout",
|
| 11008 |
|
|
OutTemp => tmp_dataout,
|
| 11009 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
|
| 11010 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 11011 |
|
|
Mode => DefGlitchMode,
|
| 11012 |
|
|
XOn => XOn,
|
| 11013 |
|
|
MsgOn => MsgOn );
|
| 11014 |
|
|
|
| 11015 |
|
|
END PROCESS; -- Path Delays
|
| 11016 |
|
|
|
| 11017 |
|
|
END stratixiii_io_config_arch;
|
| 11018 |
|
|
|
| 11019 |
|
|
-------------------------------------------------------------------------------
|
| 11020 |
|
|
--
|
| 11021 |
|
|
-- Entity Name : stratixiii_dqs_config
|
| 11022 |
|
|
--
|
| 11023 |
|
|
-------------------------------------------------------------------------------
|
| 11024 |
|
|
|
| 11025 |
|
|
library IEEE;
|
| 11026 |
|
|
use IEEE.std_logic_1164.all;
|
| 11027 |
|
|
use IEEE.std_logic_arith.all;
|
| 11028 |
|
|
use IEEE.std_logic_unsigned.all;
|
| 11029 |
|
|
use IEEE.VITAL_Timing.all;
|
| 11030 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 11031 |
|
|
use work.stratixiii_atom_pack.all;
|
| 11032 |
|
|
|
| 11033 |
|
|
ENTITY stratixiii_dqs_config IS
|
| 11034 |
|
|
GENERIC (
|
| 11035 |
|
|
lpm_type : string := "stratixiii_dqs_config";
|
| 11036 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01;
|
| 11037 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 11038 |
|
|
tipd_ena : VitalDelayType01 := DefpropDelay01;
|
| 11039 |
|
|
tipd_update : VitalDelayType01 := DefpropDelay01;
|
| 11040 |
|
|
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11041 |
|
|
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11042 |
|
|
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 11043 |
|
|
TimingChecksOn : Boolean := True;
|
| 11044 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 11045 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 11046 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 11047 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 11048 |
|
|
InstancePath : String := "*"
|
| 11049 |
|
|
);
|
| 11050 |
|
|
|
| 11051 |
|
|
PORT (
|
| 11052 |
|
|
datain : IN std_logic := '0';
|
| 11053 |
|
|
clk : IN std_logic := '0';
|
| 11054 |
|
|
ena : IN std_logic := '0';
|
| 11055 |
|
|
update : IN std_logic := '0';
|
| 11056 |
|
|
devclrn : IN std_logic := '1';
|
| 11057 |
|
|
devpor : IN std_logic := '1';
|
| 11058 |
|
|
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
|
| 11059 |
|
|
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
|
| 11060 |
|
|
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
|
| 11061 |
|
|
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
|
| 11062 |
|
|
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
|
| 11063 |
|
|
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
|
| 11064 |
|
|
dividerphasesetting : OUT std_logic;
|
| 11065 |
|
|
enaoctcycledelaysetting : OUT std_logic;
|
| 11066 |
|
|
enainputcycledelaysetting : OUT std_logic;
|
| 11067 |
|
|
enaoutputcycledelaysetting: OUT std_logic;
|
| 11068 |
|
|
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
|
| 11069 |
|
|
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
|
| 11070 |
|
|
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
|
| 11071 |
|
|
enadataoutbypass : OUT std_logic;
|
| 11072 |
|
|
enadqsenablephasetransferreg : OUT std_logic;
|
| 11073 |
|
|
enaoctphasetransferreg : OUT std_logic;
|
| 11074 |
|
|
enaoutputphasetransferreg : OUT std_logic;
|
| 11075 |
|
|
enainputphasetransferreg : OUT std_logic;
|
| 11076 |
|
|
resyncinputphaseinvert : OUT std_logic;
|
| 11077 |
|
|
dqsenablectrlphaseinvert : OUT std_logic;
|
| 11078 |
|
|
dqoutputphaseinvert : OUT std_logic;
|
| 11079 |
|
|
dqsoutputphaseinvert : OUT std_logic;
|
| 11080 |
|
|
dataout : OUT std_logic
|
| 11081 |
|
|
);
|
| 11082 |
|
|
|
| 11083 |
|
|
END;
|
| 11084 |
|
|
|
| 11085 |
|
|
ARCHITECTURE stratixiii_dqs_config_arch OF stratixiii_dqs_config IS
|
| 11086 |
|
|
-- component section
|
| 11087 |
|
|
|
| 11088 |
|
|
SIGNAL shift_reg : STD_LOGIC_VECTOR (45 DOWNTO 0) := (OTHERS => '0');
|
| 11089 |
|
|
SIGNAL output_reg : STD_LOGIC_VECTOR (45 DOWNTO 0) := (OTHERS => '0');
|
| 11090 |
|
|
SIGNAL tmp_output : STD_LOGIC_VECTOR (45 DOWNTO 0) := (OTHERS => '0');
|
| 11091 |
|
|
|
| 11092 |
|
|
-- timing outputs
|
| 11093 |
|
|
SIGNAL tmp_dataout : std_logic := '0';
|
| 11094 |
|
|
|
| 11095 |
|
|
-- timing inputs
|
| 11096 |
|
|
SIGNAL datain_in : std_logic := '0';
|
| 11097 |
|
|
SIGNAL clk_in : std_logic := '0';
|
| 11098 |
|
|
SIGNAL ena_in : std_logic := '0';
|
| 11099 |
|
|
SIGNAL update_in : std_logic := '0';
|
| 11100 |
|
|
|
| 11101 |
|
|
BEGIN
|
| 11102 |
|
|
-- primary outputs
|
| 11103 |
|
|
tmp_dataout <= shift_reg(45);
|
| 11104 |
|
|
|
| 11105 |
|
|
dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0);
|
| 11106 |
|
|
dqsinputphasesetting <= tmp_output(6 DOWNTO 4);
|
| 11107 |
|
|
dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7);
|
| 11108 |
|
|
dqsoutputphasesetting <= tmp_output(14 DOWNTO 11);
|
| 11109 |
|
|
dqoutputphasesetting <= tmp_output(18 DOWNTO 15);
|
| 11110 |
|
|
resyncinputphasesetting <= tmp_output(22 DOWNTO 19);
|
| 11111 |
|
|
dividerphasesetting <= tmp_output(23);
|
| 11112 |
|
|
enaoctcycledelaysetting <= tmp_output(24);
|
| 11113 |
|
|
enainputcycledelaysetting <= tmp_output(25);
|
| 11114 |
|
|
enaoutputcycledelaysetting<= tmp_output(26);
|
| 11115 |
|
|
dqsenabledelaysetting <= tmp_output(29 DOWNTO 27);
|
| 11116 |
|
|
octdelaysetting1 <= tmp_output(33 DOWNTO 30);
|
| 11117 |
|
|
octdelaysetting2 <= tmp_output(36 DOWNTO 34);
|
| 11118 |
|
|
enadataoutbypass <= tmp_output(37);
|
| 11119 |
|
|
enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23
|
| 11120 |
|
|
enaoctphasetransferreg <= tmp_output(39); -- new in 1.23
|
| 11121 |
|
|
enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23
|
| 11122 |
|
|
enainputphasetransferreg <= tmp_output(41); -- new in 1.23
|
| 11123 |
|
|
resyncinputphaseinvert <= tmp_output(42); -- new in 1.26
|
| 11124 |
|
|
dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26
|
| 11125 |
|
|
dqoutputphaseinvert <= tmp_output(44); -- new in 1.26
|
| 11126 |
|
|
dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26
|
| 11127 |
|
|
|
| 11128 |
|
|
tmp_output <= output_reg;
|
| 11129 |
|
|
|
| 11130 |
|
|
PROCESS(clk_in)
|
| 11131 |
|
|
begin
|
| 11132 |
|
|
if (clk_in = '1' AND ena_in = '1') then
|
| 11133 |
|
|
shift_reg(0) <= datain_in;
|
| 11134 |
|
|
shift_reg(45 DOWNTO 1) <= shift_reg(44 DOWNTO 0);
|
| 11135 |
|
|
end if;
|
| 11136 |
|
|
end process;
|
| 11137 |
|
|
|
| 11138 |
|
|
PROCESS(clk_in)
|
| 11139 |
|
|
begin
|
| 11140 |
|
|
if (clk_in = '1' AND update_in = '1') then
|
| 11141 |
|
|
output_reg <= shift_reg;
|
| 11142 |
|
|
end if;
|
| 11143 |
|
|
end process;
|
| 11144 |
|
|
|
| 11145 |
|
|
--------------------
|
| 11146 |
|
|
-- INPUT PATH DELAYS
|
| 11147 |
|
|
--------------------
|
| 11148 |
|
|
WireDelay : block
|
| 11149 |
|
|
begin
|
| 11150 |
|
|
VitalWireDelay (datain_in, datain, tipd_datain);
|
| 11151 |
|
|
VitalWireDelay (clk_in, clk, tipd_clk);
|
| 11152 |
|
|
VitalWireDelay (ena_in, ena, tipd_ena);
|
| 11153 |
|
|
VitalWireDelay (update_in, update, tipd_update);
|
| 11154 |
|
|
end block;
|
| 11155 |
|
|
|
| 11156 |
|
|
-----------------------------------
|
| 11157 |
|
|
-- Timing Check Section
|
| 11158 |
|
|
-----------------------------------
|
| 11159 |
|
|
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
|
| 11160 |
|
|
|
| 11161 |
|
|
variable Tviol_clk_datain : std_ulogic := '0';
|
| 11162 |
|
|
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
|
| 11163 |
|
|
variable Tviol_clk_ena : std_ulogic := '0';
|
| 11164 |
|
|
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
|
| 11165 |
|
|
variable Tviol_clk_update : std_ulogic := '0';
|
| 11166 |
|
|
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
|
| 11167 |
|
|
|
| 11168 |
|
|
BEGIN
|
| 11169 |
|
|
IF (TimingChecksOn) THEN
|
| 11170 |
|
|
VitalSetupHoldCheck (
|
| 11171 |
|
|
Violation => Tviol_clk_datain,
|
| 11172 |
|
|
TimingData => TimingData_clk_datain,
|
| 11173 |
|
|
TestSignal => datain_in,
|
| 11174 |
|
|
TestSignalName => "Datain",
|
| 11175 |
|
|
RefSignal => clk_in,
|
| 11176 |
|
|
RefSignalName => "clk",
|
| 11177 |
|
|
SetupHigh => tsetup_datain_clk_noedge_posedge,
|
| 11178 |
|
|
SetupLow => tsetup_datain_clk_noedge_posedge,
|
| 11179 |
|
|
HoldHigh => thold_datain_clk_noedge_posedge,
|
| 11180 |
|
|
HoldLow => thold_datain_clk_noedge_posedge,
|
| 11181 |
|
|
RefTransition => '/',
|
| 11182 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
|
| 11183 |
|
|
XOn => XOnChecks,
|
| 11184 |
|
|
MsgOn => MsgOnChecks
|
| 11185 |
|
|
);
|
| 11186 |
|
|
|
| 11187 |
|
|
VitalSetupHoldCheck (
|
| 11188 |
|
|
Violation => Tviol_clk_ena,
|
| 11189 |
|
|
TimingData => TimingData_clk_ena,
|
| 11190 |
|
|
TestSignal => ena_in,
|
| 11191 |
|
|
TestSignalName => "Ena",
|
| 11192 |
|
|
RefSignal => clk_in,
|
| 11193 |
|
|
RefSignalName => "clk",
|
| 11194 |
|
|
SetupHigh => tsetup_datain_clk_noedge_posedge,
|
| 11195 |
|
|
SetupLow => tsetup_datain_clk_noedge_posedge,
|
| 11196 |
|
|
HoldHigh => thold_datain_clk_noedge_posedge,
|
| 11197 |
|
|
HoldLow => thold_datain_clk_noedge_posedge,
|
| 11198 |
|
|
RefTransition => '/',
|
| 11199 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
|
| 11200 |
|
|
XOn => XOnChecks,
|
| 11201 |
|
|
MsgOn => MsgOnChecks
|
| 11202 |
|
|
);
|
| 11203 |
|
|
|
| 11204 |
|
|
VitalSetupHoldCheck (
|
| 11205 |
|
|
Violation => Tviol_clk_update,
|
| 11206 |
|
|
TimingData => TimingData_clk_update,
|
| 11207 |
|
|
TestSignal => update_in,
|
| 11208 |
|
|
TestSignalName => "Update",
|
| 11209 |
|
|
RefSignal => clk_in,
|
| 11210 |
|
|
RefSignalName => "clk",
|
| 11211 |
|
|
SetupHigh => tsetup_datain_clk_noedge_posedge,
|
| 11212 |
|
|
SetupLow => tsetup_datain_clk_noedge_posedge,
|
| 11213 |
|
|
HoldHigh => thold_datain_clk_noedge_posedge,
|
| 11214 |
|
|
HoldLow => thold_datain_clk_noedge_posedge,
|
| 11215 |
|
|
RefTransition => '/',
|
| 11216 |
|
|
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
|
| 11217 |
|
|
XOn => XOnChecks,
|
| 11218 |
|
|
MsgOn => MsgOnChecks
|
| 11219 |
|
|
);
|
| 11220 |
|
|
|
| 11221 |
|
|
END IF;
|
| 11222 |
|
|
END PROCESS; -- timing check
|
| 11223 |
|
|
|
| 11224 |
|
|
--------------------------------------
|
| 11225 |
|
|
-- Path Delay Section
|
| 11226 |
|
|
--------------------------------------
|
| 11227 |
|
|
|
| 11228 |
|
|
VITAL_path_delays: PROCESS (tmp_dataout)
|
| 11229 |
|
|
|
| 11230 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 11231 |
|
|
|
| 11232 |
|
|
BEGIN
|
| 11233 |
|
|
VitalPathDelay01 (
|
| 11234 |
|
|
OutSignal => dataout,
|
| 11235 |
|
|
OutSignalName => "Dataout",
|
| 11236 |
|
|
OutTemp => tmp_dataout,
|
| 11237 |
|
|
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
|
| 11238 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 11239 |
|
|
Mode => DefGlitchMode,
|
| 11240 |
|
|
XOn => XOn,
|
| 11241 |
|
|
MsgOn => MsgOn );
|
| 11242 |
|
|
|
| 11243 |
|
|
END PROCESS; -- Path Delays
|
| 11244 |
|
|
|
| 11245 |
|
|
END stratixiii_dqs_config_arch;
|
| 11246 |
|
|
-------------------------------------------------------------------------------
|
| 11247 |
|
|
-- Module Name: stratixiii_mac_bit_register --
|
| 11248 |
|
|
-- Description: Stratix III MAC single bit register --
|
| 11249 |
|
|
-------------------------------------------------------------------------------
|
| 11250 |
|
|
|
| 11251 |
|
|
LIBRARY IEEE;
|
| 11252 |
|
|
USE ieee.std_logic_1164.all;
|
| 11253 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 11254 |
|
|
use IEEE.VITAL_Timing.all;
|
| 11255 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 11256 |
|
|
use work.stratixiii_atom_pack.all;
|
| 11257 |
|
|
|
| 11258 |
|
|
ENTITY stratixiii_mac_bit_register IS
|
| 11259 |
|
|
GENERIC (
|
| 11260 |
|
|
tipd_datain : VitalDelayType01 := DefPropDelay01;
|
| 11261 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 11262 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 11263 |
|
|
tipd_aclr : VitalDelayType01 := DefPropDelay01;
|
| 11264 |
|
|
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 11265 |
|
|
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 11266 |
|
|
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11267 |
|
|
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11268 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11269 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11270 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 11271 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 11272 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 11273 |
|
|
XOnChecks: Boolean := DefXOnChecks
|
| 11274 |
|
|
);
|
| 11275 |
|
|
PORT (
|
| 11276 |
|
|
datain : IN std_logic := '0';
|
| 11277 |
|
|
clk : IN std_logic := '0';
|
| 11278 |
|
|
aclr : IN std_logic := '0';
|
| 11279 |
|
|
sload : IN std_logic := '0';
|
| 11280 |
|
|
bypass_register : IN std_logic := '0';
|
| 11281 |
|
|
dataout : OUT std_logic
|
| 11282 |
|
|
);
|
| 11283 |
|
|
END stratixiii_mac_bit_register;
|
| 11284 |
|
|
|
| 11285 |
|
|
ARCHITECTURE arch OF stratixiii_mac_bit_register IS
|
| 11286 |
|
|
SIGNAL datain_ipd : std_logic := '0';
|
| 11287 |
|
|
SIGNAL clk_ipd : std_logic := '0';
|
| 11288 |
|
|
SIGNAL aclr_ipd : std_logic := '0';
|
| 11289 |
|
|
SIGNAL sload_ipd : std_logic := '1';
|
| 11290 |
|
|
SIGNAL dataout_tmp : std_logic := '0';
|
| 11291 |
|
|
SIGNAL dataout_reg : std_logic := '0';
|
| 11292 |
|
|
BEGIN
|
| 11293 |
|
|
|
| 11294 |
|
|
WireDelay : block
|
| 11295 |
|
|
begin
|
| 11296 |
|
|
VitalWireDelay (datain_ipd, datain, tipd_datain);
|
| 11297 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 11298 |
|
|
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
|
| 11299 |
|
|
VitalWireDelay (sload_ipd, sload, tipd_sload);
|
| 11300 |
|
|
end block;
|
| 11301 |
|
|
|
| 11302 |
|
|
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
|
| 11303 |
|
|
variable Tviol_datain_clk : std_ulogic := '0';
|
| 11304 |
|
|
variable Tviol_sload_clk : std_ulogic := '0';
|
| 11305 |
|
|
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 11306 |
|
|
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 11307 |
|
|
variable q_VitalGlitchData : VitalGlitchDataType;
|
| 11308 |
|
|
VARIABLE CQDelay : TIME := 0 ns;
|
| 11309 |
|
|
|
| 11310 |
|
|
BEGIN
|
| 11311 |
|
|
IF (aclr_ipd = '1') THEN
|
| 11312 |
|
|
dataout_reg <= '0';
|
| 11313 |
|
|
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
|
| 11314 |
|
|
IF (sload_ipd = '1') THEN
|
| 11315 |
|
|
dataout_reg <= datain_ipd;
|
| 11316 |
|
|
ELSE
|
| 11317 |
|
|
dataout_reg <= dataout_reg;
|
| 11318 |
|
|
END IF;
|
| 11319 |
|
|
END IF;
|
| 11320 |
|
|
|
| 11321 |
|
|
VitalSetupHoldCheck (
|
| 11322 |
|
|
Violation => Tviol_datain_clk,
|
| 11323 |
|
|
TimingData => TimingData_datain_clk,
|
| 11324 |
|
|
TestSignal => datain,
|
| 11325 |
|
|
TestSignalName => "DATAIN",
|
| 11326 |
|
|
RefSignal => clk_ipd,
|
| 11327 |
|
|
RefSignalName => "CLK",
|
| 11328 |
|
|
SetupHigh => tsetup_datain_clk_noedge_posedge,
|
| 11329 |
|
|
SetupLow => tsetup_datain_clk_noedge_posedge,
|
| 11330 |
|
|
HoldHigh => thold_datain_clk_noedge_posedge,
|
| 11331 |
|
|
HoldLow => thold_datain_clk_noedge_posedge,
|
| 11332 |
|
|
CheckEnabled => TO_X01((NOT aclr_ipd) OR
|
| 11333 |
|
|
(sload_ipd)) /= '1',
|
| 11334 |
|
|
RefTransition => '/',
|
| 11335 |
|
|
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
|
| 11336 |
|
|
XOn => XOnChecks,
|
| 11337 |
|
|
MsgOn => MsgOnChecks );
|
| 11338 |
|
|
|
| 11339 |
|
|
VitalSetupHoldCheck (
|
| 11340 |
|
|
Violation => Tviol_sload_clk,
|
| 11341 |
|
|
TimingData => TimingData_sload_clk,
|
| 11342 |
|
|
TestSignal => sload_ipd,
|
| 11343 |
|
|
TestSignalName => "SLOAD",
|
| 11344 |
|
|
RefSignal => clk_ipd,
|
| 11345 |
|
|
RefSignalName => "CLK",
|
| 11346 |
|
|
SetupHigh => tsetup_sload_clk_noedge_posedge,
|
| 11347 |
|
|
SetupLow => tsetup_sload_clk_noedge_posedge,
|
| 11348 |
|
|
HoldHigh => thold_sload_clk_noedge_posedge,
|
| 11349 |
|
|
HoldLow => thold_sload_clk_noedge_posedge,
|
| 11350 |
|
|
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
|
| 11351 |
|
|
RefTransition => '/',
|
| 11352 |
|
|
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
|
| 11353 |
|
|
XOn => XOnChecks,
|
| 11354 |
|
|
MsgOn => MsgOnChecks );
|
| 11355 |
|
|
|
| 11356 |
|
|
END PROCESS;
|
| 11357 |
|
|
|
| 11358 |
|
|
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
|
| 11359 |
|
|
|
| 11360 |
|
|
PROCESS(dataout_tmp)
|
| 11361 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 11362 |
|
|
BEGIN
|
| 11363 |
|
|
VitalPathDelay01 (
|
| 11364 |
|
|
OutSignal => dataout,
|
| 11365 |
|
|
OutSignalName => "dataout",
|
| 11366 |
|
|
OutTemp => dataout_tmp,
|
| 11367 |
|
|
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
|
| 11368 |
|
|
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
|
| 11369 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 11370 |
|
|
Mode => DefGlitchMode,
|
| 11371 |
|
|
XOn => TRUE,
|
| 11372 |
|
|
MsgOn => TRUE );
|
| 11373 |
|
|
END PROCESS;
|
| 11374 |
|
|
END arch;
|
| 11375 |
|
|
|
| 11376 |
|
|
-------------------------------------------------------------------------------
|
| 11377 |
|
|
-- Module Name: stratixiii_mac_register --
|
| 11378 |
|
|
-- Description: Stratix III MAC variable width register --
|
| 11379 |
|
|
-------------------------------------------------------------------------------
|
| 11380 |
|
|
|
| 11381 |
|
|
LIBRARY IEEE;
|
| 11382 |
|
|
USE ieee.std_logic_1164.all;
|
| 11383 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 11384 |
|
|
use IEEE.VITAL_Timing.all;
|
| 11385 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 11386 |
|
|
use work.stratixiii_atom_pack.all;
|
| 11387 |
|
|
|
| 11388 |
|
|
ENTITY stratixiii_mac_register IS
|
| 11389 |
|
|
GENERIC (
|
| 11390 |
|
|
data_width : integer := 18;
|
| 11391 |
|
|
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 11392 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 11393 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
| 11394 |
|
|
tipd_aclr : VitalDelayType01 := DefPropDelay01;
|
| 11395 |
|
|
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 11396 |
|
|
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
|
| 11397 |
|
|
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11398 |
|
|
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11399 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11400 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 11401 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 11402 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 11403 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 11404 |
|
|
XOnChecks: Boolean := DefXOnChecks
|
| 11405 |
|
|
);
|
| 11406 |
|
|
PORT (
|
| 11407 |
|
|
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
|
| 11408 |
|
|
clk : IN std_logic := '0';
|
| 11409 |
|
|
aclr : IN std_logic := '0';
|
| 11410 |
|
|
sload : IN std_logic := '0';
|
| 11411 |
|
|
bypass_register : IN std_logic := '0';
|
| 11412 |
|
|
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
|
| 11413 |
|
|
);
|
| 11414 |
|
|
END stratixiii_mac_register;
|
| 11415 |
|
|
|
| 11416 |
|
|
ARCHITECTURE arch OF stratixiii_mac_register IS
|
| 11417 |
|
|
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
|
| 11418 |
|
|
SIGNAL clk_ipd : std_logic := '0';
|
| 11419 |
|
|
SIGNAL aclr_ipd : std_logic := '0';
|
| 11420 |
|
|
SIGNAL sload_ipd : std_logic := '1';
|
| 11421 |
|
|
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
|
| 11422 |
|
|
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
|
| 11423 |
|
|
BEGIN
|
| 11424 |
|
|
|
| 11425 |
|
|
WireDelay : block
|
| 11426 |
|
|
begin
|
| 11427 |
|
|
g1 :for i in datain'range generate
|
| 11428 |
|
|
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
|
| 11429 |
|
|
end generate;
|
| 11430 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 11431 |
|
|
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
|
| 11432 |
|
|
VitalWireDelay (sload_ipd, sload, tipd_sload);
|
| 11433 |
|
|
end block;
|
| 11434 |
|
|
|
| 11435 |
|
|
|
| 11436 |
|
|
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
|
| 11437 |
|
|
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
|
| 11438 |
|
|
variable Tviol_sload_clk : std_ulogic := '0';
|
| 11439 |
|
|
variable Tviol_datain_clk : std_ulogic := '0';
|
| 11440 |
|
|
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 11441 |
|
|
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 11442 |
|
|
|
| 11443 |
|
|
BEGIN
|
| 11444 |
|
|
IF (aclr_ipd = '1') THEN
|
| 11445 |
|
|
dataout_reg <= (OTHERS => '0');
|
| 11446 |
|
|
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
|
| 11447 |
|
|
IF (sload_ipd = '1') THEN
|
| 11448 |
|
|
dataout_reg <= datain_ipd;
|
| 11449 |
|
|
ELSE
|
| 11450 |
|
|
dataout_reg <= dataout_reg;
|
| 11451 |
|
|
END IF;
|
| 11452 |
|
|
END IF;
|
| 11453 |
|
|
|
| 11454 |
|
|
VitalSetupHoldCheck (
|
| 11455 |
|
|
Violation => Tviol_datain_clk,
|
| 11456 |
|
|
TimingData => TimingData_datain_clk,
|
| 11457 |
|
|
TestSignal => datain,
|
| 11458 |
|
|
TestSignalName => "DATAIN",
|
| 11459 |
|
|
RefSignal => clk_ipd,
|
| 11460 |
|
|
RefSignalName => "CLK",
|
| 11461 |
|
|
SetupHigh => tsetup_datain_clk_noedge_posedge,
|
| 11462 |
|
|
SetupLow => tsetup_datain_clk_noedge_posedge,
|
| 11463 |
|
|
HoldHigh => thold_datain_clk_noedge_posedge,
|
| 11464 |
|
|
HoldLow => thold_datain_clk_noedge_posedge,
|
| 11465 |
|
|
CheckEnabled => TO_X01((NOT aclr_ipd) OR
|
| 11466 |
|
|
(sload_ipd)) /= '1',
|
| 11467 |
|
|
RefTransition => '/',
|
| 11468 |
|
|
HeaderMsg => "/MAC_REG",
|
| 11469 |
|
|
XOn => XOnChecks,
|
| 11470 |
|
|
MsgOn => MsgOnChecks );
|
| 11471 |
|
|
|
| 11472 |
|
|
VitalSetupHoldCheck (
|
| 11473 |
|
|
Violation => Tviol_sload_clk,
|
| 11474 |
|
|
TimingData => TimingData_sload_clk,
|
| 11475 |
|
|
TestSignal => sload_ipd,
|
| 11476 |
|
|
TestSignalName => "SLOAD",
|
| 11477 |
|
|
RefSignal => clk_ipd,
|
| 11478 |
|
|
RefSignalName => "CLK",
|
| 11479 |
|
|
SetupHigh => tsetup_sload_clk_noedge_posedge,
|
| 11480 |
|
|
SetupLow => tsetup_sload_clk_noedge_posedge,
|
| 11481 |
|
|
HoldHigh => thold_sload_clk_noedge_posedge,
|
| 11482 |
|
|
HoldLow => thold_sload_clk_noedge_posedge,
|
| 11483 |
|
|
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
|
| 11484 |
|
|
RefTransition => '/',
|
| 11485 |
|
|
HeaderMsg => "/MAC_REG",
|
| 11486 |
|
|
XOn => XOnChecks,
|
| 11487 |
|
|
MsgOn => MsgOnChecks );
|
| 11488 |
|
|
END PROCESS;
|
| 11489 |
|
|
|
| 11490 |
|
|
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
|
| 11491 |
|
|
|
| 11492 |
|
|
PathDelay : block
|
| 11493 |
|
|
begin
|
| 11494 |
|
|
g1 : for i in dataout'range generate
|
| 11495 |
|
|
PROCESS (dataout_tmp(i))
|
| 11496 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 11497 |
|
|
begin
|
| 11498 |
|
|
VitalPathDelay01 (
|
| 11499 |
|
|
OutSignal => dataout(i),
|
| 11500 |
|
|
OutSignalName => "dataout",
|
| 11501 |
|
|
OutTemp => dataout_tmp(i),
|
| 11502 |
|
|
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
|
| 11503 |
|
|
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
|
| 11504 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 11505 |
|
|
Mode => DefGlitchMode,
|
| 11506 |
|
|
XOn => TRUE,
|
| 11507 |
|
|
MsgOn => TRUE );
|
| 11508 |
|
|
end process;
|
| 11509 |
|
|
end generate;
|
| 11510 |
|
|
end block;
|
| 11511 |
|
|
|
| 11512 |
|
|
END arch;
|
| 11513 |
|
|
|
| 11514 |
|
|
-------------------------------------------------------------------------------
|
| 11515 |
|
|
-- Module Name: stratixiii_mac_multiplier --
|
| 11516 |
|
|
-- Description: Stratix III MAC signed multiplier --
|
| 11517 |
|
|
-------------------------------------------------------------------------------
|
| 11518 |
|
|
|
| 11519 |
|
|
|
| 11520 |
|
|
LIBRARY IEEE;
|
| 11521 |
|
|
USE ieee.std_logic_1164.all;
|
| 11522 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 11523 |
|
|
use IEEE.VITAL_Timing.all;
|
| 11524 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 11525 |
|
|
use work.stratixiii_atom_pack.all;
|
| 11526 |
|
|
|
| 11527 |
|
|
ENTITY stratixiii_mac_multiplier IS
|
| 11528 |
|
|
GENERIC (
|
| 11529 |
|
|
dataa_width : integer := 18;
|
| 11530 |
|
|
datab_width : integer := 18;
|
| 11531 |
|
|
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
|
| 11532 |
|
|
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
|
| 11533 |
|
|
tipd_signa : VitalDelayType01 := DefPropDelay01;
|
| 11534 |
|
|
tipd_signb : VitalDelayType01 := DefPropDelay01;
|
| 11535 |
|
|
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
|
| 11536 |
|
|
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
|
| 11537 |
|
|
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
|
| 11538 |
|
|
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
|
| 11539 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 11540 |
|
|
MsgOn : Boolean := DefGlitchMsgOn
|
| 11541 |
|
|
);
|
| 11542 |
|
|
PORT (
|
| 11543 |
|
|
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
|
| 11544 |
|
|
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
|
| 11545 |
|
|
signa : IN std_logic := '0';
|
| 11546 |
|
|
signb : IN std_logic := '0';
|
| 11547 |
|
|
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
|
| 11548 |
|
|
);
|
| 11549 |
|
|
END stratixiii_mac_multiplier;
|
| 11550 |
|
|
|
| 11551 |
|
|
ARCHITECTURE arch OF stratixiii_mac_multiplier IS
|
| 11552 |
|
|
constant dataout_width : integer := dataa_width + datab_width;
|
| 11553 |
|
|
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
|
| 11554 |
|
|
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
|
| 11555 |
|
|
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
|
| 11556 |
|
|
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
|
| 11557 |
|
|
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
|
| 11558 |
|
|
SIGNAL product_sign : std_logic := '0';
|
| 11559 |
|
|
SIGNAL dataa_sign : std_logic := '0';
|
| 11560 |
|
|
SIGNAL datab_sign : std_logic := '0';
|
| 11561 |
|
|
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
|
| 11562 |
|
|
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
|
| 11563 |
|
|
SIGNAL signa_ipd : std_logic := '0';
|
| 11564 |
|
|
SIGNAL signb_ipd : std_logic := '0';
|
| 11565 |
|
|
BEGIN
|
| 11566 |
|
|
WireDelay : block
|
| 11567 |
|
|
begin
|
| 11568 |
|
|
g1 :for i in dataa'range generate
|
| 11569 |
|
|
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
|
| 11570 |
|
|
end generate;
|
| 11571 |
|
|
g2 :for i in datab'range generate
|
| 11572 |
|
|
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
|
| 11573 |
|
|
end generate;
|
| 11574 |
|
|
VitalWireDelay (signa_ipd, signa, tipd_signa);
|
| 11575 |
|
|
VitalWireDelay (signb_ipd, signb, tipd_signb);
|
| 11576 |
|
|
end block;
|
| 11577 |
|
|
|
| 11578 |
|
|
|
| 11579 |
|
|
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
|
| 11580 |
|
|
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
|
| 11581 |
|
|
product_sign <= dataa_sign XOR datab_sign ;
|
| 11582 |
|
|
abs_a <= (NOT dataa + '1') WHEN dataa_sign = '1' ELSE dataa;
|
| 11583 |
|
|
abs_b <= (NOT datab + '1') WHEN datab_sign = '1' ELSE datab;
|
| 11584 |
|
|
abs_product <= abs_a * abs_b ;
|
| 11585 |
|
|
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
|
| 11586 |
|
|
|
| 11587 |
|
|
PathDelay : block
|
| 11588 |
|
|
begin
|
| 11589 |
|
|
do : for i in dataout'range generate
|
| 11590 |
|
|
process(dataout_tmp(i))
|
| 11591 |
|
|
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
|
| 11592 |
|
|
|
| 11593 |
|
|
begin
|
| 11594 |
|
|
VitalPathDelay01 (
|
| 11595 |
|
|
OutSignal => dataout(i),
|
| 11596 |
|
|
OutSignalName => "dataout",
|
| 11597 |
|
|
OutTemp => dataout_tmp(i),
|
| 11598 |
|
|
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
|
| 11599 |
|
|
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
|
| 11600 |
|
|
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
|
| 11601 |
|
|
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
|
| 11602 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 11603 |
|
|
Mode => DefGlitchMode,
|
| 11604 |
|
|
MsgOn => FALSE,
|
| 11605 |
|
|
XOn => TRUE
|
| 11606 |
|
|
);
|
| 11607 |
|
|
end process;
|
| 11608 |
|
|
end generate do;
|
| 11609 |
|
|
end block;
|
| 11610 |
|
|
END arch;
|
| 11611 |
|
|
|
| 11612 |
|
|
----------------------------------------------------------------------------------
|
| 11613 |
|
|
-- Module Name: stratixiii_mac_mult_atom --
|
| 11614 |
|
|
-- Description: Simulation model for stratixiii mac mult atom. --
|
| 11615 |
|
|
-- This model instantiates the following components. --
|
| 11616 |
|
|
-- 1.stratixiii_mac_bit_register. --
|
| 11617 |
|
|
-- 2.stratixiii_mac_register. --
|
| 11618 |
|
|
-- 3.stratixiii_mac_multiplier. --
|
| 11619 |
|
|
----------------------------------------------------------------------------------
|
| 11620 |
|
|
|
| 11621 |
|
|
LIBRARY IEEE;
|
| 11622 |
|
|
USE ieee.std_logic_1164.all;
|
| 11623 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 11624 |
|
|
use ieee.std_logic_arith.all;
|
| 11625 |
|
|
use IEEE.VITAL_Timing.all;
|
| 11626 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 11627 |
|
|
use work.stratixiii_atom_pack.all;
|
| 11628 |
|
|
|
| 11629 |
|
|
ENTITY stratixiii_mac_mult IS
|
| 11630 |
|
|
GENERIC (
|
| 11631 |
|
|
dataa_width : integer := 18;
|
| 11632 |
|
|
datab_width : integer := 18;
|
| 11633 |
|
|
dataa_clock : string := "none";
|
| 11634 |
|
|
datab_clock : string := "none";
|
| 11635 |
|
|
signa_clock : string := "none";
|
| 11636 |
|
|
signb_clock : string := "none";
|
| 11637 |
|
|
scanouta_clock : string := "none";
|
| 11638 |
|
|
dataa_clear : string := "none";
|
| 11639 |
|
|
datab_clear : string := "none";
|
| 11640 |
|
|
signa_clear : string := "none";
|
| 11641 |
|
|
signb_clear : string := "none";
|
| 11642 |
|
|
scanouta_clear : string := "none";
|
| 11643 |
|
|
signa_internally_grounded : string := "false";
|
| 11644 |
|
|
signb_internally_grounded : string := "false";
|
| 11645 |
|
|
lpm_type : string := "stratixiii_mac_mult"
|
| 11646 |
|
|
);
|
| 11647 |
|
|
PORT (
|
| 11648 |
|
|
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
|
| 11649 |
|
|
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
|
| 11650 |
|
|
signa : IN std_logic := '1';
|
| 11651 |
|
|
signb : IN std_logic := '1';
|
| 11652 |
|
|
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11653 |
|
|
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11654 |
|
|
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
|
| 11655 |
|
|
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
|
| 11656 |
|
|
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
|
| 11657 |
|
|
devclrn : IN std_logic := '1';
|
| 11658 |
|
|
devpor : IN std_logic := '1'
|
| 11659 |
|
|
);
|
| 11660 |
|
|
END stratixiii_mac_mult;
|
| 11661 |
|
|
|
| 11662 |
|
|
ARCHITECTURE arch OF stratixiii_mac_mult IS
|
| 11663 |
|
|
constant dataout_width : integer := dataa_width + datab_width;
|
| 11664 |
|
|
|
| 11665 |
|
|
COMPONENT stratixiii_mac_bit_register
|
| 11666 |
|
|
PORT (
|
| 11667 |
|
|
datain : IN std_logic := '0';
|
| 11668 |
|
|
clk : IN std_logic := '0';
|
| 11669 |
|
|
aclr : IN std_logic := '0';
|
| 11670 |
|
|
sload : IN std_logic := '0';
|
| 11671 |
|
|
bypass_register : IN std_logic := '0';
|
| 11672 |
|
|
dataout : OUT std_logic
|
| 11673 |
|
|
);
|
| 11674 |
|
|
END COMPONENT;
|
| 11675 |
|
|
|
| 11676 |
|
|
COMPONENT stratixiii_mac_register
|
| 11677 |
|
|
GENERIC (
|
| 11678 |
|
|
data_width : integer := 18
|
| 11679 |
|
|
);
|
| 11680 |
|
|
PORT (
|
| 11681 |
|
|
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
|
| 11682 |
|
|
clk : IN std_logic := '0';
|
| 11683 |
|
|
aclr : IN std_logic := '0';
|
| 11684 |
|
|
sload : IN std_logic := '0';
|
| 11685 |
|
|
bypass_register : IN std_logic := '0';
|
| 11686 |
|
|
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
|
| 11687 |
|
|
);
|
| 11688 |
|
|
END COMPONENT;
|
| 11689 |
|
|
|
| 11690 |
|
|
COMPONENT stratixiii_mac_multiplier
|
| 11691 |
|
|
GENERIC (
|
| 11692 |
|
|
dataa_width : integer := 18;
|
| 11693 |
|
|
datab_width : integer := 18
|
| 11694 |
|
|
);
|
| 11695 |
|
|
PORT (
|
| 11696 |
|
|
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
|
| 11697 |
|
|
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
|
| 11698 |
|
|
signa : IN std_logic := '0';
|
| 11699 |
|
|
signb : IN std_logic := '0';
|
| 11700 |
|
|
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
|
| 11701 |
|
|
);
|
| 11702 |
|
|
END COMPONENT;
|
| 11703 |
|
|
|
| 11704 |
|
|
--Internal signals to instantiate the dataa input register unit
|
| 11705 |
|
|
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11706 |
|
|
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11707 |
|
|
SIGNAL dataa_clk : std_logic := '0';
|
| 11708 |
|
|
SIGNAL dataa_aclr : std_logic := '0';
|
| 11709 |
|
|
SIGNAL dataa_sload : std_logic := '0';
|
| 11710 |
|
|
SIGNAL dataa_bypass_register : std_logic := '0';
|
| 11711 |
|
|
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
|
| 11712 |
|
|
--Internal signals to instantiate the datab input register unit
|
| 11713 |
|
|
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11714 |
|
|
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11715 |
|
|
SIGNAL datab_clk : std_logic := '0';
|
| 11716 |
|
|
SIGNAL datab_aclr : std_logic := '0';
|
| 11717 |
|
|
SIGNAL datab_sload : std_logic := '0';
|
| 11718 |
|
|
SIGNAL datab_bypass_register : std_logic := '0';
|
| 11719 |
|
|
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
|
| 11720 |
|
|
--Internal signals to instantiate the signa input register unit
|
| 11721 |
|
|
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11722 |
|
|
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11723 |
|
|
SIGNAL signa_clk : std_logic := '0';
|
| 11724 |
|
|
SIGNAL signa_aclr : std_logic := '0';
|
| 11725 |
|
|
SIGNAL signa_sload : std_logic := '0';
|
| 11726 |
|
|
SIGNAL signa_bypass_register : std_logic := '0';
|
| 11727 |
|
|
SIGNAL signa_in_reg : std_logic := '0';
|
| 11728 |
|
|
--Internal signbls to instantiate the signb input register unit
|
| 11729 |
|
|
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11730 |
|
|
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11731 |
|
|
SIGNAL signb_clk : std_logic := '0';
|
| 11732 |
|
|
SIGNAL signb_aclr : std_logic := '0';
|
| 11733 |
|
|
SIGNAL signb_sload : std_logic := '0';
|
| 11734 |
|
|
SIGNAL signb_bypass_register : std_logic := '0';
|
| 11735 |
|
|
SIGNAL signb_in_reg : std_logic := '0';
|
| 11736 |
|
|
--Internal scanoutals to instantiate the scanouta input register unit
|
| 11737 |
|
|
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11738 |
|
|
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 11739 |
|
|
SIGNAL scanouta_clk : std_logic := '0';
|
| 11740 |
|
|
SIGNAL scanouta_aclr : std_logic := '0';
|
| 11741 |
|
|
SIGNAL scanouta_sload : std_logic := '0';
|
| 11742 |
|
|
SIGNAL scanouta_bypass_register : std_logic := '0';
|
| 11743 |
|
|
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
|
| 11744 |
|
|
--Internal Signals to instantiate the mac multiplier
|
| 11745 |
|
|
SIGNAL signa_mult : std_logic := '0';
|
| 11746 |
|
|
SIGNAL signb_mult : std_logic := '0';
|
| 11747 |
|
|
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
|
| 11748 |
|
|
|
| 11749 |
|
|
BEGIN
|
| 11750 |
|
|
|
| 11751 |
|
|
--Instantiate the dataa input Register
|
| 11752 |
|
|
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
|
| 11753 |
|
|
ELSE "0001" WHEN (dataa_clock = "1")
|
| 11754 |
|
|
ELSE "0010" WHEN (dataa_clock = "2")
|
| 11755 |
|
|
ELSE "0011" WHEN (dataa_clock = "3")
|
| 11756 |
|
|
ELSE "0000" ;
|
| 11757 |
|
|
|
| 11758 |
|
|
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
|
| 11759 |
|
|
ELSE "0001" WHEN (dataa_clear = "1")
|
| 11760 |
|
|
ELSE "0010" WHEN (dataa_clear = "2")
|
| 11761 |
|
|
ELSE "0011" WHEN (dataa_clear = "3")
|
| 11762 |
|
|
ELSE "0000" ;
|
| 11763 |
|
|
|
| 11764 |
|
|
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
|
| 11765 |
|
|
|
| 11766 |
|
|
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
|
| 11767 |
|
|
|
| 11768 |
|
|
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
|
| 11769 |
|
|
|
| 11770 |
|
|
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
|
| 11771 |
|
|
|
| 11772 |
|
|
dataa_input_register : stratixiii_mac_register
|
| 11773 |
|
|
GENERIC MAP (
|
| 11774 |
|
|
data_width => dataa_width
|
| 11775 |
|
|
)
|
| 11776 |
|
|
PORT MAP (
|
| 11777 |
|
|
datain => dataa,
|
| 11778 |
|
|
clk => dataa_clk,
|
| 11779 |
|
|
aclr => dataa_aclr,
|
| 11780 |
|
|
sload => dataa_sload,
|
| 11781 |
|
|
bypass_register => dataa_bypass_register,
|
| 11782 |
|
|
dataout => dataa_in_reg
|
| 11783 |
|
|
);
|
| 11784 |
|
|
|
| 11785 |
|
|
|
| 11786 |
|
|
--Instantiate the datab input Register
|
| 11787 |
|
|
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
|
| 11788 |
|
|
ELSE "0001" WHEN (datab_clock = "1")
|
| 11789 |
|
|
ELSE "0010" WHEN (datab_clock = "2")
|
| 11790 |
|
|
ELSE "0011" WHEN (datab_clock = "3")
|
| 11791 |
|
|
ELSE "0000" ;
|
| 11792 |
|
|
|
| 11793 |
|
|
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
|
| 11794 |
|
|
ELSE "0001" WHEN (datab_clear = "1")
|
| 11795 |
|
|
ELSE "0010" WHEN (datab_clear = "2")
|
| 11796 |
|
|
ELSE "0011" WHEN (datab_clear = "3")
|
| 11797 |
|
|
ELSE "0000" ;
|
| 11798 |
|
|
|
| 11799 |
|
|
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
|
| 11800 |
|
|
|
| 11801 |
|
|
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
|
| 11802 |
|
|
|
| 11803 |
|
|
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
|
| 11804 |
|
|
|
| 11805 |
|
|
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
|
| 11806 |
|
|
|
| 11807 |
|
|
datab_input_register : stratixiii_mac_register
|
| 11808 |
|
|
GENERIC MAP (
|
| 11809 |
|
|
data_width => datab_width
|
| 11810 |
|
|
)
|
| 11811 |
|
|
PORT MAP (
|
| 11812 |
|
|
datain => datab,
|
| 11813 |
|
|
clk => datab_clk,
|
| 11814 |
|
|
aclr => datab_aclr,
|
| 11815 |
|
|
sload => datab_sload,
|
| 11816 |
|
|
bypass_register => datab_bypass_register,
|
| 11817 |
|
|
dataout => datab_in_reg
|
| 11818 |
|
|
);
|
| 11819 |
|
|
|
| 11820 |
|
|
|
| 11821 |
|
|
--Instantiate the signa input Register
|
| 11822 |
|
|
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
|
| 11823 |
|
|
ELSE "0001" WHEN (signa_clock = "1")
|
| 11824 |
|
|
ELSE "0010" WHEN (signa_clock = "2")
|
| 11825 |
|
|
ELSE "0011" WHEN (signa_clock = "3")
|
| 11826 |
|
|
ELSE "0000" ;
|
| 11827 |
|
|
|
| 11828 |
|
|
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
|
| 11829 |
|
|
ELSE "0001" WHEN (signa_clear = "1")
|
| 11830 |
|
|
ELSE "0010" WHEN (signa_clear = "2")
|
| 11831 |
|
|
ELSE "0011" WHEN (signa_clear = "3")
|
| 11832 |
|
|
ELSE "0000" ;
|
| 11833 |
|
|
|
| 11834 |
|
|
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
|
| 11835 |
|
|
|
| 11836 |
|
|
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
|
| 11837 |
|
|
|
| 11838 |
|
|
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
|
| 11839 |
|
|
|
| 11840 |
|
|
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
|
| 11841 |
|
|
|
| 11842 |
|
|
signa_input_register : stratixiii_mac_bit_register
|
| 11843 |
|
|
PORT MAP (
|
| 11844 |
|
|
datain => signa,
|
| 11845 |
|
|
clk => signa_clk,
|
| 11846 |
|
|
aclr => signa_aclr,
|
| 11847 |
|
|
sload => signa_sload,
|
| 11848 |
|
|
bypass_register => signa_bypass_register,
|
| 11849 |
|
|
dataout => signa_in_reg
|
| 11850 |
|
|
);
|
| 11851 |
|
|
--Instantiate the signb input Register
|
| 11852 |
|
|
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
|
| 11853 |
|
|
ELSE "0001" WHEN (signb_clock = "1")
|
| 11854 |
|
|
ELSE "0010" WHEN (signb_clock = "2")
|
| 11855 |
|
|
ELSE "0011" WHEN (signb_clock = "3")
|
| 11856 |
|
|
ELSE "0000" ;
|
| 11857 |
|
|
|
| 11858 |
|
|
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
|
| 11859 |
|
|
ELSE "0001" WHEN (signb_clear = "1")
|
| 11860 |
|
|
ELSE "0010" WHEN (signb_clear = "2")
|
| 11861 |
|
|
ELSE "0011" WHEN (signb_clear = "3")
|
| 11862 |
|
|
ELSE "0000" ;
|
| 11863 |
|
|
|
| 11864 |
|
|
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
|
| 11865 |
|
|
|
| 11866 |
|
|
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
|
| 11867 |
|
|
|
| 11868 |
|
|
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
|
| 11869 |
|
|
|
| 11870 |
|
|
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
|
| 11871 |
|
|
|
| 11872 |
|
|
signb_input_register : stratixiii_mac_bit_register
|
| 11873 |
|
|
PORT MAP (
|
| 11874 |
|
|
datain => signb,
|
| 11875 |
|
|
clk => signb_clk,
|
| 11876 |
|
|
aclr => signb_aclr,
|
| 11877 |
|
|
sload => signb_sload,
|
| 11878 |
|
|
bypass_register => signb_bypass_register,
|
| 11879 |
|
|
dataout => signb_in_reg
|
| 11880 |
|
|
);
|
| 11881 |
|
|
--Instantiate the scanouta input Register
|
| 11882 |
|
|
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
|
| 11883 |
|
|
ELSE "0001" WHEN (scanouta_clock = "1")
|
| 11884 |
|
|
ELSE "0010" WHEN (scanouta_clock = "2")
|
| 11885 |
|
|
ELSE "0011" WHEN (scanouta_clock = "3")
|
| 11886 |
|
|
ELSE "0000" ;
|
| 11887 |
|
|
|
| 11888 |
|
|
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
|
| 11889 |
|
|
ELSE "0001" WHEN (scanouta_clear = "1")
|
| 11890 |
|
|
ELSE "0010" WHEN (scanouta_clear = "2")
|
| 11891 |
|
|
ELSE "0011" WHEN (scanouta_clear = "3")
|
| 11892 |
|
|
ELSE "0000" ;
|
| 11893 |
|
|
|
| 11894 |
|
|
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
|
| 11895 |
|
|
|
| 11896 |
|
|
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
|
| 11897 |
|
|
|
| 11898 |
|
|
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
|
| 11899 |
|
|
|
| 11900 |
|
|
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
|
| 11901 |
|
|
|
| 11902 |
|
|
scanouta_input_register : stratixiii_mac_register
|
| 11903 |
|
|
GENERIC MAP (
|
| 11904 |
|
|
data_width => dataa_width
|
| 11905 |
|
|
)
|
| 11906 |
|
|
PORT MAP (
|
| 11907 |
|
|
datain => dataa_in_reg,
|
| 11908 |
|
|
clk => scanouta_clk,
|
| 11909 |
|
|
aclr => scanouta_aclr,
|
| 11910 |
|
|
sload => scanouta_sload,
|
| 11911 |
|
|
bypass_register => scanouta_bypass_register,
|
| 11912 |
|
|
dataout => scanouta
|
| 11913 |
|
|
);
|
| 11914 |
|
|
|
| 11915 |
|
|
--Instantiate mac_multiplier block
|
| 11916 |
|
|
|
| 11917 |
|
|
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
|
| 11918 |
|
|
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
|
| 11919 |
|
|
|
| 11920 |
|
|
mac_multiplier : stratixiii_mac_multiplier
|
| 11921 |
|
|
GENERIC MAP (
|
| 11922 |
|
|
dataa_width => dataa_width,
|
| 11923 |
|
|
datab_width => datab_width
|
| 11924 |
|
|
)
|
| 11925 |
|
|
PORT MAP (
|
| 11926 |
|
|
dataa => dataa_in_reg,
|
| 11927 |
|
|
datab => datab_in_reg,
|
| 11928 |
|
|
signa => signa_mult,
|
| 11929 |
|
|
signb => signb_mult,
|
| 11930 |
|
|
dataout => dataout
|
| 11931 |
|
|
);
|
| 11932 |
|
|
END arch;
|
| 11933 |
|
|
|
| 11934 |
|
|
--------------------------------------------------------------------------------------------------
|
| 11935 |
|
|
-- Module Name: stratixiii_fsa_isse --
|
| 11936 |
|
|
-- Description: Stratix III first stage adder input selection and sign extension block. --
|
| 11937 |
|
|
--------------------------------------------------------------------------------------------------
|
| 11938 |
|
|
|
| 11939 |
|
|
LIBRARY IEEE;
|
| 11940 |
|
|
USE ieee.std_logic_1164.all;
|
| 11941 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 11942 |
|
|
use IEEE.std_logic_arith.all;
|
| 11943 |
|
|
use IEEE.VITAL_Timing.all;
|
| 11944 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 11945 |
|
|
use work.stratixiii_atom_pack.all;
|
| 11946 |
|
|
|
| 11947 |
|
|
ENTITY stratixiii_fsa_isse IS
|
| 11948 |
|
|
GENERIC (
|
| 11949 |
|
|
dataa_width : integer := 36;
|
| 11950 |
|
|
datab_width : integer := 36;
|
| 11951 |
|
|
datac_width : integer := 36;
|
| 11952 |
|
|
datad_width : integer := 36;
|
| 11953 |
|
|
chainin_width : integer := 44;
|
| 11954 |
|
|
operation_mode : string := "output_only"
|
| 11955 |
|
|
);
|
| 11956 |
|
|
PORT (
|
| 11957 |
|
|
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
|
| 11958 |
|
|
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
|
| 11959 |
|
|
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
|
| 11960 |
|
|
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
|
| 11961 |
|
|
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
|
| 11962 |
|
|
signa : IN std_logic := '0';
|
| 11963 |
|
|
signb : IN std_logic := '0';
|
| 11964 |
|
|
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
|
| 11965 |
|
|
datab_out : OUT std_logic_vector(71 DOWNTO 0);
|
| 11966 |
|
|
datac_out : OUT std_logic_vector(71 DOWNTO 0);
|
| 11967 |
|
|
datad_out : OUT std_logic_vector(71 DOWNTO 0);
|
| 11968 |
|
|
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
|
| 11969 |
|
|
operation : OUT std_logic_vector(3 DOWNTO 0)
|
| 11970 |
|
|
);
|
| 11971 |
|
|
END stratixiii_fsa_isse;
|
| 11972 |
|
|
|
| 11973 |
|
|
ARCHITECTURE arch OF stratixiii_fsa_isse IS
|
| 11974 |
|
|
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 11975 |
|
|
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 11976 |
|
|
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 11977 |
|
|
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 11978 |
|
|
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 11979 |
|
|
signal sign :std_logic := '0';
|
| 11980 |
|
|
|
| 11981 |
|
|
BEGIN
|
| 11982 |
|
|
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
|
| 11983 |
|
|
"0001" WHEN (operation_mode = "one_level_adder") ELSE
|
| 11984 |
|
|
"0010" WHEN (operation_mode = "loopback") ELSE
|
| 11985 |
|
|
"0011" WHEN (operation_mode = "accumulator") ELSE
|
| 11986 |
|
|
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
|
| 11987 |
|
|
"0101" WHEN (operation_mode = "two_level_adder") ELSE
|
| 11988 |
|
|
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
|
| 11989 |
|
|
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
|
| 11990 |
|
|
"1000" WHEN (operation_mode = "shift") ELSE
|
| 11991 |
|
|
"1001" WHEN (operation_mode = "double") ELSE "0000";
|
| 11992 |
|
|
sign <= signa or signb;
|
| 11993 |
|
|
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
|
| 11994 |
|
|
BEGIN
|
| 11995 |
|
|
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
|
| 11996 |
|
|
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
|
| 11997 |
|
|
ELSE
|
| 11998 |
|
|
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
|
| 11999 |
|
|
END IF;
|
| 12000 |
|
|
|
| 12001 |
|
|
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
|
| 12002 |
|
|
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
|
| 12003 |
|
|
datab_out_tmp <= sxt(datab(datab_width - 1 DOWNTO 0), 72);
|
| 12004 |
|
|
ELSE
|
| 12005 |
|
|
datab_out_tmp <= ext(datab(datab_width - 1 DOWNTO 0), 72);
|
| 12006 |
|
|
END IF;
|
| 12007 |
|
|
ELSIF(operation_mode = "double") THEN
|
| 12008 |
|
|
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
|
| 12009 |
|
|
datab_out_tmp <= sxt(datab(datab_width - 1 DOWNTO 0), 72);
|
| 12010 |
|
|
ELSE
|
| 12011 |
|
|
datab_out_tmp <= ext(datab(datab_width - 1 DOWNTO 0), 72);
|
| 12012 |
|
|
END IF;
|
| 12013 |
|
|
ELSE
|
| 12014 |
|
|
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
|
| 12015 |
|
|
datab_out_tmp <= sxt(datab(datab_width - 1 DOWNTO 0), 72);
|
| 12016 |
|
|
ELSE
|
| 12017 |
|
|
datab_out_tmp <= ext(datab(datab_width - 1 DOWNTO 0), 72);
|
| 12018 |
|
|
END IF;
|
| 12019 |
|
|
END IF;
|
| 12020 |
|
|
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
|
| 12021 |
|
|
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
|
| 12022 |
|
|
datac_out_tmp <= sxt(datac(datac_width - 1 DOWNTO 0), 72);
|
| 12023 |
|
|
ELSE
|
| 12024 |
|
|
datac_out_tmp <= ext(datac(datac_width - 1 DOWNTO 0), 72);
|
| 12025 |
|
|
END IF;
|
| 12026 |
|
|
ELSE
|
| 12027 |
|
|
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
|
| 12028 |
|
|
datac_out_tmp <= sxt(datac(datac_width - 1 DOWNTO 0), 72);
|
| 12029 |
|
|
ELSE
|
| 12030 |
|
|
datac_out_tmp <= ext(datac(datac_width - 1 DOWNTO 0), 72);
|
| 12031 |
|
|
END IF;
|
| 12032 |
|
|
END IF;
|
| 12033 |
|
|
|
| 12034 |
|
|
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
|
| 12035 |
|
|
datad_out_tmp <= ext(datad(datad_width - 1 DOWNTO 0), 72);
|
| 12036 |
|
|
ELSIF(operation_mode = "double")THEN
|
| 12037 |
|
|
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
|
| 12038 |
|
|
datad_out_tmp <= sxt(datad(datad_width - 1 DOWNTO 0), 72);
|
| 12039 |
|
|
ELSE
|
| 12040 |
|
|
datad_out_tmp <= ext(datad(datad_width - 1 DOWNTO 0), 72);
|
| 12041 |
|
|
END IF;
|
| 12042 |
|
|
ELSE
|
| 12043 |
|
|
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
|
| 12044 |
|
|
datad_out_tmp <= sxt(datad(datad_width - 1 DOWNTO 0), 72);
|
| 12045 |
|
|
ELSE
|
| 12046 |
|
|
datad_out_tmp <= ext(datad(datad_width - 1 DOWNTO 0), 72);
|
| 12047 |
|
|
END IF;
|
| 12048 |
|
|
END IF;
|
| 12049 |
|
|
|
| 12050 |
|
|
IF (chainin(chainin_width - 1) = '1') THEN
|
| 12051 |
|
|
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
|
| 12052 |
|
|
ELSE
|
| 12053 |
|
|
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
|
| 12054 |
|
|
END IF;
|
| 12055 |
|
|
END process;
|
| 12056 |
|
|
|
| 12057 |
|
|
dataa_out <= dataa_out_tmp;
|
| 12058 |
|
|
datab_out <= datab_out_tmp;
|
| 12059 |
|
|
datac_out <= datac_out_tmp;
|
| 12060 |
|
|
datad_out <= datad_out_tmp;
|
| 12061 |
|
|
chainin_out <= chainin_out_tmp;
|
| 12062 |
|
|
|
| 12063 |
|
|
END arch;
|
| 12064 |
|
|
|
| 12065 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12066 |
|
|
-- Module Name: stratixiii_first_stage_add_sub --
|
| 12067 |
|
|
-- Description: Stratix III First Stage Adder Subtractor Unit --
|
| 12068 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12069 |
|
|
|
| 12070 |
|
|
LIBRARY IEEE;
|
| 12071 |
|
|
USE ieee.std_logic_1164.all;
|
| 12072 |
|
|
--USE ieee.std_logic_unsigned.all;
|
| 12073 |
|
|
use IEEE.std_logic_arith.all;
|
| 12074 |
|
|
use IEEE.VITAL_Timing.all;
|
| 12075 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 12076 |
|
|
use work.stratixiii_atom_pack.all;
|
| 12077 |
|
|
library grlib;
|
| 12078 |
|
|
use grlib.stdlib.all;
|
| 12079 |
|
|
|
| 12080 |
|
|
|
| 12081 |
|
|
ENTITY stratixiii_first_stage_add_sub IS
|
| 12082 |
|
|
GENERIC (
|
| 12083 |
|
|
dataa_width : integer := 36;
|
| 12084 |
|
|
datab_width : integer := 36;
|
| 12085 |
|
|
fsa_mode : string := "add";
|
| 12086 |
|
|
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 12087 |
|
|
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 12088 |
|
|
tipd_sign : VitalDelayType01 :=DefPropDelay01;
|
| 12089 |
|
|
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
|
| 12090 |
|
|
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
|
| 12091 |
|
|
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
|
| 12092 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 12093 |
|
|
MsgOn : Boolean := DefGlitchMsgOn
|
| 12094 |
|
|
);
|
| 12095 |
|
|
PORT (
|
| 12096 |
|
|
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12097 |
|
|
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12098 |
|
|
sign : IN std_logic := '0';
|
| 12099 |
|
|
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 12100 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0)
|
| 12101 |
|
|
);
|
| 12102 |
|
|
END stratixiii_first_stage_add_sub;
|
| 12103 |
|
|
|
| 12104 |
|
|
ARCHITECTURE arch OF stratixiii_first_stage_add_sub IS
|
| 12105 |
|
|
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12106 |
|
|
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12107 |
|
|
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12108 |
|
|
SIGNAL sign_a : std_logic := '0';
|
| 12109 |
|
|
SIGNAL sign_b : std_logic := '0';
|
| 12110 |
|
|
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12111 |
|
|
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12112 |
|
|
SIGNAL sign_ipd : std_logic := '0';
|
| 12113 |
|
|
|
| 12114 |
|
|
BEGIN
|
| 12115 |
|
|
WireDelay : block
|
| 12116 |
|
|
begin
|
| 12117 |
|
|
g1 :for i in dataa'range generate
|
| 12118 |
|
|
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
|
| 12119 |
|
|
end generate;
|
| 12120 |
|
|
g2 :for i in datab'range generate
|
| 12121 |
|
|
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
|
| 12122 |
|
|
end generate;
|
| 12123 |
|
|
VitalWireDelay (sign_ipd, sign, tipd_sign);
|
| 12124 |
|
|
end block;
|
| 12125 |
|
|
|
| 12126 |
|
|
PROCESS
|
| 12127 |
|
|
BEGIN
|
| 12128 |
|
|
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
|
| 12129 |
|
|
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
|
| 12130 |
|
|
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
|
| 12131 |
|
|
ELSE
|
| 12132 |
|
|
IF(fsa_mode = "add")THEN
|
| 12133 |
|
|
IF (sign_ipd = '1') THEN
|
| 12134 |
|
|
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
|
| 12135 |
|
|
ELSE
|
| 12136 |
|
|
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
|
| 12137 |
|
|
END IF;
|
| 12138 |
|
|
ELSE
|
| 12139 |
|
|
IF (sign_ipd = '1') THEN
|
| 12140 |
|
|
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
|
| 12141 |
|
|
ELSE
|
| 12142 |
|
|
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
|
| 12143 |
|
|
END IF;
|
| 12144 |
|
|
END IF;
|
| 12145 |
|
|
END IF;
|
| 12146 |
|
|
END process ;
|
| 12147 |
|
|
|
| 12148 |
|
|
PathDelay : block
|
| 12149 |
|
|
begin
|
| 12150 |
|
|
do1 : for i in dataout'range generate
|
| 12151 |
|
|
process(dataout_tmp(i))
|
| 12152 |
|
|
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
|
| 12153 |
|
|
|
| 12154 |
|
|
begin
|
| 12155 |
|
|
VitalPathDelay01 (
|
| 12156 |
|
|
OutSignal => dataout(i),
|
| 12157 |
|
|
OutSignalName => "dataout",
|
| 12158 |
|
|
OutTemp => dataout_tmp(i),
|
| 12159 |
|
|
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
|
| 12160 |
|
|
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
|
| 12161 |
|
|
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
|
| 12162 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 12163 |
|
|
Mode => DefGlitchMode,
|
| 12164 |
|
|
MsgOn => FALSE,
|
| 12165 |
|
|
XOn => TRUE
|
| 12166 |
|
|
);
|
| 12167 |
|
|
end process;
|
| 12168 |
|
|
end generate do1;
|
| 12169 |
|
|
end block;
|
| 12170 |
|
|
END arch;
|
| 12171 |
|
|
|
| 12172 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12173 |
|
|
-- Module Name: stratixiii_second_stage_add_accum --
|
| 12174 |
|
|
-- Description: Stratix III Second stage Adder and Accumulator/Decimator Unit --
|
| 12175 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12176 |
|
|
|
| 12177 |
|
|
LIBRARY IEEE;
|
| 12178 |
|
|
USE ieee.std_logic_1164.all;
|
| 12179 |
|
|
--USE ieee.std_logic_unsigned.all;
|
| 12180 |
|
|
use IEEE.std_logic_arith.all;
|
| 12181 |
|
|
use IEEE.VITAL_Timing.all;
|
| 12182 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 12183 |
|
|
use work.stratixiii_atom_pack.all;
|
| 12184 |
|
|
library grlib;
|
| 12185 |
|
|
use grlib.stdlib.all;
|
| 12186 |
|
|
|
| 12187 |
|
|
ENTITY stratixiii_second_stage_add_accum IS
|
| 12188 |
|
|
GENERIC (
|
| 12189 |
|
|
dataa_width : integer := 36;
|
| 12190 |
|
|
datab_width : integer := 36;
|
| 12191 |
|
|
ssa_mode : string := "add";
|
| 12192 |
|
|
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 12193 |
|
|
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 12194 |
|
|
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 12195 |
|
|
tipd_sign : VitalDelayType01 :=DefPropDelay01;
|
| 12196 |
|
|
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
|
| 12197 |
|
|
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
|
| 12198 |
|
|
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
|
| 12199 |
|
|
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
|
| 12200 |
|
|
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
|
| 12201 |
|
|
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
|
| 12202 |
|
|
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
|
| 12203 |
|
|
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
|
| 12204 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 12205 |
|
|
MsgOn : Boolean := DefGlitchMsgOn
|
| 12206 |
|
|
);
|
| 12207 |
|
|
PORT (
|
| 12208 |
|
|
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12209 |
|
|
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12210 |
|
|
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12211 |
|
|
sign : IN std_logic := '0';
|
| 12212 |
|
|
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 12213 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12214 |
|
|
overflow : OUT std_logic
|
| 12215 |
|
|
);
|
| 12216 |
|
|
END stratixiii_second_stage_add_accum;
|
| 12217 |
|
|
|
| 12218 |
|
|
ARCHITECTURE arch OF stratixiii_second_stage_add_accum IS
|
| 12219 |
|
|
constant accum_width : integer := dataa_width + 7;
|
| 12220 |
|
|
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12221 |
|
|
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12222 |
|
|
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12223 |
|
|
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12224 |
|
|
SIGNAL overflow_tmp : std_logic := '0';
|
| 12225 |
|
|
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12226 |
|
|
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12227 |
|
|
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12228 |
|
|
SIGNAL sign_ipd : std_logic := '0';
|
| 12229 |
|
|
SIGNAL signb_ipd : std_logic := '0';
|
| 12230 |
|
|
|
| 12231 |
|
|
BEGIN
|
| 12232 |
|
|
WireDelay : block
|
| 12233 |
|
|
begin
|
| 12234 |
|
|
g1 :for i in dataa'range generate
|
| 12235 |
|
|
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
|
| 12236 |
|
|
end generate;
|
| 12237 |
|
|
g2 :for i in datab'range generate
|
| 12238 |
|
|
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
|
| 12239 |
|
|
end generate;
|
| 12240 |
|
|
g3 :for i in accumin'range generate
|
| 12241 |
|
|
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
|
| 12242 |
|
|
end generate;
|
| 12243 |
|
|
VitalWireDelay (sign_ipd, sign, tipd_sign);
|
| 12244 |
|
|
end block;
|
| 12245 |
|
|
|
| 12246 |
|
|
PROCESS
|
| 12247 |
|
|
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12248 |
|
|
BEGIN
|
| 12249 |
|
|
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
|
| 12250 |
|
|
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
|
| 12251 |
|
|
IF(ssa_mode = "add")THEN
|
| 12252 |
|
|
IF (sign_ipd = '1') THEN
|
| 12253 |
|
|
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
|
| 12254 |
|
|
ELSE
|
| 12255 |
|
|
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
|
| 12256 |
|
|
END IF;
|
| 12257 |
|
|
ELSE
|
| 12258 |
|
|
IF (sign_ipd = '1') THEN
|
| 12259 |
|
|
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
|
| 12260 |
|
|
ELSE
|
| 12261 |
|
|
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
|
| 12262 |
|
|
END IF;
|
| 12263 |
|
|
END IF;
|
| 12264 |
|
|
IF(sign_ipd = '1')THEN
|
| 12265 |
|
|
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
|
| 12266 |
|
|
ELSE
|
| 12267 |
|
|
IF(ssa_mode = "add")THEN
|
| 12268 |
|
|
overflow_tmp <= dataout_tmp(accum_width);
|
| 12269 |
|
|
ELSE
|
| 12270 |
|
|
overflow_tmp <= 'X';
|
| 12271 |
|
|
END IF;
|
| 12272 |
|
|
END IF;
|
| 12273 |
|
|
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
|
| 12274 |
|
|
overflow_tmp <= '0';
|
| 12275 |
|
|
IF (sign_ipd = '1') THEN
|
| 12276 |
|
|
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
|
| 12277 |
|
|
ELSE
|
| 12278 |
|
|
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
|
| 12279 |
|
|
END IF;
|
| 12280 |
|
|
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
|
| 12281 |
|
|
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
|
| 12282 |
|
|
overflow_tmp <= '0';
|
| 12283 |
|
|
ELSIF ((operation = "1001")) THEN --double mode
|
| 12284 |
|
|
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
|
| 12285 |
|
|
overflow_tmp <= '0';
|
| 12286 |
|
|
END IF;
|
| 12287 |
|
|
dataout_temp <= dataout_tmp;
|
| 12288 |
|
|
END PROCESS;
|
| 12289 |
|
|
|
| 12290 |
|
|
PathDelay : block
|
| 12291 |
|
|
begin
|
| 12292 |
|
|
do1 : for i in dataout'range generate
|
| 12293 |
|
|
process(dataout_temp(i))
|
| 12294 |
|
|
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
|
| 12295 |
|
|
begin
|
| 12296 |
|
|
VitalPathDelay01 (
|
| 12297 |
|
|
OutSignal => dataout(i),
|
| 12298 |
|
|
OutSignalName => "dataout",
|
| 12299 |
|
|
OutTemp => dataout_temp(i),
|
| 12300 |
|
|
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
|
| 12301 |
|
|
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
|
| 12302 |
|
|
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
|
| 12303 |
|
|
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
|
| 12304 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 12305 |
|
|
Mode => DefGlitchMode,
|
| 12306 |
|
|
MsgOn => FALSE,
|
| 12307 |
|
|
XOn => TRUE
|
| 12308 |
|
|
);
|
| 12309 |
|
|
end process;
|
| 12310 |
|
|
end generate do1;
|
| 12311 |
|
|
|
| 12312 |
|
|
process(overflow_tmp)
|
| 12313 |
|
|
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
|
| 12314 |
|
|
begin
|
| 12315 |
|
|
VitalPathDelay01 (
|
| 12316 |
|
|
OutSignal => overflow,
|
| 12317 |
|
|
OutSignalName => "overflow",
|
| 12318 |
|
|
OutTemp => overflow_tmp,
|
| 12319 |
|
|
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
|
| 12320 |
|
|
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
|
| 12321 |
|
|
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
|
| 12322 |
|
|
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
|
| 12323 |
|
|
GlitchData => overflow_VitalGlitchData,
|
| 12324 |
|
|
Mode => DefGlitchMode,
|
| 12325 |
|
|
XOn => TRUE,
|
| 12326 |
|
|
MsgOn => TRUE
|
| 12327 |
|
|
);
|
| 12328 |
|
|
end process;
|
| 12329 |
|
|
end block;
|
| 12330 |
|
|
END arch;
|
| 12331 |
|
|
|
| 12332 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12333 |
|
|
-- Module Name: stratixiii_round_block --
|
| 12334 |
|
|
-- Description: Stratix III round block --
|
| 12335 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12336 |
|
|
LIBRARY IEEE;
|
| 12337 |
|
|
USE ieee.std_logic_1164.all;
|
| 12338 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 12339 |
|
|
use IEEE.std_logic_arith.all;
|
| 12340 |
|
|
use IEEE.VITAL_Timing.all;
|
| 12341 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 12342 |
|
|
use work.stratixiii_atom_pack.all;
|
| 12343 |
|
|
|
| 12344 |
|
|
|
| 12345 |
|
|
ENTITY stratixiii_round_block IS
|
| 12346 |
|
|
GENERIC (
|
| 12347 |
|
|
round_mode : string := "nearest_integer";
|
| 12348 |
|
|
round_width : integer := 15;
|
| 12349 |
|
|
operation_mode : string := "output_only"
|
| 12350 |
|
|
);
|
| 12351 |
|
|
PORT (
|
| 12352 |
|
|
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12353 |
|
|
round : IN std_logic := '0';
|
| 12354 |
|
|
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
|
| 12355 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0)
|
| 12356 |
|
|
);
|
| 12357 |
|
|
END stratixiii_round_block;
|
| 12358 |
|
|
|
| 12359 |
|
|
ARCHITECTURE arch OF stratixiii_round_block IS
|
| 12360 |
|
|
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12361 |
|
|
|
| 12362 |
|
|
BEGIN
|
| 12363 |
|
|
dataout <= out_tmp ;
|
| 12364 |
|
|
PROCESS(datain,round,datain_width)
|
| 12365 |
|
|
variable i : integer ;
|
| 12366 |
|
|
variable j : integer ;
|
| 12367 |
|
|
variable sign : std_logic ;
|
| 12368 |
|
|
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12369 |
|
|
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12370 |
|
|
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12371 |
|
|
BEGIN
|
| 12372 |
|
|
if(round = '0')then
|
| 12373 |
|
|
dataout_value := datain;
|
| 12374 |
|
|
else
|
| 12375 |
|
|
dataout_value := datain;
|
| 12376 |
|
|
j := 0;
|
| 12377 |
|
|
sign := '0';
|
| 12378 |
|
|
IF( conv_integer(datain_width) > round_width) THEN
|
| 12379 |
|
|
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
|
| 12380 |
|
|
result_tmp(j) := datain(i);
|
| 12381 |
|
|
j := j + 1;
|
| 12382 |
|
|
END LOOP;
|
| 12383 |
|
|
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
|
| 12384 |
|
|
sign := sign or datain(i);
|
| 12385 |
|
|
dataout_value(i) := 'X';
|
| 12386 |
|
|
END LOOP;
|
| 12387 |
|
|
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
|
| 12388 |
|
|
|
| 12389 |
|
|
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
|
| 12390 |
|
|
dataout_tmp := result_tmp;
|
| 12391 |
|
|
ELSE
|
| 12392 |
|
|
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
|
| 12393 |
|
|
dataout_tmp := result_tmp + '1';
|
| 12394 |
|
|
ELSE
|
| 12395 |
|
|
IF (round_mode = "nearest_even") THEN --unbiased rounding
|
| 12396 |
|
|
IF(result_tmp(0) = '1') THEN --check for odd integer
|
| 12397 |
|
|
dataout_tmp := result_tmp + '1' ;
|
| 12398 |
|
|
ELSE
|
| 12399 |
|
|
dataout_tmp := result_tmp;
|
| 12400 |
|
|
END IF;
|
| 12401 |
|
|
ELSE --biased rounding
|
| 12402 |
|
|
dataout_tmp := result_tmp + '1';
|
| 12403 |
|
|
END IF;
|
| 12404 |
|
|
END IF;
|
| 12405 |
|
|
END IF;
|
| 12406 |
|
|
j := conv_integer(datain_width) - round_width;
|
| 12407 |
|
|
FOR i IN 0 to (round_width -1)LOOP
|
| 12408 |
|
|
dataout_value(j) := dataout_tmp(i);
|
| 12409 |
|
|
j := j + 1;
|
| 12410 |
|
|
END LOOP;
|
| 12411 |
|
|
ELSE
|
| 12412 |
|
|
dataout_value := datain;
|
| 12413 |
|
|
END IF;
|
| 12414 |
|
|
end if;
|
| 12415 |
|
|
out_tmp <= dataout_value;
|
| 12416 |
|
|
END PROCESS;
|
| 12417 |
|
|
END arch;
|
| 12418 |
|
|
|
| 12419 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12420 |
|
|
-- Module Name: stratixiii_saturate_block --
|
| 12421 |
|
|
-- Description: Stratix III saturation block --
|
| 12422 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12423 |
|
|
LIBRARY IEEE;
|
| 12424 |
|
|
USE ieee.std_logic_1164.all;
|
| 12425 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 12426 |
|
|
use IEEE.std_logic_arith.all;
|
| 12427 |
|
|
use IEEE.VITAL_Timing.all;
|
| 12428 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 12429 |
|
|
use work.stratixiii_atom_pack.all;
|
| 12430 |
|
|
|
| 12431 |
|
|
|
| 12432 |
|
|
ENTITY stratixiii_saturate_block IS
|
| 12433 |
|
|
GENERIC (
|
| 12434 |
|
|
dataa_width : integer := 36;
|
| 12435 |
|
|
datab_width : integer := 36;
|
| 12436 |
|
|
saturate_width : integer := 15;
|
| 12437 |
|
|
round_width : integer := 15;
|
| 12438 |
|
|
saturate_mode : string := " asymmetric";
|
| 12439 |
|
|
operation_mode : string := "output_only"
|
| 12440 |
|
|
);
|
| 12441 |
|
|
PORT (
|
| 12442 |
|
|
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12443 |
|
|
saturate : IN std_logic := '0';
|
| 12444 |
|
|
round : IN std_logic := '0';
|
| 12445 |
|
|
signa : IN std_logic := '0';
|
| 12446 |
|
|
signb : IN std_logic := '0';
|
| 12447 |
|
|
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
|
| 12448 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
|
| 12449 |
|
|
saturation_overflow : OUT std_logic
|
| 12450 |
|
|
);
|
| 12451 |
|
|
END stratixiii_saturate_block;
|
| 12452 |
|
|
|
| 12453 |
|
|
ARCHITECTURE arch OF stratixiii_saturate_block IS
|
| 12454 |
|
|
constant accum_width : integer := dataa_width + 8;
|
| 12455 |
|
|
SIGNAL saturation_overflow_tmp : std_logic := '0';
|
| 12456 |
|
|
signal msb : std_logic := '0';
|
| 12457 |
|
|
signal sign : std_logic := '0';
|
| 12458 |
|
|
signal min : std_logic_vector(71 downto 0):=(others => '1');
|
| 12459 |
|
|
signal max : std_logic_vector(71 downto 0):=(others => '0');
|
| 12460 |
|
|
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
|
| 12461 |
|
|
SIGNAL i : integer;
|
| 12462 |
|
|
|
| 12463 |
|
|
BEGIN
|
| 12464 |
|
|
|
| 12465 |
|
|
sign <= signa OR signb ;
|
| 12466 |
|
|
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
|
| 12467 |
|
|
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
|
| 12468 |
|
|
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
|
| 12469 |
|
|
ELSE datain(dataa_width -1);
|
| 12470 |
|
|
dataout <= dataout_tmp ;
|
| 12471 |
|
|
saturation_overflow <= saturation_overflow_tmp ;
|
| 12472 |
|
|
|
| 12473 |
|
|
PROCESS(datain,datain_width,round,saturate,sign,msb)
|
| 12474 |
|
|
variable saturation_temp : std_logic := '0';
|
| 12475 |
|
|
variable sign_tmp : std_logic := '1';
|
| 12476 |
|
|
variable data_tmp : std_logic := '0';
|
| 12477 |
|
|
BEGIN
|
| 12478 |
|
|
IF (saturate = '0') THEN
|
| 12479 |
|
|
dataout_tmp <= datain;
|
| 12480 |
|
|
saturation_overflow_tmp <= '0';
|
| 12481 |
|
|
ELSE
|
| 12482 |
|
|
saturation_temp := '0';
|
| 12483 |
|
|
data_tmp := '0';
|
| 12484 |
|
|
sign_tmp := '1';
|
| 12485 |
|
|
IF (round = '1') THEN
|
| 12486 |
|
|
|
| 12487 |
|
|
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
|
| 12488 |
|
|
min(i) <= 'X';
|
| 12489 |
|
|
max(i) <= 'X';
|
| 12490 |
|
|
END LOOP;
|
| 12491 |
|
|
END IF;
|
| 12492 |
|
|
|
| 12493 |
|
|
IF (saturate_mode = "symmetric") THEN
|
| 12494 |
|
|
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
|
| 12495 |
|
|
min(i) <= 'X';
|
| 12496 |
|
|
IF (round = '1') THEN
|
| 12497 |
|
|
max(i) <= 'X';
|
| 12498 |
|
|
ELSE
|
| 12499 |
|
|
max(i) <= '1';
|
| 12500 |
|
|
END IF;
|
| 12501 |
|
|
END LOOP;
|
| 12502 |
|
|
|
| 12503 |
|
|
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
|
| 12504 |
|
|
data_tmp := data_tmp or datain(i);
|
| 12505 |
|
|
max(i) <= '1';
|
| 12506 |
|
|
min(i) <= '0';
|
| 12507 |
|
|
END LOOP;
|
| 12508 |
|
|
|
| 12509 |
|
|
min(conv_integer(datain_width) - round_width) <= '1';
|
| 12510 |
|
|
END IF;
|
| 12511 |
|
|
|
| 12512 |
|
|
IF (saturate_mode = "asymmetric") THEN
|
| 12513 |
|
|
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
|
| 12514 |
|
|
max(i) <= '1';
|
| 12515 |
|
|
min(i) <= '0';
|
| 12516 |
|
|
END LOOP;
|
| 12517 |
|
|
END IF;
|
| 12518 |
|
|
|
| 12519 |
|
|
if((saturate_width = 1))then
|
| 12520 |
|
|
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
|
| 12521 |
|
|
saturation_temp := '1';
|
| 12522 |
|
|
ELSE
|
| 12523 |
|
|
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
|
| 12524 |
|
|
END IF;
|
| 12525 |
|
|
else
|
| 12526 |
|
|
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
|
| 12527 |
|
|
sign_tmp := sign_tmp and datain(i);
|
| 12528 |
|
|
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
|
| 12529 |
|
|
saturation_temp := '1';
|
| 12530 |
|
|
end if;
|
| 12531 |
|
|
END LOOP;
|
| 12532 |
|
|
end if;
|
| 12533 |
|
|
|
| 12534 |
|
|
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
|
| 12535 |
|
|
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
|
| 12536 |
|
|
saturation_temp := '1';
|
| 12537 |
|
|
end if;
|
| 12538 |
|
|
|
| 12539 |
|
|
saturation_overflow_tmp <= saturation_temp;
|
| 12540 |
|
|
IF (saturation_temp = '1') THEN
|
| 12541 |
|
|
|
| 12542 |
|
|
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
|
| 12543 |
|
|
IF (msb = '1') THEN
|
| 12544 |
|
|
dataout_tmp <= min;
|
| 12545 |
|
|
ELSE
|
| 12546 |
|
|
dataout_tmp <= max;
|
| 12547 |
|
|
END IF;
|
| 12548 |
|
|
ELSE
|
| 12549 |
|
|
IF (sign = '1') THEN
|
| 12550 |
|
|
IF (msb = '1') THEN
|
| 12551 |
|
|
dataout_tmp <= min;
|
| 12552 |
|
|
ELSE
|
| 12553 |
|
|
dataout_tmp <= max;
|
| 12554 |
|
|
END IF;
|
| 12555 |
|
|
ELSE
|
| 12556 |
|
|
dataout_tmp <= (others => 'X');
|
| 12557 |
|
|
END IF;
|
| 12558 |
|
|
END IF;
|
| 12559 |
|
|
ELSE
|
| 12560 |
|
|
dataout_tmp <= datain;
|
| 12561 |
|
|
END IF;
|
| 12562 |
|
|
END IF;
|
| 12563 |
|
|
END PROCESS;
|
| 12564 |
|
|
|
| 12565 |
|
|
END arch;
|
| 12566 |
|
|
|
| 12567 |
|
|
|
| 12568 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12569 |
|
|
-- Module Name: stratixiii_round_saturate_block --
|
| 12570 |
|
|
-- Description: Stratix III round and saturation Unit. --
|
| 12571 |
|
|
-- This unit instantiated the following components. --
|
| 12572 |
|
|
-- 1.stratixiii_round_block. --
|
| 12573 |
|
|
-- 2.stratixiii_saturate_block. --
|
| 12574 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12575 |
|
|
|
| 12576 |
|
|
LIBRARY IEEE;
|
| 12577 |
|
|
USE ieee.std_logic_1164.all;
|
| 12578 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 12579 |
|
|
use IEEE.std_logic_arith.all;
|
| 12580 |
|
|
use IEEE.VITAL_Timing.all;
|
| 12581 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 12582 |
|
|
use work.stratixiii_atom_pack.all;
|
| 12583 |
|
|
|
| 12584 |
|
|
|
| 12585 |
|
|
ENTITY stratixiii_round_saturate_block IS
|
| 12586 |
|
|
GENERIC (
|
| 12587 |
|
|
dataa_width : integer := 36;
|
| 12588 |
|
|
datab_width : integer := 36;
|
| 12589 |
|
|
saturate_width : integer := 15;
|
| 12590 |
|
|
round_width : integer := 15;
|
| 12591 |
|
|
saturate_mode : string := " asymmetric";
|
| 12592 |
|
|
round_mode : string := "nearest_integer";
|
| 12593 |
|
|
operation_mode : string := "output_only" ;
|
| 12594 |
|
|
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 12595 |
|
|
tipd_round : VitalDelayType01 :=DefPropDelay01;
|
| 12596 |
|
|
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
|
| 12597 |
|
|
tipd_signa : VitalDelayType01 :=DefPropDelay01;
|
| 12598 |
|
|
tipd_signb : VitalDelayType01 :=DefPropDelay01;
|
| 12599 |
|
|
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
|
| 12600 |
|
|
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
|
| 12601 |
|
|
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
|
| 12602 |
|
|
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
|
| 12603 |
|
|
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
|
| 12604 |
|
|
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
|
| 12605 |
|
|
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
|
| 12606 |
|
|
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
|
| 12607 |
|
|
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
|
| 12608 |
|
|
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
|
| 12609 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 12610 |
|
|
MsgOn : Boolean := DefGlitchMsgOn
|
| 12611 |
|
|
);
|
| 12612 |
|
|
PORT (
|
| 12613 |
|
|
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12614 |
|
|
round : IN std_logic := '0';
|
| 12615 |
|
|
saturate : IN std_logic := '0';
|
| 12616 |
|
|
signa : IN std_logic := '0';
|
| 12617 |
|
|
signb : IN std_logic := '0';
|
| 12618 |
|
|
datain_width : IN std_logic_vector(7 DOWNTO 0);
|
| 12619 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12620 |
|
|
saturationoverflow : OUT std_logic
|
| 12621 |
|
|
);
|
| 12622 |
|
|
END stratixiii_round_saturate_block;
|
| 12623 |
|
|
|
| 12624 |
|
|
ARCHITECTURE arch OF stratixiii_round_saturate_block IS
|
| 12625 |
|
|
COMPONENT stratixiii_round_block
|
| 12626 |
|
|
GENERIC (
|
| 12627 |
|
|
round_mode : string := "nearest_integer";
|
| 12628 |
|
|
round_width : integer := 15;
|
| 12629 |
|
|
operation_mode : string := "output_only"
|
| 12630 |
|
|
);
|
| 12631 |
|
|
|
| 12632 |
|
|
PORT (
|
| 12633 |
|
|
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12634 |
|
|
round : IN std_logic := '0';
|
| 12635 |
|
|
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
|
| 12636 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0)
|
| 12637 |
|
|
);
|
| 12638 |
|
|
END COMPONENT;
|
| 12639 |
|
|
|
| 12640 |
|
|
COMPONENT stratixiii_saturate_block
|
| 12641 |
|
|
GENERIC (
|
| 12642 |
|
|
dataa_width : integer := 36;
|
| 12643 |
|
|
datab_width : integer := 36;
|
| 12644 |
|
|
saturate_mode : string := " asymmetric";
|
| 12645 |
|
|
saturate_width : integer := 15;
|
| 12646 |
|
|
round_width : integer := 15;
|
| 12647 |
|
|
operation_mode : string := "output_only"
|
| 12648 |
|
|
);
|
| 12649 |
|
|
PORT (
|
| 12650 |
|
|
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12651 |
|
|
saturate : IN std_logic := '0';
|
| 12652 |
|
|
round : IN std_logic := '0';
|
| 12653 |
|
|
signa : IN std_logic := '0';
|
| 12654 |
|
|
signb : IN std_logic := '0';
|
| 12655 |
|
|
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
|
| 12656 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12657 |
|
|
saturation_overflow : OUT std_logic
|
| 12658 |
|
|
);
|
| 12659 |
|
|
END COMPONENT;
|
| 12660 |
|
|
|
| 12661 |
|
|
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12662 |
|
|
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12663 |
|
|
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12664 |
|
|
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12665 |
|
|
SIGNAL signa_ipd : std_logic := '0';
|
| 12666 |
|
|
SIGNAL signb_ipd : std_logic := '0';
|
| 12667 |
|
|
SIGNAL round_ipd : std_logic := '0';
|
| 12668 |
|
|
SIGNAL saturate_ipd : std_logic := '0';
|
| 12669 |
|
|
SIGNAL saturationoverflow_tmp : std_logic := '0';
|
| 12670 |
|
|
|
| 12671 |
|
|
BEGIN
|
| 12672 |
|
|
WireDelay : block
|
| 12673 |
|
|
begin
|
| 12674 |
|
|
g1 :for i in datain'range generate
|
| 12675 |
|
|
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
|
| 12676 |
|
|
end generate;
|
| 12677 |
|
|
VitalWireDelay (signa_ipd, signa, tipd_signa);
|
| 12678 |
|
|
VitalWireDelay (signb_ipd, signb, tipd_signb);
|
| 12679 |
|
|
VitalWireDelay (round_ipd, round, tipd_round);
|
| 12680 |
|
|
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
|
| 12681 |
|
|
end block;
|
| 12682 |
|
|
|
| 12683 |
|
|
round_unit : stratixiii_round_block
|
| 12684 |
|
|
GENERIC MAP (
|
| 12685 |
|
|
operation_mode => operation_mode,
|
| 12686 |
|
|
round_width => round_width,
|
| 12687 |
|
|
round_mode => round_mode
|
| 12688 |
|
|
)
|
| 12689 |
|
|
PORT MAP (
|
| 12690 |
|
|
datain => datain_ipd,
|
| 12691 |
|
|
round => round_ipd,
|
| 12692 |
|
|
datain_width => datain_width,
|
| 12693 |
|
|
dataout => dataout_round
|
| 12694 |
|
|
);
|
| 12695 |
|
|
|
| 12696 |
|
|
saturate_unit : stratixiii_saturate_block
|
| 12697 |
|
|
GENERIC MAP (
|
| 12698 |
|
|
dataa_width => dataa_width,
|
| 12699 |
|
|
datab_width => datab_width,
|
| 12700 |
|
|
operation_mode => operation_mode,
|
| 12701 |
|
|
saturate_mode => saturate_mode,
|
| 12702 |
|
|
saturate_width =>saturate_width,
|
| 12703 |
|
|
round_width =>round_width
|
| 12704 |
|
|
)
|
| 12705 |
|
|
PORT MAP (
|
| 12706 |
|
|
datain => dataout_round,
|
| 12707 |
|
|
saturate => saturate_ipd,
|
| 12708 |
|
|
round => round_ipd,
|
| 12709 |
|
|
signa => signa_ipd,
|
| 12710 |
|
|
signb => signb_ipd,
|
| 12711 |
|
|
datain_width => datain_width,
|
| 12712 |
|
|
dataout => dataout_saturate,
|
| 12713 |
|
|
saturation_overflow => saturationoverflow_tmp
|
| 12714 |
|
|
);
|
| 12715 |
|
|
|
| 12716 |
|
|
PathDelay : block
|
| 12717 |
|
|
begin
|
| 12718 |
|
|
do1 : for i in dataout'range generate
|
| 12719 |
|
|
process(dataout_saturate(i))
|
| 12720 |
|
|
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
|
| 12721 |
|
|
begin
|
| 12722 |
|
|
VitalPathDelay01 (
|
| 12723 |
|
|
OutSignal => dataout(i),
|
| 12724 |
|
|
OutSignalName => "dataout",
|
| 12725 |
|
|
OutTemp => dataout_saturate(i),
|
| 12726 |
|
|
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
|
| 12727 |
|
|
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
|
| 12728 |
|
|
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
|
| 12729 |
|
|
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
|
| 12730 |
|
|
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
|
| 12731 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 12732 |
|
|
Mode => DefGlitchMode,
|
| 12733 |
|
|
MsgOn => FALSE,
|
| 12734 |
|
|
XOn => TRUE
|
| 12735 |
|
|
);
|
| 12736 |
|
|
end process;
|
| 12737 |
|
|
end generate do1;
|
| 12738 |
|
|
|
| 12739 |
|
|
process(saturationoverflow_tmp)
|
| 12740 |
|
|
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
|
| 12741 |
|
|
begin
|
| 12742 |
|
|
VitalPathDelay01 (
|
| 12743 |
|
|
OutSignal => saturationoverflow,
|
| 12744 |
|
|
OutSignalName => "saturationoverflow",
|
| 12745 |
|
|
OutTemp => saturationoverflow_tmp,
|
| 12746 |
|
|
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
|
| 12747 |
|
|
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
|
| 12748 |
|
|
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
|
| 12749 |
|
|
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
|
| 12750 |
|
|
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
|
| 12751 |
|
|
GlitchData => saturationoverflow_VitalGlitchData,
|
| 12752 |
|
|
Mode => DefGlitchMode,
|
| 12753 |
|
|
XOn => TRUE,
|
| 12754 |
|
|
MsgOn => TRUE
|
| 12755 |
|
|
);
|
| 12756 |
|
|
end process;
|
| 12757 |
|
|
end block;
|
| 12758 |
|
|
END arch;
|
| 12759 |
|
|
|
| 12760 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12761 |
|
|
-- Module Name: stratixiii_rotate_shift_block --
|
| 12762 |
|
|
-- Description: Stratix III roate and shift Unit. --
|
| 12763 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12764 |
|
|
|
| 12765 |
|
|
LIBRARY IEEE;
|
| 12766 |
|
|
USE ieee.std_logic_1164.all;
|
| 12767 |
|
|
USE ieee.numeric_std.all;
|
| 12768 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 12769 |
|
|
use IEEE.std_logic_arith.all;
|
| 12770 |
|
|
use IEEE.VITAL_Timing.all;
|
| 12771 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 12772 |
|
|
use work.stratixiii_atom_pack.all;
|
| 12773 |
|
|
|
| 12774 |
|
|
ENTITY stratixiii_rotate_shift_block IS
|
| 12775 |
|
|
GENERIC (
|
| 12776 |
|
|
dataa_width : integer := 32;
|
| 12777 |
|
|
datab_width : integer := 32;
|
| 12778 |
|
|
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 12779 |
|
|
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
|
| 12780 |
|
|
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
|
| 12781 |
|
|
tipd_signa : VitalDelayType01 :=DefPropDelay01;
|
| 12782 |
|
|
tipd_signb : VitalDelayType01 :=DefPropDelay01;
|
| 12783 |
|
|
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
|
| 12784 |
|
|
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
|
| 12785 |
|
|
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
|
| 12786 |
|
|
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
|
| 12787 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 12788 |
|
|
MsgOn : Boolean := DefGlitchMsgOn
|
| 12789 |
|
|
);
|
| 12790 |
|
|
PORT (
|
| 12791 |
|
|
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12792 |
|
|
rotate : IN std_logic := '0';
|
| 12793 |
|
|
shiftright : IN std_logic := '0';
|
| 12794 |
|
|
signa : IN std_logic := '0';
|
| 12795 |
|
|
signb : IN std_logic := '0';
|
| 12796 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0)
|
| 12797 |
|
|
);
|
| 12798 |
|
|
END stratixiii_rotate_shift_block;
|
| 12799 |
|
|
|
| 12800 |
|
|
ARCHITECTURE arch OF stratixiii_rotate_shift_block IS
|
| 12801 |
|
|
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
|
| 12802 |
|
|
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12803 |
|
|
SIGNAL signa_ipd : std_logic := '0';
|
| 12804 |
|
|
SIGNAL signb_ipd : std_logic := '0';
|
| 12805 |
|
|
SIGNAL rotate_ipd : std_logic := '0';
|
| 12806 |
|
|
SIGNAL shiftright_ipd : std_logic := '0';
|
| 12807 |
|
|
SIGNAL sign : std_logic;
|
| 12808 |
|
|
|
| 12809 |
|
|
BEGIN
|
| 12810 |
|
|
WireDelay : block
|
| 12811 |
|
|
begin
|
| 12812 |
|
|
g1 :for i in datain'range generate
|
| 12813 |
|
|
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
|
| 12814 |
|
|
end generate;
|
| 12815 |
|
|
VitalWireDelay (signa_ipd, signa, tipd_signa);
|
| 12816 |
|
|
VitalWireDelay (signb_ipd, signa, tipd_signa);
|
| 12817 |
|
|
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
|
| 12818 |
|
|
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
|
| 12819 |
|
|
end block;
|
| 12820 |
|
|
|
| 12821 |
|
|
PROCESS
|
| 12822 |
|
|
BEGIN
|
| 12823 |
|
|
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT OR signa_ipd'EVENT OR signb_ipd'EVENT;
|
| 12824 |
|
|
sign <= signa_ipd xor signb_ipd;
|
| 12825 |
|
|
dataout_tmp <= datain;
|
| 12826 |
|
|
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
|
| 12827 |
|
|
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
|
| 12828 |
|
|
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
|
| 12829 |
|
|
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
|
| 12830 |
|
|
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0') AND (signa_ipd = '0')) THEN
|
| 12831 |
|
|
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
|
| 12832 |
|
|
ELSE
|
| 12833 |
|
|
dataout_tmp <= datain_ipd;
|
| 12834 |
|
|
END IF;
|
| 12835 |
|
|
END PROCESS;
|
| 12836 |
|
|
|
| 12837 |
|
|
PathDelay : block
|
| 12838 |
|
|
begin
|
| 12839 |
|
|
do1 : for i in dataout'range generate
|
| 12840 |
|
|
process(dataout_tmp(i))
|
| 12841 |
|
|
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
|
| 12842 |
|
|
begin
|
| 12843 |
|
|
VitalPathDelay01 (
|
| 12844 |
|
|
OutSignal => dataout(i),
|
| 12845 |
|
|
OutSignalName => "dataout",
|
| 12846 |
|
|
OutTemp => dataout_tmp(i),
|
| 12847 |
|
|
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
|
| 12848 |
|
|
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
|
| 12849 |
|
|
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
|
| 12850 |
|
|
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
|
| 12851 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 12852 |
|
|
Mode => DefGlitchMode,
|
| 12853 |
|
|
MsgOn => FALSE,
|
| 12854 |
|
|
XOn => TRUE
|
| 12855 |
|
|
);
|
| 12856 |
|
|
end process;
|
| 12857 |
|
|
end generate do1;
|
| 12858 |
|
|
end block;
|
| 12859 |
|
|
|
| 12860 |
|
|
END arch;
|
| 12861 |
|
|
|
| 12862 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12863 |
|
|
-- Module Name: stratixiii_carry_chain_adder --
|
| 12864 |
|
|
-- Description: Stratix III carry Chain Adder --
|
| 12865 |
|
|
--------------------------------------------------------------------------------------------------
|
| 12866 |
|
|
|
| 12867 |
|
|
LIBRARY IEEE;
|
| 12868 |
|
|
USE ieee.std_logic_1164.all;
|
| 12869 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 12870 |
|
|
use IEEE.std_logic_arith.all;
|
| 12871 |
|
|
use IEEE.VITAL_Timing.all;
|
| 12872 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 12873 |
|
|
use work.stratixiii_atom_pack.all;
|
| 12874 |
|
|
|
| 12875 |
|
|
ENTITY stratixiii_carry_chain_adder IS
|
| 12876 |
|
|
GENERIC(
|
| 12877 |
|
|
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 12878 |
|
|
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
|
| 12879 |
|
|
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
|
| 12880 |
|
|
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
|
| 12881 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 12882 |
|
|
MsgOn : Boolean := DefGlitchMsgOn
|
| 12883 |
|
|
);
|
| 12884 |
|
|
PORT (
|
| 12885 |
|
|
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12886 |
|
|
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12887 |
|
|
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
|
| 12888 |
|
|
);
|
| 12889 |
|
|
END stratixiii_carry_chain_adder;
|
| 12890 |
|
|
|
| 12891 |
|
|
ARCHITECTURE arch OF stratixiii_carry_chain_adder IS
|
| 12892 |
|
|
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12893 |
|
|
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12894 |
|
|
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 12895 |
|
|
BEGIN
|
| 12896 |
|
|
WireDelay : block
|
| 12897 |
|
|
begin
|
| 12898 |
|
|
g1 :for i in dataa'range generate
|
| 12899 |
|
|
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
|
| 12900 |
|
|
end generate;
|
| 12901 |
|
|
g2 :for i in datab'range generate
|
| 12902 |
|
|
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
|
| 12903 |
|
|
end generate;
|
| 12904 |
|
|
end block;
|
| 12905 |
|
|
|
| 12906 |
|
|
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
|
| 12907 |
|
|
|
| 12908 |
|
|
PathDelay : block
|
| 12909 |
|
|
begin
|
| 12910 |
|
|
do1 : for i in dataout'range generate
|
| 12911 |
|
|
process(dataout_tmp(i))
|
| 12912 |
|
|
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
|
| 12913 |
|
|
begin
|
| 12914 |
|
|
VitalPathDelay01 (
|
| 12915 |
|
|
OutSignal => dataout(i),
|
| 12916 |
|
|
OutSignalName => "dataout",
|
| 12917 |
|
|
OutTemp => dataout_tmp(i),
|
| 12918 |
|
|
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
|
| 12919 |
|
|
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
|
| 12920 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 12921 |
|
|
Mode => DefGlitchMode,
|
| 12922 |
|
|
MsgOn => FALSE,
|
| 12923 |
|
|
XOn => TRUE
|
| 12924 |
|
|
);
|
| 12925 |
|
|
end process;
|
| 12926 |
|
|
end generate do1;
|
| 12927 |
|
|
end block;
|
| 12928 |
|
|
END arch;
|
| 12929 |
|
|
|
| 12930 |
|
|
----------------------------------------------------------------------------------
|
| 12931 |
|
|
-- Module Name: stratixiii_mac_out_atom --
|
| 12932 |
|
|
-- Description: Simulation model for stratixiii mac out atom --
|
| 12933 |
|
|
-- This model instantiates the following components --
|
| 12934 |
|
|
-- 1.stratixiii_mac_bit_register --
|
| 12935 |
|
|
-- 2.stratixiii_mac_register --
|
| 12936 |
|
|
-- 3.stratixiii_fsa_isse --
|
| 12937 |
|
|
-- 4.stratixiii_first_stage_add_sub --
|
| 12938 |
|
|
-- 5.stratixiii_second_stage_add_accum --
|
| 12939 |
|
|
-- 6.stratixiii_round_saturate_block --
|
| 12940 |
|
|
-- 7.stratixiii_rotate_shift_block --
|
| 12941 |
|
|
-- 8.stratixiii_carry_chain_adder --
|
| 12942 |
|
|
----------------------------------------------------------------------------------
|
| 12943 |
|
|
|
| 12944 |
|
|
LIBRARY IEEE;
|
| 12945 |
|
|
USE ieee.std_logic_1164.all;
|
| 12946 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 12947 |
|
|
use IEEE.std_logic_arith.all;
|
| 12948 |
|
|
use IEEE.VITAL_Timing.all;
|
| 12949 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 12950 |
|
|
|
| 12951 |
|
|
ENTITY stratixiii_mac_out IS
|
| 12952 |
|
|
GENERIC (
|
| 12953 |
|
|
operation_mode : string := "output_only";
|
| 12954 |
|
|
dataa_width : integer := 1;
|
| 12955 |
|
|
datab_width : integer := 1;
|
| 12956 |
|
|
datac_width : integer := 1;
|
| 12957 |
|
|
datad_width : integer := 1;
|
| 12958 |
|
|
chainin_width : integer := 1;
|
| 12959 |
|
|
round_width : integer := 15;
|
| 12960 |
|
|
round_chain_out_width : integer := 15;
|
| 12961 |
|
|
saturate_width : integer := 15;
|
| 12962 |
|
|
saturate_chain_out_width : integer := 15;
|
| 12963 |
|
|
first_adder0_clock : string := "none";
|
| 12964 |
|
|
first_adder0_clear : string := "none";
|
| 12965 |
|
|
first_adder1_clock : string := "none";
|
| 12966 |
|
|
first_adder1_clear : string := "none";
|
| 12967 |
|
|
second_adder_clock : string := "none";
|
| 12968 |
|
|
second_adder_clear : string := "none";
|
| 12969 |
|
|
output_clock : string := "none";
|
| 12970 |
|
|
output_clear : string := "none";
|
| 12971 |
|
|
signa_clock : string := "none";
|
| 12972 |
|
|
signa_clear : string := "none";
|
| 12973 |
|
|
signb_clock : string := "none";
|
| 12974 |
|
|
signb_clear : string := "none";
|
| 12975 |
|
|
round_clock : string := "none";
|
| 12976 |
|
|
round_clear : string := "none";
|
| 12977 |
|
|
roundchainout_clock : string := "none";
|
| 12978 |
|
|
roundchainout_clear : string := "none";
|
| 12979 |
|
|
saturate_clock : string := "none";
|
| 12980 |
|
|
saturate_clear : string := "none";
|
| 12981 |
|
|
saturatechainout_clock : string := "none";
|
| 12982 |
|
|
saturatechainout_clear : string := "none";
|
| 12983 |
|
|
zeroacc_clock : string := "none";
|
| 12984 |
|
|
zeroacc_clear : string := "none";
|
| 12985 |
|
|
zeroloopback_clock : string := "none";
|
| 12986 |
|
|
zeroloopback_clear : string := "none";
|
| 12987 |
|
|
rotate_clock : string := "none";
|
| 12988 |
|
|
rotate_clear : string := "none";
|
| 12989 |
|
|
shiftright_clock : string := "none";
|
| 12990 |
|
|
shiftright_clear : string := "none";
|
| 12991 |
|
|
signa_pipeline_clock : string := "none";
|
| 12992 |
|
|
signa_pipeline_clear : string := "none";
|
| 12993 |
|
|
signb_pipeline_clock : string := "none";
|
| 12994 |
|
|
signb_pipeline_clear : string := "none";
|
| 12995 |
|
|
round_pipeline_clock : string := "none";
|
| 12996 |
|
|
round_pipeline_clear : string := "none";
|
| 12997 |
|
|
roundchainout_pipeline_clock : string := "none";
|
| 12998 |
|
|
roundchainout_pipeline_clear : string := "none";
|
| 12999 |
|
|
saturate_pipeline_clock : string := "none";
|
| 13000 |
|
|
saturate_pipeline_clear : string := "none";
|
| 13001 |
|
|
saturatechainout_pipeline_clock: string := "none";
|
| 13002 |
|
|
saturatechainout_pipeline_clear: string := "none";
|
| 13003 |
|
|
zeroacc_pipeline_clock : string := "none";
|
| 13004 |
|
|
zeroacc_pipeline_clear : string := "none";
|
| 13005 |
|
|
zeroloopback_pipeline_clock : string := "none";
|
| 13006 |
|
|
zeroloopback_pipeline_clear : string := "none";
|
| 13007 |
|
|
rotate_pipeline_clock : string := "none";
|
| 13008 |
|
|
rotate_pipeline_clear : string := "none";
|
| 13009 |
|
|
shiftright_pipeline_clock : string := "none";
|
| 13010 |
|
|
shiftright_pipeline_clear : string := "none";
|
| 13011 |
|
|
roundchainout_output_clock : string := "none";
|
| 13012 |
|
|
roundchainout_output_clear : string := "none";
|
| 13013 |
|
|
saturatechainout_output_clock : string := "none";
|
| 13014 |
|
|
saturatechainout_output_clear : string := "none";
|
| 13015 |
|
|
zerochainout_output_clock : string := "none";
|
| 13016 |
|
|
zerochainout_output_clear : string := "none";
|
| 13017 |
|
|
zeroloopback_output_clock : string := "none";
|
| 13018 |
|
|
zeroloopback_output_clear : string := "none";
|
| 13019 |
|
|
rotate_output_clock : string := "none";
|
| 13020 |
|
|
rotate_output_clear : string := "none";
|
| 13021 |
|
|
shiftright_output_clock : string := "none";
|
| 13022 |
|
|
shiftright_output_clear : string := "none";
|
| 13023 |
|
|
first_adder0_mode : string := "add";
|
| 13024 |
|
|
first_adder1_mode : string := "add";
|
| 13025 |
|
|
acc_adder_operation : string := "add";
|
| 13026 |
|
|
round_mode : string := "nearest_integer";
|
| 13027 |
|
|
round_chain_out_mode : string := "nearest_integer";
|
| 13028 |
|
|
saturate_mode : string := "asymmetric";
|
| 13029 |
|
|
saturate_chain_out_mode : string := "asymmetric";
|
| 13030 |
|
|
lpm_type : string := "stratixiii_mac_out";
|
| 13031 |
|
|
dataout_width : integer:=72
|
| 13032 |
|
|
);
|
| 13033 |
|
|
PORT (
|
| 13034 |
|
|
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
|
| 13035 |
|
|
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
|
| 13036 |
|
|
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
|
| 13037 |
|
|
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
|
| 13038 |
|
|
signa : IN std_logic := '1';
|
| 13039 |
|
|
signb : IN std_logic := '1';
|
| 13040 |
|
|
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
|
| 13041 |
|
|
round : IN std_logic := '0';
|
| 13042 |
|
|
saturate : IN std_logic := '0';
|
| 13043 |
|
|
zeroacc : IN std_logic := '0';
|
| 13044 |
|
|
roundchainout : IN std_logic := '0';
|
| 13045 |
|
|
saturatechainout : IN std_logic := '0';
|
| 13046 |
|
|
zerochainout : IN std_logic := '0';
|
| 13047 |
|
|
zeroloopback : IN std_logic := '0';
|
| 13048 |
|
|
rotate : IN std_logic := '0';
|
| 13049 |
|
|
shiftright : IN std_logic := '0';
|
| 13050 |
|
|
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13051 |
|
|
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
|
| 13052 |
|
|
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13053 |
|
|
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
|
| 13054 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13055 |
|
|
overflow : OUT std_logic := '0';
|
| 13056 |
|
|
saturatechainoutoverflow: OUT std_logic := '0';
|
| 13057 |
|
|
dftout : OUT std_logic := '0';
|
| 13058 |
|
|
devpor : IN std_logic := '1';
|
| 13059 |
|
|
devclrn : IN std_logic := '1'
|
| 13060 |
|
|
);
|
| 13061 |
|
|
END stratixiii_mac_out;
|
| 13062 |
|
|
|
| 13063 |
|
|
ARCHITECTURE arch OF stratixiii_mac_out IS
|
| 13064 |
|
|
COMPONENT stratixiii_mac_bit_register
|
| 13065 |
|
|
PORT (
|
| 13066 |
|
|
datain : IN std_logic := '0';
|
| 13067 |
|
|
clk : IN std_logic := '0';
|
| 13068 |
|
|
aclr : IN std_logic := '0';
|
| 13069 |
|
|
sload : IN std_logic := '0';
|
| 13070 |
|
|
bypass_register : IN std_logic := '0';
|
| 13071 |
|
|
dataout : OUT std_logic
|
| 13072 |
|
|
);
|
| 13073 |
|
|
END COMPONENT;
|
| 13074 |
|
|
|
| 13075 |
|
|
COMPONENT stratixiii_mac_register
|
| 13076 |
|
|
GENERIC (
|
| 13077 |
|
|
data_width : integer := 18
|
| 13078 |
|
|
);
|
| 13079 |
|
|
PORT (
|
| 13080 |
|
|
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
|
| 13081 |
|
|
clk : IN std_logic := '0';
|
| 13082 |
|
|
aclr : IN std_logic := '0';
|
| 13083 |
|
|
sload : IN std_logic := '0';
|
| 13084 |
|
|
bypass_register : IN std_logic := '0';
|
| 13085 |
|
|
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
|
| 13086 |
|
|
);
|
| 13087 |
|
|
END COMPONENT;
|
| 13088 |
|
|
|
| 13089 |
|
|
COMPONENT stratixiii_fsa_isse
|
| 13090 |
|
|
GENERIC (
|
| 13091 |
|
|
datab_width : integer := 36;
|
| 13092 |
|
|
dataa_width : integer := 36;
|
| 13093 |
|
|
chainin_width : integer := 44;
|
| 13094 |
|
|
operation_mode : string := "output_only";
|
| 13095 |
|
|
datad_width : integer := 36;
|
| 13096 |
|
|
datac_width : integer := 36
|
| 13097 |
|
|
);
|
| 13098 |
|
|
PORT (
|
| 13099 |
|
|
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
|
| 13100 |
|
|
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
|
| 13101 |
|
|
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
|
| 13102 |
|
|
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
|
| 13103 |
|
|
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
|
| 13104 |
|
|
signa : IN std_logic := '0';
|
| 13105 |
|
|
signb : IN std_logic := '0';
|
| 13106 |
|
|
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13107 |
|
|
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13108 |
|
|
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13109 |
|
|
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13110 |
|
|
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13111 |
|
|
operation : OUT std_logic_vector(3 DOWNTO 0)
|
| 13112 |
|
|
);
|
| 13113 |
|
|
END COMPONENT;
|
| 13114 |
|
|
|
| 13115 |
|
|
COMPONENT stratixiii_first_stage_add_sub
|
| 13116 |
|
|
GENERIC (
|
| 13117 |
|
|
dataa_width : integer := 36;
|
| 13118 |
|
|
datab_width : integer := 36;
|
| 13119 |
|
|
fsa_mode : string := "add"
|
| 13120 |
|
|
);
|
| 13121 |
|
|
PORT (
|
| 13122 |
|
|
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13123 |
|
|
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13124 |
|
|
sign : IN std_logic := '0';
|
| 13125 |
|
|
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13126 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0)
|
| 13127 |
|
|
);
|
| 13128 |
|
|
END COMPONENT;
|
| 13129 |
|
|
|
| 13130 |
|
|
COMPONENT stratixiii_second_stage_add_accum
|
| 13131 |
|
|
GENERIC (
|
| 13132 |
|
|
dataa_width : integer := 36;
|
| 13133 |
|
|
datab_width : integer := 36;
|
| 13134 |
|
|
ssa_mode : string := "add"
|
| 13135 |
|
|
);
|
| 13136 |
|
|
PORT (
|
| 13137 |
|
|
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13138 |
|
|
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13139 |
|
|
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13140 |
|
|
sign : IN std_logic := '0';
|
| 13141 |
|
|
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13142 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13143 |
|
|
overflow : OUT std_logic
|
| 13144 |
|
|
);
|
| 13145 |
|
|
END COMPONENT;
|
| 13146 |
|
|
|
| 13147 |
|
|
COMPONENT stratixiii_round_saturate_block
|
| 13148 |
|
|
GENERIC (
|
| 13149 |
|
|
datab_width : integer := 36;
|
| 13150 |
|
|
dataa_width : integer := 36;
|
| 13151 |
|
|
saturate_mode : string := " asymmetric";
|
| 13152 |
|
|
saturate_width : integer := 15;
|
| 13153 |
|
|
round_width : integer := 15;
|
| 13154 |
|
|
operation_mode : string := "output_only";
|
| 13155 |
|
|
round_mode : string := "nearest_integer"
|
| 13156 |
|
|
);
|
| 13157 |
|
|
PORT (
|
| 13158 |
|
|
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13159 |
|
|
round : IN std_logic := '0';
|
| 13160 |
|
|
saturate : IN std_logic := '0';
|
| 13161 |
|
|
signa : IN std_logic := '0';
|
| 13162 |
|
|
signb : IN std_logic := '0';
|
| 13163 |
|
|
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
|
| 13164 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13165 |
|
|
saturationoverflow : OUT std_logic
|
| 13166 |
|
|
);
|
| 13167 |
|
|
END COMPONENT;
|
| 13168 |
|
|
|
| 13169 |
|
|
COMPONENT stratixiii_rotate_shift_block
|
| 13170 |
|
|
GENERIC (
|
| 13171 |
|
|
datab_width : integer := 32;
|
| 13172 |
|
|
dataa_width : integer := 32
|
| 13173 |
|
|
);
|
| 13174 |
|
|
PORT (
|
| 13175 |
|
|
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13176 |
|
|
rotate : IN std_logic := '0';
|
| 13177 |
|
|
shiftright : IN std_logic := '0';
|
| 13178 |
|
|
signa : IN std_logic := '0';
|
| 13179 |
|
|
signb : IN std_logic := '0';
|
| 13180 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0)
|
| 13181 |
|
|
);
|
| 13182 |
|
|
END COMPONENT;
|
| 13183 |
|
|
|
| 13184 |
|
|
COMPONENT stratixiii_carry_chain_adder
|
| 13185 |
|
|
PORT (
|
| 13186 |
|
|
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13187 |
|
|
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13188 |
|
|
dataout : OUT std_logic_vector(71 DOWNTO 0)
|
| 13189 |
|
|
);
|
| 13190 |
|
|
END COMPONENT;
|
| 13191 |
|
|
|
| 13192 |
|
|
--signals for zeroloopback input register
|
| 13193 |
|
|
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13194 |
|
|
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13195 |
|
|
SIGNAL zeroloopback_clk_ir : std_logic := '0';
|
| 13196 |
|
|
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
|
| 13197 |
|
|
SIGNAL zeroloopback_sload_ir : std_logic := '0';
|
| 13198 |
|
|
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
|
| 13199 |
|
|
SIGNAL zeroloopback_in_reg : std_logic := '0';
|
| 13200 |
|
|
--signals for zeroacc input register
|
| 13201 |
|
|
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13202 |
|
|
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13203 |
|
|
SIGNAL zeroacc_clk_ir : std_logic := '0';
|
| 13204 |
|
|
SIGNAL zeroacc_aclr_ir : std_logic := '0';
|
| 13205 |
|
|
SIGNAL zeroacc_sload_ir : std_logic := '0';
|
| 13206 |
|
|
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
|
| 13207 |
|
|
SIGNAL zeroacc_in_reg : std_logic := '0';
|
| 13208 |
|
|
--Signals for signa input register
|
| 13209 |
|
|
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13210 |
|
|
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13211 |
|
|
SIGNAL signa_clk_ir : std_logic := '0';
|
| 13212 |
|
|
SIGNAL signa_aclr_ir : std_logic := '0';
|
| 13213 |
|
|
SIGNAL signa_sload_ir : std_logic := '0';
|
| 13214 |
|
|
SIGNAL signa_bypass_register_ir : std_logic := '0';
|
| 13215 |
|
|
SIGNAL signa_in_reg : std_logic := '0';
|
| 13216 |
|
|
--signals for signb input register
|
| 13217 |
|
|
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13218 |
|
|
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13219 |
|
|
SIGNAL signb_clk_ir : std_logic := '0';
|
| 13220 |
|
|
SIGNAL signb_aclr_ir : std_logic := '0';
|
| 13221 |
|
|
SIGNAL signb_sload_ir : std_logic := '0';
|
| 13222 |
|
|
SIGNAL signb_bypass_register_ir : std_logic := '0';
|
| 13223 |
|
|
SIGNAL signb_in_reg : std_logic := '0';
|
| 13224 |
|
|
--signals for rotate input register
|
| 13225 |
|
|
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13226 |
|
|
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13227 |
|
|
SIGNAL rotate_clk_ir : std_logic := '0';
|
| 13228 |
|
|
SIGNAL rotate_aclr_ir : std_logic := '0';
|
| 13229 |
|
|
SIGNAL rotate_sload_ir : std_logic := '0';
|
| 13230 |
|
|
SIGNAL rotate_bypass_register_ir: std_logic := '0';
|
| 13231 |
|
|
SIGNAL rotate_in_reg : std_logic := '0';
|
| 13232 |
|
|
--signals for shiftright input register
|
| 13233 |
|
|
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13234 |
|
|
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13235 |
|
|
SIGNAL shiftright_clk_ir : std_logic := '0';
|
| 13236 |
|
|
SIGNAL shiftright_aclr_ir : std_logic := '0';
|
| 13237 |
|
|
SIGNAL shiftright_sload_ir : std_logic := '0';
|
| 13238 |
|
|
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
|
| 13239 |
|
|
SIGNAL shiftright_in_reg : std_logic := '0';
|
| 13240 |
|
|
--signals for round input register
|
| 13241 |
|
|
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13242 |
|
|
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13243 |
|
|
SIGNAL round_clk_ir : std_logic := '0';
|
| 13244 |
|
|
SIGNAL round_aclr_ir : std_logic := '0';
|
| 13245 |
|
|
SIGNAL round_sload_ir : std_logic := '0';
|
| 13246 |
|
|
SIGNAL round_bypass_register_ir : std_logic := '0';
|
| 13247 |
|
|
SIGNAL round_in_reg : std_logic := '0';
|
| 13248 |
|
|
--signals for saturate input register
|
| 13249 |
|
|
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13250 |
|
|
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13251 |
|
|
SIGNAL saturate_clk_ir : std_logic := '0';
|
| 13252 |
|
|
SIGNAL saturate_aclr_ir : std_logic := '0';
|
| 13253 |
|
|
SIGNAL saturate_sload_ir : std_logic := '0';
|
| 13254 |
|
|
SIGNAL saturate_bypass_register_ir : std_logic := '0';
|
| 13255 |
|
|
SIGNAL saturate_in_reg : std_logic := '0';
|
| 13256 |
|
|
--signals for roundchainout input register
|
| 13257 |
|
|
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13258 |
|
|
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13259 |
|
|
SIGNAL roundchainout_clk_ir : std_logic := '0';
|
| 13260 |
|
|
SIGNAL roundchainout_aclr_ir : std_logic := '0';
|
| 13261 |
|
|
SIGNAL roundchainout_sload_ir : std_logic := '0';
|
| 13262 |
|
|
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
|
| 13263 |
|
|
SIGNAL roundchainout_in_reg : std_logic := '0';
|
| 13264 |
|
|
--signals for saturatechainout input register
|
| 13265 |
|
|
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13266 |
|
|
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13267 |
|
|
SIGNAL saturatechainout_clk_ir : std_logic := '0';
|
| 13268 |
|
|
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
|
| 13269 |
|
|
SIGNAL saturatechainout_sload_ir: std_logic := '0';
|
| 13270 |
|
|
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
|
| 13271 |
|
|
SIGNAL saturatechainout_in_reg : std_logic := '0';
|
| 13272 |
|
|
--signals for fsa_input_interface
|
| 13273 |
|
|
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13274 |
|
|
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13275 |
|
|
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13276 |
|
|
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13277 |
|
|
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13278 |
|
|
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13279 |
|
|
--Signals for First Stage Adder units
|
| 13280 |
|
|
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13281 |
|
|
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13282 |
|
|
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13283 |
|
|
SIGNAL overflow_fsa0 : std_logic := '0';
|
| 13284 |
|
|
SIGNAL overflow_fsa1 : std_logic := '0';
|
| 13285 |
|
|
--signals for zeroloopback pipeline register
|
| 13286 |
|
|
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13287 |
|
|
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13288 |
|
|
SIGNAL zeroloopback_clk_pip : std_logic := '0';
|
| 13289 |
|
|
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
|
| 13290 |
|
|
SIGNAL zeroloopback_sload_pip : std_logic := '0';
|
| 13291 |
|
|
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
|
| 13292 |
|
|
SIGNAL zeroloopback_pip_reg : std_logic := '0';
|
| 13293 |
|
|
--signals for zeroacc pipeline register
|
| 13294 |
|
|
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13295 |
|
|
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13296 |
|
|
SIGNAL zeroacc_clk_pip : std_logic := '0';
|
| 13297 |
|
|
SIGNAL zeroacc_aclr_pip : std_logic := '0';
|
| 13298 |
|
|
SIGNAL zeroacc_sload_pip : std_logic := '0';
|
| 13299 |
|
|
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
|
| 13300 |
|
|
SIGNAL zeroacc_pip_reg : std_logic := '0';
|
| 13301 |
|
|
--Signals for signa pipeline register
|
| 13302 |
|
|
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13303 |
|
|
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13304 |
|
|
SIGNAL signa_clk_pip : std_logic := '0';
|
| 13305 |
|
|
SIGNAL signa_aclr_pip : std_logic := '0';
|
| 13306 |
|
|
SIGNAL signa_sload_pip : std_logic := '0';
|
| 13307 |
|
|
SIGNAL signa_bypass_register_pip: std_logic := '0';
|
| 13308 |
|
|
SIGNAL signa_pip_reg : std_logic := '0';
|
| 13309 |
|
|
--signals for signb pipeline register
|
| 13310 |
|
|
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13311 |
|
|
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13312 |
|
|
SIGNAL signb_clk_pip : std_logic := '0';
|
| 13313 |
|
|
SIGNAL signb_aclr_pip : std_logic := '0';
|
| 13314 |
|
|
SIGNAL signb_sload_pip : std_logic := '0';
|
| 13315 |
|
|
SIGNAL signb_bypass_register_pip: std_logic := '0';
|
| 13316 |
|
|
SIGNAL signb_pip_reg : std_logic := '0';
|
| 13317 |
|
|
--signals for rotate pipeline register
|
| 13318 |
|
|
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13319 |
|
|
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13320 |
|
|
SIGNAL rotate_clk_pip : std_logic := '0';
|
| 13321 |
|
|
SIGNAL rotate_aclr_pip : std_logic := '0';
|
| 13322 |
|
|
SIGNAL rotate_sload_pip : std_logic := '0';
|
| 13323 |
|
|
SIGNAL rotate_bypass_register_pip : std_logic := '0';
|
| 13324 |
|
|
SIGNAL rotate_pip_reg : std_logic := '0';
|
| 13325 |
|
|
--signals for shiftright pipeline register
|
| 13326 |
|
|
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13327 |
|
|
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13328 |
|
|
SIGNAL shiftright_clk_pip : std_logic := '0';
|
| 13329 |
|
|
SIGNAL shiftright_aclr_pip : std_logic := '0';
|
| 13330 |
|
|
SIGNAL shiftright_sload_pip : std_logic := '0';
|
| 13331 |
|
|
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
|
| 13332 |
|
|
SIGNAL shiftright_pip_reg : std_logic := '0';
|
| 13333 |
|
|
--signals for round pipeline register
|
| 13334 |
|
|
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13335 |
|
|
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13336 |
|
|
SIGNAL round_clk_pip : std_logic := '0';
|
| 13337 |
|
|
SIGNAL round_aclr_pip : std_logic := '0';
|
| 13338 |
|
|
SIGNAL round_sload_pip : std_logic := '0';
|
| 13339 |
|
|
SIGNAL round_bypass_register_pip: std_logic := '0';
|
| 13340 |
|
|
SIGNAL round_pip_reg : std_logic := '0';
|
| 13341 |
|
|
--signals for saturate pipeline register
|
| 13342 |
|
|
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13343 |
|
|
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13344 |
|
|
SIGNAL saturate_clk_pip : std_logic := '0';
|
| 13345 |
|
|
SIGNAL saturate_aclr_pip : std_logic := '0';
|
| 13346 |
|
|
SIGNAL saturate_sload_pip : std_logic := '0';
|
| 13347 |
|
|
SIGNAL saturate_bypass_register_pip : std_logic := '0';
|
| 13348 |
|
|
SIGNAL saturate_pip_reg : std_logic := '0';
|
| 13349 |
|
|
--signals for roundchainout pipeline register
|
| 13350 |
|
|
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13351 |
|
|
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13352 |
|
|
SIGNAL roundchainout_clk_pip : std_logic := '0';
|
| 13353 |
|
|
SIGNAL roundchainout_aclr_pip : std_logic := '0';
|
| 13354 |
|
|
SIGNAL roundchainout_sload_pip : std_logic := '0';
|
| 13355 |
|
|
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
|
| 13356 |
|
|
SIGNAL roundchainout_pip_reg : std_logic := '0';
|
| 13357 |
|
|
--signals for saturatechainout pipeline register
|
| 13358 |
|
|
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13359 |
|
|
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13360 |
|
|
SIGNAL saturatechainout_clk_pip : std_logic := '0';
|
| 13361 |
|
|
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
|
| 13362 |
|
|
SIGNAL saturatechainout_sload_pip : std_logic := '0';
|
| 13363 |
|
|
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
|
| 13364 |
|
|
SIGNAL saturatechainout_pip_reg : std_logic := '0';
|
| 13365 |
|
|
--signals for fsa0 pipeline register
|
| 13366 |
|
|
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13367 |
|
|
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13368 |
|
|
SIGNAL fsa0_clk_pip : std_logic := '0';
|
| 13369 |
|
|
SIGNAL fsa0_aclr_pip : std_logic := '0';
|
| 13370 |
|
|
SIGNAL fsa0_sload_pip : std_logic := '0';
|
| 13371 |
|
|
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
|
| 13372 |
|
|
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13373 |
|
|
--signals for fsa1 pipeline register
|
| 13374 |
|
|
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13375 |
|
|
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13376 |
|
|
SIGNAL fsa1_clk_pip : std_logic := '0';
|
| 13377 |
|
|
SIGNAL fsa1_aclr_pip : std_logic := '0';
|
| 13378 |
|
|
SIGNAL fsa1_sload_pip : std_logic := '0';
|
| 13379 |
|
|
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
|
| 13380 |
|
|
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13381 |
|
|
--Signals for second stage adder
|
| 13382 |
|
|
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13383 |
|
|
SIGNAL ssa_sign : std_logic := '0';
|
| 13384 |
|
|
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13385 |
|
|
SIGNAL ssa_overflow : std_logic := '0';
|
| 13386 |
|
|
--Signals for RS block
|
| 13387 |
|
|
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13388 |
|
|
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13389 |
|
|
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13390 |
|
|
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13391 |
|
|
SIGNAL rs_saturation_overflow : std_logic := '0';
|
| 13392 |
|
|
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
|
| 13393 |
|
|
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13394 |
|
|
--signals for zeroloopback output register
|
| 13395 |
|
|
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13396 |
|
|
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13397 |
|
|
SIGNAL zeroloopback_clk_or : std_logic := '0';
|
| 13398 |
|
|
SIGNAL zeroloopback_aclr_or : std_logic := '0';
|
| 13399 |
|
|
SIGNAL zeroloopback_sload_or : std_logic := '0';
|
| 13400 |
|
|
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
|
| 13401 |
|
|
SIGNAL zeroloopback_out_reg : std_logic := '0';
|
| 13402 |
|
|
--signals for zerochainout output register
|
| 13403 |
|
|
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13404 |
|
|
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13405 |
|
|
SIGNAL zerochainout_clk_or : std_logic := '0';
|
| 13406 |
|
|
SIGNAL zerochainout_aclr_or : std_logic := '0';
|
| 13407 |
|
|
SIGNAL zerochainout_sload_or : std_logic := '0';
|
| 13408 |
|
|
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
|
| 13409 |
|
|
SIGNAL zerochainout_out_reg : std_logic := '0';
|
| 13410 |
|
|
--Signals for saturation_overflow output register
|
| 13411 |
|
|
SIGNAL rs_saturation_overflow_in : std_logic := '0';
|
| 13412 |
|
|
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13413 |
|
|
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13414 |
|
|
SIGNAL saturation_overflow_clk_or : std_logic := '0';
|
| 13415 |
|
|
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
|
| 13416 |
|
|
SIGNAL saturation_overflow_sload_or : std_logic := '0';
|
| 13417 |
|
|
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
|
| 13418 |
|
|
SIGNAL saturation_overflow_out_reg : std_logic := '0';
|
| 13419 |
|
|
--signals for rs_dataout output register
|
| 13420 |
|
|
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13421 |
|
|
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13422 |
|
|
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13423 |
|
|
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13424 |
|
|
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13425 |
|
|
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13426 |
|
|
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13427 |
|
|
SIGNAL rs_dataout_clk_or : std_logic := '0';
|
| 13428 |
|
|
SIGNAL rs_dataout_aclr_or : std_logic := '0';
|
| 13429 |
|
|
SIGNAL rs_dataout_sload_or : std_logic := '0';
|
| 13430 |
|
|
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
|
| 13431 |
|
|
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
|
| 13432 |
|
|
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
|
| 13433 |
|
|
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13434 |
|
|
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
|
| 13435 |
|
|
|
| 13436 |
|
|
--signals for rotate output register
|
| 13437 |
|
|
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13438 |
|
|
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13439 |
|
|
SIGNAL rotate_clk_or : std_logic := '0';
|
| 13440 |
|
|
SIGNAL rotate_aclr_or : std_logic := '0';
|
| 13441 |
|
|
SIGNAL rotate_sload_or : std_logic := '0';
|
| 13442 |
|
|
SIGNAL rotate_bypass_register_or: std_logic := '0';
|
| 13443 |
|
|
SIGNAL rotate_out_reg : std_logic := '0';
|
| 13444 |
|
|
--signals for shiftright output register
|
| 13445 |
|
|
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13446 |
|
|
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13447 |
|
|
SIGNAL shiftright_clk_or : std_logic := '0';
|
| 13448 |
|
|
SIGNAL shiftright_aclr_or : std_logic := '0';
|
| 13449 |
|
|
SIGNAL shiftright_sload_or : std_logic := '0';
|
| 13450 |
|
|
SIGNAL shiftright_bypass_register_or : std_logic := '0';
|
| 13451 |
|
|
SIGNAL shiftright_out_reg : std_logic := '0';
|
| 13452 |
|
|
--signals for roundchainout output register
|
| 13453 |
|
|
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13454 |
|
|
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13455 |
|
|
SIGNAL roundchainout_clk_or : std_logic := '0';
|
| 13456 |
|
|
SIGNAL roundchainout_aclr_or : std_logic := '0';
|
| 13457 |
|
|
SIGNAL roundchainout_sload_or : std_logic := '0';
|
| 13458 |
|
|
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
|
| 13459 |
|
|
SIGNAL roundchainout_out_reg : std_logic := '0';
|
| 13460 |
|
|
--signals for saturatechainout output register
|
| 13461 |
|
|
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13462 |
|
|
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13463 |
|
|
SIGNAL saturatechainout_clk_or : std_logic := '0';
|
| 13464 |
|
|
SIGNAL saturatechainout_aclr_or : std_logic := '0';
|
| 13465 |
|
|
SIGNAL saturatechainout_sload_or: std_logic := '0';
|
| 13466 |
|
|
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
|
| 13467 |
|
|
SIGNAL saturatechainout_out_reg : std_logic := '0';
|
| 13468 |
|
|
--Signals for chainout Adder RS Block
|
| 13469 |
|
|
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13470 |
|
|
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13471 |
|
|
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13472 |
|
|
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
|
| 13473 |
|
|
--signals for control signals for COA output register
|
| 13474 |
|
|
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13475 |
|
|
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
|
| 13476 |
|
|
SIGNAL coa_reg_clk_or : std_logic := '0';
|
| 13477 |
|
|
SIGNAL coa_reg_aclr_or : std_logic := '0';
|
| 13478 |
|
|
SIGNAL coa_reg_sload_or : std_logic := '0';
|
| 13479 |
|
|
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
|
| 13480 |
|
|
SIGNAL coa_reg_out_reg : std_logic := '0';
|
| 13481 |
|
|
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
|
| 13482 |
|
|
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
|
| 13483 |
|
|
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13484 |
|
|
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
|
| 13485 |
|
|
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13486 |
|
|
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13487 |
|
|
SIGNAL saturation_overflow_tmp : std_logic := '0';
|
| 13488 |
|
|
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
|
| 13489 |
|
|
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
|
| 13490 |
|
|
SIGNAL sign : std_logic := '0';
|
| 13491 |
|
|
|
| 13492 |
|
|
BEGIN
|
| 13493 |
|
|
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
|
| 13494 |
|
|
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
|
| 13495 |
|
|
begin
|
| 13496 |
|
|
rs_tmp := rs_dataout;
|
| 13497 |
|
|
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
|
| 13498 |
|
|
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
|
| 13499 |
|
|
end if;
|
| 13500 |
|
|
rs_dataout_of <= rs_tmp;
|
| 13501 |
|
|
end process;
|
| 13502 |
|
|
--Instantiate the zeroloopback input Register
|
| 13503 |
|
|
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
|
| 13504 |
|
|
ELSE "0001" WHEN (zeroloopback_clock = "1")
|
| 13505 |
|
|
ELSE "0010" WHEN (zeroloopback_clock = "2")
|
| 13506 |
|
|
ELSE "0011" WHEN (zeroloopback_clock = "3")
|
| 13507 |
|
|
ELSE "0000" ;
|
| 13508 |
|
|
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
|
| 13509 |
|
|
ELSE "0001" WHEN (zeroloopback_clear = "1")
|
| 13510 |
|
|
ELSE "0010" WHEN (zeroloopback_clear = "2")
|
| 13511 |
|
|
ELSE "0011" WHEN (zeroloopback_clear = "3")
|
| 13512 |
|
|
ELSE "0000" ;
|
| 13513 |
|
|
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
|
| 13514 |
|
|
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13515 |
|
|
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
|
| 13516 |
|
|
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
|
| 13517 |
|
|
|
| 13518 |
|
|
zeroloopback_input_register : stratixiii_mac_bit_register
|
| 13519 |
|
|
PORT MAP (
|
| 13520 |
|
|
datain => zeroloopback,
|
| 13521 |
|
|
clk => zeroloopback_clk_ir,
|
| 13522 |
|
|
aclr => zeroloopback_aclr_ir,
|
| 13523 |
|
|
sload => zeroloopback_sload_ir,
|
| 13524 |
|
|
bypass_register => zeroloopback_bypass_register_ir,
|
| 13525 |
|
|
dataout => zeroloopback_in_reg
|
| 13526 |
|
|
);
|
| 13527 |
|
|
|
| 13528 |
|
|
--Instantiate the zeroacc input Register
|
| 13529 |
|
|
|
| 13530 |
|
|
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
|
| 13531 |
|
|
ELSE "0001" WHEN (zeroacc_clock = "1")
|
| 13532 |
|
|
ELSE "0010" WHEN (zeroacc_clock = "2")
|
| 13533 |
|
|
ELSE "0011" WHEN (zeroacc_clock = "3")
|
| 13534 |
|
|
ELSE "0000" ;
|
| 13535 |
|
|
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
|
| 13536 |
|
|
ELSE "0001" WHEN (zeroacc_clear = "1")
|
| 13537 |
|
|
ELSE "0010" WHEN (zeroacc_clear = "2")
|
| 13538 |
|
|
ELSE "0011" WHEN (zeroacc_clear = "3")
|
| 13539 |
|
|
ELSE "0000" ;
|
| 13540 |
|
|
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
|
| 13541 |
|
|
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13542 |
|
|
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
|
| 13543 |
|
|
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
|
| 13544 |
|
|
|
| 13545 |
|
|
zeroacc_input_register : stratixiii_mac_bit_register
|
| 13546 |
|
|
PORT MAP (
|
| 13547 |
|
|
datain => zeroacc,
|
| 13548 |
|
|
clk => zeroacc_clk_ir,
|
| 13549 |
|
|
aclr => zeroacc_aclr_ir,
|
| 13550 |
|
|
sload => zeroacc_sload_ir,
|
| 13551 |
|
|
bypass_register => zeroacc_bypass_register_ir,
|
| 13552 |
|
|
dataout => zeroacc_in_reg
|
| 13553 |
|
|
);
|
| 13554 |
|
|
|
| 13555 |
|
|
--Instantiate the signa input Register
|
| 13556 |
|
|
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
|
| 13557 |
|
|
ELSE "0001" WHEN (signa_clock = "1")
|
| 13558 |
|
|
ELSE "0010" WHEN (signa_clock = "2")
|
| 13559 |
|
|
ELSE "0011" WHEN (signa_clock = "3")
|
| 13560 |
|
|
ELSE "0000" ;
|
| 13561 |
|
|
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
|
| 13562 |
|
|
ELSE "0001" WHEN (signa_clear = "1")
|
| 13563 |
|
|
ELSE "0010" WHEN (signa_clear = "2")
|
| 13564 |
|
|
ELSE "0011" WHEN (signa_clear = "3")
|
| 13565 |
|
|
ELSE "0000" ;
|
| 13566 |
|
|
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
|
| 13567 |
|
|
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13568 |
|
|
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
|
| 13569 |
|
|
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
|
| 13570 |
|
|
|
| 13571 |
|
|
signa_input_register : stratixiii_mac_bit_register
|
| 13572 |
|
|
PORT MAP (
|
| 13573 |
|
|
datain => signa,
|
| 13574 |
|
|
clk => signa_clk_ir,
|
| 13575 |
|
|
aclr => signa_aclr_ir,
|
| 13576 |
|
|
sload => signa_sload_ir,
|
| 13577 |
|
|
bypass_register => signa_bypass_register_ir,
|
| 13578 |
|
|
dataout => signa_in_reg
|
| 13579 |
|
|
);
|
| 13580 |
|
|
|
| 13581 |
|
|
--Instantiate the signb input Register
|
| 13582 |
|
|
|
| 13583 |
|
|
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
|
| 13584 |
|
|
ELSE "0001" WHEN (signb_clock = "1")
|
| 13585 |
|
|
ELSE "0010" WHEN (signb_clock = "2")
|
| 13586 |
|
|
ELSE "0011" WHEN (signb_clock = "3")
|
| 13587 |
|
|
ELSE "0000" ;
|
| 13588 |
|
|
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
|
| 13589 |
|
|
ELSE "0001" WHEN (signb_clear = "1")
|
| 13590 |
|
|
ELSE "0010" WHEN (signb_clear = "2")
|
| 13591 |
|
|
ELSE "0011" WHEN (signb_clear = "3")
|
| 13592 |
|
|
ELSE "0000" ;
|
| 13593 |
|
|
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
|
| 13594 |
|
|
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13595 |
|
|
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
|
| 13596 |
|
|
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
|
| 13597 |
|
|
|
| 13598 |
|
|
signb_input_register : stratixiii_mac_bit_register
|
| 13599 |
|
|
PORT MAP (
|
| 13600 |
|
|
datain => signb,
|
| 13601 |
|
|
clk => signb_clk_ir,
|
| 13602 |
|
|
aclr => signb_aclr_ir,
|
| 13603 |
|
|
sload => signb_sload_ir,
|
| 13604 |
|
|
bypass_register => signb_bypass_register_ir,
|
| 13605 |
|
|
dataout => signb_in_reg
|
| 13606 |
|
|
);
|
| 13607 |
|
|
|
| 13608 |
|
|
--Instantiate the rotate input Register
|
| 13609 |
|
|
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
|
| 13610 |
|
|
ELSE "0001" WHEN (rotate_clock = "1")
|
| 13611 |
|
|
ELSE "0010" WHEN (rotate_clock = "2")
|
| 13612 |
|
|
ELSE "0011" WHEN (rotate_clock = "3")
|
| 13613 |
|
|
ELSE "0000" ;
|
| 13614 |
|
|
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
|
| 13615 |
|
|
ELSE "0001" WHEN (rotate_clear = "1")
|
| 13616 |
|
|
ELSE "0010" WHEN (rotate_clear = "2")
|
| 13617 |
|
|
ELSE "0011" WHEN (rotate_clear = "3")
|
| 13618 |
|
|
ELSE "0000" ;
|
| 13619 |
|
|
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
|
| 13620 |
|
|
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13621 |
|
|
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
|
| 13622 |
|
|
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
|
| 13623 |
|
|
|
| 13624 |
|
|
rotate_input_register : stratixiii_mac_bit_register
|
| 13625 |
|
|
PORT MAP (
|
| 13626 |
|
|
datain => rotate,
|
| 13627 |
|
|
clk => rotate_clk_ir,
|
| 13628 |
|
|
aclr => rotate_aclr_ir,
|
| 13629 |
|
|
sload => rotate_sload_ir,
|
| 13630 |
|
|
bypass_register => rotate_bypass_register_ir,
|
| 13631 |
|
|
dataout => rotate_in_reg
|
| 13632 |
|
|
);
|
| 13633 |
|
|
|
| 13634 |
|
|
|
| 13635 |
|
|
--Instantiate the shiftright input Register
|
| 13636 |
|
|
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
|
| 13637 |
|
|
ELSE "0001" WHEN (shiftright_clock = "1")
|
| 13638 |
|
|
ELSE "0010" WHEN (shiftright_clock = "2")
|
| 13639 |
|
|
ELSE "0011" WHEN (shiftright_clock = "3")
|
| 13640 |
|
|
ELSE "0000" ;
|
| 13641 |
|
|
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
|
| 13642 |
|
|
ELSE "0001" WHEN (shiftright_clear = "1")
|
| 13643 |
|
|
ELSE "0010" WHEN (shiftright_clear = "2")
|
| 13644 |
|
|
ELSE "0011" WHEN (shiftright_clear = "3")
|
| 13645 |
|
|
ELSE "0000" ;
|
| 13646 |
|
|
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
|
| 13647 |
|
|
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
|
| 13648 |
|
|
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
|
| 13649 |
|
|
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
|
| 13650 |
|
|
|
| 13651 |
|
|
shiftright_input_register : stratixiii_mac_bit_register
|
| 13652 |
|
|
PORT MAP (
|
| 13653 |
|
|
datain => shiftright,
|
| 13654 |
|
|
clk => shiftright_clk_ir,
|
| 13655 |
|
|
aclr => shiftright_aclr_ir,
|
| 13656 |
|
|
sload => shiftright_sload_ir,
|
| 13657 |
|
|
bypass_register => shiftright_bypass_register_ir,
|
| 13658 |
|
|
dataout => shiftright_in_reg
|
| 13659 |
|
|
);
|
| 13660 |
|
|
|
| 13661 |
|
|
--Instantiate the round input Register
|
| 13662 |
|
|
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
|
| 13663 |
|
|
ELSE "0001" WHEN (round_clock = "1")
|
| 13664 |
|
|
ELSE "0010" WHEN (round_clock = "2")
|
| 13665 |
|
|
ELSE "0011" WHEN (round_clock = "3")
|
| 13666 |
|
|
ELSE "0000" ;
|
| 13667 |
|
|
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
|
| 13668 |
|
|
ELSE "0001" WHEN (round_clear = "1")
|
| 13669 |
|
|
ELSE "0010" WHEN (round_clear = "2")
|
| 13670 |
|
|
ELSE "0011" WHEN (round_clear = "3")
|
| 13671 |
|
|
ELSE "0000" ;
|
| 13672 |
|
|
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
|
| 13673 |
|
|
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13674 |
|
|
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
|
| 13675 |
|
|
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
|
| 13676 |
|
|
|
| 13677 |
|
|
round_input_register : stratixiii_mac_bit_register
|
| 13678 |
|
|
PORT MAP (
|
| 13679 |
|
|
datain => round,
|
| 13680 |
|
|
clk => round_clk_ir,
|
| 13681 |
|
|
aclr => round_aclr_ir,
|
| 13682 |
|
|
sload => round_sload_ir,
|
| 13683 |
|
|
bypass_register => round_bypass_register_ir,
|
| 13684 |
|
|
dataout => round_in_reg
|
| 13685 |
|
|
);
|
| 13686 |
|
|
|
| 13687 |
|
|
--Instantiate the saturate input Register
|
| 13688 |
|
|
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
|
| 13689 |
|
|
ELSE "0001" WHEN (saturate_clock = "1")
|
| 13690 |
|
|
ELSE "0010" WHEN (saturate_clock = "2")
|
| 13691 |
|
|
ELSE "0011" WHEN (saturate_clock = "3")
|
| 13692 |
|
|
ELSE "0000" ;
|
| 13693 |
|
|
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
|
| 13694 |
|
|
ELSE "0001" WHEN (saturate_clear = "1")
|
| 13695 |
|
|
ELSE "0010" WHEN (saturate_clear = "2")
|
| 13696 |
|
|
ELSE "0011" WHEN (saturate_clear = "3")
|
| 13697 |
|
|
ELSE "0000" ;
|
| 13698 |
|
|
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
|
| 13699 |
|
|
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13700 |
|
|
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
|
| 13701 |
|
|
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
|
| 13702 |
|
|
|
| 13703 |
|
|
saturate_input_register : stratixiii_mac_bit_register
|
| 13704 |
|
|
PORT MAP (
|
| 13705 |
|
|
datain => saturate,
|
| 13706 |
|
|
clk => saturate_clk_ir,
|
| 13707 |
|
|
aclr => saturate_aclr_ir,
|
| 13708 |
|
|
sload => saturate_sload_ir,
|
| 13709 |
|
|
bypass_register => saturate_bypass_register_ir,
|
| 13710 |
|
|
dataout => saturate_in_reg
|
| 13711 |
|
|
);
|
| 13712 |
|
|
|
| 13713 |
|
|
|
| 13714 |
|
|
--Instantiate the roundchainout input Register
|
| 13715 |
|
|
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
|
| 13716 |
|
|
ELSE "0001" WHEN (roundchainout_clock = "1")
|
| 13717 |
|
|
ELSE "0010" WHEN (roundchainout_clock = "2")
|
| 13718 |
|
|
ELSE "0011" WHEN (roundchainout_clock = "3")
|
| 13719 |
|
|
ELSE "0000" ;
|
| 13720 |
|
|
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
|
| 13721 |
|
|
ELSE "0001" WHEN (roundchainout_clear = "1")
|
| 13722 |
|
|
ELSE "0010" WHEN (roundchainout_clear = "2")
|
| 13723 |
|
|
ELSE "0011" WHEN (roundchainout_clear = "3")
|
| 13724 |
|
|
ELSE "0000" ;
|
| 13725 |
|
|
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
|
| 13726 |
|
|
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13727 |
|
|
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
|
| 13728 |
|
|
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
|
| 13729 |
|
|
|
| 13730 |
|
|
roundchainout_input_register : stratixiii_mac_bit_register
|
| 13731 |
|
|
PORT MAP (
|
| 13732 |
|
|
datain => roundchainout,
|
| 13733 |
|
|
clk => roundchainout_clk_ir,
|
| 13734 |
|
|
aclr => roundchainout_aclr_ir,
|
| 13735 |
|
|
sload => roundchainout_sload_ir,
|
| 13736 |
|
|
bypass_register => roundchainout_bypass_register_ir,
|
| 13737 |
|
|
dataout => roundchainout_in_reg
|
| 13738 |
|
|
);
|
| 13739 |
|
|
|
| 13740 |
|
|
--Instantiate the saturatechainout input Register
|
| 13741 |
|
|
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
|
| 13742 |
|
|
ELSE "0001" WHEN (saturatechainout_clock = "1")
|
| 13743 |
|
|
ELSE "0010" WHEN (saturatechainout_clock = "2")
|
| 13744 |
|
|
ELSE "0011" WHEN (saturatechainout_clock = "3")
|
| 13745 |
|
|
ELSE "0000" ;
|
| 13746 |
|
|
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
|
| 13747 |
|
|
ELSE "0001" WHEN (saturatechainout_clear = "1")
|
| 13748 |
|
|
ELSE "0010" WHEN (saturatechainout_clear = "2")
|
| 13749 |
|
|
ELSE "0011" WHEN (saturatechainout_clear = "3")
|
| 13750 |
|
|
ELSE "0000" ;
|
| 13751 |
|
|
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
|
| 13752 |
|
|
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13753 |
|
|
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
|
| 13754 |
|
|
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
|
| 13755 |
|
|
|
| 13756 |
|
|
saturatechainout_input_register : stratixiii_mac_bit_register
|
| 13757 |
|
|
PORT MAP (
|
| 13758 |
|
|
datain => saturatechainout,
|
| 13759 |
|
|
clk => saturatechainout_clk_ir,
|
| 13760 |
|
|
aclr => saturatechainout_aclr_ir,
|
| 13761 |
|
|
sload => saturatechainout_sload_ir,
|
| 13762 |
|
|
bypass_register => saturatechainout_bypass_register_ir,
|
| 13763 |
|
|
dataout => saturatechainout_in_reg
|
| 13764 |
|
|
);
|
| 13765 |
|
|
|
| 13766 |
|
|
--Instantiate the First level adder interface and sign extension block
|
| 13767 |
|
|
sign <= signa_in_reg OR signb_in_reg ;
|
| 13768 |
|
|
fsa_interface : stratixiii_fsa_isse
|
| 13769 |
|
|
GENERIC MAP (
|
| 13770 |
|
|
chainin_width => chainin_width,
|
| 13771 |
|
|
dataa_width => dataa_width,
|
| 13772 |
|
|
datab_width => datab_width,
|
| 13773 |
|
|
datac_width => datac_width,
|
| 13774 |
|
|
datad_width => datad_width,
|
| 13775 |
|
|
operation_mode => operation_mode
|
| 13776 |
|
|
)
|
| 13777 |
|
|
PORT MAP (
|
| 13778 |
|
|
dataa => dataa,
|
| 13779 |
|
|
datab => datab,
|
| 13780 |
|
|
datac => datac,
|
| 13781 |
|
|
datad => datad,
|
| 13782 |
|
|
chainin => chainin,
|
| 13783 |
|
|
signa => signa_in_reg,
|
| 13784 |
|
|
signb => signb_in_reg,
|
| 13785 |
|
|
dataa_out => dataa_fsa_in,
|
| 13786 |
|
|
datab_out => datab_fsa_in,
|
| 13787 |
|
|
datac_out => datac_fsa_in,
|
| 13788 |
|
|
datad_out => datad_fsa_in,
|
| 13789 |
|
|
chainin_out => chainin_coa_in,
|
| 13790 |
|
|
operation => operation
|
| 13791 |
|
|
);
|
| 13792 |
|
|
|
| 13793 |
|
|
--Instantiate First Stage Adder/Subtractor Unit0
|
| 13794 |
|
|
fsaunit0 : stratixiii_first_stage_add_sub
|
| 13795 |
|
|
GENERIC MAP (
|
| 13796 |
|
|
dataa_width => dataa_width,
|
| 13797 |
|
|
datab_width => datab_width,
|
| 13798 |
|
|
fsa_mode => first_adder0_mode
|
| 13799 |
|
|
)
|
| 13800 |
|
|
PORT MAP (
|
| 13801 |
|
|
dataa => dataa_fsa_in,
|
| 13802 |
|
|
datab => datab_fsa_in,
|
| 13803 |
|
|
sign => sign,
|
| 13804 |
|
|
operation => operation,
|
| 13805 |
|
|
dataout => dataout_fsa0
|
| 13806 |
|
|
);
|
| 13807 |
|
|
|
| 13808 |
|
|
|
| 13809 |
|
|
--Instantiate First Stage Adder/Subtractor Unit1
|
| 13810 |
|
|
fsaunit1 : stratixiii_first_stage_add_sub
|
| 13811 |
|
|
GENERIC MAP (
|
| 13812 |
|
|
dataa_width => datac_width,
|
| 13813 |
|
|
datab_width => datad_width,
|
| 13814 |
|
|
fsa_mode => first_adder1_mode
|
| 13815 |
|
|
)
|
| 13816 |
|
|
PORT MAP (
|
| 13817 |
|
|
dataa => datac_fsa_in,
|
| 13818 |
|
|
datab => datad_fsa_in,
|
| 13819 |
|
|
sign => sign,
|
| 13820 |
|
|
operation => operation,
|
| 13821 |
|
|
dataout => dataout_fsa1
|
| 13822 |
|
|
);
|
| 13823 |
|
|
|
| 13824 |
|
|
|
| 13825 |
|
|
--Instantiate the zeroloopback pipeline Register
|
| 13826 |
|
|
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
|
| 13827 |
|
|
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
|
| 13828 |
|
|
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
|
| 13829 |
|
|
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
|
| 13830 |
|
|
ELSE "0000" ;
|
| 13831 |
|
|
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
|
| 13832 |
|
|
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
|
| 13833 |
|
|
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
|
| 13834 |
|
|
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
|
| 13835 |
|
|
ELSE "0000" ;
|
| 13836 |
|
|
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
|
| 13837 |
|
|
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13838 |
|
|
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
|
| 13839 |
|
|
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
|
| 13840 |
|
|
|
| 13841 |
|
|
|
| 13842 |
|
|
zeroloopback_pipeline_register : stratixiii_mac_bit_register
|
| 13843 |
|
|
PORT MAP (
|
| 13844 |
|
|
datain => zeroloopback_in_reg,
|
| 13845 |
|
|
clk => zeroloopback_clk_pip,
|
| 13846 |
|
|
aclr => zeroloopback_aclr_pip,
|
| 13847 |
|
|
sload => zeroloopback_sload_pip,
|
| 13848 |
|
|
bypass_register => zeroloopback_bypass_register_pip,
|
| 13849 |
|
|
dataout => zeroloopback_pip_reg
|
| 13850 |
|
|
);
|
| 13851 |
|
|
--Instantiate the zeroacc pipeline Register
|
| 13852 |
|
|
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
|
| 13853 |
|
|
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
|
| 13854 |
|
|
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
|
| 13855 |
|
|
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
|
| 13856 |
|
|
ELSE "0000" ;
|
| 13857 |
|
|
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
|
| 13858 |
|
|
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
|
| 13859 |
|
|
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
|
| 13860 |
|
|
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
|
| 13861 |
|
|
ELSE "0000" ;
|
| 13862 |
|
|
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
|
| 13863 |
|
|
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13864 |
|
|
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
|
| 13865 |
|
|
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
|
| 13866 |
|
|
|
| 13867 |
|
|
zeroacc_pipeline_register : stratixiii_mac_bit_register
|
| 13868 |
|
|
PORT MAP (
|
| 13869 |
|
|
datain => zeroacc_in_reg,
|
| 13870 |
|
|
clk => zeroacc_clk_pip,
|
| 13871 |
|
|
aclr => zeroacc_aclr_pip,
|
| 13872 |
|
|
sload => zeroacc_sload_pip,
|
| 13873 |
|
|
bypass_register => zeroacc_bypass_register_pip,
|
| 13874 |
|
|
dataout => zeroacc_pip_reg
|
| 13875 |
|
|
);
|
| 13876 |
|
|
|
| 13877 |
|
|
--Instantiate the signa pipeline Register
|
| 13878 |
|
|
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
|
| 13879 |
|
|
ELSE "0001" WHEN (signa_pipeline_clock = "1")
|
| 13880 |
|
|
ELSE "0010" WHEN (signa_pipeline_clock = "2")
|
| 13881 |
|
|
ELSE "0011" WHEN (signa_pipeline_clock = "3")
|
| 13882 |
|
|
ELSE "0000" ;
|
| 13883 |
|
|
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
|
| 13884 |
|
|
ELSE "0001" WHEN (signa_pipeline_clear = "1")
|
| 13885 |
|
|
ELSE "0010" WHEN (signa_pipeline_clear = "2")
|
| 13886 |
|
|
ELSE "0011" WHEN (signa_pipeline_clear = "3")
|
| 13887 |
|
|
ELSE "0000" ;
|
| 13888 |
|
|
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
|
| 13889 |
|
|
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13890 |
|
|
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
|
| 13891 |
|
|
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
|
| 13892 |
|
|
|
| 13893 |
|
|
signa_pipeline_register : stratixiii_mac_bit_register
|
| 13894 |
|
|
PORT MAP (
|
| 13895 |
|
|
datain => signa_in_reg,
|
| 13896 |
|
|
clk => signa_clk_pip,
|
| 13897 |
|
|
aclr => signa_aclr_pip,
|
| 13898 |
|
|
sload => signa_sload_pip,
|
| 13899 |
|
|
bypass_register => signa_bypass_register_pip,
|
| 13900 |
|
|
dataout => signa_pip_reg
|
| 13901 |
|
|
);
|
| 13902 |
|
|
|
| 13903 |
|
|
--Instantiate the signb pipeline Register
|
| 13904 |
|
|
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
|
| 13905 |
|
|
ELSE "0001" WHEN (signb_pipeline_clock = "1")
|
| 13906 |
|
|
ELSE "0010" WHEN (signb_pipeline_clock = "2")
|
| 13907 |
|
|
ELSE "0011" WHEN (signb_pipeline_clock = "3")
|
| 13908 |
|
|
ELSE "0000" ;
|
| 13909 |
|
|
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
|
| 13910 |
|
|
ELSE "0001" WHEN (signb_pipeline_clear = "1")
|
| 13911 |
|
|
ELSE "0010" WHEN (signb_pipeline_clear = "2")
|
| 13912 |
|
|
ELSE "0011" WHEN (signb_pipeline_clear = "3")
|
| 13913 |
|
|
ELSE "0000" ;
|
| 13914 |
|
|
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
|
| 13915 |
|
|
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13916 |
|
|
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
|
| 13917 |
|
|
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
|
| 13918 |
|
|
|
| 13919 |
|
|
signb_pipeline_register : stratixiii_mac_bit_register
|
| 13920 |
|
|
PORT MAP (
|
| 13921 |
|
|
datain => signb_in_reg,
|
| 13922 |
|
|
clk => signb_clk_pip,
|
| 13923 |
|
|
aclr => signb_aclr_pip,
|
| 13924 |
|
|
sload => signb_sload_pip,
|
| 13925 |
|
|
bypass_register => signb_bypass_register_pip,
|
| 13926 |
|
|
dataout => signb_pip_reg
|
| 13927 |
|
|
);
|
| 13928 |
|
|
|
| 13929 |
|
|
--Instantiate the rotate pipeline Register
|
| 13930 |
|
|
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
|
| 13931 |
|
|
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
|
| 13932 |
|
|
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
|
| 13933 |
|
|
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
|
| 13934 |
|
|
ELSE "0000" ;
|
| 13935 |
|
|
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
|
| 13936 |
|
|
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
|
| 13937 |
|
|
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
|
| 13938 |
|
|
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
|
| 13939 |
|
|
ELSE "0000" ;
|
| 13940 |
|
|
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
|
| 13941 |
|
|
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13942 |
|
|
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
|
| 13943 |
|
|
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
|
| 13944 |
|
|
|
| 13945 |
|
|
rotate_pipeline_register : stratixiii_mac_bit_register
|
| 13946 |
|
|
PORT MAP (
|
| 13947 |
|
|
datain => rotate_in_reg,
|
| 13948 |
|
|
clk => rotate_clk_pip,
|
| 13949 |
|
|
aclr => rotate_aclr_pip,
|
| 13950 |
|
|
sload => rotate_sload_pip,
|
| 13951 |
|
|
bypass_register => rotate_bypass_register_pip,
|
| 13952 |
|
|
dataout => rotate_pip_reg
|
| 13953 |
|
|
);
|
| 13954 |
|
|
|
| 13955 |
|
|
--Instantiate the shiftright pipeline Register
|
| 13956 |
|
|
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
|
| 13957 |
|
|
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
|
| 13958 |
|
|
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
|
| 13959 |
|
|
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
|
| 13960 |
|
|
ELSE "0000" ;
|
| 13961 |
|
|
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
|
| 13962 |
|
|
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
|
| 13963 |
|
|
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
|
| 13964 |
|
|
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
|
| 13965 |
|
|
ELSE "0000" ;
|
| 13966 |
|
|
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
|
| 13967 |
|
|
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13968 |
|
|
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
|
| 13969 |
|
|
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
|
| 13970 |
|
|
|
| 13971 |
|
|
shiftright_pipeline_register : stratixiii_mac_bit_register
|
| 13972 |
|
|
PORT MAP (
|
| 13973 |
|
|
datain => shiftright_in_reg,
|
| 13974 |
|
|
clk => shiftright_clk_pip,
|
| 13975 |
|
|
aclr => shiftright_aclr_pip,
|
| 13976 |
|
|
sload => shiftright_sload_pip,
|
| 13977 |
|
|
bypass_register => shiftright_bypass_register_pip,
|
| 13978 |
|
|
dataout => shiftright_pip_reg
|
| 13979 |
|
|
);
|
| 13980 |
|
|
|
| 13981 |
|
|
--Instantiate the round pipeline Register
|
| 13982 |
|
|
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
|
| 13983 |
|
|
ELSE "0001" WHEN (round_pipeline_clock = "1")
|
| 13984 |
|
|
ELSE "0010" WHEN (round_pipeline_clock = "2")
|
| 13985 |
|
|
ELSE "0011" WHEN (round_pipeline_clock = "3")
|
| 13986 |
|
|
ELSE "0000" ;
|
| 13987 |
|
|
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
|
| 13988 |
|
|
ELSE "0001" WHEN (round_pipeline_clear = "1")
|
| 13989 |
|
|
ELSE "0010" WHEN (round_pipeline_clear = "2")
|
| 13990 |
|
|
ELSE "0011" WHEN (round_pipeline_clear = "3")
|
| 13991 |
|
|
ELSE "0000" ;
|
| 13992 |
|
|
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
|
| 13993 |
|
|
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 13994 |
|
|
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
|
| 13995 |
|
|
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
|
| 13996 |
|
|
|
| 13997 |
|
|
round_pipeline_register : stratixiii_mac_bit_register
|
| 13998 |
|
|
PORT MAP (
|
| 13999 |
|
|
datain => round_in_reg,
|
| 14000 |
|
|
clk => round_clk_pip,
|
| 14001 |
|
|
aclr => round_aclr_pip,
|
| 14002 |
|
|
sload => round_sload_pip,
|
| 14003 |
|
|
bypass_register => round_bypass_register_pip,
|
| 14004 |
|
|
dataout => round_pip_reg
|
| 14005 |
|
|
);
|
| 14006 |
|
|
|
| 14007 |
|
|
--Instantiate the saturate pipeline Register
|
| 14008 |
|
|
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
|
| 14009 |
|
|
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
|
| 14010 |
|
|
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
|
| 14011 |
|
|
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
|
| 14012 |
|
|
ELSE "0000" ;
|
| 14013 |
|
|
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
|
| 14014 |
|
|
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
|
| 14015 |
|
|
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
|
| 14016 |
|
|
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
|
| 14017 |
|
|
ELSE "0000" ;
|
| 14018 |
|
|
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
|
| 14019 |
|
|
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14020 |
|
|
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
|
| 14021 |
|
|
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
|
| 14022 |
|
|
|
| 14023 |
|
|
saturate_pipeline_register : stratixiii_mac_bit_register
|
| 14024 |
|
|
PORT MAP (
|
| 14025 |
|
|
datain => saturate_in_reg,
|
| 14026 |
|
|
clk => saturate_clk_pip,
|
| 14027 |
|
|
aclr => saturate_aclr_pip,
|
| 14028 |
|
|
sload => saturate_sload_pip,
|
| 14029 |
|
|
bypass_register => saturate_bypass_register_pip,
|
| 14030 |
|
|
dataout => saturate_pip_reg
|
| 14031 |
|
|
);
|
| 14032 |
|
|
|
| 14033 |
|
|
--Instantiate the roundchainout pipeline Register
|
| 14034 |
|
|
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
|
| 14035 |
|
|
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
|
| 14036 |
|
|
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
|
| 14037 |
|
|
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
|
| 14038 |
|
|
ELSE "0000" ;
|
| 14039 |
|
|
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
|
| 14040 |
|
|
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
|
| 14041 |
|
|
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
|
| 14042 |
|
|
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
|
| 14043 |
|
|
ELSE "0000" ;
|
| 14044 |
|
|
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
|
| 14045 |
|
|
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14046 |
|
|
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
|
| 14047 |
|
|
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
|
| 14048 |
|
|
|
| 14049 |
|
|
roundchainout_pipeline_register : stratixiii_mac_bit_register
|
| 14050 |
|
|
PORT MAP (
|
| 14051 |
|
|
datain => roundchainout_in_reg,
|
| 14052 |
|
|
clk => roundchainout_clk_pip,
|
| 14053 |
|
|
aclr => roundchainout_aclr_pip,
|
| 14054 |
|
|
sload => roundchainout_sload_pip,
|
| 14055 |
|
|
bypass_register => roundchainout_bypass_register_pip,
|
| 14056 |
|
|
dataout => roundchainout_pip_reg
|
| 14057 |
|
|
);
|
| 14058 |
|
|
|
| 14059 |
|
|
--Instantiate the saturatechainout pipeline Register
|
| 14060 |
|
|
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
|
| 14061 |
|
|
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
|
| 14062 |
|
|
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
|
| 14063 |
|
|
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
|
| 14064 |
|
|
ELSE "0000" ;
|
| 14065 |
|
|
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
|
| 14066 |
|
|
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
|
| 14067 |
|
|
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
|
| 14068 |
|
|
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
|
| 14069 |
|
|
ELSE "0000" ;
|
| 14070 |
|
|
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
|
| 14071 |
|
|
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14072 |
|
|
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
|
| 14073 |
|
|
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
|
| 14074 |
|
|
|
| 14075 |
|
|
saturatechainout_pipeline_register : stratixiii_mac_bit_register
|
| 14076 |
|
|
PORT MAP (
|
| 14077 |
|
|
datain => saturatechainout_in_reg,
|
| 14078 |
|
|
clk => saturatechainout_clk_pip,
|
| 14079 |
|
|
aclr => saturatechainout_aclr_pip,
|
| 14080 |
|
|
sload => saturatechainout_sload_pip,
|
| 14081 |
|
|
bypass_register => saturatechainout_bypass_register_pip,
|
| 14082 |
|
|
dataout => saturatechainout_pip_reg
|
| 14083 |
|
|
);
|
| 14084 |
|
|
|
| 14085 |
|
|
-- Instantiate fsa0 dataout pipline register
|
| 14086 |
|
|
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
|
| 14087 |
|
|
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
|
| 14088 |
|
|
ELSE "0001" WHEN (first_adder0_clock = "1")
|
| 14089 |
|
|
ELSE "0010" WHEN (first_adder0_clock = "2")
|
| 14090 |
|
|
ELSE "0011" WHEN (first_adder0_clock = "3")
|
| 14091 |
|
|
ELSE "0000" ;
|
| 14092 |
|
|
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
|
| 14093 |
|
|
ELSE "0001" WHEN (first_adder0_clear = "1")
|
| 14094 |
|
|
ELSE "0010" WHEN (first_adder0_clear = "2")
|
| 14095 |
|
|
ELSE "0011" WHEN (first_adder0_clear = "3")
|
| 14096 |
|
|
ELSE "0000" ;
|
| 14097 |
|
|
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
|
| 14098 |
|
|
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14099 |
|
|
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
|
| 14100 |
|
|
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
|
| 14101 |
|
|
|
| 14102 |
|
|
|
| 14103 |
|
|
fsa0_pipeline_register : stratixiii_mac_register
|
| 14104 |
|
|
GENERIC MAP (
|
| 14105 |
|
|
data_width => 72
|
| 14106 |
|
|
)
|
| 14107 |
|
|
PORT MAP (
|
| 14108 |
|
|
datain => fsa_pip_datain1,
|
| 14109 |
|
|
clk => fsa0_clk_pip,
|
| 14110 |
|
|
aclr => fsa0_aclr_pip,
|
| 14111 |
|
|
sload => fsa0_sload_pip,
|
| 14112 |
|
|
bypass_register => fsa0_bypass_register_pip,
|
| 14113 |
|
|
dataout => fsa0_pip_reg
|
| 14114 |
|
|
);
|
| 14115 |
|
|
|
| 14116 |
|
|
-- Instantiate fsa1 dataout pipline register
|
| 14117 |
|
|
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
|
| 14118 |
|
|
ELSE "0001" WHEN (first_adder1_clock = "1")
|
| 14119 |
|
|
ELSE "0010" WHEN (first_adder1_clock = "2")
|
| 14120 |
|
|
ELSE "0011" WHEN (first_adder1_clock = "3")
|
| 14121 |
|
|
ELSE "0000" ;
|
| 14122 |
|
|
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
|
| 14123 |
|
|
ELSE "0001" WHEN (first_adder1_clear = "1")
|
| 14124 |
|
|
ELSE "0010" WHEN (first_adder1_clear = "2")
|
| 14125 |
|
|
ELSE "0011" WHEN (first_adder1_clear = "3")
|
| 14126 |
|
|
ELSE "0000" ;
|
| 14127 |
|
|
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
|
| 14128 |
|
|
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14129 |
|
|
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
|
| 14130 |
|
|
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
|
| 14131 |
|
|
|
| 14132 |
|
|
fsa1_pipeline_register : stratixiii_mac_register
|
| 14133 |
|
|
GENERIC MAP (
|
| 14134 |
|
|
data_width => 72
|
| 14135 |
|
|
)
|
| 14136 |
|
|
PORT MAP (
|
| 14137 |
|
|
datain => dataout_fsa1,
|
| 14138 |
|
|
clk => fsa1_clk_pip,
|
| 14139 |
|
|
aclr => fsa1_aclr_pip,
|
| 14140 |
|
|
sload => fsa1_sload_pip,
|
| 14141 |
|
|
bypass_register => fsa1_bypass_register_pip,
|
| 14142 |
|
|
dataout => fsa1_pip_reg
|
| 14143 |
|
|
);
|
| 14144 |
|
|
|
| 14145 |
|
|
--Instantiate the second level adder/accumulator block
|
| 14146 |
|
|
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
|
| 14147 |
|
|
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
|
| 14148 |
|
|
|
| 14149 |
|
|
ssa_unit : stratixiii_second_stage_add_accum
|
| 14150 |
|
|
GENERIC MAP (
|
| 14151 |
|
|
dataa_width => dataa_width + 1,
|
| 14152 |
|
|
datab_width => datac_width + 1,
|
| 14153 |
|
|
ssa_mode => acc_adder_operation
|
| 14154 |
|
|
)
|
| 14155 |
|
|
PORT MAP (
|
| 14156 |
|
|
dataa => fsa0_pip_reg,
|
| 14157 |
|
|
datab => fsa1_pip_reg,
|
| 14158 |
|
|
accumin => ssa_accum_in,
|
| 14159 |
|
|
sign => ssa_sign,
|
| 14160 |
|
|
operation => operation,
|
| 14161 |
|
|
dataout => ssa_dataout,
|
| 14162 |
|
|
overflow => ssa_overflow
|
| 14163 |
|
|
);
|
| 14164 |
|
|
|
| 14165 |
|
|
|
| 14166 |
|
|
-- Instantiate round and saturation block
|
| 14167 |
|
|
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
|
| 14168 |
|
|
ELSE ssa_dataout ;
|
| 14169 |
|
|
|
| 14170 |
|
|
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
|
| 14171 |
|
|
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
|
| 14172 |
|
|
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
|
| 14173 |
|
|
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
|
| 14174 |
|
|
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
|
| 14175 |
|
|
|
| 14176 |
|
|
|
| 14177 |
|
|
|
| 14178 |
|
|
|
| 14179 |
|
|
rs_block : stratixiii_round_saturate_block
|
| 14180 |
|
|
GENERIC MAP (
|
| 14181 |
|
|
dataa_width => dataa_width,
|
| 14182 |
|
|
datab_width => datab_width,
|
| 14183 |
|
|
operation_mode => operation_mode,
|
| 14184 |
|
|
round_mode => round_mode,
|
| 14185 |
|
|
saturate_mode => saturate_mode,
|
| 14186 |
|
|
saturate_width => saturate_width,
|
| 14187 |
|
|
round_width => round_width
|
| 14188 |
|
|
)
|
| 14189 |
|
|
PORT MAP (
|
| 14190 |
|
|
datain => rs_datain,
|
| 14191 |
|
|
round => round_pip_reg,
|
| 14192 |
|
|
saturate => saturate_pip_reg,
|
| 14193 |
|
|
signa => signa_pip_reg,
|
| 14194 |
|
|
signb => signb_pip_reg,
|
| 14195 |
|
|
datain_width => ssa_datain_width,
|
| 14196 |
|
|
dataout => rs_dataout,
|
| 14197 |
|
|
saturationoverflow => rs_saturation_overflow
|
| 14198 |
|
|
);
|
| 14199 |
|
|
--Instantiate the zeroloopback output Register
|
| 14200 |
|
|
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
|
| 14201 |
|
|
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
|
| 14202 |
|
|
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
|
| 14203 |
|
|
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
|
| 14204 |
|
|
ELSE "0000" ;
|
| 14205 |
|
|
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
|
| 14206 |
|
|
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
|
| 14207 |
|
|
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
|
| 14208 |
|
|
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
|
| 14209 |
|
|
ELSE "0000" ;
|
| 14210 |
|
|
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
|
| 14211 |
|
|
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14212 |
|
|
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
|
| 14213 |
|
|
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
|
| 14214 |
|
|
|
| 14215 |
|
|
zeroloopback_output_register : stratixiii_mac_bit_register
|
| 14216 |
|
|
PORT MAP (
|
| 14217 |
|
|
datain => zeroloopback_pip_reg,
|
| 14218 |
|
|
clk => zeroloopback_clk_or,
|
| 14219 |
|
|
aclr => zeroloopback_aclr_or,
|
| 14220 |
|
|
sload => zeroloopback_sload_or,
|
| 14221 |
|
|
bypass_register => zeroloopback_bypass_register_or,
|
| 14222 |
|
|
dataout => zeroloopback_out_reg
|
| 14223 |
|
|
);
|
| 14224 |
|
|
|
| 14225 |
|
|
--Instantiate the zerochainout output Register
|
| 14226 |
|
|
|
| 14227 |
|
|
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
|
| 14228 |
|
|
ELSE "0001" WHEN (zerochainout_output_clock = "1")
|
| 14229 |
|
|
ELSE "0010" WHEN (zerochainout_output_clock = "2")
|
| 14230 |
|
|
ELSE "0011" WHEN (zerochainout_output_clock = "3")
|
| 14231 |
|
|
ELSE "0000" ;
|
| 14232 |
|
|
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
|
| 14233 |
|
|
ELSE "0001" WHEN (zerochainout_output_clear = "1")
|
| 14234 |
|
|
ELSE "0010" WHEN (zerochainout_output_clear = "2")
|
| 14235 |
|
|
ELSE "0011" WHEN (zerochainout_output_clear = "3")
|
| 14236 |
|
|
ELSE "0000" ;
|
| 14237 |
|
|
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
|
| 14238 |
|
|
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14239 |
|
|
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
|
| 14240 |
|
|
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
|
| 14241 |
|
|
|
| 14242 |
|
|
zerochainout_output_register : stratixiii_mac_bit_register
|
| 14243 |
|
|
PORT MAP (
|
| 14244 |
|
|
datain => zerochainout,
|
| 14245 |
|
|
clk => zerochainout_clk_or,
|
| 14246 |
|
|
aclr => zerochainout_aclr_or,
|
| 14247 |
|
|
sload => zerochainout_sload_or,
|
| 14248 |
|
|
bypass_register => zerochainout_bypass_register_or,
|
| 14249 |
|
|
dataout => zerochainout_out_reg
|
| 14250 |
|
|
);
|
| 14251 |
|
|
|
| 14252 |
|
|
|
| 14253 |
|
|
-- Instantiate Round_Saturate dataout output register
|
| 14254 |
|
|
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
|
| 14255 |
|
|
ELSE "0001" WHEN (second_adder_clock = "1")
|
| 14256 |
|
|
ELSE "0010" WHEN (second_adder_clock = "2")
|
| 14257 |
|
|
ELSE "0011" WHEN (second_adder_clock = "3")
|
| 14258 |
|
|
ELSE "0000" ;
|
| 14259 |
|
|
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
|
| 14260 |
|
|
ELSE "0001" WHEN (second_adder_clear = "1")
|
| 14261 |
|
|
ELSE "0010" WHEN (second_adder_clear = "2")
|
| 14262 |
|
|
ELSE "0011" WHEN (second_adder_clear = "3")
|
| 14263 |
|
|
ELSE "0000" ;
|
| 14264 |
|
|
|
| 14265 |
|
|
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
|
| 14266 |
|
|
ELSE "0001" WHEN (output_clock = "1")
|
| 14267 |
|
|
ELSE "0010" WHEN (output_clock = "2")
|
| 14268 |
|
|
ELSE "0011" WHEN (output_clock = "3")
|
| 14269 |
|
|
ELSE "0000" ;
|
| 14270 |
|
|
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
|
| 14271 |
|
|
ELSE "0001" WHEN (output_clear = "1")
|
| 14272 |
|
|
ELSE "0010" WHEN (output_clear = "2")
|
| 14273 |
|
|
ELSE "0011" WHEN (output_clear = "3")
|
| 14274 |
|
|
ELSE "0000" ;
|
| 14275 |
|
|
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
|
| 14276 |
|
|
ELSE rs_dataout_aclrval_or_o;
|
| 14277 |
|
|
|
| 14278 |
|
|
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
|
| 14279 |
|
|
ELSE rs_dataout_clkval_or_o;
|
| 14280 |
|
|
|
| 14281 |
|
|
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
|
| 14282 |
|
|
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
|
| 14283 |
|
|
|
| 14284 |
|
|
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
|
| 14285 |
|
|
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14286 |
|
|
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
|
| 14287 |
|
|
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
|
| 14288 |
|
|
ELSE rs_dataout_bypass_register_or_o;
|
| 14289 |
|
|
|
| 14290 |
|
|
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
|
| 14291 |
|
|
|
| 14292 |
|
|
rs_dataout_output_register : stratixiii_mac_register
|
| 14293 |
|
|
GENERIC MAP (
|
| 14294 |
|
|
data_width => 72
|
| 14295 |
|
|
)
|
| 14296 |
|
|
PORT MAP (
|
| 14297 |
|
|
datain => rs_dataout_in,
|
| 14298 |
|
|
clk => rs_dataout_clk_or,
|
| 14299 |
|
|
aclr => rs_dataout_aclr_or,
|
| 14300 |
|
|
sload => rs_dataout_sload_or,
|
| 14301 |
|
|
bypass_register => rs_dataout_bypass_register_or,
|
| 14302 |
|
|
dataout => rs_dataout_out_reg
|
| 14303 |
|
|
);
|
| 14304 |
|
|
|
| 14305 |
|
|
-- Instantiate Round_Saturate saturation_overflow output register
|
| 14306 |
|
|
|
| 14307 |
|
|
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
|
| 14308 |
|
|
rs_saturation_overflow_output_register : stratixiii_mac_bit_register
|
| 14309 |
|
|
PORT MAP (
|
| 14310 |
|
|
datain => rs_saturation_overflow_in,
|
| 14311 |
|
|
clk => rs_dataout_clk_or,
|
| 14312 |
|
|
aclr => rs_dataout_aclr_or,
|
| 14313 |
|
|
sload => rs_dataout_sload_or,
|
| 14314 |
|
|
bypass_register => rs_dataout_bypass_register_or,
|
| 14315 |
|
|
dataout => rs_saturation_overflow_out_reg
|
| 14316 |
|
|
);
|
| 14317 |
|
|
|
| 14318 |
|
|
|
| 14319 |
|
|
--Instantiate the rotate output Register
|
| 14320 |
|
|
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
|
| 14321 |
|
|
ELSE "0001" WHEN (rotate_output_clock = "1")
|
| 14322 |
|
|
ELSE "0010" WHEN (rotate_output_clock = "2")
|
| 14323 |
|
|
ELSE "0011" WHEN (rotate_output_clock = "3")
|
| 14324 |
|
|
ELSE "0000" ;
|
| 14325 |
|
|
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
|
| 14326 |
|
|
ELSE "0001" WHEN (rotate_output_clear = "1")
|
| 14327 |
|
|
ELSE "0010" WHEN (rotate_output_clear = "2")
|
| 14328 |
|
|
ELSE "0011" WHEN (rotate_output_clear = "3")
|
| 14329 |
|
|
ELSE "0000" ;
|
| 14330 |
|
|
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
|
| 14331 |
|
|
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14332 |
|
|
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
|
| 14333 |
|
|
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
|
| 14334 |
|
|
|
| 14335 |
|
|
rotate_output_register : stratixiii_mac_bit_register
|
| 14336 |
|
|
PORT MAP (
|
| 14337 |
|
|
datain => rotate_pip_reg,
|
| 14338 |
|
|
clk => rotate_clk_or,
|
| 14339 |
|
|
aclr => rotate_aclr_or,
|
| 14340 |
|
|
sload => rotate_sload_or,
|
| 14341 |
|
|
bypass_register => rotate_bypass_register_or,
|
| 14342 |
|
|
dataout => rotate_out_reg
|
| 14343 |
|
|
);
|
| 14344 |
|
|
|
| 14345 |
|
|
--Instantiate the shiftright output Register
|
| 14346 |
|
|
shiftright_output_register : stratixiii_mac_bit_register
|
| 14347 |
|
|
PORT MAP (
|
| 14348 |
|
|
datain => shiftright_pip_reg,
|
| 14349 |
|
|
clk => shiftright_clk_or,
|
| 14350 |
|
|
aclr => shiftright_aclr_or,
|
| 14351 |
|
|
sload => shiftright_sload_or,
|
| 14352 |
|
|
bypass_register => shiftright_bypass_register_or,
|
| 14353 |
|
|
dataout => shiftright_out_reg
|
| 14354 |
|
|
);
|
| 14355 |
|
|
|
| 14356 |
|
|
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
|
| 14357 |
|
|
ELSE "0001" WHEN (shiftright_output_clock = "1")
|
| 14358 |
|
|
ELSE "0010" WHEN (shiftright_output_clock = "2")
|
| 14359 |
|
|
ELSE "0011" WHEN (shiftright_output_clock = "3")
|
| 14360 |
|
|
ELSE "0000" ;
|
| 14361 |
|
|
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
|
| 14362 |
|
|
ELSE "0001" WHEN (shiftright_output_clear = "1")
|
| 14363 |
|
|
ELSE "0010" WHEN (shiftright_output_clear = "2")
|
| 14364 |
|
|
ELSE "0011" WHEN (shiftright_output_clear = "3")
|
| 14365 |
|
|
ELSE "0000" ;
|
| 14366 |
|
|
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
|
| 14367 |
|
|
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14368 |
|
|
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
|
| 14369 |
|
|
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
|
| 14370 |
|
|
|
| 14371 |
|
|
--Instantiate the roundchainout output Register
|
| 14372 |
|
|
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
|
| 14373 |
|
|
ELSE "0001" WHEN (roundchainout_output_clock = "1")
|
| 14374 |
|
|
ELSE "0010" WHEN (roundchainout_output_clock = "2")
|
| 14375 |
|
|
ELSE "0011" WHEN (roundchainout_output_clock = "3")
|
| 14376 |
|
|
ELSE "0000" ;
|
| 14377 |
|
|
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
|
| 14378 |
|
|
ELSE "0001" WHEN (roundchainout_output_clear = "1")
|
| 14379 |
|
|
ELSE "0010" WHEN (roundchainout_output_clear = "2")
|
| 14380 |
|
|
ELSE "0011" WHEN (roundchainout_output_clear = "3")
|
| 14381 |
|
|
ELSE "0000" ;
|
| 14382 |
|
|
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
|
| 14383 |
|
|
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14384 |
|
|
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
|
| 14385 |
|
|
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
|
| 14386 |
|
|
|
| 14387 |
|
|
roundchainout_output_register : stratixiii_mac_bit_register
|
| 14388 |
|
|
PORT MAP (
|
| 14389 |
|
|
datain => roundchainout_pip_reg,
|
| 14390 |
|
|
clk => roundchainout_clk_or,
|
| 14391 |
|
|
aclr => roundchainout_aclr_or,
|
| 14392 |
|
|
sload => roundchainout_sload_or,
|
| 14393 |
|
|
bypass_register => roundchainout_bypass_register_or,
|
| 14394 |
|
|
dataout => roundchainout_out_reg
|
| 14395 |
|
|
);
|
| 14396 |
|
|
|
| 14397 |
|
|
|
| 14398 |
|
|
--Instantiate the saturatechainout output Register
|
| 14399 |
|
|
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
|
| 14400 |
|
|
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
|
| 14401 |
|
|
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
|
| 14402 |
|
|
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
|
| 14403 |
|
|
ELSE "0000" ;
|
| 14404 |
|
|
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
|
| 14405 |
|
|
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
|
| 14406 |
|
|
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
|
| 14407 |
|
|
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
|
| 14408 |
|
|
ELSE "0000" ;
|
| 14409 |
|
|
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
|
| 14410 |
|
|
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14411 |
|
|
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
|
| 14412 |
|
|
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
|
| 14413 |
|
|
|
| 14414 |
|
|
saturatechainout_output_register : stratixiii_mac_bit_register
|
| 14415 |
|
|
PORT MAP (
|
| 14416 |
|
|
datain => saturatechainout_pip_reg,
|
| 14417 |
|
|
clk => saturatechainout_clk_or,
|
| 14418 |
|
|
aclr => saturatechainout_aclr_or,
|
| 14419 |
|
|
sload => saturatechainout_sload_or,
|
| 14420 |
|
|
bypass_register => saturatechainout_bypass_register_or,
|
| 14421 |
|
|
dataout => saturatechainout_out_reg
|
| 14422 |
|
|
);
|
| 14423 |
|
|
|
| 14424 |
|
|
--Instantiate the Carry chainout Adder
|
| 14425 |
|
|
chainout_adder : stratixiii_carry_chain_adder
|
| 14426 |
|
|
PORT MAP (
|
| 14427 |
|
|
dataa => rs_dataout_out_reg,
|
| 14428 |
|
|
datab => chainin_coa_in,
|
| 14429 |
|
|
dataout => coa_dataout
|
| 14430 |
|
|
);
|
| 14431 |
|
|
|
| 14432 |
|
|
|
| 14433 |
|
|
--Instantiate the carry chainout adder RS Block
|
| 14434 |
|
|
|
| 14435 |
|
|
|
| 14436 |
|
|
|
| 14437 |
|
|
coa_rs_block : stratixiii_round_saturate_block
|
| 14438 |
|
|
GENERIC MAP (
|
| 14439 |
|
|
dataa_width => dataa_width,
|
| 14440 |
|
|
datab_width => datab_width,
|
| 14441 |
|
|
operation_mode => operation_mode,
|
| 14442 |
|
|
round_mode => round_chain_out_mode,
|
| 14443 |
|
|
saturate_mode => saturate_chain_out_mode,
|
| 14444 |
|
|
saturate_width => saturate_chain_out_width,
|
| 14445 |
|
|
round_width => round_chain_out_width
|
| 14446 |
|
|
)
|
| 14447 |
|
|
PORT MAP (
|
| 14448 |
|
|
datain => coa_dataout,
|
| 14449 |
|
|
round => roundchainout_out_reg,
|
| 14450 |
|
|
saturate => saturatechainout_out_reg,
|
| 14451 |
|
|
signa => signa_pip_reg,
|
| 14452 |
|
|
signb => signb_pip_reg,
|
| 14453 |
|
|
datain_width => ssa_datain_width,
|
| 14454 |
|
|
dataout => coa_rs_dataout,
|
| 14455 |
|
|
saturationoverflow => coa_rs_saturation_overflow
|
| 14456 |
|
|
);
|
| 14457 |
|
|
|
| 14458 |
|
|
--Instantiate the rs_saturation_overflow output register (after COA)
|
| 14459 |
|
|
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
|
| 14460 |
|
|
ELSE "0001" WHEN (output_clock = "1")
|
| 14461 |
|
|
ELSE "0010" WHEN (output_clock = "2")
|
| 14462 |
|
|
ELSE "0011" WHEN (output_clock = "3")
|
| 14463 |
|
|
ELSE "0000" ;
|
| 14464 |
|
|
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
|
| 14465 |
|
|
ELSE "0001" WHEN (output_clear = "1")
|
| 14466 |
|
|
ELSE "0010" WHEN (output_clear = "2")
|
| 14467 |
|
|
ELSE "0011" WHEN (output_clear = "3")
|
| 14468 |
|
|
ELSE "0000" ;
|
| 14469 |
|
|
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
|
| 14470 |
|
|
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
|
| 14471 |
|
|
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
|
| 14472 |
|
|
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
|
| 14473 |
|
|
|
| 14474 |
|
|
coa_rs_saturation_overflow_register : stratixiii_mac_bit_register
|
| 14475 |
|
|
PORT MAP (
|
| 14476 |
|
|
datain => rs_saturation_overflow_out_reg,
|
| 14477 |
|
|
clk => coa_reg_clk_or,
|
| 14478 |
|
|
aclr => coa_reg_aclr_or,
|
| 14479 |
|
|
sload => coa_reg_sload_or,
|
| 14480 |
|
|
bypass_register => '1',
|
| 14481 |
|
|
dataout => coa_rs_saturation_overflow_out_reg
|
| 14482 |
|
|
);
|
| 14483 |
|
|
|
| 14484 |
|
|
|
| 14485 |
|
|
--Instantiate the rs_saturationchainout_overflow output register
|
| 14486 |
|
|
coa_rs_saturationchainout_overflow_register : stratixiii_mac_bit_register
|
| 14487 |
|
|
PORT MAP (
|
| 14488 |
|
|
datain => coa_rs_saturation_overflow,
|
| 14489 |
|
|
clk => coa_reg_clk_or,
|
| 14490 |
|
|
aclr => coa_reg_aclr_or,
|
| 14491 |
|
|
sload => coa_reg_sload_or,
|
| 14492 |
|
|
bypass_register => coa_reg_bypass_register_or,
|
| 14493 |
|
|
dataout => coa_rs_saturationchainout_overflow_out_reg
|
| 14494 |
|
|
);
|
| 14495 |
|
|
|
| 14496 |
|
|
|
| 14497 |
|
|
-- Instantiate the coa_rs_dataout output register
|
| 14498 |
|
|
coa_rs_dataout_register : stratixiii_mac_register
|
| 14499 |
|
|
GENERIC MAP (
|
| 14500 |
|
|
data_width => 72
|
| 14501 |
|
|
)
|
| 14502 |
|
|
PORT MAP (
|
| 14503 |
|
|
datain => coa_rs_dataout,
|
| 14504 |
|
|
clk => coa_reg_clk_or,
|
| 14505 |
|
|
aclr => coa_reg_aclr_or,
|
| 14506 |
|
|
sload => coa_reg_sload_or,
|
| 14507 |
|
|
bypass_register => coa_reg_bypass_register_or,
|
| 14508 |
|
|
dataout => coa_rs_dataout_out_reg
|
| 14509 |
|
|
);
|
| 14510 |
|
|
|
| 14511 |
|
|
--Instantiate the shift/Rotate Unit
|
| 14512 |
|
|
shift_rot_unit : stratixiii_rotate_shift_block
|
| 14513 |
|
|
GENERIC MAP (
|
| 14514 |
|
|
dataa_width => dataa_width,
|
| 14515 |
|
|
datab_width => datab_width
|
| 14516 |
|
|
)
|
| 14517 |
|
|
PORT MAP (
|
| 14518 |
|
|
datain => rs_dataout_out_reg,
|
| 14519 |
|
|
rotate => rotate_out_reg,
|
| 14520 |
|
|
shiftright => shiftright_out_reg,
|
| 14521 |
|
|
signa => signa_pip_reg,
|
| 14522 |
|
|
signb => signb_pip_reg,
|
| 14523 |
|
|
dataout => dataout_shift_rot
|
| 14524 |
|
|
);
|
| 14525 |
|
|
|
| 14526 |
|
|
--Assign the dataout depENDing on the mode of operation
|
| 14527 |
|
|
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
|
| 14528 |
|
|
ELSE dataout_shift_rot when (operation_mode = "shift")
|
| 14529 |
|
|
ELSE rs_dataout_out_reg;
|
| 14530 |
|
|
|
| 14531 |
|
|
|
| 14532 |
|
|
--Assign the loopbackout for loopback mode
|
| 14533 |
|
|
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
|
| 14534 |
|
|
ELSE (others => '0');
|
| 14535 |
|
|
|
| 14536 |
|
|
--Assign the saturation overflow output
|
| 14537 |
|
|
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
|
| 14538 |
|
|
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
|
| 14539 |
|
|
ELSE '0';
|
| 14540 |
|
|
|
| 14541 |
|
|
--Assign the saturationchainout overflow output
|
| 14542 |
|
|
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
|
| 14543 |
|
|
ELSE '0';
|
| 14544 |
|
|
|
| 14545 |
|
|
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
|
| 14546 |
|
|
ELSE dataout_tmp;
|
| 14547 |
|
|
loopbackout <= loopbackout_tmp(35 downto 18);
|
| 14548 |
|
|
overflow <= saturation_overflow_tmp;
|
| 14549 |
|
|
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
|
| 14550 |
|
|
END arch;
|
| 14551 |
|
|
----------------------------------------------------------------------------
|
| 14552 |
|
|
-- Module Name : stratixiii_io_pad
|
| 14553 |
|
|
-- Description : Simulation model for stratixiii IO pad
|
| 14554 |
|
|
----------------------------------------------------------------------------
|
| 14555 |
|
|
LIBRARY IEEE;
|
| 14556 |
|
|
USE ieee.std_logic_1164.all;
|
| 14557 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 14558 |
|
|
use IEEE.std_logic_arith.all;
|
| 14559 |
|
|
use IEEE.VITAL_Timing.all;
|
| 14560 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 14561 |
|
|
|
| 14562 |
|
|
ENTITY stratixiii_io_pad IS
|
| 14563 |
|
|
GENERIC (
|
| 14564 |
|
|
lpm_type : string := "stratixiii_io_pad");
|
| 14565 |
|
|
PORT (
|
| 14566 |
|
|
--INPUT PORTS
|
| 14567 |
|
|
|
| 14568 |
|
|
padin : IN std_logic := '0'; -- Input Pad
|
| 14569 |
|
|
--OUTPUT PORTS
|
| 14570 |
|
|
|
| 14571 |
|
|
padout : OUT std_logic); -- Output Pad
|
| 14572 |
|
|
END stratixiii_io_pad;
|
| 14573 |
|
|
|
| 14574 |
|
|
ARCHITECTURE arch OF stratixiii_io_pad IS
|
| 14575 |
|
|
|
| 14576 |
|
|
BEGIN
|
| 14577 |
|
|
padout <= padin;
|
| 14578 |
|
|
END arch;
|
| 14579 |
|
|
--///////////////////////////////////////////////////////////////////////////
|
| 14580 |
|
|
--
|
| 14581 |
|
|
-- Entity Name : stratixiii_mn_cntr
|
| 14582 |
|
|
--
|
| 14583 |
|
|
-- Description : Timing simulation model for the M and N counter. This is a
|
| 14584 |
|
|
-- common model for the input counter and the loop feedback
|
| 14585 |
|
|
-- counter of the StratixII PLL.
|
| 14586 |
|
|
--
|
| 14587 |
|
|
--///////////////////////////////////////////////////////////////////////////
|
| 14588 |
|
|
|
| 14589 |
|
|
LIBRARY IEEE;
|
| 14590 |
|
|
USE IEEE.std_logic_1164.all;
|
| 14591 |
|
|
USE IEEE.std_logic_arith.all;
|
| 14592 |
|
|
USE IEEE.std_logic_unsigned.all;
|
| 14593 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 14594 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 14595 |
|
|
|
| 14596 |
|
|
ENTITY stratixiii_mn_cntr is
|
| 14597 |
|
|
PORT( clk : IN std_logic;
|
| 14598 |
|
|
reset : IN std_logic := '0';
|
| 14599 |
|
|
cout : OUT std_logic;
|
| 14600 |
|
|
initial_value : IN integer := 1;
|
| 14601 |
|
|
modulus : IN integer := 1;
|
| 14602 |
|
|
time_delay : IN integer := 0
|
| 14603 |
|
|
);
|
| 14604 |
|
|
END stratixiii_mn_cntr;
|
| 14605 |
|
|
|
| 14606 |
|
|
ARCHITECTURE behave of stratixiii_mn_cntr is
|
| 14607 |
|
|
begin
|
| 14608 |
|
|
|
| 14609 |
|
|
process (clk, reset)
|
| 14610 |
|
|
variable count : integer := 1;
|
| 14611 |
|
|
variable first_rising_edge : boolean := true;
|
| 14612 |
|
|
variable tmp_cout : std_logic;
|
| 14613 |
|
|
begin
|
| 14614 |
|
|
if (reset = '1') then
|
| 14615 |
|
|
count := 1;
|
| 14616 |
|
|
tmp_cout := '0';
|
| 14617 |
|
|
first_rising_edge := true;
|
| 14618 |
|
|
elsif (clk'event) then
|
| 14619 |
|
|
if (clk = '1' and first_rising_edge) then
|
| 14620 |
|
|
first_rising_edge := false;
|
| 14621 |
|
|
tmp_cout := clk;
|
| 14622 |
|
|
elsif (not first_rising_edge) then
|
| 14623 |
|
|
if (count < modulus) then
|
| 14624 |
|
|
count := count + 1;
|
| 14625 |
|
|
else
|
| 14626 |
|
|
count := 1;
|
| 14627 |
|
|
tmp_cout := not tmp_cout;
|
| 14628 |
|
|
end if;
|
| 14629 |
|
|
end if;
|
| 14630 |
|
|
end if;
|
| 14631 |
|
|
cout <= transport tmp_cout after time_delay * 1 ps;
|
| 14632 |
|
|
end process;
|
| 14633 |
|
|
end behave;
|
| 14634 |
|
|
|
| 14635 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 14636 |
|
|
--
|
| 14637 |
|
|
-- Entity Name : stratixiii_scale_cntr
|
| 14638 |
|
|
--
|
| 14639 |
|
|
-- Description : Timing simulation model for the output scale-down counters.
|
| 14640 |
|
|
-- This is a common model for the C0, C1, C2, C3, C4 and C5
|
| 14641 |
|
|
-- output counters of the StratixII PLL.
|
| 14642 |
|
|
--
|
| 14643 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 14644 |
|
|
|
| 14645 |
|
|
LIBRARY IEEE;
|
| 14646 |
|
|
USE IEEE.std_logic_1164.all;
|
| 14647 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 14648 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 14649 |
|
|
|
| 14650 |
|
|
ENTITY stratixiii_scale_cntr is
|
| 14651 |
|
|
PORT( clk : IN std_logic;
|
| 14652 |
|
|
reset : IN std_logic := '0';
|
| 14653 |
|
|
initial : IN integer := 1;
|
| 14654 |
|
|
high : IN integer := 1;
|
| 14655 |
|
|
low : IN integer := 1;
|
| 14656 |
|
|
mode : IN string := "bypass";
|
| 14657 |
|
|
ph_tap : IN integer := 0;
|
| 14658 |
|
|
cout : OUT std_logic
|
| 14659 |
|
|
);
|
| 14660 |
|
|
END stratixiii_scale_cntr;
|
| 14661 |
|
|
|
| 14662 |
|
|
ARCHITECTURE behave of stratixiii_scale_cntr is
|
| 14663 |
|
|
begin
|
| 14664 |
|
|
process (clk, reset)
|
| 14665 |
|
|
variable tmp_cout : std_logic := '0';
|
| 14666 |
|
|
variable count : integer := 1;
|
| 14667 |
|
|
variable output_shift_count : integer := 1;
|
| 14668 |
|
|
variable first_rising_edge : boolean := false;
|
| 14669 |
|
|
begin
|
| 14670 |
|
|
if (reset = '1') then
|
| 14671 |
|
|
count := 1;
|
| 14672 |
|
|
output_shift_count := 1;
|
| 14673 |
|
|
tmp_cout := '0';
|
| 14674 |
|
|
first_rising_edge := false;
|
| 14675 |
|
|
elsif (clk'event) then
|
| 14676 |
|
|
if (mode = " off") then
|
| 14677 |
|
|
tmp_cout := '0';
|
| 14678 |
|
|
elsif (mode = "bypass") then
|
| 14679 |
|
|
tmp_cout := clk;
|
| 14680 |
|
|
first_rising_edge := true;
|
| 14681 |
|
|
elsif (not first_rising_edge) then
|
| 14682 |
|
|
if (clk = '1') then
|
| 14683 |
|
|
if (output_shift_count = initial) then
|
| 14684 |
|
|
tmp_cout := clk;
|
| 14685 |
|
|
first_rising_edge := true;
|
| 14686 |
|
|
else
|
| 14687 |
|
|
output_shift_count := output_shift_count + 1;
|
| 14688 |
|
|
end if;
|
| 14689 |
|
|
end if;
|
| 14690 |
|
|
elsif (output_shift_count < initial) then
|
| 14691 |
|
|
if (clk = '1') then
|
| 14692 |
|
|
output_shift_count := output_shift_count + 1;
|
| 14693 |
|
|
end if;
|
| 14694 |
|
|
else
|
| 14695 |
|
|
count := count + 1;
|
| 14696 |
|
|
if (mode = " even" and (count = (high*2) + 1)) then
|
| 14697 |
|
|
tmp_cout := '0';
|
| 14698 |
|
|
elsif (mode = " odd" and (count = high*2)) then
|
| 14699 |
|
|
tmp_cout := '0';
|
| 14700 |
|
|
elsif (count = (high + low)*2 + 1) then
|
| 14701 |
|
|
tmp_cout := '1';
|
| 14702 |
|
|
count := 1; -- reset count
|
| 14703 |
|
|
end if;
|
| 14704 |
|
|
end if;
|
| 14705 |
|
|
end if;
|
| 14706 |
|
|
cout <= transport tmp_cout;
|
| 14707 |
|
|
end process;
|
| 14708 |
|
|
|
| 14709 |
|
|
end behave;
|
| 14710 |
|
|
|
| 14711 |
|
|
--BEGIN MF PORTING DELETE
|
| 14712 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 14713 |
|
|
--
|
| 14714 |
|
|
-- Entity Name : stratixiii_pll_reg
|
| 14715 |
|
|
--
|
| 14716 |
|
|
-- Description : Simulation model for a simple DFF.
|
| 14717 |
|
|
-- This is required for the generation of the bit slip-signals.
|
| 14718 |
|
|
-- No timing, powers upto 0.
|
| 14719 |
|
|
--
|
| 14720 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 14721 |
|
|
LIBRARY IEEE;
|
| 14722 |
|
|
USE IEEE.std_logic_1164.all;
|
| 14723 |
|
|
|
| 14724 |
|
|
ENTITY stratixiii_pll_reg is
|
| 14725 |
|
|
PORT( clk : in std_logic;
|
| 14726 |
|
|
ena : in std_logic := '1';
|
| 14727 |
|
|
d : in std_logic;
|
| 14728 |
|
|
clrn : in std_logic := '1';
|
| 14729 |
|
|
prn : in std_logic := '1';
|
| 14730 |
|
|
q : out std_logic
|
| 14731 |
|
|
);
|
| 14732 |
|
|
end stratixiii_pll_reg;
|
| 14733 |
|
|
|
| 14734 |
|
|
ARCHITECTURE behave of stratixiii_pll_reg is
|
| 14735 |
|
|
begin
|
| 14736 |
|
|
process (clk, prn, clrn)
|
| 14737 |
|
|
variable q_reg : std_logic := '0';
|
| 14738 |
|
|
begin
|
| 14739 |
|
|
if (prn = '0') then
|
| 14740 |
|
|
q_reg := '1';
|
| 14741 |
|
|
elsif (clrn = '0') then
|
| 14742 |
|
|
q_reg := '0';
|
| 14743 |
|
|
elsif (clk'event and clk = '1' and (ena = '1')) then
|
| 14744 |
|
|
q_reg := D;
|
| 14745 |
|
|
end if;
|
| 14746 |
|
|
|
| 14747 |
|
|
Q <= q_reg;
|
| 14748 |
|
|
end process;
|
| 14749 |
|
|
end behave;
|
| 14750 |
|
|
--END MF PORTING DELETE
|
| 14751 |
|
|
--///////////////////////////////////////////////////////////////////////////
|
| 14752 |
|
|
--
|
| 14753 |
|
|
-- Entity Name : stratixiii_pll
|
| 14754 |
|
|
--
|
| 14755 |
|
|
-- Description : Timing simulation model for the StratixII PLL.
|
| 14756 |
|
|
-- In the functional mode, it is also the model for the altpll
|
| 14757 |
|
|
-- megafunction.
|
| 14758 |
|
|
--
|
| 14759 |
|
|
-- Limitations : Does not support Spread Spectrum and Bandwidth.
|
| 14760 |
|
|
--
|
| 14761 |
|
|
-- Outputs : Up to 10 output clocks, each defined by its own set of
|
| 14762 |
|
|
-- parameters. Locked output (active high) indicates when the
|
| 14763 |
|
|
-- PLL locks. clkbad and activeclock are used for
|
| 14764 |
|
|
-- clock switchover to indicate which input clock has gone
|
| 14765 |
|
|
-- bad, when the clock switchover initiates and which input
|
| 14766 |
|
|
-- clock is being used as the reference, respectively.
|
| 14767 |
|
|
-- scandataout is the data output of the serial scan chain.
|
| 14768 |
|
|
--
|
| 14769 |
|
|
--///////////////////////////////////////////////////////////////////////////
|
| 14770 |
|
|
LIBRARY IEEE, std;
|
| 14771 |
|
|
USE IEEE.std_logic_1164.all;
|
| 14772 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 14773 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 14774 |
|
|
USE STD.TEXTIO.all;
|
| 14775 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 14776 |
|
|
USE work.stratixiii_pllpack.all;
|
| 14777 |
|
|
USE work.stratixiii_mn_cntr;
|
| 14778 |
|
|
USE work.stratixiii_scale_cntr;
|
| 14779 |
|
|
USE work.stratixiii_dffe;
|
| 14780 |
|
|
USE work.stratixiii_pll_reg;
|
| 14781 |
|
|
|
| 14782 |
|
|
-- New Features : The list below outlines key new features in STRATIXIII:
|
| 14783 |
|
|
-- 1. Dynamic Phase Reconfiguration
|
| 14784 |
|
|
-- 2. Dynamic PLL Reconfiguration (different protocol)
|
| 14785 |
|
|
-- 3. More output counters
|
| 14786 |
|
|
|
| 14787 |
|
|
ENTITY stratixiii_pll is
|
| 14788 |
|
|
GENERIC (
|
| 14789 |
|
|
operation_mode : string := "normal";
|
| 14790 |
|
|
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
|
| 14791 |
|
|
compensate_clock : string := "clock0";
|
| 14792 |
|
|
|
| 14793 |
|
|
inclk0_input_frequency : integer := 0;
|
| 14794 |
|
|
inclk1_input_frequency : integer := 0;
|
| 14795 |
|
|
|
| 14796 |
|
|
self_reset_on_loss_lock : string := "off";
|
| 14797 |
|
|
switch_over_type : string := "auto";
|
| 14798 |
|
|
switch_over_counter : integer := 1;
|
| 14799 |
|
|
enable_switch_over_counter : string := "off";
|
| 14800 |
|
|
|
| 14801 |
|
|
dpa_multiply_by : integer := 0;
|
| 14802 |
|
|
dpa_divide_by : integer := 0;
|
| 14803 |
|
|
dpa_divider : integer := 0;
|
| 14804 |
|
|
|
| 14805 |
|
|
bandwidth : integer := 0;
|
| 14806 |
|
|
bandwidth_type : string := "auto";
|
| 14807 |
|
|
use_dc_coupling : string := "false";
|
| 14808 |
|
|
|
| 14809 |
|
|
|
| 14810 |
|
|
|
| 14811 |
|
|
lock_c : integer := 4;
|
| 14812 |
|
|
sim_gate_lock_device_behavior : string := "off";
|
| 14813 |
|
|
lock_high : integer := 0;
|
| 14814 |
|
|
lock_low : integer := 0;
|
| 14815 |
|
|
lock_window_ui : string := "0.05";
|
| 14816 |
|
|
lock_window : time := 5 ps;
|
| 14817 |
|
|
test_bypass_lock_detect : string := "off";
|
| 14818 |
|
|
|
| 14819 |
|
|
|
| 14820 |
|
|
clk0_output_frequency : integer := 0;
|
| 14821 |
|
|
clk0_multiply_by : integer := 0;
|
| 14822 |
|
|
clk0_divide_by : integer := 0;
|
| 14823 |
|
|
clk0_phase_shift : string := "0";
|
| 14824 |
|
|
clk0_duty_cycle : integer := 50;
|
| 14825 |
|
|
|
| 14826 |
|
|
clk1_output_frequency : integer := 0;
|
| 14827 |
|
|
clk1_multiply_by : integer := 0;
|
| 14828 |
|
|
clk1_divide_by : integer := 0;
|
| 14829 |
|
|
clk1_phase_shift : string := "0";
|
| 14830 |
|
|
clk1_duty_cycle : integer := 50;
|
| 14831 |
|
|
|
| 14832 |
|
|
clk2_output_frequency : integer := 0;
|
| 14833 |
|
|
clk2_multiply_by : integer := 0;
|
| 14834 |
|
|
clk2_divide_by : integer := 0;
|
| 14835 |
|
|
clk2_phase_shift : string := "0";
|
| 14836 |
|
|
clk2_duty_cycle : integer := 50;
|
| 14837 |
|
|
|
| 14838 |
|
|
clk3_output_frequency : integer := 0;
|
| 14839 |
|
|
clk3_multiply_by : integer := 0;
|
| 14840 |
|
|
clk3_divide_by : integer := 0;
|
| 14841 |
|
|
clk3_phase_shift : string := "0";
|
| 14842 |
|
|
clk3_duty_cycle : integer := 50;
|
| 14843 |
|
|
|
| 14844 |
|
|
clk4_output_frequency : integer := 0;
|
| 14845 |
|
|
clk4_multiply_by : integer := 0;
|
| 14846 |
|
|
clk4_divide_by : integer := 0;
|
| 14847 |
|
|
clk4_phase_shift : string := "0";
|
| 14848 |
|
|
clk4_duty_cycle : integer := 50;
|
| 14849 |
|
|
|
| 14850 |
|
|
clk5_output_frequency : integer := 0;
|
| 14851 |
|
|
clk5_multiply_by : integer := 0;
|
| 14852 |
|
|
clk5_divide_by : integer := 0;
|
| 14853 |
|
|
clk5_phase_shift : string := "0";
|
| 14854 |
|
|
clk5_duty_cycle : integer := 50;
|
| 14855 |
|
|
|
| 14856 |
|
|
clk6_output_frequency : integer := 0;
|
| 14857 |
|
|
clk6_multiply_by : integer := 0;
|
| 14858 |
|
|
clk6_divide_by : integer := 0;
|
| 14859 |
|
|
clk6_phase_shift : string := "0";
|
| 14860 |
|
|
clk6_duty_cycle : integer := 50;
|
| 14861 |
|
|
|
| 14862 |
|
|
clk7_output_frequency : integer := 0;
|
| 14863 |
|
|
clk7_multiply_by : integer := 0;
|
| 14864 |
|
|
clk7_divide_by : integer := 0;
|
| 14865 |
|
|
clk7_phase_shift : string := "0";
|
| 14866 |
|
|
clk7_duty_cycle : integer := 50;
|
| 14867 |
|
|
|
| 14868 |
|
|
clk8_output_frequency : integer := 0;
|
| 14869 |
|
|
clk8_multiply_by : integer := 0;
|
| 14870 |
|
|
clk8_divide_by : integer := 0;
|
| 14871 |
|
|
clk8_phase_shift : string := "0";
|
| 14872 |
|
|
clk8_duty_cycle : integer := 50;
|
| 14873 |
|
|
|
| 14874 |
|
|
clk9_output_frequency : integer := 0;
|
| 14875 |
|
|
clk9_multiply_by : integer := 0;
|
| 14876 |
|
|
clk9_divide_by : integer := 0;
|
| 14877 |
|
|
clk9_phase_shift : string := "0";
|
| 14878 |
|
|
clk9_duty_cycle : integer := 50;
|
| 14879 |
|
|
|
| 14880 |
|
|
|
| 14881 |
|
|
pfd_min : integer := 0;
|
| 14882 |
|
|
pfd_max : integer := 0;
|
| 14883 |
|
|
vco_min : integer := 0;
|
| 14884 |
|
|
vco_max : integer := 0;
|
| 14885 |
|
|
vco_center : integer := 0;
|
| 14886 |
|
|
|
| 14887 |
|
|
-- ADVANCED USER PARAMETERS
|
| 14888 |
|
|
m_initial : integer := 1;
|
| 14889 |
|
|
m : integer := 0;
|
| 14890 |
|
|
n : integer := 1;
|
| 14891 |
|
|
|
| 14892 |
|
|
c0_high : integer := 1;
|
| 14893 |
|
|
c0_low : integer := 1;
|
| 14894 |
|
|
c0_initial : integer := 1;
|
| 14895 |
|
|
c0_mode : string := "bypass";
|
| 14896 |
|
|
c0_ph : integer := 0;
|
| 14897 |
|
|
|
| 14898 |
|
|
c1_high : integer := 1;
|
| 14899 |
|
|
c1_low : integer := 1;
|
| 14900 |
|
|
c1_initial : integer := 1;
|
| 14901 |
|
|
c1_mode : string := "bypass";
|
| 14902 |
|
|
c1_ph : integer := 0;
|
| 14903 |
|
|
|
| 14904 |
|
|
c2_high : integer := 1;
|
| 14905 |
|
|
c2_low : integer := 1;
|
| 14906 |
|
|
c2_initial : integer := 1;
|
| 14907 |
|
|
c2_mode : string := "bypass";
|
| 14908 |
|
|
c2_ph : integer := 0;
|
| 14909 |
|
|
|
| 14910 |
|
|
c3_high : integer := 1;
|
| 14911 |
|
|
c3_low : integer := 1;
|
| 14912 |
|
|
c3_initial : integer := 1;
|
| 14913 |
|
|
c3_mode : string := "bypass";
|
| 14914 |
|
|
c3_ph : integer := 0;
|
| 14915 |
|
|
|
| 14916 |
|
|
c4_high : integer := 1;
|
| 14917 |
|
|
c4_low : integer := 1;
|
| 14918 |
|
|
c4_initial : integer := 1;
|
| 14919 |
|
|
c4_mode : string := "bypass";
|
| 14920 |
|
|
c4_ph : integer := 0;
|
| 14921 |
|
|
|
| 14922 |
|
|
c5_high : integer := 1;
|
| 14923 |
|
|
c5_low : integer := 1;
|
| 14924 |
|
|
c5_initial : integer := 1;
|
| 14925 |
|
|
c5_mode : string := "bypass";
|
| 14926 |
|
|
c5_ph : integer := 0;
|
| 14927 |
|
|
|
| 14928 |
|
|
c6_high : integer := 1;
|
| 14929 |
|
|
c6_low : integer := 1;
|
| 14930 |
|
|
c6_initial : integer := 1;
|
| 14931 |
|
|
c6_mode : string := "bypass";
|
| 14932 |
|
|
c6_ph : integer := 0;
|
| 14933 |
|
|
|
| 14934 |
|
|
c7_high : integer := 1;
|
| 14935 |
|
|
c7_low : integer := 1;
|
| 14936 |
|
|
c7_initial : integer := 1;
|
| 14937 |
|
|
c7_mode : string := "bypass";
|
| 14938 |
|
|
c7_ph : integer := 0;
|
| 14939 |
|
|
|
| 14940 |
|
|
c8_high : integer := 1;
|
| 14941 |
|
|
c8_low : integer := 1;
|
| 14942 |
|
|
c8_initial : integer := 1;
|
| 14943 |
|
|
c8_mode : string := "bypass";
|
| 14944 |
|
|
c8_ph : integer := 0;
|
| 14945 |
|
|
|
| 14946 |
|
|
c9_high : integer := 1;
|
| 14947 |
|
|
c9_low : integer := 1;
|
| 14948 |
|
|
c9_initial : integer := 1;
|
| 14949 |
|
|
c9_mode : string := "bypass";
|
| 14950 |
|
|
c9_ph : integer := 0;
|
| 14951 |
|
|
|
| 14952 |
|
|
m_ph : integer := 0;
|
| 14953 |
|
|
|
| 14954 |
|
|
clk0_counter : string := "unused";
|
| 14955 |
|
|
clk1_counter : string := "unused";
|
| 14956 |
|
|
clk2_counter : string := "unused";
|
| 14957 |
|
|
clk3_counter : string := "unused";
|
| 14958 |
|
|
clk4_counter : string := "unused";
|
| 14959 |
|
|
clk5_counter : string := "unused";
|
| 14960 |
|
|
clk6_counter : string := "unused";
|
| 14961 |
|
|
clk7_counter : string := "unused";
|
| 14962 |
|
|
clk8_counter : string := "unused";
|
| 14963 |
|
|
clk9_counter : string := "unused";
|
| 14964 |
|
|
|
| 14965 |
|
|
c1_use_casc_in : string := "off";
|
| 14966 |
|
|
c2_use_casc_in : string := "off";
|
| 14967 |
|
|
c3_use_casc_in : string := "off";
|
| 14968 |
|
|
c4_use_casc_in : string := "off";
|
| 14969 |
|
|
c5_use_casc_in : string := "off";
|
| 14970 |
|
|
c6_use_casc_in : string := "off";
|
| 14971 |
|
|
c7_use_casc_in : string := "off";
|
| 14972 |
|
|
c8_use_casc_in : string := "off";
|
| 14973 |
|
|
c9_use_casc_in : string := "off";
|
| 14974 |
|
|
|
| 14975 |
|
|
m_test_source : integer := -1;
|
| 14976 |
|
|
c0_test_source : integer := -1;
|
| 14977 |
|
|
c1_test_source : integer := -1;
|
| 14978 |
|
|
c2_test_source : integer := -1;
|
| 14979 |
|
|
c3_test_source : integer := -1;
|
| 14980 |
|
|
c4_test_source : integer := -1;
|
| 14981 |
|
|
c5_test_source : integer := -1;
|
| 14982 |
|
|
c6_test_source : integer := -1;
|
| 14983 |
|
|
c7_test_source : integer := -1;
|
| 14984 |
|
|
c8_test_source : integer := -1;
|
| 14985 |
|
|
c9_test_source : integer := -1;
|
| 14986 |
|
|
|
| 14987 |
|
|
vco_multiply_by : integer := 0;
|
| 14988 |
|
|
vco_divide_by : integer := 0;
|
| 14989 |
|
|
vco_post_scale : integer := 1;
|
| 14990 |
|
|
vco_frequency_control : string := "auto";
|
| 14991 |
|
|
vco_phase_shift_step : integer := 0;
|
| 14992 |
|
|
|
| 14993 |
|
|
charge_pump_current : integer := 10;
|
| 14994 |
|
|
loop_filter_r : string := " 1.0";
|
| 14995 |
|
|
loop_filter_c : integer := 0;
|
| 14996 |
|
|
|
| 14997 |
|
|
|
| 14998 |
|
|
pll_compensation_delay : integer := 0;
|
| 14999 |
|
|
simulation_type : string := "functional";
|
| 15000 |
|
|
lpm_type : string := "stratixiii_pll";
|
| 15001 |
|
|
|
| 15002 |
|
|
clk0_use_even_counter_mode : string := "off";
|
| 15003 |
|
|
clk1_use_even_counter_mode : string := "off";
|
| 15004 |
|
|
clk2_use_even_counter_mode : string := "off";
|
| 15005 |
|
|
clk3_use_even_counter_mode : string := "off";
|
| 15006 |
|
|
clk4_use_even_counter_mode : string := "off";
|
| 15007 |
|
|
clk5_use_even_counter_mode : string := "off";
|
| 15008 |
|
|
clk6_use_even_counter_mode : string := "off";
|
| 15009 |
|
|
clk7_use_even_counter_mode : string := "off";
|
| 15010 |
|
|
clk8_use_even_counter_mode : string := "off";
|
| 15011 |
|
|
clk9_use_even_counter_mode : string := "off";
|
| 15012 |
|
|
|
| 15013 |
|
|
clk0_use_even_counter_value : string := "off";
|
| 15014 |
|
|
clk1_use_even_counter_value : string := "off";
|
| 15015 |
|
|
clk2_use_even_counter_value : string := "off";
|
| 15016 |
|
|
clk3_use_even_counter_value : string := "off";
|
| 15017 |
|
|
clk4_use_even_counter_value : string := "off";
|
| 15018 |
|
|
clk5_use_even_counter_value : string := "off";
|
| 15019 |
|
|
clk6_use_even_counter_value : string := "off";
|
| 15020 |
|
|
clk7_use_even_counter_value : string := "off";
|
| 15021 |
|
|
clk8_use_even_counter_value : string := "off";
|
| 15022 |
|
|
clk9_use_even_counter_value : string := "off";
|
| 15023 |
|
|
|
| 15024 |
|
|
-- Test only
|
| 15025 |
|
|
init_block_reset_a_count : integer := 1;
|
| 15026 |
|
|
init_block_reset_b_count : integer := 1;
|
| 15027 |
|
|
charge_pump_current_bits : integer := 0;
|
| 15028 |
|
|
lock_window_ui_bits : integer := 0;
|
| 15029 |
|
|
loop_filter_c_bits : integer := 0;
|
| 15030 |
|
|
loop_filter_r_bits : integer := 0;
|
| 15031 |
|
|
test_counter_c0_delay_chain_bits : integer := 0;
|
| 15032 |
|
|
test_counter_c1_delay_chain_bits : integer := 0;
|
| 15033 |
|
|
test_counter_c2_delay_chain_bits : integer := 0;
|
| 15034 |
|
|
test_counter_c3_delay_chain_bits : integer := 0;
|
| 15035 |
|
|
test_counter_c4_delay_chain_bits : integer := 0;
|
| 15036 |
|
|
test_counter_c5_delay_chain_bits : integer := 0;
|
| 15037 |
|
|
test_counter_c6_delay_chain_bits : integer := 0;
|
| 15038 |
|
|
test_counter_c7_delay_chain_bits : integer := 0;
|
| 15039 |
|
|
test_counter_c8_delay_chain_bits : integer := 0;
|
| 15040 |
|
|
test_counter_c9_delay_chain_bits : integer := 0;
|
| 15041 |
|
|
test_counter_m_delay_chain_bits : integer := 0;
|
| 15042 |
|
|
test_counter_n_delay_chain_bits : integer := 0;
|
| 15043 |
|
|
test_feedback_comp_delay_chain_bits : integer := 0;
|
| 15044 |
|
|
test_input_comp_delay_chain_bits : integer := 0;
|
| 15045 |
|
|
test_volt_reg_output_mode_bits : integer := 0;
|
| 15046 |
|
|
test_volt_reg_output_voltage_bits : integer := 0;
|
| 15047 |
|
|
test_volt_reg_test_mode : string := "false";
|
| 15048 |
|
|
vco_range_detector_high_bits : integer := -1;
|
| 15049 |
|
|
vco_range_detector_low_bits : integer := -1;
|
| 15050 |
|
|
scan_chain_mif_file : string := "";
|
| 15051 |
|
|
dpa_output_clock_phase_shift : integer := 0;
|
| 15052 |
|
|
test_counter_c3_sclk_delay_chain_bits : integer := -1;
|
| 15053 |
|
|
test_counter_c4_sclk_delay_chain_bits : integer := -1;
|
| 15054 |
|
|
test_counter_c5_lden_delay_chain_bits : integer := -1;
|
| 15055 |
|
|
test_counter_c6_lden_delay_chain_bits : integer := -1;
|
| 15056 |
|
|
|
| 15057 |
|
|
-- Simulation only generics
|
| 15058 |
|
|
family_name : string := "StratixIII";
|
| 15059 |
|
|
|
| 15060 |
|
|
-- VITAL generics
|
| 15061 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 15062 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 15063 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 15064 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 15065 |
|
|
TimingChecksOn : Boolean := true;
|
| 15066 |
|
|
InstancePath : STRING := "*";
|
| 15067 |
|
|
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
|
| 15068 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
| 15069 |
|
|
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
|
| 15070 |
|
|
tipd_areset : VitalDelayType01 := DefPropDelay01;
|
| 15071 |
|
|
tipd_fbin : VitalDelayType01 := DefPropDelay01;
|
| 15072 |
|
|
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
|
| 15073 |
|
|
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
|
| 15074 |
|
|
tipd_scandata : VitalDelayType01 := DefPropDelay01;
|
| 15075 |
|
|
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
|
| 15076 |
|
|
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
|
| 15077 |
|
|
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
|
| 15078 |
|
|
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
|
| 15079 |
|
|
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
|
| 15080 |
|
|
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 15081 |
|
|
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 15082 |
|
|
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 15083 |
|
|
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 15084 |
|
|
use_vco_bypass : string := "false"
|
| 15085 |
|
|
);
|
| 15086 |
|
|
|
| 15087 |
|
|
PORT
|
| 15088 |
|
|
(
|
| 15089 |
|
|
inclk : in std_logic_vector(1 downto 0);
|
| 15090 |
|
|
fbin : in std_logic := '0';
|
| 15091 |
|
|
fbout : out std_logic;
|
| 15092 |
|
|
clkswitch : in std_logic := '0';
|
| 15093 |
|
|
areset : in std_logic := '0';
|
| 15094 |
|
|
pfdena : in std_logic := '1';
|
| 15095 |
|
|
scandata : in std_logic := '0';
|
| 15096 |
|
|
scanclk : in std_logic := '0';
|
| 15097 |
|
|
scanclkena : in std_logic := '1';
|
| 15098 |
|
|
configupdate : in std_logic := '0';
|
| 15099 |
|
|
clk : out std_logic_vector(9 downto 0);
|
| 15100 |
|
|
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
|
| 15101 |
|
|
phaseupdown : in std_logic := '0';
|
| 15102 |
|
|
phasestep : in std_logic := '0';
|
| 15103 |
|
|
clkbad : out std_logic_vector(1 downto 0);
|
| 15104 |
|
|
activeclock : out std_logic;
|
| 15105 |
|
|
locked : out std_logic;
|
| 15106 |
|
|
scandataout : out std_logic;
|
| 15107 |
|
|
scandone : out std_logic;
|
| 15108 |
|
|
phasedone : out std_logic;
|
| 15109 |
|
|
vcooverrange : out std_logic;
|
| 15110 |
|
|
vcounderrange : out std_logic
|
| 15111 |
|
|
|
| 15112 |
|
|
);
|
| 15113 |
|
|
END stratixiii_pll;
|
| 15114 |
|
|
|
| 15115 |
|
|
ARCHITECTURE vital_pll of stratixiii_pll is
|
| 15116 |
|
|
|
| 15117 |
|
|
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
|
| 15118 |
|
|
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
|
| 15119 |
|
|
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
|
| 15120 |
|
|
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
|
| 15121 |
|
|
|
| 15122 |
|
|
-- internal advanced parameter signals
|
| 15123 |
|
|
signal i_vco_min : integer := vco_min * (vco_post_scale/2);
|
| 15124 |
|
|
signal i_vco_max : integer := vco_max * (vco_post_scale/2);
|
| 15125 |
|
|
signal i_vco_center : integer;
|
| 15126 |
|
|
signal i_pfd_min : integer;
|
| 15127 |
|
|
signal i_pfd_max : integer;
|
| 15128 |
|
|
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
|
| 15129 |
|
|
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
|
| 15130 |
|
|
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
|
| 15131 |
|
|
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
|
| 15132 |
|
|
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
|
| 15133 |
|
|
signal c_mode_val : str_array(0 to 9);
|
| 15134 |
|
|
|
| 15135 |
|
|
-- old values
|
| 15136 |
|
|
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
|
| 15137 |
|
|
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
|
| 15138 |
|
|
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
|
| 15139 |
|
|
signal c_mode_val_old : str_array(0 to 9);
|
| 15140 |
|
|
-- hold registers
|
| 15141 |
|
|
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
|
| 15142 |
|
|
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
|
| 15143 |
|
|
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
|
| 15144 |
|
|
signal c_mode_val_hold : str_array(0 to 9);
|
| 15145 |
|
|
|
| 15146 |
|
|
-- temp registers
|
| 15147 |
|
|
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
|
| 15148 |
|
|
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
|
| 15149 |
|
|
|
| 15150 |
|
|
signal i_clk9_counter : integer := 9;
|
| 15151 |
|
|
signal i_clk8_counter : integer := 8;
|
| 15152 |
|
|
signal i_clk7_counter : integer := 7;
|
| 15153 |
|
|
signal i_clk6_counter : integer := 6;
|
| 15154 |
|
|
signal i_clk5_counter : integer := 5;
|
| 15155 |
|
|
signal real_lock_high : integer := 0;
|
| 15156 |
|
|
signal i_clk4_counter : integer := 4;
|
| 15157 |
|
|
signal i_clk3_counter : integer := 3;
|
| 15158 |
|
|
signal i_clk2_counter : integer := 2;
|
| 15159 |
|
|
signal i_clk1_counter : integer := 1;
|
| 15160 |
|
|
signal i_clk0_counter : integer := 0;
|
| 15161 |
|
|
signal i_charge_pump_current : integer;
|
| 15162 |
|
|
signal i_loop_filter_r : integer;
|
| 15163 |
|
|
|
| 15164 |
|
|
-- end internal advanced parameter signals
|
| 15165 |
|
|
|
| 15166 |
|
|
-- CONSTANTS
|
| 15167 |
|
|
CONSTANT SCAN_CHAIN : integer := 144;
|
| 15168 |
|
|
CONSTANT GPP_SCAN_CHAIN : integer := 234;
|
| 15169 |
|
|
CONSTANT FAST_SCAN_CHAIN : integer := 180;
|
| 15170 |
|
|
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
|
| 15171 |
|
|
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
|
| 15172 |
|
|
|
| 15173 |
|
|
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
|
| 15174 |
|
|
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
|
| 15175 |
|
|
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
|
| 15176 |
|
|
|
| 15177 |
|
|
CONSTANT num_phase_taps : integer := 8;
|
| 15178 |
|
|
-- signals
|
| 15179 |
|
|
|
| 15180 |
|
|
signal vcc : std_logic := '1';
|
| 15181 |
|
|
|
| 15182 |
|
|
signal fbclk : std_logic;
|
| 15183 |
|
|
signal refclk : std_logic;
|
| 15184 |
|
|
signal vco_over : std_logic := '0';
|
| 15185 |
|
|
signal vco_under : std_logic := '1';
|
| 15186 |
|
|
|
| 15187 |
|
|
signal pll_locked : boolean := false;
|
| 15188 |
|
|
|
| 15189 |
|
|
|
| 15190 |
|
|
signal c_clk : std_logic_array(0 to 9);
|
| 15191 |
|
|
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
|
| 15192 |
|
|
|
| 15193 |
|
|
-- signals to assign values to counter params
|
| 15194 |
|
|
signal m_val : integer := 1;
|
| 15195 |
|
|
signal n_val : integer := 1;
|
| 15196 |
|
|
signal m_ph_val : integer := 0;
|
| 15197 |
|
|
signal m_ph_initial : integer := 0;
|
| 15198 |
|
|
signal m_ph_val_tmp : integer := 0;
|
| 15199 |
|
|
signal m_initial_val : integer := m_initial;
|
| 15200 |
|
|
|
| 15201 |
|
|
signal m_mode_val : string(1 to 6) := " ";
|
| 15202 |
|
|
signal n_mode_val : string(1 to 6) := " ";
|
| 15203 |
|
|
signal lfc_val : integer := 0;
|
| 15204 |
|
|
signal cp_curr_val : integer := 0;
|
| 15205 |
|
|
signal lfr_val : string(1 to 2) := " ";
|
| 15206 |
|
|
|
| 15207 |
|
|
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
|
| 15208 |
|
|
signal cp_curr_val_bit_setting : std_logic_vector(14 to 16) := (OTHERS => '0');
|
| 15209 |
|
|
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
|
| 15210 |
|
|
signal lfr_val_bit_setting : std_logic_vector(3 to 7) := (OTHERS => '0');
|
| 15211 |
|
|
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
|
| 15212 |
|
|
signal lfc_val_bit_setting : std_logic_vector(1 to 2) := (OTHERS => '0');
|
| 15213 |
|
|
|
| 15214 |
|
|
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
|
| 15215 |
|
|
-- old values
|
| 15216 |
|
|
signal m_val_old : integer := 1;
|
| 15217 |
|
|
signal n_val_old : integer := 1;
|
| 15218 |
|
|
signal m_mode_val_old : string(1 to 6) := " ";
|
| 15219 |
|
|
signal n_mode_val_old : string(1 to 6) := " ";
|
| 15220 |
|
|
signal m_ph_val_old : integer := 0;
|
| 15221 |
|
|
signal lfc_old : integer := 0;
|
| 15222 |
|
|
signal cp_curr_old : integer := 0;
|
| 15223 |
|
|
signal lfr_old : string(1 to 2) := " ";
|
| 15224 |
|
|
signal num_output_cntrs : integer := 10;
|
| 15225 |
|
|
signal scanclk_period : time := 1 ps;
|
| 15226 |
|
|
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
|
| 15227 |
|
|
|
| 15228 |
|
|
|
| 15229 |
|
|
signal clk_pfd : std_logic_vector(0 to 9);
|
| 15230 |
|
|
signal clk0_tmp : std_logic;
|
| 15231 |
|
|
signal clk1_tmp : std_logic;
|
| 15232 |
|
|
signal clk2_tmp : std_logic;
|
| 15233 |
|
|
signal clk3_tmp : std_logic;
|
| 15234 |
|
|
signal clk4_tmp : std_logic;
|
| 15235 |
|
|
signal clk5_tmp : std_logic;
|
| 15236 |
|
|
signal clk6_tmp : std_logic;
|
| 15237 |
|
|
signal clk7_tmp : std_logic;
|
| 15238 |
|
|
signal clk8_tmp : std_logic;
|
| 15239 |
|
|
signal clk9_tmp : std_logic;
|
| 15240 |
|
|
|
| 15241 |
|
|
signal update_conf_latches : std_logic := '0';
|
| 15242 |
|
|
signal update_conf_latches_reg : std_logic := '0';
|
| 15243 |
|
|
|
| 15244 |
|
|
signal clkin : std_logic := '0';
|
| 15245 |
|
|
signal gate_locked : std_logic := '0';
|
| 15246 |
|
|
signal pfd_locked : std_logic := '0';
|
| 15247 |
|
|
signal lock : std_logic := '0';
|
| 15248 |
|
|
signal about_to_lock : boolean := false;
|
| 15249 |
|
|
signal reconfig_err : boolean := false;
|
| 15250 |
|
|
|
| 15251 |
|
|
signal inclk_c0 : std_logic;
|
| 15252 |
|
|
signal inclk_c1 : std_logic;
|
| 15253 |
|
|
signal inclk_c2 : std_logic;
|
| 15254 |
|
|
signal inclk_c3 : std_logic;
|
| 15255 |
|
|
signal inclk_c4 : std_logic;
|
| 15256 |
|
|
signal inclk_c5 : std_logic;
|
| 15257 |
|
|
signal inclk_c6 : std_logic;
|
| 15258 |
|
|
signal inclk_c7 : std_logic;
|
| 15259 |
|
|
signal inclk_c8 : std_logic;
|
| 15260 |
|
|
signal inclk_c9 : std_logic;
|
| 15261 |
|
|
signal inclk_m : std_logic;
|
| 15262 |
|
|
signal devpor : std_logic;
|
| 15263 |
|
|
signal devclrn : std_logic;
|
| 15264 |
|
|
|
| 15265 |
|
|
signal inclk0_ipd : std_logic;
|
| 15266 |
|
|
signal inclk1_ipd : std_logic;
|
| 15267 |
|
|
signal pfdena_ipd : std_logic;
|
| 15268 |
|
|
signal areset_ipd : std_logic;
|
| 15269 |
|
|
signal fbin_ipd : std_logic;
|
| 15270 |
|
|
signal scanclk_ipd : std_logic;
|
| 15271 |
|
|
signal scanclkena_ipd, scanclkena_reg : std_logic;
|
| 15272 |
|
|
signal scandata_ipd : std_logic;
|
| 15273 |
|
|
signal clkswitch_ipd : std_logic;
|
| 15274 |
|
|
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
|
| 15275 |
|
|
signal phaseupdown_ipd : std_logic;
|
| 15276 |
|
|
signal phasestep_ipd : std_logic;
|
| 15277 |
|
|
signal configupdate_ipd : std_logic;
|
| 15278 |
|
|
-- registered signals
|
| 15279 |
|
|
|
| 15280 |
|
|
signal sig_offset : time := 0 ps;
|
| 15281 |
|
|
signal sig_refclk_time : time := 0 ps;
|
| 15282 |
|
|
signal sig_fbclk_period : time := 0 ps;
|
| 15283 |
|
|
signal sig_vco_period_was_phase_adjusted : boolean := false;
|
| 15284 |
|
|
signal sig_phase_adjust_was_scheduled : boolean := false;
|
| 15285 |
|
|
signal sig_stop_vco : std_logic := '0';
|
| 15286 |
|
|
signal sig_m_times_vco_period : time := 0 ps;
|
| 15287 |
|
|
signal sig_new_m_times_vco_period : time := 0 ps;
|
| 15288 |
|
|
signal sig_got_refclk_posedge : boolean := false;
|
| 15289 |
|
|
signal sig_got_fbclk_posedge : boolean := false;
|
| 15290 |
|
|
signal sig_got_second_refclk : boolean := false;
|
| 15291 |
|
|
|
| 15292 |
|
|
signal m_delay : integer := 0;
|
| 15293 |
|
|
signal n_delay : integer := 0;
|
| 15294 |
|
|
|
| 15295 |
|
|
signal inclk1_tmp : std_logic := '0';
|
| 15296 |
|
|
|
| 15297 |
|
|
|
| 15298 |
|
|
signal reset_low : std_logic := '0';
|
| 15299 |
|
|
|
| 15300 |
|
|
-- Phase Reconfig
|
| 15301 |
|
|
|
| 15302 |
|
|
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
|
| 15303 |
|
|
|
| 15304 |
|
|
SIGNAL phaseupdown_reg : std_logic := '0';
|
| 15305 |
|
|
SIGNAL phasestep_reg : std_logic := '0';
|
| 15306 |
|
|
SIGNAL phasestep_high_count : integer := 0;
|
| 15307 |
|
|
SIGNAL update_phase : std_logic := '0';
|
| 15308 |
|
|
|
| 15309 |
|
|
signal scandataout_tmp : std_logic := '0';
|
| 15310 |
|
|
signal scandata_in : std_logic := '0';
|
| 15311 |
|
|
signal scandata_out : std_logic := '0';
|
| 15312 |
|
|
signal scandone_tmp : std_logic := '1';
|
| 15313 |
|
|
signal initiate_reconfig : std_logic := '0';
|
| 15314 |
|
|
|
| 15315 |
|
|
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
|
| 15316 |
|
|
|
| 15317 |
|
|
signal schedule_vco : std_logic := '0';
|
| 15318 |
|
|
|
| 15319 |
|
|
signal areset_ena_sig : std_logic := '0';
|
| 15320 |
|
|
signal pll_in_test_mode : boolean := false;
|
| 15321 |
|
|
|
| 15322 |
|
|
signal inclk_c_from_vco : std_logic_array(0 to 9);
|
| 15323 |
|
|
|
| 15324 |
|
|
signal inclk_m_from_vco : std_logic;
|
| 15325 |
|
|
|
| 15326 |
|
|
COMPONENT stratixiii_mn_cntr
|
| 15327 |
|
|
PORT (
|
| 15328 |
|
|
clk : IN std_logic;
|
| 15329 |
|
|
reset : IN std_logic := '0';
|
| 15330 |
|
|
cout : OUT std_logic;
|
| 15331 |
|
|
initial_value : IN integer := 1;
|
| 15332 |
|
|
modulus : IN integer := 1;
|
| 15333 |
|
|
time_delay : IN integer := 0
|
| 15334 |
|
|
);
|
| 15335 |
|
|
END COMPONENT;
|
| 15336 |
|
|
|
| 15337 |
|
|
COMPONENT stratixiii_scale_cntr
|
| 15338 |
|
|
PORT (
|
| 15339 |
|
|
clk : IN std_logic;
|
| 15340 |
|
|
reset : IN std_logic := '0';
|
| 15341 |
|
|
cout : OUT std_logic;
|
| 15342 |
|
|
initial : IN integer := 1;
|
| 15343 |
|
|
high : IN integer := 1;
|
| 15344 |
|
|
low : IN integer := 1;
|
| 15345 |
|
|
mode : IN string := "bypass";
|
| 15346 |
|
|
ph_tap : IN integer := 0
|
| 15347 |
|
|
);
|
| 15348 |
|
|
END COMPONENT;
|
| 15349 |
|
|
|
| 15350 |
|
|
COMPONENT stratixiii_dffe
|
| 15351 |
|
|
GENERIC(
|
| 15352 |
|
|
TimingChecksOn: Boolean := true;
|
| 15353 |
|
|
InstancePath: STRING := "*";
|
| 15354 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 15355 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 15356 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 15357 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
| 15358 |
|
|
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 15359 |
|
|
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 15360 |
|
|
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 15361 |
|
|
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 15362 |
|
|
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 15363 |
|
|
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 15364 |
|
|
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 15365 |
|
|
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 15366 |
|
|
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
| 15367 |
|
|
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
| 15368 |
|
|
tipd_D : VitalDelayType01 := DefPropDelay01;
|
| 15369 |
|
|
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
|
| 15370 |
|
|
tipd_PRN : VitalDelayType01 := DefPropDelay01;
|
| 15371 |
|
|
tipd_CLK : VitalDelayType01 := DefPropDelay01;
|
| 15372 |
|
|
tipd_ENA : VitalDelayType01 := DefPropDelay01);
|
| 15373 |
|
|
|
| 15374 |
|
|
PORT(
|
| 15375 |
|
|
Q : out STD_LOGIC := '0';
|
| 15376 |
|
|
D : in STD_LOGIC := '1';
|
| 15377 |
|
|
CLRN : in STD_LOGIC := '1';
|
| 15378 |
|
|
PRN : in STD_LOGIC := '1';
|
| 15379 |
|
|
CLK : in STD_LOGIC := '0';
|
| 15380 |
|
|
ENA : in STD_LOGIC := '1');
|
| 15381 |
|
|
END COMPONENT;
|
| 15382 |
|
|
|
| 15383 |
|
|
COMPONENT stratixiii_pll_reg
|
| 15384 |
|
|
PORT(
|
| 15385 |
|
|
Q : out STD_LOGIC := '0';
|
| 15386 |
|
|
D : in STD_LOGIC := '1';
|
| 15387 |
|
|
CLRN : in STD_LOGIC := '1';
|
| 15388 |
|
|
PRN : in STD_LOGIC := '1';
|
| 15389 |
|
|
CLK : in STD_LOGIC := '0';
|
| 15390 |
|
|
ENA : in STD_LOGIC := '1');
|
| 15391 |
|
|
END COMPONENT;
|
| 15392 |
|
|
|
| 15393 |
|
|
begin
|
| 15394 |
|
|
|
| 15395 |
|
|
----------------------
|
| 15396 |
|
|
-- INPUT PATH DELAYs
|
| 15397 |
|
|
----------------------
|
| 15398 |
|
|
WireDelay : block
|
| 15399 |
|
|
begin
|
| 15400 |
|
|
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
|
| 15401 |
|
|
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
|
| 15402 |
|
|
VitalWireDelay (areset_ipd, areset, tipd_areset);
|
| 15403 |
|
|
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
|
| 15404 |
|
|
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
|
| 15405 |
|
|
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
|
| 15406 |
|
|
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
|
| 15407 |
|
|
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
|
| 15408 |
|
|
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
|
| 15409 |
|
|
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
|
| 15410 |
|
|
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
|
| 15411 |
|
|
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
|
| 15412 |
|
|
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
|
| 15413 |
|
|
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
|
| 15414 |
|
|
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
|
| 15415 |
|
|
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
|
| 15416 |
|
|
|
| 15417 |
|
|
end block;
|
| 15418 |
|
|
|
| 15419 |
|
|
inclk_m <= fbclk when m_test_source = 0 else
|
| 15420 |
|
|
refclk when m_test_source = 1 else
|
| 15421 |
|
|
inclk_m_from_vco;
|
| 15422 |
|
|
|
| 15423 |
|
|
areset_ena_sig <= areset_ipd or sig_stop_vco;
|
| 15424 |
|
|
|
| 15425 |
|
|
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
|
| 15426 |
|
|
c1_test_source /= -1 or c2_test_source /= -1 or
|
| 15427 |
|
|
c3_test_source /= -1 or c4_test_source /= -1 or
|
| 15428 |
|
|
c5_test_source /= -1 or c6_test_source /= -1 or
|
| 15429 |
|
|
c7_test_source /= -1 or c8_test_source /= -1 or
|
| 15430 |
|
|
c9_test_source /= -1)
|
| 15431 |
|
|
else
|
| 15432 |
|
|
false;
|
| 15433 |
|
|
|
| 15434 |
|
|
|
| 15435 |
|
|
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
|
| 15436 |
|
|
m1 : stratixiii_mn_cntr
|
| 15437 |
|
|
port map ( clk => inclk_m,
|
| 15438 |
|
|
reset => areset_ena_sig,
|
| 15439 |
|
|
cout => fbclk,
|
| 15440 |
|
|
initial_value => m_initial_val,
|
| 15441 |
|
|
modulus => m_val,
|
| 15442 |
|
|
time_delay => m_delay
|
| 15443 |
|
|
);
|
| 15444 |
|
|
|
| 15445 |
|
|
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
|
| 15446 |
|
|
-- in different simulation deltas.
|
| 15447 |
|
|
inclk1_tmp <= inclk1_ipd;
|
| 15448 |
|
|
|
| 15449 |
|
|
|
| 15450 |
|
|
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
|
| 15451 |
|
|
variable input_value : std_logic := '0';
|
| 15452 |
|
|
variable current_clock : integer := 0;
|
| 15453 |
|
|
variable clk0_count, clk1_count : integer := 0;
|
| 15454 |
|
|
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
|
| 15455 |
|
|
variable primary_clk_is_bad : boolean := false;
|
| 15456 |
|
|
variable current_clk_is_bad : boolean := false;
|
| 15457 |
|
|
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
|
| 15458 |
|
|
variable switch_over_count : integer := 0;
|
| 15459 |
|
|
variable active_clock : std_logic := '0';
|
| 15460 |
|
|
variable external_switch : boolean := false;
|
| 15461 |
|
|
begin
|
| 15462 |
|
|
if (now = 0 ps) then
|
| 15463 |
|
|
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
|
| 15464 |
|
|
current_clock := 1;
|
| 15465 |
|
|
active_clock := '1';
|
| 15466 |
|
|
end if;
|
| 15467 |
|
|
end if;
|
| 15468 |
|
|
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
|
| 15469 |
|
|
external_switch := true;
|
| 15470 |
|
|
elsif (switch_over_type = "manual") then
|
| 15471 |
|
|
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
|
| 15472 |
|
|
if (current_clock = 0) then
|
| 15473 |
|
|
current_clock := 1;
|
| 15474 |
|
|
active_clock := '1';
|
| 15475 |
|
|
clkin <= transport inclk1_tmp;
|
| 15476 |
|
|
elsif (current_clock = 1) then
|
| 15477 |
|
|
current_clock := 0;
|
| 15478 |
|
|
active_clock := '0';
|
| 15479 |
|
|
clkin <= transport inclk0_ipd;
|
| 15480 |
|
|
end if;
|
| 15481 |
|
|
end if;
|
| 15482 |
|
|
end if;
|
| 15483 |
|
|
-- save the current inclk event value
|
| 15484 |
|
|
if (inclk0_ipd'event) then
|
| 15485 |
|
|
input_value := inclk0_ipd;
|
| 15486 |
|
|
elsif (inclk1_tmp'event) then
|
| 15487 |
|
|
input_value := inclk1_tmp;
|
| 15488 |
|
|
end if;
|
| 15489 |
|
|
|
| 15490 |
|
|
-- check if either input clk is bad
|
| 15491 |
|
|
if (inclk0_ipd'event and inclk0_ipd = '1') then
|
| 15492 |
|
|
clk0_count := clk0_count + 1;
|
| 15493 |
|
|
clk0_is_bad := '0';
|
| 15494 |
|
|
clk1_count := 0;
|
| 15495 |
|
|
if (clk0_count > 2) then
|
| 15496 |
|
|
-- no event on other clk for 2 cycles
|
| 15497 |
|
|
clk1_is_bad := '1';
|
| 15498 |
|
|
if (current_clock = 1) then
|
| 15499 |
|
|
current_clk_is_bad := true;
|
| 15500 |
|
|
end if;
|
| 15501 |
|
|
end if;
|
| 15502 |
|
|
end if;
|
| 15503 |
|
|
if (inclk1_tmp'event and inclk1_tmp = '1') then
|
| 15504 |
|
|
clk1_count := clk1_count + 1;
|
| 15505 |
|
|
clk1_is_bad := '0';
|
| 15506 |
|
|
clk0_count := 0;
|
| 15507 |
|
|
if (clk1_count > 2) then
|
| 15508 |
|
|
-- no event on other clk for 2 cycles
|
| 15509 |
|
|
clk0_is_bad := '1';
|
| 15510 |
|
|
if (current_clock = 0) then
|
| 15511 |
|
|
current_clk_is_bad := true;
|
| 15512 |
|
|
end if;
|
| 15513 |
|
|
end if;
|
| 15514 |
|
|
end if;
|
| 15515 |
|
|
|
| 15516 |
|
|
-- check if the bad clk is the primary clock
|
| 15517 |
|
|
if (clk0_is_bad = '1') then
|
| 15518 |
|
|
primary_clk_is_bad := true;
|
| 15519 |
|
|
else
|
| 15520 |
|
|
primary_clk_is_bad := false;
|
| 15521 |
|
|
end if;
|
| 15522 |
|
|
|
| 15523 |
|
|
-- actual switching
|
| 15524 |
|
|
if (inclk0_ipd'event and current_clock = 0) then
|
| 15525 |
|
|
if (external_switch) then
|
| 15526 |
|
|
if (not got_curr_clk_falling_edge_after_clkswitch) then
|
| 15527 |
|
|
if (inclk0_ipd = '0') then
|
| 15528 |
|
|
got_curr_clk_falling_edge_after_clkswitch := true;
|
| 15529 |
|
|
end if;
|
| 15530 |
|
|
clkin <= transport inclk0_ipd;
|
| 15531 |
|
|
end if;
|
| 15532 |
|
|
else
|
| 15533 |
|
|
clkin <= transport inclk0_ipd;
|
| 15534 |
|
|
end if;
|
| 15535 |
|
|
elsif (inclk1_tmp'event and current_clock = 1) then
|
| 15536 |
|
|
if (external_switch) then
|
| 15537 |
|
|
if (not got_curr_clk_falling_edge_after_clkswitch) then
|
| 15538 |
|
|
if (inclk1_tmp = '0') then
|
| 15539 |
|
|
got_curr_clk_falling_edge_after_clkswitch := true;
|
| 15540 |
|
|
end if;
|
| 15541 |
|
|
clkin <= transport inclk1_tmp;
|
| 15542 |
|
|
end if;
|
| 15543 |
|
|
else
|
| 15544 |
|
|
clkin <= transport inclk1_tmp;
|
| 15545 |
|
|
end if;
|
| 15546 |
|
|
else
|
| 15547 |
|
|
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
|
| 15548 |
|
|
switch_over_count := switch_over_count + 1;
|
| 15549 |
|
|
end if;
|
| 15550 |
|
|
if ((input_value = '0')) then
|
| 15551 |
|
|
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
|
| 15552 |
|
|
got_curr_clk_falling_edge_after_clkswitch := false;
|
| 15553 |
|
|
if (current_clock = 0) then
|
| 15554 |
|
|
current_clock := 1;
|
| 15555 |
|
|
else
|
| 15556 |
|
|
current_clock := 0;
|
| 15557 |
|
|
end if;
|
| 15558 |
|
|
active_clock := not active_clock;
|
| 15559 |
|
|
switch_over_count := 0;
|
| 15560 |
|
|
external_switch := false;
|
| 15561 |
|
|
current_clk_is_bad := false;
|
| 15562 |
|
|
else
|
| 15563 |
|
|
if(switch_over_type = "auto") then
|
| 15564 |
|
|
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
|
| 15565 |
|
|
current_clock := 1;
|
| 15566 |
|
|
active_clock := not active_clock;
|
| 15567 |
|
|
end if;
|
| 15568 |
|
|
|
| 15569 |
|
|
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
|
| 15570 |
|
|
current_clock := 0;
|
| 15571 |
|
|
active_clock := not active_clock;
|
| 15572 |
|
|
end if;
|
| 15573 |
|
|
end if;
|
| 15574 |
|
|
end if;
|
| 15575 |
|
|
|
| 15576 |
|
|
end if;
|
| 15577 |
|
|
end if;
|
| 15578 |
|
|
|
| 15579 |
|
|
-- schedule outputs
|
| 15580 |
|
|
clkbad(0) <= clk0_is_bad;
|
| 15581 |
|
|
clkbad(1) <= clk1_is_bad;
|
| 15582 |
|
|
activeclock <= active_clock;
|
| 15583 |
|
|
|
| 15584 |
|
|
end process;
|
| 15585 |
|
|
|
| 15586 |
|
|
|
| 15587 |
|
|
n1 : stratixiii_mn_cntr
|
| 15588 |
|
|
port map (
|
| 15589 |
|
|
clk => clkin,
|
| 15590 |
|
|
reset => areset_ipd,
|
| 15591 |
|
|
cout => refclk,
|
| 15592 |
|
|
initial_value => n_val,
|
| 15593 |
|
|
modulus => n_val);
|
| 15594 |
|
|
|
| 15595 |
|
|
inclk_c0 <= refclk when c0_test_source = 1 else
|
| 15596 |
|
|
fbclk when c0_test_source = 0 else
|
| 15597 |
|
|
inclk_c_from_vco(0);
|
| 15598 |
|
|
|
| 15599 |
|
|
|
| 15600 |
|
|
c0 : stratixiii_scale_cntr
|
| 15601 |
|
|
port map (
|
| 15602 |
|
|
clk => inclk_c0,
|
| 15603 |
|
|
reset => areset_ena_sig,
|
| 15604 |
|
|
cout => c_clk(0),
|
| 15605 |
|
|
initial => c_initial_val(0),
|
| 15606 |
|
|
high => c_high_val(0),
|
| 15607 |
|
|
low => c_low_val(0),
|
| 15608 |
|
|
mode => c_mode_val(0),
|
| 15609 |
|
|
ph_tap => c_ph_val(0));
|
| 15610 |
|
|
|
| 15611 |
|
|
inclk_c1 <= refclk when c1_test_source = 1 else
|
| 15612 |
|
|
fbclk when c1_test_source = 0 else
|
| 15613 |
|
|
c_clk(0) when c1_use_casc_in = "on" else
|
| 15614 |
|
|
inclk_c_from_vco(1);
|
| 15615 |
|
|
|
| 15616 |
|
|
|
| 15617 |
|
|
c1 : stratixiii_scale_cntr
|
| 15618 |
|
|
port map (
|
| 15619 |
|
|
clk => inclk_c1,
|
| 15620 |
|
|
reset => areset_ena_sig,
|
| 15621 |
|
|
cout => c_clk(1),
|
| 15622 |
|
|
initial => c_initial_val(1),
|
| 15623 |
|
|
high => c_high_val(1),
|
| 15624 |
|
|
low => c_low_val(1),
|
| 15625 |
|
|
mode => c_mode_val(1),
|
| 15626 |
|
|
ph_tap => c_ph_val(1));
|
| 15627 |
|
|
|
| 15628 |
|
|
inclk_c2 <= refclk when c2_test_source = 1 else
|
| 15629 |
|
|
fbclk when c2_test_source = 0 else
|
| 15630 |
|
|
c_clk(1) when c2_use_casc_in = "on" else
|
| 15631 |
|
|
inclk_c_from_vco(2);
|
| 15632 |
|
|
|
| 15633 |
|
|
c2 : stratixiii_scale_cntr
|
| 15634 |
|
|
port map (
|
| 15635 |
|
|
clk => inclk_c2,
|
| 15636 |
|
|
reset => areset_ena_sig,
|
| 15637 |
|
|
cout => c_clk(2),
|
| 15638 |
|
|
initial => c_initial_val(2),
|
| 15639 |
|
|
high => c_high_val(2),
|
| 15640 |
|
|
low => c_low_val(2),
|
| 15641 |
|
|
mode => c_mode_val(2),
|
| 15642 |
|
|
ph_tap => c_ph_val(2));
|
| 15643 |
|
|
|
| 15644 |
|
|
|
| 15645 |
|
|
inclk_c3 <= refclk when c3_test_source = 1 else
|
| 15646 |
|
|
fbclk when c3_test_source = 0 else
|
| 15647 |
|
|
c_clk(2) when c3_use_casc_in = "on" else
|
| 15648 |
|
|
inclk_c_from_vco(3);
|
| 15649 |
|
|
|
| 15650 |
|
|
c3 : stratixiii_scale_cntr
|
| 15651 |
|
|
port map (
|
| 15652 |
|
|
clk => inclk_c3,
|
| 15653 |
|
|
reset => areset_ena_sig,
|
| 15654 |
|
|
cout => c_clk(3),
|
| 15655 |
|
|
initial => c_initial_val(3),
|
| 15656 |
|
|
high => c_high_val(3),
|
| 15657 |
|
|
low => c_low_val(3),
|
| 15658 |
|
|
mode => c_mode_val(3),
|
| 15659 |
|
|
ph_tap => c_ph_val(3));
|
| 15660 |
|
|
|
| 15661 |
|
|
inclk_c4 <= refclk when c4_test_source = 1 else
|
| 15662 |
|
|
fbclk when c4_test_source = 0 else
|
| 15663 |
|
|
c_clk(3) when (c4_use_casc_in = "on") else
|
| 15664 |
|
|
inclk_c_from_vco(4);
|
| 15665 |
|
|
|
| 15666 |
|
|
c4 : stratixiii_scale_cntr
|
| 15667 |
|
|
port map (
|
| 15668 |
|
|
clk => inclk_c4,
|
| 15669 |
|
|
reset => areset_ena_sig,
|
| 15670 |
|
|
cout => c_clk(4),
|
| 15671 |
|
|
initial => c_initial_val(4),
|
| 15672 |
|
|
high => c_high_val(4),
|
| 15673 |
|
|
low => c_low_val(4),
|
| 15674 |
|
|
mode => c_mode_val(4),
|
| 15675 |
|
|
ph_tap => c_ph_val(4));
|
| 15676 |
|
|
|
| 15677 |
|
|
inclk_c5 <= refclk when c5_test_source = 1 else
|
| 15678 |
|
|
fbclk when c5_test_source = 0 else
|
| 15679 |
|
|
c_clk(4) when c5_use_casc_in = "on" else
|
| 15680 |
|
|
inclk_c_from_vco(5);
|
| 15681 |
|
|
|
| 15682 |
|
|
c5 : stratixiii_scale_cntr
|
| 15683 |
|
|
port map (
|
| 15684 |
|
|
clk => inclk_c5,
|
| 15685 |
|
|
reset => areset_ena_sig,
|
| 15686 |
|
|
cout => c_clk(5),
|
| 15687 |
|
|
initial => c_initial_val(5),
|
| 15688 |
|
|
high => c_high_val(5),
|
| 15689 |
|
|
low => c_low_val(5),
|
| 15690 |
|
|
mode => c_mode_val(5),
|
| 15691 |
|
|
ph_tap => c_ph_val(5));
|
| 15692 |
|
|
|
| 15693 |
|
|
inclk_c6 <= refclk when c6_test_source = 1 else
|
| 15694 |
|
|
fbclk when c6_test_source = 0 else
|
| 15695 |
|
|
c_clk(5) when c6_use_casc_in = "on" else
|
| 15696 |
|
|
inclk_c_from_vco(6);
|
| 15697 |
|
|
|
| 15698 |
|
|
c6 : stratixiii_scale_cntr
|
| 15699 |
|
|
port map (
|
| 15700 |
|
|
clk => inclk_c6,
|
| 15701 |
|
|
reset => areset_ena_sig,
|
| 15702 |
|
|
cout => c_clk(6),
|
| 15703 |
|
|
initial => c_initial_val(6),
|
| 15704 |
|
|
high => c_high_val(6),
|
| 15705 |
|
|
low => c_low_val(6),
|
| 15706 |
|
|
mode => c_mode_val(6),
|
| 15707 |
|
|
ph_tap => c_ph_val(6));
|
| 15708 |
|
|
|
| 15709 |
|
|
inclk_c7 <= refclk when c7_test_source = 1 else
|
| 15710 |
|
|
fbclk when c7_test_source = 0 else
|
| 15711 |
|
|
c_clk(6) when c7_use_casc_in = "on" else
|
| 15712 |
|
|
inclk_c_from_vco(7);
|
| 15713 |
|
|
|
| 15714 |
|
|
c7 : stratixiii_scale_cntr
|
| 15715 |
|
|
port map (
|
| 15716 |
|
|
clk => inclk_c7,
|
| 15717 |
|
|
reset => areset_ena_sig,
|
| 15718 |
|
|
cout => c_clk(7),
|
| 15719 |
|
|
initial => c_initial_val(7),
|
| 15720 |
|
|
high => c_high_val(7),
|
| 15721 |
|
|
low => c_low_val(7),
|
| 15722 |
|
|
mode => c_mode_val(7),
|
| 15723 |
|
|
ph_tap => c_ph_val(7));
|
| 15724 |
|
|
|
| 15725 |
|
|
inclk_c8 <= refclk when c8_test_source = 1 else
|
| 15726 |
|
|
fbclk when c8_test_source = 0 else
|
| 15727 |
|
|
c_clk(7) when c8_use_casc_in = "on" else
|
| 15728 |
|
|
inclk_c_from_vco(8);
|
| 15729 |
|
|
|
| 15730 |
|
|
c8 : stratixiii_scale_cntr
|
| 15731 |
|
|
port map (
|
| 15732 |
|
|
clk => inclk_c8,
|
| 15733 |
|
|
reset => areset_ena_sig,
|
| 15734 |
|
|
cout => c_clk(8),
|
| 15735 |
|
|
initial => c_initial_val(8),
|
| 15736 |
|
|
high => c_high_val(8),
|
| 15737 |
|
|
low => c_low_val(8),
|
| 15738 |
|
|
mode => c_mode_val(8),
|
| 15739 |
|
|
ph_tap => c_ph_val(8));
|
| 15740 |
|
|
|
| 15741 |
|
|
inclk_c9 <= refclk when c9_test_source = 1 else
|
| 15742 |
|
|
fbclk when c9_test_source = 0 else
|
| 15743 |
|
|
c_clk(8) when c9_use_casc_in = "on" else
|
| 15744 |
|
|
inclk_c_from_vco(9);
|
| 15745 |
|
|
|
| 15746 |
|
|
c9 : stratixiii_scale_cntr
|
| 15747 |
|
|
port map (
|
| 15748 |
|
|
clk => inclk_c9,
|
| 15749 |
|
|
reset => areset_ena_sig,
|
| 15750 |
|
|
cout => c_clk(9),
|
| 15751 |
|
|
initial => c_initial_val(9),
|
| 15752 |
|
|
high => c_high_val(9),
|
| 15753 |
|
|
low => c_low_val(9),
|
| 15754 |
|
|
mode => c_mode_val(9),
|
| 15755 |
|
|
ph_tap => c_ph_val(9));
|
| 15756 |
|
|
|
| 15757 |
|
|
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
|
| 15758 |
|
|
variable c0_got_first_rising_edge : boolean := false;
|
| 15759 |
|
|
variable c0_count : integer := 2;
|
| 15760 |
|
|
variable c0_initial_count : integer := 1;
|
| 15761 |
|
|
variable c0_tmp, c1_tmp : std_logic := '0';
|
| 15762 |
|
|
variable c1_got_first_rising_edge : boolean := false;
|
| 15763 |
|
|
variable c1_count : integer := 2;
|
| 15764 |
|
|
variable c1_initial_count : integer := 1;
|
| 15765 |
|
|
begin
|
| 15766 |
|
|
if (areset_ipd = '1' or sig_stop_vco = '1') then
|
| 15767 |
|
|
c0_count := 2;
|
| 15768 |
|
|
c1_count := 2;
|
| 15769 |
|
|
c0_initial_count := 1;
|
| 15770 |
|
|
c1_initial_count := 1;
|
| 15771 |
|
|
c0_got_first_rising_edge := false;
|
| 15772 |
|
|
c1_got_first_rising_edge := false;
|
| 15773 |
|
|
else
|
| 15774 |
|
|
if (not c0_got_first_rising_edge) then
|
| 15775 |
|
|
if (inclk_c0'event and inclk_c0 = '1') then
|
| 15776 |
|
|
if (c0_initial_count = c_initial_val(0)) then
|
| 15777 |
|
|
c0_got_first_rising_edge := true;
|
| 15778 |
|
|
else
|
| 15779 |
|
|
c0_initial_count := c0_initial_count + 1;
|
| 15780 |
|
|
end if;
|
| 15781 |
|
|
end if;
|
| 15782 |
|
|
elsif (inclk_c0'event) then
|
| 15783 |
|
|
c0_count := c0_count + 1;
|
| 15784 |
|
|
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
|
| 15785 |
|
|
c0_count := 1;
|
| 15786 |
|
|
end if;
|
| 15787 |
|
|
end if;
|
| 15788 |
|
|
if (inclk_c0'event and inclk_c0 = '0') then
|
| 15789 |
|
|
if (c0_count = 1) then
|
| 15790 |
|
|
c0_tmp := '1';
|
| 15791 |
|
|
c0_got_first_rising_edge := false;
|
| 15792 |
|
|
else
|
| 15793 |
|
|
c0_tmp := '0';
|
| 15794 |
|
|
end if;
|
| 15795 |
|
|
end if;
|
| 15796 |
|
|
|
| 15797 |
|
|
if (not c1_got_first_rising_edge) then
|
| 15798 |
|
|
if (inclk_c1'event and inclk_c1 = '1') then
|
| 15799 |
|
|
if (c1_initial_count = c_initial_val(1)) then
|
| 15800 |
|
|
c1_got_first_rising_edge := true;
|
| 15801 |
|
|
else
|
| 15802 |
|
|
c1_initial_count := c1_initial_count + 1;
|
| 15803 |
|
|
end if;
|
| 15804 |
|
|
end if;
|
| 15805 |
|
|
elsif (inclk_c1'event) then
|
| 15806 |
|
|
c1_count := c1_count + 1;
|
| 15807 |
|
|
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
|
| 15808 |
|
|
c1_count := 1;
|
| 15809 |
|
|
end if;
|
| 15810 |
|
|
end if;
|
| 15811 |
|
|
if (inclk_c1'event and inclk_c1 = '0') then
|
| 15812 |
|
|
if (c1_count = 1) then
|
| 15813 |
|
|
c1_tmp := '1';
|
| 15814 |
|
|
c1_got_first_rising_edge := false;
|
| 15815 |
|
|
else
|
| 15816 |
|
|
c1_tmp := '0';
|
| 15817 |
|
|
end if;
|
| 15818 |
|
|
end if;
|
| 15819 |
|
|
end if;
|
| 15820 |
|
|
|
| 15821 |
|
|
end process;
|
| 15822 |
|
|
|
| 15823 |
|
|
|
| 15824 |
|
|
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
|
| 15825 |
|
|
lock;
|
| 15826 |
|
|
|
| 15827 |
|
|
|
| 15828 |
|
|
process (scandone_tmp)
|
| 15829 |
|
|
variable buf : line;
|
| 15830 |
|
|
begin
|
| 15831 |
|
|
if (scandone_tmp'event and scandone_tmp = '1') then
|
| 15832 |
|
|
if (reconfig_err = false) then
|
| 15833 |
|
|
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
|
| 15834 |
|
|
write (buf, string'(" N modulus = "));
|
| 15835 |
|
|
write (buf, n_val);
|
| 15836 |
|
|
write (buf, string'(" ( "));
|
| 15837 |
|
|
write (buf, n_val_old);
|
| 15838 |
|
|
write (buf, string'(" )"));
|
| 15839 |
|
|
writeline (output, buf);
|
| 15840 |
|
|
|
| 15841 |
|
|
write (buf, string'(" M modulus = "));
|
| 15842 |
|
|
write (buf, m_val);
|
| 15843 |
|
|
write (buf, string'(" ( "));
|
| 15844 |
|
|
write (buf, m_val_old);
|
| 15845 |
|
|
write (buf, string'(" )"));
|
| 15846 |
|
|
writeline (output, buf);
|
| 15847 |
|
|
|
| 15848 |
|
|
write (buf, string'(" M ph_tap = "));
|
| 15849 |
|
|
write (buf, m_ph_val);
|
| 15850 |
|
|
write (buf, string'(" ( "));
|
| 15851 |
|
|
write (buf, m_ph_val_old);
|
| 15852 |
|
|
write (buf, string'(" )"));
|
| 15853 |
|
|
writeline (output, buf);
|
| 15854 |
|
|
|
| 15855 |
|
|
for i in 0 to (num_output_cntrs-1) loop
|
| 15856 |
|
|
write (buf, cntrs(i));
|
| 15857 |
|
|
write (buf, string'(" : high = "));
|
| 15858 |
|
|
write (buf, c_high_val(i));
|
| 15859 |
|
|
write (buf, string'(" ("));
|
| 15860 |
|
|
write (buf, c_high_val_old(i));
|
| 15861 |
|
|
write (buf, string'(") "));
|
| 15862 |
|
|
write (buf, string'(" , low = "));
|
| 15863 |
|
|
write (buf, c_low_val(i));
|
| 15864 |
|
|
write (buf, string'(" ("));
|
| 15865 |
|
|
write (buf, c_low_val_old(i));
|
| 15866 |
|
|
write (buf, string'(") "));
|
| 15867 |
|
|
write (buf, string'(" , mode = "));
|
| 15868 |
|
|
write (buf, c_mode_val(i));
|
| 15869 |
|
|
write (buf, string'(" ("));
|
| 15870 |
|
|
write (buf, c_mode_val_old(i));
|
| 15871 |
|
|
write (buf, string'(") "));
|
| 15872 |
|
|
write (buf, string'(" , phase tap = "));
|
| 15873 |
|
|
write (buf, c_ph_val(i));
|
| 15874 |
|
|
write (buf, string'(" ("));
|
| 15875 |
|
|
write (buf, c_ph_val_old(i));
|
| 15876 |
|
|
write (buf, string'(") "));
|
| 15877 |
|
|
writeline(output, buf);
|
| 15878 |
|
|
end loop;
|
| 15879 |
|
|
|
| 15880 |
|
|
IF (pll_reconfig_display_full_setting) THEN
|
| 15881 |
|
|
write (buf, string'(" Charge Pump Current (uA) = "));
|
| 15882 |
|
|
write (buf, cp_curr_val);
|
| 15883 |
|
|
write (buf, string'(" ( "));
|
| 15884 |
|
|
write (buf, cp_curr_old);
|
| 15885 |
|
|
write (buf, string'(" ) "));
|
| 15886 |
|
|
writeline (output, buf);
|
| 15887 |
|
|
|
| 15888 |
|
|
write (buf, string'(" Loop Filter Capacitor (pF) = "));
|
| 15889 |
|
|
write (buf, lfc_val);
|
| 15890 |
|
|
write (buf, string'(" ( "));
|
| 15891 |
|
|
write (buf, lfc_old);
|
| 15892 |
|
|
write (buf, string'(" ) "));
|
| 15893 |
|
|
writeline (output, buf);
|
| 15894 |
|
|
|
| 15895 |
|
|
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
|
| 15896 |
|
|
write (buf, lfr_val);
|
| 15897 |
|
|
write (buf, string'(" ( "));
|
| 15898 |
|
|
write (buf, lfr_old);
|
| 15899 |
|
|
write (buf, string'(" ) "));
|
| 15900 |
|
|
writeline (output, buf);
|
| 15901 |
|
|
ELSE
|
| 15902 |
|
|
write (buf, string'(" Charge Pump Current (bit setting) = "));
|
| 15903 |
|
|
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
|
| 15904 |
|
|
write (buf, string'(" ( "));
|
| 15905 |
|
|
write (buf, cp_curr_old_bit_setting);
|
| 15906 |
|
|
write (buf, string'(" ) "));
|
| 15907 |
|
|
writeline (output, buf);
|
| 15908 |
|
|
|
| 15909 |
|
|
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
|
| 15910 |
|
|
write (buf, alt_conv_integer(lfc_val_bit_setting));
|
| 15911 |
|
|
write (buf, string'(" ( "));
|
| 15912 |
|
|
write (buf, lfc_old_bit_setting);
|
| 15913 |
|
|
write (buf, string'(" ) "));
|
| 15914 |
|
|
writeline (output, buf);
|
| 15915 |
|
|
|
| 15916 |
|
|
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
|
| 15917 |
|
|
write (buf, alt_conv_integer(lfr_val_bit_setting));
|
| 15918 |
|
|
write (buf, string'(" ( "));
|
| 15919 |
|
|
write (buf, lfr_old_bit_setting);
|
| 15920 |
|
|
write (buf, string'(" ) "));
|
| 15921 |
|
|
writeline (output, buf);
|
| 15922 |
|
|
END IF;
|
| 15923 |
|
|
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
|
| 15924 |
|
|
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
|
| 15925 |
|
|
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
|
| 15926 |
|
|
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
|
| 15927 |
|
|
end if;
|
| 15928 |
|
|
end if;
|
| 15929 |
|
|
|
| 15930 |
|
|
end process;
|
| 15931 |
|
|
|
| 15932 |
|
|
update_conf_latches <= configupdate_ipd;
|
| 15933 |
|
|
|
| 15934 |
|
|
|
| 15935 |
|
|
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
|
| 15936 |
|
|
variable init : boolean := true;
|
| 15937 |
|
|
variable low, high : std_logic_vector(7 downto 0);
|
| 15938 |
|
|
variable low_fast, high_fast : std_logic_vector(3 downto 0);
|
| 15939 |
|
|
variable mode : string(1 to 6) := "bypass";
|
| 15940 |
|
|
variable is_error : boolean := false;
|
| 15941 |
|
|
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
|
| 15942 |
|
|
variable lfr_val_tmp : string(1 to 2) := " ";
|
| 15943 |
|
|
|
| 15944 |
|
|
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
|
| 15945 |
|
|
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
|
| 15946 |
|
|
variable c_mode_val_tmp : str_array(0 to 9);
|
| 15947 |
|
|
variable m_val_tmp : integer := 0;
|
| 15948 |
|
|
variable c0_rising_edge_transfer_done : boolean := false;
|
| 15949 |
|
|
variable c1_rising_edge_transfer_done : boolean := false;
|
| 15950 |
|
|
variable c2_rising_edge_transfer_done : boolean := false;
|
| 15951 |
|
|
variable c3_rising_edge_transfer_done : boolean := false;
|
| 15952 |
|
|
variable c4_rising_edge_transfer_done : boolean := false;
|
| 15953 |
|
|
variable c5_rising_edge_transfer_done : boolean := false;
|
| 15954 |
|
|
variable c6_rising_edge_transfer_done : boolean := false;
|
| 15955 |
|
|
variable c7_rising_edge_transfer_done : boolean := false;
|
| 15956 |
|
|
variable c8_rising_edge_transfer_done : boolean := false;
|
| 15957 |
|
|
variable c9_rising_edge_transfer_done : boolean := false;
|
| 15958 |
|
|
|
| 15959 |
|
|
-- variables for scaling of multiply_by and divide_by values
|
| 15960 |
|
|
variable i_clk0_mult_by : integer := 1;
|
| 15961 |
|
|
variable i_clk0_div_by : integer := 1;
|
| 15962 |
|
|
variable i_clk1_mult_by : integer := 1;
|
| 15963 |
|
|
variable i_clk1_div_by : integer := 1;
|
| 15964 |
|
|
variable i_clk2_mult_by : integer := 1;
|
| 15965 |
|
|
variable i_clk2_div_by : integer := 1;
|
| 15966 |
|
|
variable i_clk3_mult_by : integer := 1;
|
| 15967 |
|
|
variable i_clk3_div_by : integer := 1;
|
| 15968 |
|
|
variable i_clk4_mult_by : integer := 1;
|
| 15969 |
|
|
variable i_clk4_div_by : integer := 1;
|
| 15970 |
|
|
variable i_clk5_mult_by : integer := 1;
|
| 15971 |
|
|
variable i_clk5_div_by : integer := 1;
|
| 15972 |
|
|
variable i_clk6_mult_by : integer := 1;
|
| 15973 |
|
|
variable i_clk6_div_by : integer := 1;
|
| 15974 |
|
|
variable i_clk7_mult_by : integer := 1;
|
| 15975 |
|
|
variable i_clk7_div_by : integer := 1;
|
| 15976 |
|
|
variable i_clk8_mult_by : integer := 1;
|
| 15977 |
|
|
variable i_clk8_div_by : integer := 1;
|
| 15978 |
|
|
variable i_clk9_mult_by : integer := 1;
|
| 15979 |
|
|
variable i_clk9_div_by : integer := 1;
|
| 15980 |
|
|
variable max_d_value : integer := 1;
|
| 15981 |
|
|
variable new_multiplier : integer := 1;
|
| 15982 |
|
|
|
| 15983 |
|
|
-- internal variables for storing the phase shift number.(used in lvds mode only)
|
| 15984 |
|
|
variable i_clk0_phase_shift : integer := 1;
|
| 15985 |
|
|
variable i_clk1_phase_shift : integer := 1;
|
| 15986 |
|
|
variable i_clk2_phase_shift : integer := 1;
|
| 15987 |
|
|
|
| 15988 |
|
|
-- user to advanced variables
|
| 15989 |
|
|
|
| 15990 |
|
|
variable max_neg_abs : integer := 0;
|
| 15991 |
|
|
variable i_m_initial : integer;
|
| 15992 |
|
|
variable i_m : integer := 1;
|
| 15993 |
|
|
variable i_n : integer := 1;
|
| 15994 |
|
|
variable i_c_high : int_array(0 to 9);
|
| 15995 |
|
|
variable i_c_low : int_array(0 to 9);
|
| 15996 |
|
|
variable i_c_initial : int_array(0 to 9);
|
| 15997 |
|
|
variable i_c_ph : int_array(0 to 9);
|
| 15998 |
|
|
variable i_c_mode : str_array(0 to 9);
|
| 15999 |
|
|
variable i_m_ph : integer;
|
| 16000 |
|
|
variable output_count : integer;
|
| 16001 |
|
|
variable new_divisor : integer;
|
| 16002 |
|
|
|
| 16003 |
|
|
variable clk0_cntr : string(1 to 6) := " c0";
|
| 16004 |
|
|
variable clk1_cntr : string(1 to 6) := " c1";
|
| 16005 |
|
|
variable clk2_cntr : string(1 to 6) := " c2";
|
| 16006 |
|
|
variable clk3_cntr : string(1 to 6) := " c3";
|
| 16007 |
|
|
variable clk4_cntr : string(1 to 6) := " c4";
|
| 16008 |
|
|
variable clk5_cntr : string(1 to 6) := " c5";
|
| 16009 |
|
|
variable clk6_cntr : string(1 to 6) := " c6";
|
| 16010 |
|
|
variable clk7_cntr : string(1 to 6) := " c7";
|
| 16011 |
|
|
variable clk8_cntr : string(1 to 6) := " c8";
|
| 16012 |
|
|
variable clk9_cntr : string(1 to 6) := " c9";
|
| 16013 |
|
|
|
| 16014 |
|
|
variable fbk_cntr : string(1 to 2);
|
| 16015 |
|
|
variable fbk_cntr_index : integer;
|
| 16016 |
|
|
variable start_bit : integer;
|
| 16017 |
|
|
variable quiet_time : time := 0 ps;
|
| 16018 |
|
|
variable slowest_clk_old : time := 0 ps;
|
| 16019 |
|
|
variable slowest_clk_new : time := 0 ps;
|
| 16020 |
|
|
|
| 16021 |
|
|
variable i : integer := 0;
|
| 16022 |
|
|
variable j : integer := 0;
|
| 16023 |
|
|
variable scanread_active_edge : time := 0 ps;
|
| 16024 |
|
|
variable got_first_scanclk : boolean := false;
|
| 16025 |
|
|
variable scanclk_last_rising_edge : time := 0 ps;
|
| 16026 |
|
|
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
|
| 16027 |
|
|
|
| 16028 |
|
|
variable index : integer := 0;
|
| 16029 |
|
|
variable Tviol_scandata_scanclk : std_ulogic := '0';
|
| 16030 |
|
|
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
|
| 16031 |
|
|
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
|
| 16032 |
|
|
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
|
| 16033 |
|
|
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
|
| 16034 |
|
|
variable tmp_rem : integer := 0;
|
| 16035 |
|
|
variable scanclk_cycles : integer := 0;
|
| 16036 |
|
|
variable lfc_tmp : std_logic_vector(1 downto 0);
|
| 16037 |
|
|
variable lfr_tmp : std_logic_vector(5 downto 0);
|
| 16038 |
|
|
variable lfr_int : integer := 0;
|
| 16039 |
|
|
|
| 16040 |
|
|
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
|
| 16041 |
|
|
variable buf : line;
|
| 16042 |
|
|
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
|
| 16043 |
|
|
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
|
| 16044 |
|
|
|
| 16045 |
|
|
function slowest_clk (
|
| 16046 |
|
|
C0 : integer; C0_mode : string(1 to 6);
|
| 16047 |
|
|
C1 : integer; C1_mode : string(1 to 6);
|
| 16048 |
|
|
C2 : integer; C2_mode : string(1 to 6);
|
| 16049 |
|
|
C3 : integer; C3_mode : string(1 to 6);
|
| 16050 |
|
|
C4 : integer; C4_mode : string(1 to 6);
|
| 16051 |
|
|
C5 : integer; C5_mode : string(1 to 6);
|
| 16052 |
|
|
C6 : integer; C6_mode : string(1 to 6);
|
| 16053 |
|
|
C7 : integer; C7_mode : string(1 to 6);
|
| 16054 |
|
|
C8 : integer; C8_mode : string(1 to 6);
|
| 16055 |
|
|
C9 : integer; C9_mode : string(1 to 6);
|
| 16056 |
|
|
refclk : time; m_mod : integer) return time is
|
| 16057 |
|
|
variable max_modulus : integer := 1;
|
| 16058 |
|
|
variable q_period : time := 0 ps;
|
| 16059 |
|
|
variable refclk_int : integer := 0;
|
| 16060 |
|
|
begin
|
| 16061 |
|
|
if (C0_mode /= "bypass" and C0_mode /= " off") then
|
| 16062 |
|
|
max_modulus := C0;
|
| 16063 |
|
|
end if;
|
| 16064 |
|
|
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
|
| 16065 |
|
|
max_modulus := C1;
|
| 16066 |
|
|
end if;
|
| 16067 |
|
|
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
|
| 16068 |
|
|
max_modulus := C2;
|
| 16069 |
|
|
end if;
|
| 16070 |
|
|
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
|
| 16071 |
|
|
max_modulus := C3;
|
| 16072 |
|
|
end if;
|
| 16073 |
|
|
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
|
| 16074 |
|
|
max_modulus := C4;
|
| 16075 |
|
|
end if;
|
| 16076 |
|
|
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
|
| 16077 |
|
|
max_modulus := C5;
|
| 16078 |
|
|
end if;
|
| 16079 |
|
|
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
|
| 16080 |
|
|
max_modulus := C6;
|
| 16081 |
|
|
end if;
|
| 16082 |
|
|
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
|
| 16083 |
|
|
max_modulus := C7;
|
| 16084 |
|
|
end if;
|
| 16085 |
|
|
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
|
| 16086 |
|
|
max_modulus := C8;
|
| 16087 |
|
|
end if;
|
| 16088 |
|
|
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
|
| 16089 |
|
|
max_modulus := C9;
|
| 16090 |
|
|
end if;
|
| 16091 |
|
|
|
| 16092 |
|
|
refclk_int := refclk / 1 ps;
|
| 16093 |
|
|
if (m_mod /= 0) then
|
| 16094 |
|
|
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
|
| 16095 |
|
|
end if;
|
| 16096 |
|
|
return (2*q_period);
|
| 16097 |
|
|
end slowest_clk;
|
| 16098 |
|
|
|
| 16099 |
|
|
function int2bin (arg : integer; size : integer) return std_logic_vector is
|
| 16100 |
|
|
variable int_val : integer := arg;
|
| 16101 |
|
|
variable result : std_logic_vector(size-1 downto 0);
|
| 16102 |
|
|
begin
|
| 16103 |
|
|
for i in 0 to result'left loop
|
| 16104 |
|
|
if ((int_val mod 2) = 0) then
|
| 16105 |
|
|
result(i) := '0';
|
| 16106 |
|
|
else
|
| 16107 |
|
|
result(i) := '1';
|
| 16108 |
|
|
end if;
|
| 16109 |
|
|
int_val := int_val/2;
|
| 16110 |
|
|
end loop;
|
| 16111 |
|
|
return result;
|
| 16112 |
|
|
end int2bin;
|
| 16113 |
|
|
|
| 16114 |
|
|
function extract_cntr_string (arg:string) return string is
|
| 16115 |
|
|
variable str : string(1 to 6) := " c0";
|
| 16116 |
|
|
begin
|
| 16117 |
|
|
if (arg = "c0") then
|
| 16118 |
|
|
str := " c0";
|
| 16119 |
|
|
elsif (arg = "c1") then
|
| 16120 |
|
|
str := " c1";
|
| 16121 |
|
|
elsif (arg = "c2") then
|
| 16122 |
|
|
str := " c2";
|
| 16123 |
|
|
elsif (arg = "c3") then
|
| 16124 |
|
|
str := " c3";
|
| 16125 |
|
|
elsif (arg = "c4") then
|
| 16126 |
|
|
str := " c4";
|
| 16127 |
|
|
elsif (arg = "c5") then
|
| 16128 |
|
|
str := " c5";
|
| 16129 |
|
|
elsif (arg = "c6") then
|
| 16130 |
|
|
str := " c6";
|
| 16131 |
|
|
elsif (arg = "c7") then
|
| 16132 |
|
|
str := " c7";
|
| 16133 |
|
|
elsif (arg = "c8") then
|
| 16134 |
|
|
str := " c8";
|
| 16135 |
|
|
elsif (arg = "c9") then
|
| 16136 |
|
|
str := " c9";
|
| 16137 |
|
|
else str := " c0";
|
| 16138 |
|
|
|
| 16139 |
|
|
end if;
|
| 16140 |
|
|
|
| 16141 |
|
|
return str;
|
| 16142 |
|
|
|
| 16143 |
|
|
end extract_cntr_string;
|
| 16144 |
|
|
|
| 16145 |
|
|
function extract_cntr_index (arg:string) return integer is
|
| 16146 |
|
|
variable index : integer := 0;
|
| 16147 |
|
|
begin
|
| 16148 |
|
|
if (arg(6) = '0') then
|
| 16149 |
|
|
index := 0;
|
| 16150 |
|
|
elsif (arg(6) = '1') then
|
| 16151 |
|
|
index := 1;
|
| 16152 |
|
|
elsif (arg(6) = '2') then
|
| 16153 |
|
|
index := 2;
|
| 16154 |
|
|
elsif (arg(6) = '3') then
|
| 16155 |
|
|
index := 3;
|
| 16156 |
|
|
elsif (arg(6) = '4') then
|
| 16157 |
|
|
index := 4;
|
| 16158 |
|
|
elsif (arg(6) = '5') then
|
| 16159 |
|
|
index := 5;
|
| 16160 |
|
|
elsif (arg(6) = '6') then
|
| 16161 |
|
|
index := 6;
|
| 16162 |
|
|
elsif (arg(6) = '7') then
|
| 16163 |
|
|
index := 7;
|
| 16164 |
|
|
elsif (arg(6) = '8') then
|
| 16165 |
|
|
index := 8;
|
| 16166 |
|
|
else index := 9;
|
| 16167 |
|
|
end if;
|
| 16168 |
|
|
|
| 16169 |
|
|
return index;
|
| 16170 |
|
|
end extract_cntr_index;
|
| 16171 |
|
|
|
| 16172 |
|
|
begin
|
| 16173 |
|
|
IF (areset_ipd'EVENT AND areset_ipd = '1') then
|
| 16174 |
|
|
c_ph_val <= i_c_ph;
|
| 16175 |
|
|
END IF;
|
| 16176 |
|
|
|
| 16177 |
|
|
if (init) then
|
| 16178 |
|
|
if (m = 0) then
|
| 16179 |
|
|
clk9_cntr := " c9";
|
| 16180 |
|
|
clk8_cntr := " c8";
|
| 16181 |
|
|
clk7_cntr := " c7";
|
| 16182 |
|
|
clk6_cntr := " c6";
|
| 16183 |
|
|
clk5_cntr := " c5";
|
| 16184 |
|
|
clk4_cntr := " c4";
|
| 16185 |
|
|
clk3_cntr := " c3";
|
| 16186 |
|
|
clk2_cntr := " c2";
|
| 16187 |
|
|
clk1_cntr := " c1";
|
| 16188 |
|
|
clk0_cntr := " c0";
|
| 16189 |
|
|
else
|
| 16190 |
|
|
clk9_cntr := extract_cntr_string(clk9_counter);
|
| 16191 |
|
|
clk8_cntr := extract_cntr_string(clk8_counter);
|
| 16192 |
|
|
clk7_cntr := extract_cntr_string(clk7_counter);
|
| 16193 |
|
|
clk6_cntr := extract_cntr_string(clk6_counter);
|
| 16194 |
|
|
clk5_cntr := extract_cntr_string(clk5_counter);
|
| 16195 |
|
|
clk4_cntr := extract_cntr_string(clk4_counter);
|
| 16196 |
|
|
clk3_cntr := extract_cntr_string(clk3_counter);
|
| 16197 |
|
|
clk2_cntr := extract_cntr_string(clk2_counter);
|
| 16198 |
|
|
clk1_cntr := extract_cntr_string(clk1_counter);
|
| 16199 |
|
|
clk0_cntr := extract_cntr_string(clk0_counter);
|
| 16200 |
|
|
end if;
|
| 16201 |
|
|
|
| 16202 |
|
|
|
| 16203 |
|
|
i_clk0_counter <= extract_cntr_index(clk0_cntr);
|
| 16204 |
|
|
i_clk1_counter <= extract_cntr_index(clk1_cntr);
|
| 16205 |
|
|
i_clk2_counter <= extract_cntr_index(clk2_cntr);
|
| 16206 |
|
|
i_clk3_counter <= extract_cntr_index(clk3_cntr);
|
| 16207 |
|
|
i_clk4_counter <= extract_cntr_index(clk4_cntr);
|
| 16208 |
|
|
i_clk5_counter <= extract_cntr_index(clk5_cntr);
|
| 16209 |
|
|
i_clk6_counter <= extract_cntr_index(clk6_cntr);
|
| 16210 |
|
|
i_clk7_counter <= extract_cntr_index(clk7_cntr);
|
| 16211 |
|
|
i_clk8_counter <= extract_cntr_index(clk8_cntr);
|
| 16212 |
|
|
i_clk9_counter <= extract_cntr_index(clk9_cntr);
|
| 16213 |
|
|
|
| 16214 |
|
|
|
| 16215 |
|
|
if (m = 0) then -- convert user parameters to advanced
|
| 16216 |
|
|
-- set the limit of the divide_by value that can be returned by
|
| 16217 |
|
|
-- the following function.
|
| 16218 |
|
|
max_d_value := 500;
|
| 16219 |
|
|
|
| 16220 |
|
|
-- scale down the multiply_by and divide_by values provided by the design
|
| 16221 |
|
|
-- before attempting to use them in the calculations below
|
| 16222 |
|
|
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
|
| 16223 |
|
|
max_d_value, i_clk0_mult_by, i_clk0_div_by);
|
| 16224 |
|
|
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
|
| 16225 |
|
|
max_d_value, i_clk1_mult_by, i_clk1_div_by);
|
| 16226 |
|
|
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
|
| 16227 |
|
|
max_d_value, i_clk2_mult_by, i_clk2_div_by);
|
| 16228 |
|
|
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
|
| 16229 |
|
|
max_d_value, i_clk3_mult_by, i_clk3_div_by);
|
| 16230 |
|
|
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
|
| 16231 |
|
|
max_d_value, i_clk4_mult_by, i_clk4_div_by);
|
| 16232 |
|
|
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
|
| 16233 |
|
|
max_d_value, i_clk5_mult_by, i_clk5_div_by);
|
| 16234 |
|
|
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
|
| 16235 |
|
|
max_d_value, i_clk6_mult_by, i_clk6_div_by);
|
| 16236 |
|
|
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
|
| 16237 |
|
|
max_d_value, i_clk7_mult_by, i_clk7_div_by);
|
| 16238 |
|
|
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
|
| 16239 |
|
|
max_d_value, i_clk8_mult_by, i_clk8_div_by);
|
| 16240 |
|
|
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
|
| 16241 |
|
|
max_d_value, i_clk9_mult_by, i_clk9_div_by);
|
| 16242 |
|
|
|
| 16243 |
|
|
if (vco_frequency_control = "manual_phase") then
|
| 16244 |
|
|
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
|
| 16245 |
|
|
i_clk0_mult_by, i_clk1_mult_by,
|
| 16246 |
|
|
i_clk2_mult_by, i_clk3_mult_by,
|
| 16247 |
|
|
i_clk4_mult_by,
|
| 16248 |
|
|
i_clk5_mult_by,i_clk6_mult_by,
|
| 16249 |
|
|
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
|
| 16250 |
|
|
i_clk0_div_by, i_clk1_div_by,
|
| 16251 |
|
|
i_clk2_div_by, i_clk3_div_by,
|
| 16252 |
|
|
i_clk4_div_by,
|
| 16253 |
|
|
i_clk5_div_by,i_clk6_div_by,
|
| 16254 |
|
|
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
|
| 16255 |
|
|
i_m, i_n);
|
| 16256 |
|
|
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
|
| 16257 |
|
|
i_n := vco_divide_by;
|
| 16258 |
|
|
i_m := vco_multiply_by;
|
| 16259 |
|
|
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((dpa_multiply_by /= 0) and (dpa_divide_by /= 0))) then
|
| 16260 |
|
|
i_n := dpa_divide_by;
|
| 16261 |
|
|
i_m := dpa_multiply_by;
|
| 16262 |
|
|
else
|
| 16263 |
|
|
i_n := 1;
|
| 16264 |
|
|
|
| 16265 |
|
|
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
|
| 16266 |
|
|
i_m := i_clk0_mult_by;
|
| 16267 |
|
|
else
|
| 16268 |
|
|
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
|
| 16269 |
|
|
i_clk2_mult_by, i_clk3_mult_by,
|
| 16270 |
|
|
i_clk4_mult_by,
|
| 16271 |
|
|
i_clk5_mult_by,i_clk6_mult_by,
|
| 16272 |
|
|
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
|
| 16273 |
|
|
inclk0_input_frequency);
|
| 16274 |
|
|
end if;
|
| 16275 |
|
|
end if;
|
| 16276 |
|
|
|
| 16277 |
|
|
if (pll_type = "flvds") then
|
| 16278 |
|
|
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
|
| 16279 |
|
|
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
|
| 16280 |
|
|
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
|
| 16281 |
|
|
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
|
| 16282 |
|
|
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
|
| 16283 |
|
|
else
|
| 16284 |
|
|
i_clk0_phase_shift := str2int(clk0_phase_shift);
|
| 16285 |
|
|
i_clk1_phase_shift := str2int(clk1_phase_shift);
|
| 16286 |
|
|
i_clk2_phase_shift := str2int(clk2_phase_shift);
|
| 16287 |
|
|
end if;
|
| 16288 |
|
|
|
| 16289 |
|
|
max_neg_abs := maxnegabs(i_clk0_phase_shift,
|
| 16290 |
|
|
i_clk1_phase_shift,
|
| 16291 |
|
|
i_clk2_phase_shift,
|
| 16292 |
|
|
str2int(clk3_phase_shift),
|
| 16293 |
|
|
str2int(clk4_phase_shift),
|
| 16294 |
|
|
str2int(clk5_phase_shift),
|
| 16295 |
|
|
str2int(clk6_phase_shift),
|
| 16296 |
|
|
str2int(clk7_phase_shift),
|
| 16297 |
|
|
str2int(clk8_phase_shift),
|
| 16298 |
|
|
str2int(clk9_phase_shift)
|
| 16299 |
|
|
);
|
| 16300 |
|
|
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
|
| 16301 |
|
|
|
| 16302 |
|
|
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16303 |
|
|
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16304 |
|
|
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16305 |
|
|
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16306 |
|
|
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16307 |
|
|
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16308 |
|
|
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16309 |
|
|
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16310 |
|
|
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16311 |
|
|
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
|
| 16312 |
|
|
|
| 16313 |
|
|
|
| 16314 |
|
|
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
|
| 16315 |
|
|
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
|
| 16316 |
|
|
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
|
| 16317 |
|
|
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
|
| 16318 |
|
|
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
|
| 16319 |
|
|
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
|
| 16320 |
|
|
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
|
| 16321 |
|
|
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
|
| 16322 |
|
|
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
|
| 16323 |
|
|
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
|
| 16324 |
|
|
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
|
| 16325 |
|
|
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
|
| 16326 |
|
|
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
|
| 16327 |
|
|
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
|
| 16328 |
|
|
|
| 16329 |
|
|
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
|
| 16330 |
|
|
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
|
| 16331 |
|
|
|
| 16332 |
|
|
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
|
| 16333 |
|
|
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
|
| 16334 |
|
|
|
| 16335 |
|
|
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
|
| 16336 |
|
|
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
|
| 16337 |
|
|
|
| 16338 |
|
|
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
|
| 16339 |
|
|
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
|
| 16340 |
|
|
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
|
| 16341 |
|
|
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
|
| 16342 |
|
|
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
|
| 16343 |
|
|
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
|
| 16344 |
|
|
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
|
| 16345 |
|
|
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
|
| 16346 |
|
|
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
|
| 16347 |
|
|
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
|
| 16348 |
|
|
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
|
| 16349 |
|
|
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
|
| 16350 |
|
|
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
|
| 16351 |
|
|
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
|
| 16352 |
|
|
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
|
| 16353 |
|
|
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
|
| 16354 |
|
|
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
|
| 16355 |
|
|
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
|
| 16356 |
|
|
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
|
| 16357 |
|
|
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
|
| 16358 |
|
|
|
| 16359 |
|
|
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
|
| 16360 |
|
|
|
| 16361 |
|
|
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16362 |
|
|
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16363 |
|
|
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16364 |
|
|
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16365 |
|
|
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16366 |
|
|
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16367 |
|
|
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16368 |
|
|
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16369 |
|
|
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16370 |
|
|
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
|
| 16371 |
|
|
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
|
| 16372 |
|
|
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
|
| 16373 |
|
|
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
|
| 16374 |
|
|
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
|
| 16375 |
|
|
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
|
| 16376 |
|
|
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
|
| 16377 |
|
|
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
|
| 16378 |
|
|
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
|
| 16379 |
|
|
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
|
| 16380 |
|
|
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
|
| 16381 |
|
|
|
| 16382 |
|
|
|
| 16383 |
|
|
|
| 16384 |
|
|
else -- m /= 0
|
| 16385 |
|
|
|
| 16386 |
|
|
i_n := n;
|
| 16387 |
|
|
i_m := m;
|
| 16388 |
|
|
i_m_initial := m_initial;
|
| 16389 |
|
|
i_m_ph := m_ph;
|
| 16390 |
|
|
i_c_ph(0) := c0_ph;
|
| 16391 |
|
|
i_c_ph(1) := c1_ph;
|
| 16392 |
|
|
i_c_ph(2) := c2_ph;
|
| 16393 |
|
|
i_c_ph(3) := c3_ph;
|
| 16394 |
|
|
i_c_ph(4) := c4_ph;
|
| 16395 |
|
|
i_c_ph(5) := c5_ph;
|
| 16396 |
|
|
i_c_ph(6) := c5_ph;
|
| 16397 |
|
|
i_c_ph(7) := c5_ph;
|
| 16398 |
|
|
i_c_ph(8) := c5_ph;
|
| 16399 |
|
|
i_c_ph(9) := c5_ph;
|
| 16400 |
|
|
i_c_high(0) := c0_high;
|
| 16401 |
|
|
i_c_high(1) := c1_high;
|
| 16402 |
|
|
i_c_high(2) := c2_high;
|
| 16403 |
|
|
i_c_high(3) := c3_high;
|
| 16404 |
|
|
i_c_high(4) := c4_high;
|
| 16405 |
|
|
i_c_high(5) := c5_high;
|
| 16406 |
|
|
i_c_high(6) := c6_high;
|
| 16407 |
|
|
i_c_high(7) := c7_high;
|
| 16408 |
|
|
i_c_high(8) := c8_high;
|
| 16409 |
|
|
i_c_high(9) := c9_high;
|
| 16410 |
|
|
i_c_low(0) := c0_low;
|
| 16411 |
|
|
i_c_low(1) := c1_low;
|
| 16412 |
|
|
i_c_low(2) := c2_low;
|
| 16413 |
|
|
i_c_low(3) := c3_low;
|
| 16414 |
|
|
i_c_low(4) := c4_low;
|
| 16415 |
|
|
i_c_low(5) := c5_low;
|
| 16416 |
|
|
i_c_low(6) := c6_low;
|
| 16417 |
|
|
i_c_low(7) := c7_low;
|
| 16418 |
|
|
i_c_low(8) := c8_low;
|
| 16419 |
|
|
i_c_low(9) := c9_low;
|
| 16420 |
|
|
i_c_initial(0) := c0_initial;
|
| 16421 |
|
|
i_c_initial(1) := c1_initial;
|
| 16422 |
|
|
i_c_initial(2) := c2_initial;
|
| 16423 |
|
|
i_c_initial(3) := c3_initial;
|
| 16424 |
|
|
i_c_initial(4) := c4_initial;
|
| 16425 |
|
|
i_c_initial(5) := c5_initial;
|
| 16426 |
|
|
i_c_initial(6) := c6_initial;
|
| 16427 |
|
|
i_c_initial(7) := c7_initial;
|
| 16428 |
|
|
i_c_initial(8) := c8_initial;
|
| 16429 |
|
|
i_c_initial(9) := c9_initial;
|
| 16430 |
|
|
i_c_mode(0) := translate_string(c0_mode);
|
| 16431 |
|
|
i_c_mode(1) := translate_string(c1_mode);
|
| 16432 |
|
|
i_c_mode(2) := translate_string(c2_mode);
|
| 16433 |
|
|
i_c_mode(3) := translate_string(c3_mode);
|
| 16434 |
|
|
i_c_mode(4) := translate_string(c4_mode);
|
| 16435 |
|
|
i_c_mode(5) := translate_string(c5_mode);
|
| 16436 |
|
|
i_c_mode(6) := translate_string(c6_mode);
|
| 16437 |
|
|
i_c_mode(7) := translate_string(c7_mode);
|
| 16438 |
|
|
i_c_mode(8) := translate_string(c8_mode);
|
| 16439 |
|
|
i_c_mode(9) := translate_string(c9_mode);
|
| 16440 |
|
|
|
| 16441 |
|
|
end if; -- user to advanced conversion.
|
| 16442 |
|
|
|
| 16443 |
|
|
m_initial_val <= i_m_initial;
|
| 16444 |
|
|
n_val <= i_n;
|
| 16445 |
|
|
m_val <= i_m;
|
| 16446 |
|
|
|
| 16447 |
|
|
if (i_m = 1) then
|
| 16448 |
|
|
m_mode_val <= "bypass";
|
| 16449 |
|
|
else
|
| 16450 |
|
|
m_mode_val <= " ";
|
| 16451 |
|
|
end if;
|
| 16452 |
|
|
if (i_n = 1) then
|
| 16453 |
|
|
n_mode_val <= "bypass";
|
| 16454 |
|
|
else
|
| 16455 |
|
|
n_mode_val <= " ";
|
| 16456 |
|
|
end if;
|
| 16457 |
|
|
|
| 16458 |
|
|
m_ph_val <= i_m_ph;
|
| 16459 |
|
|
m_ph_initial <= i_m_ph;
|
| 16460 |
|
|
m_val_tmp := i_m;
|
| 16461 |
|
|
|
| 16462 |
|
|
for i in 0 to 9 loop
|
| 16463 |
|
|
if (i_c_mode(i) = "bypass") then
|
| 16464 |
|
|
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
|
| 16465 |
|
|
i_c_high(i) := 16;
|
| 16466 |
|
|
i_c_low(i) := 16;
|
| 16467 |
|
|
else
|
| 16468 |
|
|
i_c_high(i) := 256;
|
| 16469 |
|
|
i_c_low(i) := 256;
|
| 16470 |
|
|
end if;
|
| 16471 |
|
|
end if;
|
| 16472 |
|
|
c_ph_val(i) <= i_c_ph(i);
|
| 16473 |
|
|
c_initial_val(i) <= i_c_initial(i);
|
| 16474 |
|
|
c_high_val(i) <= i_c_high(i);
|
| 16475 |
|
|
c_low_val(i) <= i_c_low(i);
|
| 16476 |
|
|
c_mode_val(i) <= i_c_mode(i);
|
| 16477 |
|
|
c_high_val_tmp(i) := i_c_high(i);
|
| 16478 |
|
|
c_hval(i) := i_c_high(i);
|
| 16479 |
|
|
c_low_val_tmp(i) := i_c_low(i);
|
| 16480 |
|
|
c_lval(i) := i_c_low(i);
|
| 16481 |
|
|
c_mode_val_tmp(i) := i_c_mode(i);
|
| 16482 |
|
|
c_ph_val_orig(i) <= i_c_ph(i);
|
| 16483 |
|
|
c_high_val_hold(i) <= i_c_high(i);
|
| 16484 |
|
|
c_low_val_hold(i) <= i_c_low(i);
|
| 16485 |
|
|
c_mode_val_hold(i) <= i_c_mode(i);
|
| 16486 |
|
|
end loop;
|
| 16487 |
|
|
|
| 16488 |
|
|
|
| 16489 |
|
|
|
| 16490 |
|
|
if (pll_type = "fast" OR (pll_type = "left_right")) then
|
| 16491 |
|
|
scan_chain_length := FAST_SCAN_CHAIN;
|
| 16492 |
|
|
else
|
| 16493 |
|
|
scan_chain_length := GPP_SCAN_CHAIN;
|
| 16494 |
|
|
end if;
|
| 16495 |
|
|
|
| 16496 |
|
|
|
| 16497 |
|
|
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
|
| 16498 |
|
|
num_output_cntrs <= 7;
|
| 16499 |
|
|
else
|
| 16500 |
|
|
num_output_cntrs <= 10;
|
| 16501 |
|
|
end if;
|
| 16502 |
|
|
|
| 16503 |
|
|
init := false;
|
| 16504 |
|
|
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
|
| 16505 |
|
|
c0_rising_edge_transfer_done := false;
|
| 16506 |
|
|
c1_rising_edge_transfer_done := false;
|
| 16507 |
|
|
c2_rising_edge_transfer_done := false;
|
| 16508 |
|
|
c3_rising_edge_transfer_done := false;
|
| 16509 |
|
|
c4_rising_edge_transfer_done := false;
|
| 16510 |
|
|
c5_rising_edge_transfer_done := false;
|
| 16511 |
|
|
c6_rising_edge_transfer_done := false;
|
| 16512 |
|
|
c7_rising_edge_transfer_done := false;
|
| 16513 |
|
|
c8_rising_edge_transfer_done := false;
|
| 16514 |
|
|
c9_rising_edge_transfer_done := false;
|
| 16515 |
|
|
update_conf_latches_reg <= '0';
|
| 16516 |
|
|
elsif (update_conf_latches'event and update_conf_latches = '1') then
|
| 16517 |
|
|
initiate_reconfig <= '1';
|
| 16518 |
|
|
elsif (areset_ipd'event AND areset_ipd = '1') then
|
| 16519 |
|
|
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
|
| 16520 |
|
|
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16521 |
|
|
IF (initiate_reconfig = '1') THEN
|
| 16522 |
|
|
initiate_reconfig <= '0';
|
| 16523 |
|
|
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
|
| 16524 |
|
|
|
| 16525 |
|
|
update_conf_latches_reg <= update_conf_latches;
|
| 16526 |
|
|
reconfig_err <= false;
|
| 16527 |
|
|
scandone_tmp <= '0';
|
| 16528 |
|
|
cp_curr_old <= cp_curr_val;
|
| 16529 |
|
|
lfc_old <= lfc_val;
|
| 16530 |
|
|
lfr_old <= lfr_val;
|
| 16531 |
|
|
-- LF unused : bit 0,1
|
| 16532 |
|
|
-- LF Capacitance : bits 2,3 : all values are legal
|
| 16533 |
|
|
buf_scan_data := scan_data(2 TO 3);
|
| 16534 |
|
|
|
| 16535 |
|
|
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
|
| 16536 |
|
|
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
|
| 16537 |
|
|
ELSE
|
| 16538 |
|
|
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
|
| 16539 |
|
|
END IF;
|
| 16540 |
|
|
-- LF Resistance : bits 4-8
|
| 16541 |
|
|
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
|
| 16542 |
|
|
IF (scan_data(4 TO 8) = "00000") THEN
|
| 16543 |
|
|
lfr_val <= "20";
|
| 16544 |
|
|
ELSIF (scan_data(4 TO 8) = "00100") THEN
|
| 16545 |
|
|
lfr_val <= "16";
|
| 16546 |
|
|
ELSIF (scan_data(4 TO 8) = "10000") THEN
|
| 16547 |
|
|
lfr_val <= "12";
|
| 16548 |
|
|
ELSIF (scan_data(4 TO 8) = "10100") THEN
|
| 16549 |
|
|
lfr_val <= "08";
|
| 16550 |
|
|
ELSIF (scan_data(4 TO 8) = "11000") THEN
|
| 16551 |
|
|
lfr_val <= "06";
|
| 16552 |
|
|
ELSIF (scan_data(4 TO 8) = "11011") THEN
|
| 16553 |
|
|
lfr_val <= "04";
|
| 16554 |
|
|
ELSIF (scan_data(4 TO 8) = "11100") THEN
|
| 16555 |
|
|
lfr_val <= "02";
|
| 16556 |
|
|
ELSE
|
| 16557 |
|
|
lfr_val <= "01";
|
| 16558 |
|
|
END IF;
|
| 16559 |
|
|
|
| 16560 |
|
|
|
| 16561 |
|
|
-- VCO post scale assignment
|
| 16562 |
|
|
if (scan_data(9) = '0') then -- vco_post_scale = 1
|
| 16563 |
|
|
i_vco_max <= vco_max/2;
|
| 16564 |
|
|
i_vco_min <= vco_min/2;
|
| 16565 |
|
|
else
|
| 16566 |
|
|
i_vco_max <= vco_max;
|
| 16567 |
|
|
i_vco_min <= vco_min;
|
| 16568 |
|
|
end if;
|
| 16569 |
|
|
-- CP
|
| 16570 |
|
|
-- Bit 9 : CRBYPASS
|
| 16571 |
|
|
-- Bit 10-14 : unused
|
| 16572 |
|
|
-- Bits 15-17 : all values are legal
|
| 16573 |
|
|
|
| 16574 |
|
|
buf_scan_data_2 := scan_data(15 TO 17);
|
| 16575 |
|
|
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
|
| 16576 |
|
|
-- save old values for display info.
|
| 16577 |
|
|
|
| 16578 |
|
|
cp_curr_val_bit_setting <= scan_data(15 TO 17);
|
| 16579 |
|
|
lfc_val_bit_setting <= scan_data(2 TO 3);
|
| 16580 |
|
|
lfr_val_bit_setting <= scan_data(4 TO 8);
|
| 16581 |
|
|
|
| 16582 |
|
|
m_val_old <= m_val;
|
| 16583 |
|
|
n_val_old <= n_val;
|
| 16584 |
|
|
m_mode_val_old <= m_mode_val;
|
| 16585 |
|
|
n_mode_val_old <= n_mode_val;
|
| 16586 |
|
|
WHILE (i < num_output_cntrs) LOOP
|
| 16587 |
|
|
c_high_val_old(i) <= c_high_val(i);
|
| 16588 |
|
|
c_low_val_old(i) <= c_low_val(i);
|
| 16589 |
|
|
c_mode_val_old(i) <= c_mode_val(i);
|
| 16590 |
|
|
i := i + 1;
|
| 16591 |
|
|
END LOOP;
|
| 16592 |
|
|
-- M counter
|
| 16593 |
|
|
-- 1. Mode - bypass (bit 18)
|
| 16594 |
|
|
|
| 16595 |
|
|
IF (scan_data(18) = '1') THEN
|
| 16596 |
|
|
m_mode_val <= "bypass";
|
| 16597 |
|
|
-- 3. Mode - odd/even (bit 27)
|
| 16598 |
|
|
ELSIF (scan_data(27) = '1') THEN
|
| 16599 |
|
|
m_mode_val <= " odd";
|
| 16600 |
|
|
ELSE
|
| 16601 |
|
|
m_mode_val <= " even";
|
| 16602 |
|
|
END IF;
|
| 16603 |
|
|
|
| 16604 |
|
|
-- 2. High (bit 19-26)
|
| 16605 |
|
|
|
| 16606 |
|
|
m_hi := scan_data(19 TO 26);
|
| 16607 |
|
|
|
| 16608 |
|
|
-- 4. Low (bit 28-35)
|
| 16609 |
|
|
|
| 16610 |
|
|
m_lo := scan_data(28 TO 35);
|
| 16611 |
|
|
-- N counter
|
| 16612 |
|
|
-- 1. Mode - bypass (bit 36)
|
| 16613 |
|
|
|
| 16614 |
|
|
IF (scan_data(36) = '1') THEN
|
| 16615 |
|
|
n_mode_val <= "bypass";
|
| 16616 |
|
|
-- 3. Mode - odd/even (bit 45)
|
| 16617 |
|
|
ELSIF (scan_data(45) = '1') THEN
|
| 16618 |
|
|
n_mode_val <= " odd";
|
| 16619 |
|
|
ELSE
|
| 16620 |
|
|
n_mode_val <= " even";
|
| 16621 |
|
|
END IF;
|
| 16622 |
|
|
|
| 16623 |
|
|
-- 2. High (bit 37-44)
|
| 16624 |
|
|
|
| 16625 |
|
|
n_hi := scan_data(37 TO 44);
|
| 16626 |
|
|
|
| 16627 |
|
|
-- 4. Low (bit 46-53)
|
| 16628 |
|
|
|
| 16629 |
|
|
n_lo := scan_data(46 TO 53);
|
| 16630 |
|
|
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
|
| 16631 |
|
|
|
| 16632 |
|
|
i := 0;
|
| 16633 |
|
|
WHILE (i < num_output_cntrs) LOOP
|
| 16634 |
|
|
-- 1. Mode - bypass
|
| 16635 |
|
|
|
| 16636 |
|
|
IF (scan_data(54 + i * 18 + 0) = '1') THEN
|
| 16637 |
|
|
c_mode_val_tmp(i) := "bypass";
|
| 16638 |
|
|
-- 3. Mode - odd/even
|
| 16639 |
|
|
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
|
| 16640 |
|
|
c_mode_val_tmp(i) := " odd";
|
| 16641 |
|
|
ELSE
|
| 16642 |
|
|
c_mode_val_tmp(i) := " even";
|
| 16643 |
|
|
END IF;
|
| 16644 |
|
|
-- 2. Hi
|
| 16645 |
|
|
|
| 16646 |
|
|
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
|
| 16647 |
|
|
c_hval(i) := alt_conv_integer(high);
|
| 16648 |
|
|
IF (c_hval(i) /= 0) THEN
|
| 16649 |
|
|
c_high_val_tmp(i) := c_hval(i);
|
| 16650 |
|
|
ELSE
|
| 16651 |
|
|
c_high_val_tmp(i) := alt_conv_integer("000000001");
|
| 16652 |
|
|
END IF;
|
| 16653 |
|
|
|
| 16654 |
|
|
-- 4. Low
|
| 16655 |
|
|
|
| 16656 |
|
|
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
|
| 16657 |
|
|
c_lval(i) := alt_conv_integer(low);
|
| 16658 |
|
|
IF (c_lval(i) /= 0) THEN
|
| 16659 |
|
|
c_low_val_tmp(i) := c_lval(i);
|
| 16660 |
|
|
ELSE
|
| 16661 |
|
|
c_low_val_tmp(i) := alt_conv_integer("000000001");
|
| 16662 |
|
|
END IF;
|
| 16663 |
|
|
i := i + 1;
|
| 16664 |
|
|
END LOOP;
|
| 16665 |
|
|
-- Legality Checks
|
| 16666 |
|
|
|
| 16667 |
|
|
-- M counter value
|
| 16668 |
|
|
IF(scan_data(18) /= '1') THEN
|
| 16669 |
|
|
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
|
| 16670 |
|
|
reconfig_err <= TRUE;
|
| 16671 |
|
|
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
|
| 16672 |
|
|
writeline(output, buf);
|
| 16673 |
|
|
ELSIF (m_hi /= "00000000") THEN
|
| 16674 |
|
|
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
|
| 16675 |
|
|
ELSE
|
| 16676 |
|
|
m_val_tmp := alt_conv_integer("000000001");
|
| 16677 |
|
|
END IF;
|
| 16678 |
|
|
ELSE
|
| 16679 |
|
|
m_val_tmp := alt_conv_integer("10000000");
|
| 16680 |
|
|
END IF;
|
| 16681 |
|
|
-- N counter value
|
| 16682 |
|
|
IF(scan_data(36) /= '1') THEN
|
| 16683 |
|
|
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
|
| 16684 |
|
|
reconfig_err <= TRUE;
|
| 16685 |
|
|
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
|
| 16686 |
|
|
writeline(output, buf);
|
| 16687 |
|
|
ELSIF (n_hi /= "00000000") THEN
|
| 16688 |
|
|
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
|
| 16689 |
|
|
ELSE
|
| 16690 |
|
|
n_val <= alt_conv_integer("000000001");
|
| 16691 |
|
|
END IF;
|
| 16692 |
|
|
ELSE
|
| 16693 |
|
|
n_val <= alt_conv_integer("10000000");
|
| 16694 |
|
|
END IF;
|
| 16695 |
|
|
-- TODO : Give warnings/errors in the following cases?
|
| 16696 |
|
|
-- 1. Illegal counter values (error)
|
| 16697 |
|
|
-- 2. Change of mode (warning)
|
| 16698 |
|
|
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
|
| 16699 |
|
|
|
| 16700 |
|
|
END IF;
|
| 16701 |
|
|
end if;
|
| 16702 |
|
|
|
| 16703 |
|
|
|
| 16704 |
|
|
if (fbclk'event and fbclk = '1') then
|
| 16705 |
|
|
m_val <= m_val_tmp;
|
| 16706 |
|
|
end if;
|
| 16707 |
|
|
|
| 16708 |
|
|
if (update_conf_latches_reg = '1') then
|
| 16709 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16710 |
|
|
c0_rising_edge_transfer_done := true;
|
| 16711 |
|
|
c_high_val(0) <= c_high_val_tmp(0);
|
| 16712 |
|
|
c_mode_val(0) <= c_mode_val_tmp(0);
|
| 16713 |
|
|
end if;
|
| 16714 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16715 |
|
|
c1_rising_edge_transfer_done := true;
|
| 16716 |
|
|
c_high_val(1) <= c_high_val_tmp(1);
|
| 16717 |
|
|
c_mode_val(1) <= c_mode_val_tmp(1);
|
| 16718 |
|
|
end if;
|
| 16719 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16720 |
|
|
c2_rising_edge_transfer_done := true;
|
| 16721 |
|
|
c_high_val(2) <= c_high_val_tmp(2);
|
| 16722 |
|
|
c_mode_val(2) <= c_mode_val_tmp(2);
|
| 16723 |
|
|
end if;
|
| 16724 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16725 |
|
|
c_high_val(3) <= c_high_val_tmp(3);
|
| 16726 |
|
|
c_mode_val(3) <= c_mode_val_tmp(3);
|
| 16727 |
|
|
c3_rising_edge_transfer_done := true;
|
| 16728 |
|
|
end if;
|
| 16729 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16730 |
|
|
c_high_val(4) <= c_high_val_tmp(4);
|
| 16731 |
|
|
c_mode_val(4) <= c_mode_val_tmp(4);
|
| 16732 |
|
|
c4_rising_edge_transfer_done := true;
|
| 16733 |
|
|
end if;
|
| 16734 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16735 |
|
|
c_high_val(5) <= c_high_val_tmp(5);
|
| 16736 |
|
|
c_mode_val(5) <= c_mode_val_tmp(5);
|
| 16737 |
|
|
c5_rising_edge_transfer_done := true;
|
| 16738 |
|
|
end if;
|
| 16739 |
|
|
|
| 16740 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16741 |
|
|
c_high_val(6) <= c_high_val_tmp(6);
|
| 16742 |
|
|
c_mode_val(6) <= c_mode_val_tmp(6);
|
| 16743 |
|
|
c6_rising_edge_transfer_done := true;
|
| 16744 |
|
|
end if;
|
| 16745 |
|
|
|
| 16746 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16747 |
|
|
c_high_val(7) <= c_high_val_tmp(7);
|
| 16748 |
|
|
c_mode_val(7) <= c_mode_val_tmp(7);
|
| 16749 |
|
|
c7_rising_edge_transfer_done := true;
|
| 16750 |
|
|
end if;
|
| 16751 |
|
|
|
| 16752 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16753 |
|
|
c_high_val(8) <= c_high_val_tmp(8);
|
| 16754 |
|
|
c_mode_val(8) <= c_mode_val_tmp(8);
|
| 16755 |
|
|
c8_rising_edge_transfer_done := true;
|
| 16756 |
|
|
end if;
|
| 16757 |
|
|
|
| 16758 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1') then
|
| 16759 |
|
|
c_high_val(9) <= c_high_val_tmp(9);
|
| 16760 |
|
|
c_mode_val(9) <= c_mode_val_tmp(9);
|
| 16761 |
|
|
c9_rising_edge_transfer_done := true;
|
| 16762 |
|
|
end if;
|
| 16763 |
|
|
|
| 16764 |
|
|
end if;
|
| 16765 |
|
|
|
| 16766 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
|
| 16767 |
|
|
c_low_val(0) <= c_low_val_tmp(0);
|
| 16768 |
|
|
end if;
|
| 16769 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
|
| 16770 |
|
|
c_low_val(1) <= c_low_val_tmp(1);
|
| 16771 |
|
|
end if;
|
| 16772 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
|
| 16773 |
|
|
c_low_val(2) <= c_low_val_tmp(2);
|
| 16774 |
|
|
end if;
|
| 16775 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
|
| 16776 |
|
|
c_low_val(3) <= c_low_val_tmp(3);
|
| 16777 |
|
|
end if;
|
| 16778 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
|
| 16779 |
|
|
c_low_val(4) <= c_low_val_tmp(4);
|
| 16780 |
|
|
end if;
|
| 16781 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
|
| 16782 |
|
|
c_low_val(5) <= c_low_val_tmp(5);
|
| 16783 |
|
|
end if;
|
| 16784 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
|
| 16785 |
|
|
c_low_val(6) <= c_low_val_tmp(6);
|
| 16786 |
|
|
end if;
|
| 16787 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
|
| 16788 |
|
|
c_low_val(7) <= c_low_val_tmp(7);
|
| 16789 |
|
|
end if;
|
| 16790 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
|
| 16791 |
|
|
c_low_val(8) <= c_low_val_tmp(8);
|
| 16792 |
|
|
end if;
|
| 16793 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
|
| 16794 |
|
|
c_low_val(9) <= c_low_val_tmp(9);
|
| 16795 |
|
|
end if;
|
| 16796 |
|
|
|
| 16797 |
|
|
if (update_phase = '1') then
|
| 16798 |
|
|
if (vco_out(0)'event and vco_out(0) = '0') then
|
| 16799 |
|
|
for i in 0 to 9 loop
|
| 16800 |
|
|
if (c_ph_val(i) = 0) then
|
| 16801 |
|
|
c_ph_val(i) <= c_ph_val_tmp(i);
|
| 16802 |
|
|
end if;
|
| 16803 |
|
|
end loop;
|
| 16804 |
|
|
if (m_ph_val = 0) then
|
| 16805 |
|
|
m_ph_val <= m_ph_val_tmp;
|
| 16806 |
|
|
end if;
|
| 16807 |
|
|
end if;
|
| 16808 |
|
|
if (vco_out(1)'event and vco_out(1) = '0') then
|
| 16809 |
|
|
for i in 0 to 9 loop
|
| 16810 |
|
|
if (c_ph_val(i) = 1) then
|
| 16811 |
|
|
c_ph_val(i) <= c_ph_val_tmp(i);
|
| 16812 |
|
|
end if;
|
| 16813 |
|
|
end loop;
|
| 16814 |
|
|
if (m_ph_val = 1) then
|
| 16815 |
|
|
m_ph_val <= m_ph_val_tmp;
|
| 16816 |
|
|
end if;
|
| 16817 |
|
|
end if;
|
| 16818 |
|
|
if (vco_out(2)'event and vco_out(2) = '0') then
|
| 16819 |
|
|
for i in 0 to 9 loop
|
| 16820 |
|
|
if (c_ph_val(i) = 2) then
|
| 16821 |
|
|
c_ph_val(i) <= c_ph_val_tmp(i);
|
| 16822 |
|
|
end if;
|
| 16823 |
|
|
end loop;
|
| 16824 |
|
|
if (m_ph_val = 2) then
|
| 16825 |
|
|
m_ph_val <= m_ph_val_tmp;
|
| 16826 |
|
|
end if;
|
| 16827 |
|
|
end if;
|
| 16828 |
|
|
if (vco_out(3)'event and vco_out(3) = '0') then
|
| 16829 |
|
|
for i in 0 to 9 loop
|
| 16830 |
|
|
if (c_ph_val(i) = 3) then
|
| 16831 |
|
|
c_ph_val(i) <= c_ph_val_tmp(i);
|
| 16832 |
|
|
end if;
|
| 16833 |
|
|
end loop;
|
| 16834 |
|
|
if (m_ph_val = 3) then
|
| 16835 |
|
|
m_ph_val <= m_ph_val_tmp;
|
| 16836 |
|
|
end if;
|
| 16837 |
|
|
end if;
|
| 16838 |
|
|
if (vco_out(4)'event and vco_out(4) = '0') then
|
| 16839 |
|
|
for i in 0 to 9 loop
|
| 16840 |
|
|
if (c_ph_val(i) = 4) then
|
| 16841 |
|
|
c_ph_val(i) <= c_ph_val_tmp(i);
|
| 16842 |
|
|
end if;
|
| 16843 |
|
|
end loop;
|
| 16844 |
|
|
if (m_ph_val = 4) then
|
| 16845 |
|
|
m_ph_val <= m_ph_val_tmp;
|
| 16846 |
|
|
end if;
|
| 16847 |
|
|
end if;
|
| 16848 |
|
|
if (vco_out(5)'event and vco_out(5) = '0') then
|
| 16849 |
|
|
for i in 0 to 9 loop
|
| 16850 |
|
|
if (c_ph_val(i) = 5) then
|
| 16851 |
|
|
c_ph_val(i) <= c_ph_val_tmp(i);
|
| 16852 |
|
|
end if;
|
| 16853 |
|
|
end loop;
|
| 16854 |
|
|
if (m_ph_val = 5) then
|
| 16855 |
|
|
m_ph_val <= m_ph_val_tmp;
|
| 16856 |
|
|
end if;
|
| 16857 |
|
|
end if;
|
| 16858 |
|
|
if (vco_out(6)'event and vco_out(6) = '0') then
|
| 16859 |
|
|
for i in 0 to 9 loop
|
| 16860 |
|
|
if (c_ph_val(i) = 6) then
|
| 16861 |
|
|
c_ph_val(i) <= c_ph_val_tmp(i);
|
| 16862 |
|
|
end if;
|
| 16863 |
|
|
end loop;
|
| 16864 |
|
|
if (m_ph_val = 6) then
|
| 16865 |
|
|
m_ph_val <= m_ph_val_tmp;
|
| 16866 |
|
|
end if;
|
| 16867 |
|
|
end if;
|
| 16868 |
|
|
if (vco_out(7)'event and vco_out(7) = '0') then
|
| 16869 |
|
|
for i in 0 to 9 loop
|
| 16870 |
|
|
if (c_ph_val(i) = 7) then
|
| 16871 |
|
|
c_ph_val(i) <= c_ph_val_tmp(i);
|
| 16872 |
|
|
end if;
|
| 16873 |
|
|
end loop;
|
| 16874 |
|
|
if (m_ph_val = 7) then
|
| 16875 |
|
|
m_ph_val <= m_ph_val_tmp;
|
| 16876 |
|
|
end if;
|
| 16877 |
|
|
end if;
|
| 16878 |
|
|
end if;
|
| 16879 |
|
|
|
| 16880 |
|
|
|
| 16881 |
|
|
|
| 16882 |
|
|
if (vco_out(0)'event) then
|
| 16883 |
|
|
for i in 0 to 9 loop
|
| 16884 |
|
|
if (c_ph_val(i) = 0) then
|
| 16885 |
|
|
inclk_c_from_vco(i) <= vco_out(0);
|
| 16886 |
|
|
end if;
|
| 16887 |
|
|
end loop;
|
| 16888 |
|
|
if (m_ph_val = 0) then
|
| 16889 |
|
|
inclk_m_from_vco <= vco_out(0);
|
| 16890 |
|
|
end if;
|
| 16891 |
|
|
end if;
|
| 16892 |
|
|
if (vco_out(1)'event) then
|
| 16893 |
|
|
for i in 0 to 9 loop
|
| 16894 |
|
|
if (c_ph_val(i) = 1) then
|
| 16895 |
|
|
inclk_c_from_vco(i) <= vco_out(1);
|
| 16896 |
|
|
end if;
|
| 16897 |
|
|
end loop;
|
| 16898 |
|
|
if (m_ph_val = 1) then
|
| 16899 |
|
|
inclk_m_from_vco <= vco_out(1);
|
| 16900 |
|
|
end if;
|
| 16901 |
|
|
end if;
|
| 16902 |
|
|
if (vco_out(2)'event) then
|
| 16903 |
|
|
for i in 0 to 9 loop
|
| 16904 |
|
|
if (c_ph_val(i) = 2) then
|
| 16905 |
|
|
inclk_c_from_vco(i) <= vco_out(2);
|
| 16906 |
|
|
end if;
|
| 16907 |
|
|
end loop;
|
| 16908 |
|
|
if (m_ph_val = 2) then
|
| 16909 |
|
|
inclk_m_from_vco <= vco_out(2);
|
| 16910 |
|
|
end if;
|
| 16911 |
|
|
end if;
|
| 16912 |
|
|
if (vco_out(3)'event) then
|
| 16913 |
|
|
for i in 0 to 9 loop
|
| 16914 |
|
|
if (c_ph_val(i) = 3) then
|
| 16915 |
|
|
inclk_c_from_vco(i) <= vco_out(3);
|
| 16916 |
|
|
end if;
|
| 16917 |
|
|
end loop;
|
| 16918 |
|
|
if (m_ph_val = 3) then
|
| 16919 |
|
|
inclk_m_from_vco <= vco_out(3);
|
| 16920 |
|
|
end if;
|
| 16921 |
|
|
end if;
|
| 16922 |
|
|
if (vco_out(4)'event) then
|
| 16923 |
|
|
for i in 0 to 9 loop
|
| 16924 |
|
|
if (c_ph_val(i) = 4) then
|
| 16925 |
|
|
inclk_c_from_vco(i) <= vco_out(4);
|
| 16926 |
|
|
end if;
|
| 16927 |
|
|
end loop;
|
| 16928 |
|
|
if (m_ph_val = 4) then
|
| 16929 |
|
|
inclk_m_from_vco <= vco_out(4);
|
| 16930 |
|
|
end if;
|
| 16931 |
|
|
end if;
|
| 16932 |
|
|
if (vco_out(5)'event) then
|
| 16933 |
|
|
for i in 0 to 9 loop
|
| 16934 |
|
|
if (c_ph_val(i) = 5) then
|
| 16935 |
|
|
inclk_c_from_vco(i) <= vco_out(5);
|
| 16936 |
|
|
end if;
|
| 16937 |
|
|
end loop;
|
| 16938 |
|
|
if (m_ph_val = 5) then
|
| 16939 |
|
|
inclk_m_from_vco <= vco_out(5);
|
| 16940 |
|
|
end if;
|
| 16941 |
|
|
end if;
|
| 16942 |
|
|
if (vco_out(6)'event) then
|
| 16943 |
|
|
for i in 0 to 9 loop
|
| 16944 |
|
|
if (c_ph_val(i) = 6) then
|
| 16945 |
|
|
inclk_c_from_vco(i) <= vco_out(6);
|
| 16946 |
|
|
end if;
|
| 16947 |
|
|
end loop;
|
| 16948 |
|
|
if (m_ph_val = 6) then
|
| 16949 |
|
|
inclk_m_from_vco <= vco_out(6);
|
| 16950 |
|
|
end if;
|
| 16951 |
|
|
end if;
|
| 16952 |
|
|
if (vco_out(7)'event) then
|
| 16953 |
|
|
for i in 0 to 9 loop
|
| 16954 |
|
|
if (c_ph_val(i) = 7) then
|
| 16955 |
|
|
inclk_c_from_vco(i) <= vco_out(7);
|
| 16956 |
|
|
end if;
|
| 16957 |
|
|
end loop;
|
| 16958 |
|
|
if (m_ph_val = 7) then
|
| 16959 |
|
|
inclk_m_from_vco <= vco_out(7);
|
| 16960 |
|
|
end if;
|
| 16961 |
|
|
end if;
|
| 16962 |
|
|
|
| 16963 |
|
|
|
| 16964 |
|
|
------------------------
|
| 16965 |
|
|
-- Timing Check Section
|
| 16966 |
|
|
------------------------
|
| 16967 |
|
|
if (TimingChecksOn) then
|
| 16968 |
|
|
VitalSetupHoldCheck (
|
| 16969 |
|
|
Violation => Tviol_scandata_scanclk,
|
| 16970 |
|
|
TimingData => TimingData_scandata_scanclk,
|
| 16971 |
|
|
TestSignal => scandata_ipd,
|
| 16972 |
|
|
TestSignalName => "scandata",
|
| 16973 |
|
|
RefSignal => scanclk_ipd,
|
| 16974 |
|
|
RefSignalName => "scanclk",
|
| 16975 |
|
|
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
|
| 16976 |
|
|
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
|
| 16977 |
|
|
HoldHigh => thold_scandata_scanclk_noedge_negedge,
|
| 16978 |
|
|
HoldLow => thold_scandata_scanclk_noedge_negedge,
|
| 16979 |
|
|
CheckEnabled => TRUE,
|
| 16980 |
|
|
RefTransition => '\',
|
| 16981 |
|
|
HeaderMsg => InstancePath & "/stratixiii_pll",
|
| 16982 |
|
|
XOn => XOnChecks,
|
| 16983 |
|
|
MsgOn => MsgOnChecks );
|
| 16984 |
|
|
|
| 16985 |
|
|
|
| 16986 |
|
|
|
| 16987 |
|
|
VitalSetupHoldCheck (
|
| 16988 |
|
|
Violation => Tviol_scanclkena_scanclk,
|
| 16989 |
|
|
TimingData => TimingData_scanclkena_scanclk,
|
| 16990 |
|
|
TestSignal => scanclkena_ipd,
|
| 16991 |
|
|
TestSignalName => "scanclkena",
|
| 16992 |
|
|
RefSignal => scanclk_ipd,
|
| 16993 |
|
|
RefSignalName => "scanclk",
|
| 16994 |
|
|
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
|
| 16995 |
|
|
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
|
| 16996 |
|
|
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
|
| 16997 |
|
|
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
|
| 16998 |
|
|
CheckEnabled => TRUE,
|
| 16999 |
|
|
RefTransition => '\',
|
| 17000 |
|
|
HeaderMsg => InstancePath & "/stratixiii_pll",
|
| 17001 |
|
|
XOn => XOnChecks,
|
| 17002 |
|
|
MsgOn => MsgOnChecks );
|
| 17003 |
|
|
|
| 17004 |
|
|
end if;
|
| 17005 |
|
|
|
| 17006 |
|
|
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
|
| 17007 |
|
|
scanclkena_reg <= scanclkena_ipd;
|
| 17008 |
|
|
if (scanclkena_reg = '1') then
|
| 17009 |
|
|
scandata_in <= scandata_ipd;
|
| 17010 |
|
|
scandata_out <= scandataout_tmp;
|
| 17011 |
|
|
end if;
|
| 17012 |
|
|
end if;
|
| 17013 |
|
|
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
|
| 17014 |
|
|
if (got_first_scanclk) then
|
| 17015 |
|
|
scanclk_period <= now - scanclk_last_rising_edge;
|
| 17016 |
|
|
else
|
| 17017 |
|
|
got_first_scanclk := true;
|
| 17018 |
|
|
end if;
|
| 17019 |
|
|
if (scanclkena_reg = '1') then
|
| 17020 |
|
|
for j in scan_chain_length - 1 downto 1 loop
|
| 17021 |
|
|
scan_data(j) <= scan_data(j-1);
|
| 17022 |
|
|
end loop;
|
| 17023 |
|
|
scan_data(0) <= scandata_in;
|
| 17024 |
|
|
end if;
|
| 17025 |
|
|
scanclk_last_rising_edge := now;
|
| 17026 |
|
|
end if;
|
| 17027 |
|
|
end process;
|
| 17028 |
|
|
|
| 17029 |
|
|
-- PLL Phase Reconfiguration
|
| 17030 |
|
|
|
| 17031 |
|
|
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
|
| 17032 |
|
|
VARIABLE i : INTEGER := 0;
|
| 17033 |
|
|
VARIABLE c_ph : INTEGER := 0;
|
| 17034 |
|
|
VARIABLE m_ph : INTEGER := 0;
|
| 17035 |
|
|
VARIABLE select_counter : INTEGER := 0;
|
| 17036 |
|
|
BEGIN
|
| 17037 |
|
|
IF (NOW = 0 ps) THEN
|
| 17038 |
|
|
m_ph_val_tmp <= m_ph_initial;
|
| 17039 |
|
|
END IF;
|
| 17040 |
|
|
|
| 17041 |
|
|
-- Latch phase enable (same as phasestep) on neg edge of scan clock
|
| 17042 |
|
|
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
|
| 17043 |
|
|
phasestep_reg <= phasestep_ipd;
|
| 17044 |
|
|
END IF;
|
| 17045 |
|
|
|
| 17046 |
|
|
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
|
| 17047 |
|
|
IF (update_phase = '0') THEN
|
| 17048 |
|
|
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
|
| 17049 |
|
|
-- if not, next phasestep cycle is skipped
|
| 17050 |
|
|
END IF;
|
| 17051 |
|
|
END IF;
|
| 17052 |
|
|
-- revert counter phase tap values to POF programmed values
|
| 17053 |
|
|
-- if PLL is reset
|
| 17054 |
|
|
|
| 17055 |
|
|
IF (areset_ipd'EVENT AND areset_ipd = '1') then
|
| 17056 |
|
|
c_ph_val_tmp <= c_ph_val_orig;
|
| 17057 |
|
|
m_ph_val_tmp <= m_ph_initial;
|
| 17058 |
|
|
END IF;
|
| 17059 |
|
|
|
| 17060 |
|
|
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
|
| 17061 |
|
|
IF (phasestep_reg = '1') THEN
|
| 17062 |
|
|
IF (phasestep_high_count = 1) THEN
|
| 17063 |
|
|
phasecounterselect_reg <= phasecounterselect_ipd;
|
| 17064 |
|
|
phaseupdown_reg <= phaseupdown_ipd;
|
| 17065 |
|
|
-- start reconfiguration
|
| 17066 |
|
|
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
|
| 17067 |
|
|
IF (phasecounterselect_ipd = "0000") THEN
|
| 17068 |
|
|
WHILE (i < num_output_cntrs) LOOP
|
| 17069 |
|
|
c_ph := c_ph_val(i);
|
| 17070 |
|
|
IF (phaseupdown_ipd = '1') THEN
|
| 17071 |
|
|
c_ph := (c_ph + 1) mod num_phase_taps;
|
| 17072 |
|
|
ELSIF (c_ph = 0) THEN
|
| 17073 |
|
|
c_ph := num_phase_taps - 1;
|
| 17074 |
|
|
ELSE
|
| 17075 |
|
|
c_ph := (c_ph - 1) mod num_phase_taps;
|
| 17076 |
|
|
END IF;
|
| 17077 |
|
|
c_ph_val_tmp(i) <= c_ph;
|
| 17078 |
|
|
i := i + 1;
|
| 17079 |
|
|
END LOOP;
|
| 17080 |
|
|
ELSIF (phasecounterselect_ipd = "0001") THEN
|
| 17081 |
|
|
m_ph := m_ph_val;
|
| 17082 |
|
|
IF (phaseupdown_ipd = '1') THEN
|
| 17083 |
|
|
m_ph := (m_ph + 1) mod num_phase_taps;
|
| 17084 |
|
|
ELSIF (m_ph = 0) THEN
|
| 17085 |
|
|
m_ph := num_phase_taps - 1;
|
| 17086 |
|
|
ELSE
|
| 17087 |
|
|
m_ph := (m_ph - 1) mod num_phase_taps;
|
| 17088 |
|
|
END IF;
|
| 17089 |
|
|
m_ph_val_tmp <= m_ph;
|
| 17090 |
|
|
ELSE
|
| 17091 |
|
|
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
|
| 17092 |
|
|
c_ph := c_ph_val(select_counter);
|
| 17093 |
|
|
IF (phaseupdown_ipd = '1') THEN
|
| 17094 |
|
|
c_ph := (c_ph + 1) mod num_phase_taps;
|
| 17095 |
|
|
ELSIF (c_ph = 0) THEN
|
| 17096 |
|
|
c_ph := num_phase_taps - 1;
|
| 17097 |
|
|
ELSE
|
| 17098 |
|
|
c_ph := (c_ph - 1) mod num_phase_taps;
|
| 17099 |
|
|
END IF;
|
| 17100 |
|
|
c_ph_val_tmp(select_counter) <= c_ph;
|
| 17101 |
|
|
END IF;
|
| 17102 |
|
|
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
|
| 17103 |
|
|
END IF;
|
| 17104 |
|
|
END IF;
|
| 17105 |
|
|
phasestep_high_count <= phasestep_high_count + 1;
|
| 17106 |
|
|
|
| 17107 |
|
|
END IF;
|
| 17108 |
|
|
END IF;
|
| 17109 |
|
|
END PROCESS;
|
| 17110 |
|
|
|
| 17111 |
|
|
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
|
| 17112 |
|
|
|
| 17113 |
|
|
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
|
| 17114 |
|
|
variable sched_time : time := 0 ps;
|
| 17115 |
|
|
|
| 17116 |
|
|
TYPE time_array is ARRAY (0 to 7) of time;
|
| 17117 |
|
|
variable init : boolean := true;
|
| 17118 |
|
|
variable refclk_period : time;
|
| 17119 |
|
|
variable m_times_vco_period : time;
|
| 17120 |
|
|
variable new_m_times_vco_period : time;
|
| 17121 |
|
|
|
| 17122 |
|
|
variable phase_shift : time_array := (OTHERS => 0 ps);
|
| 17123 |
|
|
variable last_phase_shift : time_array := (OTHERS => 0 ps);
|
| 17124 |
|
|
|
| 17125 |
|
|
variable l_index : integer := 1;
|
| 17126 |
|
|
variable cycle_to_adjust : integer := 0;
|
| 17127 |
|
|
|
| 17128 |
|
|
variable stop_vco : boolean := false;
|
| 17129 |
|
|
|
| 17130 |
|
|
variable locked_tmp : std_logic := '0';
|
| 17131 |
|
|
variable pll_is_locked : boolean := false;
|
| 17132 |
|
|
variable cycles_pfd_low : integer := 0;
|
| 17133 |
|
|
variable cycles_pfd_high : integer := 0;
|
| 17134 |
|
|
variable cycles_to_lock : integer := 0;
|
| 17135 |
|
|
variable cycles_to_unlock : integer := 0;
|
| 17136 |
|
|
|
| 17137 |
|
|
variable got_first_refclk : boolean := false;
|
| 17138 |
|
|
variable got_second_refclk : boolean := false;
|
| 17139 |
|
|
variable got_first_fbclk : boolean := false;
|
| 17140 |
|
|
|
| 17141 |
|
|
variable refclk_time : time := 0 ps;
|
| 17142 |
|
|
variable fbclk_time : time := 0 ps;
|
| 17143 |
|
|
variable first_fbclk_time : time := 0 ps;
|
| 17144 |
|
|
|
| 17145 |
|
|
variable fbclk_period : time := 0 ps;
|
| 17146 |
|
|
|
| 17147 |
|
|
variable first_schedule : boolean := true;
|
| 17148 |
|
|
|
| 17149 |
|
|
variable vco_val : std_logic := '0';
|
| 17150 |
|
|
variable vco_period_was_phase_adjusted : boolean := false;
|
| 17151 |
|
|
variable phase_adjust_was_scheduled : boolean := false;
|
| 17152 |
|
|
|
| 17153 |
|
|
variable loop_xplier : integer;
|
| 17154 |
|
|
variable loop_initial : integer := 0;
|
| 17155 |
|
|
variable loop_ph : integer := 0;
|
| 17156 |
|
|
variable loop_time_delay : integer := 0;
|
| 17157 |
|
|
|
| 17158 |
|
|
variable initial_delay : time := 0 ps;
|
| 17159 |
|
|
variable vco_per : time;
|
| 17160 |
|
|
variable tmp_rem : integer;
|
| 17161 |
|
|
variable my_rem : integer;
|
| 17162 |
|
|
variable fbk_phase : integer := 0;
|
| 17163 |
|
|
|
| 17164 |
|
|
variable pull_back_M : integer := 0;
|
| 17165 |
|
|
variable total_pull_back : integer := 0;
|
| 17166 |
|
|
variable fbk_delay : integer := 0;
|
| 17167 |
|
|
|
| 17168 |
|
|
variable offset : time := 0 ps;
|
| 17169 |
|
|
|
| 17170 |
|
|
variable tmp_vco_per : integer := 0;
|
| 17171 |
|
|
variable high_time : time;
|
| 17172 |
|
|
variable low_time : time;
|
| 17173 |
|
|
|
| 17174 |
|
|
variable got_refclk_posedge : boolean := false;
|
| 17175 |
|
|
variable got_fbclk_posedge : boolean := false;
|
| 17176 |
|
|
variable inclk_out_of_range : boolean := false;
|
| 17177 |
|
|
variable no_warn : boolean := false;
|
| 17178 |
|
|
|
| 17179 |
|
|
variable ext_fbk_cntr_modulus : integer := 1;
|
| 17180 |
|
|
variable init_clks : boolean := true;
|
| 17181 |
|
|
variable pll_is_in_reset : boolean := false;
|
| 17182 |
|
|
variable buf : line;
|
| 17183 |
|
|
begin
|
| 17184 |
|
|
if (init) then
|
| 17185 |
|
|
|
| 17186 |
|
|
-- jump-start the VCO
|
| 17187 |
|
|
-- add 1 ps delay to ensure all signals are updated to initial
|
| 17188 |
|
|
-- values
|
| 17189 |
|
|
schedule_vco <= transport not schedule_vco after 1 ps;
|
| 17190 |
|
|
|
| 17191 |
|
|
init := false;
|
| 17192 |
|
|
end if;
|
| 17193 |
|
|
|
| 17194 |
|
|
if (schedule_vco'event) then
|
| 17195 |
|
|
if (init_clks) then
|
| 17196 |
|
|
refclk_period := inclk0_input_frequency * n_val * 1 ps;
|
| 17197 |
|
|
|
| 17198 |
|
|
m_times_vco_period := refclk_period;
|
| 17199 |
|
|
new_m_times_vco_period := refclk_period;
|
| 17200 |
|
|
init_clks := false;
|
| 17201 |
|
|
end if;
|
| 17202 |
|
|
sched_time := 0 ps;
|
| 17203 |
|
|
for i in 0 to 7 loop
|
| 17204 |
|
|
last_phase_shift(i) := phase_shift(i);
|
| 17205 |
|
|
end loop;
|
| 17206 |
|
|
cycle_to_adjust := 0;
|
| 17207 |
|
|
l_index := 1;
|
| 17208 |
|
|
m_times_vco_period := new_m_times_vco_period;
|
| 17209 |
|
|
end if;
|
| 17210 |
|
|
|
| 17211 |
|
|
-- areset was asserted
|
| 17212 |
|
|
if (areset_ipd'event and areset_ipd = '1') then
|
| 17213 |
|
|
assert false report family_name & " PLL was reset" severity note;
|
| 17214 |
|
|
-- reset lock parameters
|
| 17215 |
|
|
pll_is_locked := false;
|
| 17216 |
|
|
cycles_to_lock := 0;
|
| 17217 |
|
|
cycles_to_unlock := 0;
|
| 17218 |
|
|
end if;
|
| 17219 |
|
|
|
| 17220 |
|
|
|
| 17221 |
|
|
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
|
| 17222 |
|
|
|
| 17223 |
|
|
if (areset_ipd = '1') then
|
| 17224 |
|
|
pll_is_in_reset := true;
|
| 17225 |
|
|
end if;
|
| 17226 |
|
|
|
| 17227 |
|
|
-- drop VCO taps to 0
|
| 17228 |
|
|
for i in 0 to 7 loop
|
| 17229 |
|
|
vco_out(i) <= transport '0' after last_phase_shift(i);
|
| 17230 |
|
|
phase_shift(i) := 0 ps;
|
| 17231 |
|
|
last_phase_shift(i) := 0 ps;
|
| 17232 |
|
|
end loop;
|
| 17233 |
|
|
|
| 17234 |
|
|
-- reset lock parameters
|
| 17235 |
|
|
pll_is_locked := false;
|
| 17236 |
|
|
cycles_to_lock := 0;
|
| 17237 |
|
|
cycles_to_unlock := 0;
|
| 17238 |
|
|
|
| 17239 |
|
|
got_first_refclk := false;
|
| 17240 |
|
|
got_second_refclk := false;
|
| 17241 |
|
|
refclk_time := 0 ps;
|
| 17242 |
|
|
got_first_fbclk := false;
|
| 17243 |
|
|
fbclk_time := 0 ps;
|
| 17244 |
|
|
first_fbclk_time := 0 ps;
|
| 17245 |
|
|
fbclk_period := 0 ps;
|
| 17246 |
|
|
|
| 17247 |
|
|
first_schedule := true;
|
| 17248 |
|
|
vco_val := '0';
|
| 17249 |
|
|
vco_period_was_phase_adjusted := false;
|
| 17250 |
|
|
phase_adjust_was_scheduled := false;
|
| 17251 |
|
|
|
| 17252 |
|
|
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
|
| 17253 |
|
|
|
| 17254 |
|
|
-- note areset deassert time
|
| 17255 |
|
|
-- note it as refclk_time to prevent false triggering
|
| 17256 |
|
|
-- of stop_vco after areset
|
| 17257 |
|
|
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
|
| 17258 |
|
|
refclk_time := now;
|
| 17259 |
|
|
pll_is_in_reset := false;
|
| 17260 |
|
|
locked_tmp := '0';
|
| 17261 |
|
|
end if;
|
| 17262 |
|
|
|
| 17263 |
|
|
-- calculate loop_xplier : this will be different from m_val
|
| 17264 |
|
|
-- in external_feedback_mode
|
| 17265 |
|
|
loop_xplier := m_val;
|
| 17266 |
|
|
loop_initial := m_initial_val - 1;
|
| 17267 |
|
|
loop_ph := m_ph_val;
|
| 17268 |
|
|
|
| 17269 |
|
|
|
| 17270 |
|
|
-- convert initial value to delay
|
| 17271 |
|
|
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
|
| 17272 |
|
|
|
| 17273 |
|
|
-- convert loop ph_tap to delay
|
| 17274 |
|
|
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
|
| 17275 |
|
|
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
|
| 17276 |
|
|
if (my_rem /= 0) then
|
| 17277 |
|
|
tmp_vco_per := tmp_vco_per + 1;
|
| 17278 |
|
|
end if;
|
| 17279 |
|
|
fbk_phase := (loop_ph * tmp_vco_per)/8;
|
| 17280 |
|
|
|
| 17281 |
|
|
pull_back_M := initial_delay/1 ps + fbk_phase;
|
| 17282 |
|
|
|
| 17283 |
|
|
total_pull_back := pull_back_M;
|
| 17284 |
|
|
|
| 17285 |
|
|
if (simulation_type = "timing") then
|
| 17286 |
|
|
total_pull_back := total_pull_back + pll_compensation_delay;
|
| 17287 |
|
|
end if;
|
| 17288 |
|
|
while (total_pull_back > refclk_period/1 ps) loop
|
| 17289 |
|
|
total_pull_back := total_pull_back - refclk_period/1 ps;
|
| 17290 |
|
|
end loop;
|
| 17291 |
|
|
|
| 17292 |
|
|
if (total_pull_back > 0) then
|
| 17293 |
|
|
offset := refclk_period - (total_pull_back * 1 ps);
|
| 17294 |
|
|
end if;
|
| 17295 |
|
|
|
| 17296 |
|
|
fbk_delay := total_pull_back - fbk_phase;
|
| 17297 |
|
|
if (fbk_delay < 0) then
|
| 17298 |
|
|
offset := offset - (fbk_phase * 1 ps);
|
| 17299 |
|
|
fbk_delay := total_pull_back;
|
| 17300 |
|
|
end if;
|
| 17301 |
|
|
|
| 17302 |
|
|
-- assign m_delay
|
| 17303 |
|
|
m_delay <= transport fbk_delay after 1 ps;
|
| 17304 |
|
|
|
| 17305 |
|
|
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
|
| 17306 |
|
|
for i in 1 to loop_xplier loop
|
| 17307 |
|
|
-- adjust cycles
|
| 17308 |
|
|
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
|
| 17309 |
|
|
if (my_rem /= 0 and l_index <= my_rem) then
|
| 17310 |
|
|
tmp_rem := (loop_xplier * l_index) rem my_rem;
|
| 17311 |
|
|
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
|
| 17312 |
|
|
if (tmp_rem /= 0) then
|
| 17313 |
|
|
cycle_to_adjust := cycle_to_adjust + 1;
|
| 17314 |
|
|
end if;
|
| 17315 |
|
|
end if;
|
| 17316 |
|
|
if (cycle_to_adjust = i) then
|
| 17317 |
|
|
tmp_vco_per := tmp_vco_per + 1;
|
| 17318 |
|
|
l_index := l_index + 1;
|
| 17319 |
|
|
end if;
|
| 17320 |
|
|
|
| 17321 |
|
|
-- calculate high and low periods
|
| 17322 |
|
|
vco_per := tmp_vco_per * 1 ps;
|
| 17323 |
|
|
high_time := (tmp_vco_per/2) * 1 ps;
|
| 17324 |
|
|
if (tmp_vco_per rem 2 /= 0) then
|
| 17325 |
|
|
high_time := high_time + 1 ps;
|
| 17326 |
|
|
end if;
|
| 17327 |
|
|
low_time := vco_per - high_time;
|
| 17328 |
|
|
|
| 17329 |
|
|
-- schedule the rising and falling edges
|
| 17330 |
|
|
for j in 1 to 2 loop
|
| 17331 |
|
|
vco_val := not vco_val;
|
| 17332 |
|
|
if (vco_val = '0') then
|
| 17333 |
|
|
sched_time := sched_time + high_time;
|
| 17334 |
|
|
elsif (vco_val = '1') then
|
| 17335 |
|
|
sched_time := sched_time + low_time;
|
| 17336 |
|
|
end if;
|
| 17337 |
|
|
|
| 17338 |
|
|
-- schedule the phase taps
|
| 17339 |
|
|
for k in 0 to 7 loop
|
| 17340 |
|
|
phase_shift(k) := (k * vco_per)/8;
|
| 17341 |
|
|
if (first_schedule) then
|
| 17342 |
|
|
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
|
| 17343 |
|
|
else
|
| 17344 |
|
|
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
|
| 17345 |
|
|
end if;
|
| 17346 |
|
|
end loop;
|
| 17347 |
|
|
end loop;
|
| 17348 |
|
|
end loop;
|
| 17349 |
|
|
|
| 17350 |
|
|
-- schedule once more
|
| 17351 |
|
|
if (first_schedule) then
|
| 17352 |
|
|
vco_val := not vco_val;
|
| 17353 |
|
|
if (vco_val = '0') then
|
| 17354 |
|
|
sched_time := sched_time + high_time;
|
| 17355 |
|
|
elsif (vco_val = '1') then
|
| 17356 |
|
|
sched_time := sched_time + low_time;
|
| 17357 |
|
|
end if;
|
| 17358 |
|
|
-- schedule the phase taps
|
| 17359 |
|
|
for k in 0 to 7 loop
|
| 17360 |
|
|
phase_shift(k) := (k * vco_per)/8;
|
| 17361 |
|
|
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
|
| 17362 |
|
|
end loop;
|
| 17363 |
|
|
first_schedule := false;
|
| 17364 |
|
|
end if;
|
| 17365 |
|
|
|
| 17366 |
|
|
schedule_vco <= transport not schedule_vco after sched_time;
|
| 17367 |
|
|
|
| 17368 |
|
|
if (vco_period_was_phase_adjusted) then
|
| 17369 |
|
|
m_times_vco_period := refclk_period;
|
| 17370 |
|
|
new_m_times_vco_period := refclk_period;
|
| 17371 |
|
|
vco_period_was_phase_adjusted := false;
|
| 17372 |
|
|
phase_adjust_was_scheduled := true;
|
| 17373 |
|
|
|
| 17374 |
|
|
vco_per := m_times_vco_period/loop_xplier;
|
| 17375 |
|
|
for k in 0 to 7 loop
|
| 17376 |
|
|
phase_shift(k) := (k * vco_per)/8;
|
| 17377 |
|
|
end loop;
|
| 17378 |
|
|
end if;
|
| 17379 |
|
|
end if;
|
| 17380 |
|
|
-- Bypass lock detect
|
| 17381 |
|
|
|
| 17382 |
|
|
if (refclk'event and refclk = '1' and areset_ipd = '0') then
|
| 17383 |
|
|
if (test_bypass_lock_detect = "on") then
|
| 17384 |
|
|
if (pfdena_ipd = '1') then
|
| 17385 |
|
|
cycles_pfd_low := 0;
|
| 17386 |
|
|
if (pfd_locked = '0') then
|
| 17387 |
|
|
if (cycles_pfd_high = lock_high) then
|
| 17388 |
|
|
assert false report family_name & " PLL locked in test mode on PFD enable assertion.";
|
| 17389 |
|
|
pfd_locked <= '1';
|
| 17390 |
|
|
end if;
|
| 17391 |
|
|
cycles_pfd_high := cycles_pfd_high + 1;
|
| 17392 |
|
|
end if;
|
| 17393 |
|
|
end if;
|
| 17394 |
|
|
|
| 17395 |
|
|
if (pfdena_ipd = '0') then
|
| 17396 |
|
|
cycles_pfd_high := 0;
|
| 17397 |
|
|
if (pfd_locked = '1') then
|
| 17398 |
|
|
if (cycles_pfd_low = lock_low) then
|
| 17399 |
|
|
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion.";
|
| 17400 |
|
|
pfd_locked <= '0';
|
| 17401 |
|
|
end if;
|
| 17402 |
|
|
cycles_pfd_low := cycles_pfd_low + 1;
|
| 17403 |
|
|
end if;
|
| 17404 |
|
|
end if;
|
| 17405 |
|
|
end if;
|
| 17406 |
|
|
|
| 17407 |
|
|
|
| 17408 |
|
|
if (refclk'event and refclk = '1' and areset_ipd = '0') then
|
| 17409 |
|
|
got_refclk_posedge := true;
|
| 17410 |
|
|
if (not got_first_refclk) then
|
| 17411 |
|
|
got_first_refclk := true;
|
| 17412 |
|
|
else
|
| 17413 |
|
|
got_second_refclk := true;
|
| 17414 |
|
|
refclk_period := now - refclk_time;
|
| 17415 |
|
|
|
| 17416 |
|
|
-- check if incoming freq. will cause VCO range to be
|
| 17417 |
|
|
-- exceeded
|
| 17418 |
|
|
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
|
| 17419 |
|
|
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
|
| 17420 |
|
|
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
|
| 17421 |
|
|
if (pll_is_locked) then
|
| 17422 |
|
|
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
|
| 17423 |
|
|
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
|
| 17424 |
|
|
vco_over <= '1';
|
| 17425 |
|
|
end if;
|
| 17426 |
|
|
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
|
| 17427 |
|
|
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
|
| 17428 |
|
|
vco_under <= '1';
|
| 17429 |
|
|
end if;
|
| 17430 |
|
|
if (inclk_out_of_range) then
|
| 17431 |
|
|
pll_is_locked := false;
|
| 17432 |
|
|
locked_tmp := '0';
|
| 17433 |
|
|
cycles_to_lock := 0;
|
| 17434 |
|
|
vco_period_was_phase_adjusted := false;
|
| 17435 |
|
|
phase_adjust_was_scheduled := false;
|
| 17436 |
|
|
assert false report family_name & " PLL lost lock." severity note;
|
| 17437 |
|
|
end if;
|
| 17438 |
|
|
elsif (not no_warn) then
|
| 17439 |
|
|
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
|
| 17440 |
|
|
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
|
| 17441 |
|
|
vco_over <= '1';
|
| 17442 |
|
|
end if;
|
| 17443 |
|
|
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
|
| 17444 |
|
|
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
|
| 17445 |
|
|
vco_under <= '1';
|
| 17446 |
|
|
end if;
|
| 17447 |
|
|
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
|
| 17448 |
|
|
no_warn := true;
|
| 17449 |
|
|
end if;
|
| 17450 |
|
|
inclk_out_of_range := true;
|
| 17451 |
|
|
else
|
| 17452 |
|
|
vco_over <= '0';
|
| 17453 |
|
|
vco_under <= '0';
|
| 17454 |
|
|
inclk_out_of_range := false;
|
| 17455 |
|
|
no_warn := false;
|
| 17456 |
|
|
end if;
|
| 17457 |
|
|
end if;
|
| 17458 |
|
|
end if;
|
| 17459 |
|
|
|
| 17460 |
|
|
if (stop_vco) then
|
| 17461 |
|
|
stop_vco := false;
|
| 17462 |
|
|
schedule_vco <= not schedule_vco;
|
| 17463 |
|
|
end if;
|
| 17464 |
|
|
|
| 17465 |
|
|
refclk_time := now;
|
| 17466 |
|
|
else
|
| 17467 |
|
|
got_refclk_posedge := false;
|
| 17468 |
|
|
end if;
|
| 17469 |
|
|
|
| 17470 |
|
|
-- Update M counter value on feedback clock edge
|
| 17471 |
|
|
|
| 17472 |
|
|
if (fbclk'event and fbclk = '1') then
|
| 17473 |
|
|
got_fbclk_posedge := true;
|
| 17474 |
|
|
if (not got_first_fbclk) then
|
| 17475 |
|
|
got_first_fbclk := true;
|
| 17476 |
|
|
else
|
| 17477 |
|
|
fbclk_period := now - fbclk_time;
|
| 17478 |
|
|
end if;
|
| 17479 |
|
|
|
| 17480 |
|
|
-- need refclk_period here, so initialized to proper value above
|
| 17481 |
|
|
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
|
| 17482 |
|
|
stop_vco := true;
|
| 17483 |
|
|
-- reset
|
| 17484 |
|
|
got_first_refclk := false;
|
| 17485 |
|
|
got_first_fbclk := false;
|
| 17486 |
|
|
got_second_refclk := false;
|
| 17487 |
|
|
if (pll_is_locked) then
|
| 17488 |
|
|
pll_is_locked := false;
|
| 17489 |
|
|
locked_tmp := '0';
|
| 17490 |
|
|
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
|
| 17491 |
|
|
end if;
|
| 17492 |
|
|
cycles_to_lock := 0;
|
| 17493 |
|
|
cycles_to_unlock := 0;
|
| 17494 |
|
|
first_schedule := true;
|
| 17495 |
|
|
vco_period_was_phase_adjusted := false;
|
| 17496 |
|
|
phase_adjust_was_scheduled := false;
|
| 17497 |
|
|
end if;
|
| 17498 |
|
|
fbclk_time := now;
|
| 17499 |
|
|
else
|
| 17500 |
|
|
got_fbclk_posedge := false;
|
| 17501 |
|
|
end if;
|
| 17502 |
|
|
|
| 17503 |
|
|
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
|
| 17504 |
|
|
|
| 17505 |
|
|
-- now we know actual incoming period
|
| 17506 |
|
|
if ( abs(fbclk_time - refclk_time) <= 5 ps or
|
| 17507 |
|
|
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
|
| 17508 |
|
|
-- considered in phase
|
| 17509 |
|
|
if (cycles_to_lock = real_lock_high) then
|
| 17510 |
|
|
if (not pll_is_locked) then
|
| 17511 |
|
|
assert false report family_name & " PLL locked to incoming clock" severity note;
|
| 17512 |
|
|
end if;
|
| 17513 |
|
|
pll_is_locked := true;
|
| 17514 |
|
|
locked_tmp := '1';
|
| 17515 |
|
|
cycles_to_unlock := 0;
|
| 17516 |
|
|
end if;
|
| 17517 |
|
|
-- increment lock counter only if second part of above
|
| 17518 |
|
|
-- time check is NOT true
|
| 17519 |
|
|
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
|
| 17520 |
|
|
cycles_to_lock := cycles_to_lock + 1;
|
| 17521 |
|
|
end if;
|
| 17522 |
|
|
|
| 17523 |
|
|
-- adjust m_times_vco_period
|
| 17524 |
|
|
new_m_times_vco_period := refclk_period;
|
| 17525 |
|
|
else
|
| 17526 |
|
|
-- if locked, begin unlock
|
| 17527 |
|
|
if (pll_is_locked) then
|
| 17528 |
|
|
cycles_to_unlock := cycles_to_unlock + 1;
|
| 17529 |
|
|
if (cycles_to_unlock = lock_low) then
|
| 17530 |
|
|
pll_is_locked := false;
|
| 17531 |
|
|
locked_tmp := '0';
|
| 17532 |
|
|
cycles_to_lock := 0;
|
| 17533 |
|
|
vco_period_was_phase_adjusted := false;
|
| 17534 |
|
|
phase_adjust_was_scheduled := false;
|
| 17535 |
|
|
assert false report family_name & " PLL lost lock." severity note;
|
| 17536 |
|
|
end if;
|
| 17537 |
|
|
end if;
|
| 17538 |
|
|
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
|
| 17539 |
|
|
-- frequency is still good
|
| 17540 |
|
|
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
|
| 17541 |
|
|
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
|
| 17542 |
|
|
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
|
| 17543 |
|
|
vco_period_was_phase_adjusted := true;
|
| 17544 |
|
|
else
|
| 17545 |
|
|
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
|
| 17546 |
|
|
vco_period_was_phase_adjusted := true;
|
| 17547 |
|
|
end if;
|
| 17548 |
|
|
|
| 17549 |
|
|
end if;
|
| 17550 |
|
|
else
|
| 17551 |
|
|
phase_adjust_was_scheduled := false;
|
| 17552 |
|
|
new_m_times_vco_period := refclk_period;
|
| 17553 |
|
|
end if;
|
| 17554 |
|
|
end if;
|
| 17555 |
|
|
end if;
|
| 17556 |
|
|
|
| 17557 |
|
|
if (pfdena_ipd = '0') then
|
| 17558 |
|
|
if (pll_is_locked) then
|
| 17559 |
|
|
locked_tmp := 'X';
|
| 17560 |
|
|
end if;
|
| 17561 |
|
|
pll_is_locked := false;
|
| 17562 |
|
|
cycles_to_lock := 0;
|
| 17563 |
|
|
end if;
|
| 17564 |
|
|
|
| 17565 |
|
|
-- give message only at time of deassertion
|
| 17566 |
|
|
if (pfdena_ipd'event and pfdena_ipd = '0') then
|
| 17567 |
|
|
assert false report "PFDENA deasserted." severity note;
|
| 17568 |
|
|
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
|
| 17569 |
|
|
got_first_refclk := false;
|
| 17570 |
|
|
got_second_refclk := false;
|
| 17571 |
|
|
refclk_time := now;
|
| 17572 |
|
|
end if;
|
| 17573 |
|
|
|
| 17574 |
|
|
if (reconfig_err) then
|
| 17575 |
|
|
lock <= '0';
|
| 17576 |
|
|
else
|
| 17577 |
|
|
lock <= locked_tmp;
|
| 17578 |
|
|
end if;
|
| 17579 |
|
|
|
| 17580 |
|
|
-- signal to calculate quiet_time
|
| 17581 |
|
|
sig_refclk_period <= refclk_period;
|
| 17582 |
|
|
|
| 17583 |
|
|
if (stop_vco = true) then
|
| 17584 |
|
|
sig_stop_vco <= '1';
|
| 17585 |
|
|
else
|
| 17586 |
|
|
sig_stop_vco <= '0';
|
| 17587 |
|
|
end if;
|
| 17588 |
|
|
|
| 17589 |
|
|
pll_locked <= pll_is_locked;
|
| 17590 |
|
|
end process;
|
| 17591 |
|
|
|
| 17592 |
|
|
clk0_tmp <= c_clk(i_clk0_counter);
|
| 17593 |
|
|
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17594 |
|
|
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17595 |
|
|
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
|
| 17596 |
|
|
'X';
|
| 17597 |
|
|
|
| 17598 |
|
|
clk1_tmp <= c_clk(i_clk1_counter);
|
| 17599 |
|
|
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17600 |
|
|
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17601 |
|
|
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
|
| 17602 |
|
|
|
| 17603 |
|
|
clk2_tmp <= c_clk(i_clk2_counter);
|
| 17604 |
|
|
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17605 |
|
|
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17606 |
|
|
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
|
| 17607 |
|
|
|
| 17608 |
|
|
clk3_tmp <= c_clk(i_clk3_counter);
|
| 17609 |
|
|
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17610 |
|
|
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17611 |
|
|
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
|
| 17612 |
|
|
|
| 17613 |
|
|
clk4_tmp <= c_clk(i_clk4_counter);
|
| 17614 |
|
|
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17615 |
|
|
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17616 |
|
|
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
|
| 17617 |
|
|
|
| 17618 |
|
|
clk5_tmp <= c_clk(i_clk5_counter);
|
| 17619 |
|
|
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17620 |
|
|
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17621 |
|
|
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
|
| 17622 |
|
|
|
| 17623 |
|
|
|
| 17624 |
|
|
clk6_tmp <= c_clk(i_clk6_counter);
|
| 17625 |
|
|
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17626 |
|
|
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17627 |
|
|
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
|
| 17628 |
|
|
|
| 17629 |
|
|
|
| 17630 |
|
|
clk7_tmp <= c_clk(i_clk7_counter);
|
| 17631 |
|
|
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17632 |
|
|
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17633 |
|
|
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
|
| 17634 |
|
|
|
| 17635 |
|
|
|
| 17636 |
|
|
clk8_tmp <= c_clk(i_clk8_counter);
|
| 17637 |
|
|
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17638 |
|
|
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17639 |
|
|
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
|
| 17640 |
|
|
|
| 17641 |
|
|
|
| 17642 |
|
|
clk9_tmp <= c_clk(i_clk9_counter);
|
| 17643 |
|
|
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
|
| 17644 |
|
|
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
|
| 17645 |
|
|
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
|
| 17646 |
|
|
|
| 17647 |
|
|
|
| 17648 |
|
|
|
| 17649 |
|
|
scandataout <= scandata_out;
|
| 17650 |
|
|
scandone <= NOT scandone_tmp;
|
| 17651 |
|
|
phasedone <= NOT update_phase;
|
| 17652 |
|
|
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
|
| 17653 |
|
|
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
|
| 17654 |
|
|
|
| 17655 |
|
|
end vital_pll;
|
| 17656 |
|
|
-- END ARCHITECTURE VITAL_PLL
|
| 17657 |
|
|
-------------------------------------------------------------------
|
| 17658 |
|
|
--
|
| 17659 |
|
|
-- Entity Name : stratixiii_asmiblock
|
| 17660 |
|
|
--
|
| 17661 |
|
|
-- Description : Stratix III ASMIBLOCK VHDL Simulation model
|
| 17662 |
|
|
--
|
| 17663 |
|
|
-------------------------------------------------------------------
|
| 17664 |
|
|
LIBRARY IEEE;
|
| 17665 |
|
|
use IEEE.std_logic_1164.all;
|
| 17666 |
|
|
use work.stratixiii_atom_pack.all;
|
| 17667 |
|
|
|
| 17668 |
|
|
entity stratixiii_asmiblock is
|
| 17669 |
|
|
generic (
|
| 17670 |
|
|
lpm_type : string := "stratixiii_asmiblock"
|
| 17671 |
|
|
);
|
| 17672 |
|
|
port (
|
| 17673 |
|
|
dclkin : in std_logic := '0';
|
| 17674 |
|
|
scein : in std_logic := '0';
|
| 17675 |
|
|
sdoin : in std_logic := '0';
|
| 17676 |
|
|
data0in : in std_logic := '0';
|
| 17677 |
|
|
oe : in std_logic := '0';
|
| 17678 |
|
|
dclkout : out std_logic;
|
| 17679 |
|
|
sceout : out std_logic;
|
| 17680 |
|
|
sdoout : out std_logic;
|
| 17681 |
|
|
data0out: out std_logic
|
| 17682 |
|
|
);
|
| 17683 |
|
|
end stratixiii_asmiblock;
|
| 17684 |
|
|
|
| 17685 |
|
|
architecture architecture_asmiblock of stratixiii_asmiblock is
|
| 17686 |
|
|
begin
|
| 17687 |
|
|
|
| 17688 |
|
|
end architecture_asmiblock; -- end of stratixiii_asmiblock
|
| 17689 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 17690 |
|
|
--
|
| 17691 |
|
|
-- Module Name : stratixiii_lvds_reg
|
| 17692 |
|
|
--
|
| 17693 |
|
|
-- Description : Simulation model for a simple DFF.
|
| 17694 |
|
|
-- This is used for registering the enable inputs.
|
| 17695 |
|
|
-- No timing, powers upto 0.
|
| 17696 |
|
|
--
|
| 17697 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 17698 |
|
|
|
| 17699 |
|
|
LIBRARY IEEE, std;
|
| 17700 |
|
|
USE ieee.std_logic_1164.all;
|
| 17701 |
|
|
--USE ieee.std_logic_unsigned.all;
|
| 17702 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 17703 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 17704 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 17705 |
|
|
|
| 17706 |
|
|
ENTITY stratixiii_lvds_reg is
|
| 17707 |
|
|
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
|
| 17708 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 17709 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 17710 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 17711 |
|
|
TimingChecksOn : Boolean := True;
|
| 17712 |
|
|
InstancePath : String := "*";
|
| 17713 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 17714 |
|
|
tipd_ena : VitalDelayType01 := DefpropDelay01;
|
| 17715 |
|
|
tipd_d : VitalDelayType01 := DefpropDelay01;
|
| 17716 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
| 17717 |
|
|
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
| 17718 |
|
|
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
|
| 17719 |
|
|
);
|
| 17720 |
|
|
|
| 17721 |
|
|
PORT ( q : OUT std_logic;
|
| 17722 |
|
|
clk : IN std_logic;
|
| 17723 |
|
|
ena : IN std_logic := '1';
|
| 17724 |
|
|
d : IN std_logic;
|
| 17725 |
|
|
clrn : IN std_logic := '1';
|
| 17726 |
|
|
prn : IN std_logic := '1'
|
| 17727 |
|
|
);
|
| 17728 |
|
|
END stratixiii_lvds_reg;
|
| 17729 |
|
|
|
| 17730 |
|
|
ARCHITECTURE vital_stratixiii_lvds_reg of stratixiii_lvds_reg is
|
| 17731 |
|
|
|
| 17732 |
|
|
|
| 17733 |
|
|
-- INTERNAL SIGNALS
|
| 17734 |
|
|
signal clk_ipd : std_logic;
|
| 17735 |
|
|
signal d_ipd : std_logic;
|
| 17736 |
|
|
signal ena_ipd : std_logic;
|
| 17737 |
|
|
|
| 17738 |
|
|
begin
|
| 17739 |
|
|
|
| 17740 |
|
|
----------------------
|
| 17741 |
|
|
-- INPUT PATH DELAYs
|
| 17742 |
|
|
----------------------
|
| 17743 |
|
|
WireDelay : block
|
| 17744 |
|
|
begin
|
| 17745 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 17746 |
|
|
VitalWireDelay (ena_ipd, ena, tipd_ena);
|
| 17747 |
|
|
VitalWireDelay (d_ipd, d, tipd_d);
|
| 17748 |
|
|
end block;
|
| 17749 |
|
|
|
| 17750 |
|
|
process (clk_ipd, d_ipd, clrn, prn)
|
| 17751 |
|
|
variable q_tmp : std_logic := '0';
|
| 17752 |
|
|
variable q_VitalGlitchData : VitalGlitchDataType;
|
| 17753 |
|
|
variable Tviol_d_clk : std_ulogic := '0';
|
| 17754 |
|
|
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
|
| 17755 |
|
|
begin
|
| 17756 |
|
|
|
| 17757 |
|
|
------------------------
|
| 17758 |
|
|
-- Timing Check Section
|
| 17759 |
|
|
------------------------
|
| 17760 |
|
|
|
| 17761 |
|
|
if (prn = '0') then
|
| 17762 |
|
|
q_tmp := '1';
|
| 17763 |
|
|
elsif (clrn = '0') then
|
| 17764 |
|
|
q_tmp := '0';
|
| 17765 |
|
|
elsif (clk_ipd'event and clk_ipd = '1') then
|
| 17766 |
|
|
if (ena_ipd = '1') then
|
| 17767 |
|
|
q_tmp := d_ipd;
|
| 17768 |
|
|
end if;
|
| 17769 |
|
|
end if;
|
| 17770 |
|
|
|
| 17771 |
|
|
----------------------
|
| 17772 |
|
|
-- Path Delay Section
|
| 17773 |
|
|
----------------------
|
| 17774 |
|
|
VitalPathDelay01 (
|
| 17775 |
|
|
OutSignal => q,
|
| 17776 |
|
|
OutSignalName => "Q",
|
| 17777 |
|
|
OutTemp => q_tmp,
|
| 17778 |
|
|
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
|
| 17779 |
|
|
GlitchData => q_VitalGlitchData,
|
| 17780 |
|
|
Mode => DefGlitchMode,
|
| 17781 |
|
|
XOn => XOn,
|
| 17782 |
|
|
MsgOn => MsgOn );
|
| 17783 |
|
|
|
| 17784 |
|
|
end process;
|
| 17785 |
|
|
|
| 17786 |
|
|
end vital_stratixiii_lvds_reg;
|
| 17787 |
|
|
|
| 17788 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 17789 |
|
|
--
|
| 17790 |
|
|
-- Module Name : stratixiii_lvds_rx_fifo_sync_ram
|
| 17791 |
|
|
--
|
| 17792 |
|
|
-- Description :
|
| 17793 |
|
|
--
|
| 17794 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 17795 |
|
|
|
| 17796 |
|
|
LIBRARY IEEE, std;
|
| 17797 |
|
|
USE ieee.std_logic_1164.all;
|
| 17798 |
|
|
--USE ieee.std_logic_unsigned.all;
|
| 17799 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 17800 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 17801 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 17802 |
|
|
|
| 17803 |
|
|
ENTITY stratixiii_lvds_rx_fifo_sync_ram is
|
| 17804 |
|
|
PORT ( clk : IN std_logic;
|
| 17805 |
|
|
datain : IN std_logic := '0';
|
| 17806 |
|
|
writereset : IN std_logic := '0';
|
| 17807 |
|
|
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
|
| 17808 |
|
|
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
|
| 17809 |
|
|
we : IN std_logic := '0';
|
| 17810 |
|
|
dataout : OUT std_logic
|
| 17811 |
|
|
);
|
| 17812 |
|
|
|
| 17813 |
|
|
END stratixiii_lvds_rx_fifo_sync_ram;
|
| 17814 |
|
|
|
| 17815 |
|
|
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF stratixiii_lvds_rx_fifo_sync_ram IS
|
| 17816 |
|
|
|
| 17817 |
|
|
-- INTERNAL SIGNALS
|
| 17818 |
|
|
signal dataout_tmp : std_logic;
|
| 17819 |
|
|
signal ram_d : std_logic_vector(0 TO 5);
|
| 17820 |
|
|
signal ram_q : std_logic_vector(0 TO 5);
|
| 17821 |
|
|
signal data_reg : std_logic_vector(0 TO 5);
|
| 17822 |
|
|
|
| 17823 |
|
|
begin
|
| 17824 |
|
|
dataout <= dataout_tmp;
|
| 17825 |
|
|
|
| 17826 |
|
|
process (clk, writereset)
|
| 17827 |
|
|
variable initial : boolean := true;
|
| 17828 |
|
|
begin
|
| 17829 |
|
|
if (initial) then
|
| 17830 |
|
|
for i in 0 to 5 loop
|
| 17831 |
|
|
ram_q(i) <= '0';
|
| 17832 |
|
|
end loop;
|
| 17833 |
|
|
initial := false;
|
| 17834 |
|
|
end if;
|
| 17835 |
|
|
if (writereset = '1') then
|
| 17836 |
|
|
for i in 0 to 5 loop
|
| 17837 |
|
|
ram_q(i) <= '0';
|
| 17838 |
|
|
end loop;
|
| 17839 |
|
|
elsif (clk'event and clk = '1') then
|
| 17840 |
|
|
for i in 0 to 5 loop
|
| 17841 |
|
|
ram_q(i) <= ram_d(i);
|
| 17842 |
|
|
end loop;
|
| 17843 |
|
|
end if;
|
| 17844 |
|
|
end process;
|
| 17845 |
|
|
|
| 17846 |
|
|
process (we, data_reg, ram_q)
|
| 17847 |
|
|
begin
|
| 17848 |
|
|
if (we = '1') then
|
| 17849 |
|
|
ram_d <= data_reg;
|
| 17850 |
|
|
else
|
| 17851 |
|
|
ram_d <= ram_q;
|
| 17852 |
|
|
end if;
|
| 17853 |
|
|
end process;
|
| 17854 |
|
|
|
| 17855 |
|
|
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
|
| 17856 |
|
|
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
|
| 17857 |
|
|
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
|
| 17858 |
|
|
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
|
| 17859 |
|
|
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
|
| 17860 |
|
|
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
|
| 17861 |
|
|
|
| 17862 |
|
|
process (ram_q, we, waddr, raddr)
|
| 17863 |
|
|
variable initial : boolean := true;
|
| 17864 |
|
|
begin
|
| 17865 |
|
|
if (initial) then
|
| 17866 |
|
|
dataout_tmp <= '0';
|
| 17867 |
|
|
initial := false;
|
| 17868 |
|
|
end if;
|
| 17869 |
|
|
case raddr is
|
| 17870 |
|
|
when "000" =>
|
| 17871 |
|
|
dataout_tmp <= ram_q(0);
|
| 17872 |
|
|
when "001" =>
|
| 17873 |
|
|
dataout_tmp <= ram_q(1);
|
| 17874 |
|
|
when "010" =>
|
| 17875 |
|
|
dataout_tmp <= ram_q(2);
|
| 17876 |
|
|
when "011" =>
|
| 17877 |
|
|
dataout_tmp <= ram_q(3);
|
| 17878 |
|
|
when "100" =>
|
| 17879 |
|
|
dataout_tmp <= ram_q(4);
|
| 17880 |
|
|
when "101" =>
|
| 17881 |
|
|
dataout_tmp <= ram_q(5);
|
| 17882 |
|
|
when others =>
|
| 17883 |
|
|
dataout_tmp <= '0';
|
| 17884 |
|
|
end case;
|
| 17885 |
|
|
end process;
|
| 17886 |
|
|
|
| 17887 |
|
|
END vital_arm_lvds_rx_fifo_sync_ram;
|
| 17888 |
|
|
|
| 17889 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 17890 |
|
|
--
|
| 17891 |
|
|
-- Module Name : stratixiii_lvds_rx_fifo
|
| 17892 |
|
|
--
|
| 17893 |
|
|
-- Description :
|
| 17894 |
|
|
--
|
| 17895 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 17896 |
|
|
LIBRARY IEEE, std;
|
| 17897 |
|
|
USE ieee.std_logic_1164.all;
|
| 17898 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 17899 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 17900 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 17901 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 17902 |
|
|
USE work.stratixiii_lvds_rx_fifo_sync_ram;
|
| 17903 |
|
|
|
| 17904 |
|
|
ENTITY stratixiii_lvds_rx_fifo is
|
| 17905 |
|
|
GENERIC ( channel_width : integer := 10;
|
| 17906 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 17907 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 17908 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 17909 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 17910 |
|
|
InstancePath : String := "*";
|
| 17911 |
|
|
tipd_wclk : VitalDelayType01 := DefpropDelay01;
|
| 17912 |
|
|
tipd_rclk : VitalDelayType01 := DefpropDelay01;
|
| 17913 |
|
|
tipd_dparst : VitalDelayType01 := DefpropDelay01;
|
| 17914 |
|
|
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
|
| 17915 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01;
|
| 17916 |
|
|
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
|
| 17917 |
|
|
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
|
| 17918 |
|
|
);
|
| 17919 |
|
|
|
| 17920 |
|
|
PORT ( wclk : IN std_logic:= '0';
|
| 17921 |
|
|
rclk : IN std_logic:= '0';
|
| 17922 |
|
|
dparst : IN std_logic := '0';
|
| 17923 |
|
|
fiforst : IN std_logic := '0';
|
| 17924 |
|
|
datain : IN std_logic := '0';
|
| 17925 |
|
|
dataout : OUT std_logic
|
| 17926 |
|
|
);
|
| 17927 |
|
|
|
| 17928 |
|
|
END stratixiii_lvds_rx_fifo;
|
| 17929 |
|
|
|
| 17930 |
|
|
ARCHITECTURE vital_arm_lvds_rx_fifo of stratixiii_lvds_rx_fifo is
|
| 17931 |
|
|
-- INTERNAL SIGNALS
|
| 17932 |
|
|
signal datain_in : std_logic;
|
| 17933 |
|
|
signal rclk_in : std_logic;
|
| 17934 |
|
|
signal dparst_in : std_logic;
|
| 17935 |
|
|
signal fiforst_in : std_logic;
|
| 17936 |
|
|
signal wclk_in : std_logic;
|
| 17937 |
|
|
|
| 17938 |
|
|
signal ram_datain : std_logic;
|
| 17939 |
|
|
signal ram_dataout : std_logic;
|
| 17940 |
|
|
signal wrPtr : std_logic_vector(2 DOWNTO 0);
|
| 17941 |
|
|
signal rdPtr : std_logic_vector(2 DOWNTO 0);
|
| 17942 |
|
|
signal rdAddr : std_logic_vector(2 DOWNTO 0);
|
| 17943 |
|
|
signal ram_we : std_logic;
|
| 17944 |
|
|
signal write_side_sync_reset : std_logic;
|
| 17945 |
|
|
signal read_side_sync_reset : std_logic;
|
| 17946 |
|
|
|
| 17947 |
|
|
COMPONENT stratixiii_lvds_rx_fifo_sync_ram
|
| 17948 |
|
|
PORT ( clk : IN std_logic;
|
| 17949 |
|
|
datain : IN std_logic := '0';
|
| 17950 |
|
|
writereset : IN std_logic := '0';
|
| 17951 |
|
|
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
|
| 17952 |
|
|
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
|
| 17953 |
|
|
we : IN std_logic := '0';
|
| 17954 |
|
|
dataout : OUT std_logic
|
| 17955 |
|
|
);
|
| 17956 |
|
|
END COMPONENT;
|
| 17957 |
|
|
|
| 17958 |
|
|
begin
|
| 17959 |
|
|
|
| 17960 |
|
|
----------------------
|
| 17961 |
|
|
-- INPUT PATH DELAYs
|
| 17962 |
|
|
----------------------
|
| 17963 |
|
|
WireDelay : block
|
| 17964 |
|
|
begin
|
| 17965 |
|
|
VitalWireDelay (wclk_in, wclk, tipd_wclk);
|
| 17966 |
|
|
VitalWireDelay (rclk_in, rclk, tipd_rclk);
|
| 17967 |
|
|
VitalWireDelay (dparst_in, dparst, tipd_dparst);
|
| 17968 |
|
|
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
|
| 17969 |
|
|
VitalWireDelay (datain_in, datain, tipd_datain);
|
| 17970 |
|
|
end block;
|
| 17971 |
|
|
|
| 17972 |
|
|
rdAddr <= rdPtr ;
|
| 17973 |
|
|
s_fifo_ram : stratixiii_lvds_rx_fifo_sync_ram
|
| 17974 |
|
|
PORT MAP ( clk => wclk_in,
|
| 17975 |
|
|
datain => ram_datain,
|
| 17976 |
|
|
writereset => write_side_sync_reset,
|
| 17977 |
|
|
waddr => wrPtr,
|
| 17978 |
|
|
raddr => rdAddr,
|
| 17979 |
|
|
we => ram_we,
|
| 17980 |
|
|
dataout => ram_dataout
|
| 17981 |
|
|
);
|
| 17982 |
|
|
|
| 17983 |
|
|
|
| 17984 |
|
|
process (wclk_in, dparst_in)
|
| 17985 |
|
|
variable initial : boolean := true;
|
| 17986 |
|
|
begin
|
| 17987 |
|
|
if (initial) then
|
| 17988 |
|
|
wrPtr <= "000";
|
| 17989 |
|
|
write_side_sync_reset <= '0';
|
| 17990 |
|
|
ram_we <= '0';
|
| 17991 |
|
|
ram_datain <= '0';
|
| 17992 |
|
|
initial := false;
|
| 17993 |
|
|
end if;
|
| 17994 |
|
|
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
|
| 17995 |
|
|
write_side_sync_reset <= '1';
|
| 17996 |
|
|
ram_datain <= '0';
|
| 17997 |
|
|
wrPtr <= "000";
|
| 17998 |
|
|
ram_we <= '0';
|
| 17999 |
|
|
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
|
| 18000 |
|
|
write_side_sync_reset <= '0';
|
| 18001 |
|
|
end if;
|
| 18002 |
|
|
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
|
| 18003 |
|
|
ram_datain <= datain_in;
|
| 18004 |
|
|
ram_we <= '1';
|
| 18005 |
|
|
case wrPtr is
|
| 18006 |
|
|
when "000" => wrPtr <= "001";
|
| 18007 |
|
|
when "001" => wrPtr <= "010";
|
| 18008 |
|
|
when "010" => wrPtr <= "011";
|
| 18009 |
|
|
when "011" => wrPtr <= "100";
|
| 18010 |
|
|
when "100" => wrPtr <= "101";
|
| 18011 |
|
|
when "101" => wrPtr <= "000";
|
| 18012 |
|
|
when others => wrPtr <= "000";
|
| 18013 |
|
|
end case;
|
| 18014 |
|
|
end if;
|
| 18015 |
|
|
end process;
|
| 18016 |
|
|
|
| 18017 |
|
|
process (rclk_in, dparst_in)
|
| 18018 |
|
|
variable initial : boolean := true;
|
| 18019 |
|
|
variable dataout_tmp : std_logic := '0';
|
| 18020 |
|
|
variable dataout_VitalGlitchData : VitalGlitchDataType;
|
| 18021 |
|
|
begin
|
| 18022 |
|
|
if (initial) then
|
| 18023 |
|
|
rdPtr <= "011";
|
| 18024 |
|
|
read_side_sync_reset <= '0';
|
| 18025 |
|
|
dataout_tmp := '0';
|
| 18026 |
|
|
initial := false;
|
| 18027 |
|
|
end if;
|
| 18028 |
|
|
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
|
| 18029 |
|
|
read_side_sync_reset <= '1';
|
| 18030 |
|
|
rdPtr <= "011";
|
| 18031 |
|
|
dataout_tmp := '0';
|
| 18032 |
|
|
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
|
| 18033 |
|
|
read_side_sync_reset <= '0';
|
| 18034 |
|
|
end if;
|
| 18035 |
|
|
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
|
| 18036 |
|
|
case rdPtr is
|
| 18037 |
|
|
when "000" => rdPtr <= "001";
|
| 18038 |
|
|
when "001" => rdPtr <= "010";
|
| 18039 |
|
|
when "010" => rdPtr <= "011";
|
| 18040 |
|
|
when "011" => rdPtr <= "100";
|
| 18041 |
|
|
when "100" => rdPtr <= "101";
|
| 18042 |
|
|
when "101" => rdPtr <= "000";
|
| 18043 |
|
|
when others => rdPtr <= "000";
|
| 18044 |
|
|
end case;
|
| 18045 |
|
|
dataout_tmp := ram_dataout;
|
| 18046 |
|
|
end if;
|
| 18047 |
|
|
|
| 18048 |
|
|
----------------------
|
| 18049 |
|
|
-- Path Delay Section
|
| 18050 |
|
|
----------------------
|
| 18051 |
|
|
VitalPathDelay01 (
|
| 18052 |
|
|
Outsignal => dataout,
|
| 18053 |
|
|
OutsignalName => "DATAOUT",
|
| 18054 |
|
|
OutTemp => dataout_tmp,
|
| 18055 |
|
|
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
|
| 18056 |
|
|
GlitchData => dataout_VitalGlitchData,
|
| 18057 |
|
|
Mode => DefGlitchMode,
|
| 18058 |
|
|
XOn => XOn,
|
| 18059 |
|
|
MsgOn => MsgOn );
|
| 18060 |
|
|
|
| 18061 |
|
|
end process;
|
| 18062 |
|
|
|
| 18063 |
|
|
END vital_arm_lvds_rx_fifo;
|
| 18064 |
|
|
|
| 18065 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 18066 |
|
|
--
|
| 18067 |
|
|
-- Module Name : stratixiii_lvds_rx_bitslip
|
| 18068 |
|
|
--
|
| 18069 |
|
|
-- Description :
|
| 18070 |
|
|
--
|
| 18071 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 18072 |
|
|
LIBRARY IEEE, std;
|
| 18073 |
|
|
USE ieee.std_logic_1164.all;
|
| 18074 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 18075 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 18076 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 18077 |
|
|
USE work.stratixiii_lvds_reg;
|
| 18078 |
|
|
|
| 18079 |
|
|
ENTITY stratixiii_lvds_rx_bitslip is
|
| 18080 |
|
|
GENERIC ( channel_width : integer := 10;
|
| 18081 |
|
|
bitslip_rollover : integer := 12;
|
| 18082 |
|
|
x_on_bitslip : string := "on";
|
| 18083 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 18084 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 18085 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 18086 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 18087 |
|
|
InstancePath : String := "*";
|
| 18088 |
|
|
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
|
| 18089 |
|
|
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
|
| 18090 |
|
|
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
|
| 18091 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01;
|
| 18092 |
|
|
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
|
| 18093 |
|
|
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
|
| 18094 |
|
|
);
|
| 18095 |
|
|
|
| 18096 |
|
|
PORT ( clk0 : IN std_logic := '0';
|
| 18097 |
|
|
bslipcntl : IN std_logic := '0';
|
| 18098 |
|
|
bsliprst : IN std_logic := '0';
|
| 18099 |
|
|
datain : IN std_logic := '0';
|
| 18100 |
|
|
bslipmax : OUT std_logic;
|
| 18101 |
|
|
dataout : OUT std_logic
|
| 18102 |
|
|
);
|
| 18103 |
|
|
END stratixiii_lvds_rx_bitslip;
|
| 18104 |
|
|
|
| 18105 |
|
|
ARCHITECTURE vital_arm_lvds_rx_bitslip OF stratixiii_lvds_rx_bitslip IS
|
| 18106 |
|
|
-- INTERNAL SIGNALS
|
| 18107 |
|
|
signal clk0_in : std_logic;
|
| 18108 |
|
|
signal bslipcntl_in : std_logic;
|
| 18109 |
|
|
signal bsliprst_in : std_logic;
|
| 18110 |
|
|
signal datain_in : std_logic;
|
| 18111 |
|
|
|
| 18112 |
|
|
signal slip_count : integer := 0;
|
| 18113 |
|
|
signal dataout_tmp : std_logic;
|
| 18114 |
|
|
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
|
| 18115 |
|
|
signal bslipcntl_reg : std_logic;
|
| 18116 |
|
|
signal vcc : std_logic := '1';
|
| 18117 |
|
|
signal slip_data : std_logic := '0';
|
| 18118 |
|
|
signal start_corrupt_bits : std_logic := '0';
|
| 18119 |
|
|
signal num_corrupt_bits : integer := 0;
|
| 18120 |
|
|
|
| 18121 |
|
|
COMPONENT stratixiii_lvds_reg
|
| 18122 |
|
|
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
|
| 18123 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 18124 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 18125 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 18126 |
|
|
InstancePath : String := "*";
|
| 18127 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 18128 |
|
|
tipd_ena : VitalDelayType01 := DefpropDelay01;
|
| 18129 |
|
|
tipd_d : VitalDelayType01 := DefpropDelay01;
|
| 18130 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
|
| 18131 |
|
|
);
|
| 18132 |
|
|
|
| 18133 |
|
|
PORT ( q : OUT std_logic;
|
| 18134 |
|
|
clk : IN std_logic;
|
| 18135 |
|
|
ena : IN std_logic := '1';
|
| 18136 |
|
|
d : IN std_logic;
|
| 18137 |
|
|
clrn : IN std_logic := '1';
|
| 18138 |
|
|
prn : IN std_logic := '1'
|
| 18139 |
|
|
);
|
| 18140 |
|
|
END COMPONENT;
|
| 18141 |
|
|
|
| 18142 |
|
|
begin
|
| 18143 |
|
|
|
| 18144 |
|
|
----------------------
|
| 18145 |
|
|
-- INPUT PATH DELAYs
|
| 18146 |
|
|
----------------------
|
| 18147 |
|
|
WireDelay : block
|
| 18148 |
|
|
begin
|
| 18149 |
|
|
VitalWireDelay (clk0_in, clk0, tipd_clk0);
|
| 18150 |
|
|
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
|
| 18151 |
|
|
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
|
| 18152 |
|
|
VitalWireDelay (datain_in, datain, tipd_datain);
|
| 18153 |
|
|
end block;
|
| 18154 |
|
|
|
| 18155 |
|
|
bslipcntlreg : stratixiii_lvds_reg
|
| 18156 |
|
|
PORT MAP ( d => bslipcntl_in,
|
| 18157 |
|
|
clk => clk0_in,
|
| 18158 |
|
|
ena => vcc,
|
| 18159 |
|
|
clrn => vcc,
|
| 18160 |
|
|
prn => vcc,
|
| 18161 |
|
|
q => bslipcntl_reg
|
| 18162 |
|
|
);
|
| 18163 |
|
|
|
| 18164 |
|
|
-- 4-bit slip counter and 12-bit shift register
|
| 18165 |
|
|
process (bslipcntl_reg, bsliprst_in, clk0_in)
|
| 18166 |
|
|
variable initial : boolean := true;
|
| 18167 |
|
|
variable bslipmax_tmp : std_logic := '0';
|
| 18168 |
|
|
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
|
| 18169 |
|
|
begin
|
| 18170 |
|
|
if (bsliprst_in = '1') then
|
| 18171 |
|
|
slip_count <= 0;
|
| 18172 |
|
|
bslipmax_tmp := '0';
|
| 18173 |
|
|
-- bitslip_arr <= (OTHERS => '0');
|
| 18174 |
|
|
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
|
| 18175 |
|
|
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
|
| 18176 |
|
|
end if;
|
| 18177 |
|
|
else
|
| 18178 |
|
|
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
|
| 18179 |
|
|
if (x_on_bitslip = "on") then
|
| 18180 |
|
|
start_corrupt_bits <= '1';
|
| 18181 |
|
|
end if;
|
| 18182 |
|
|
num_corrupt_bits <= 0;
|
| 18183 |
|
|
if (slip_count = bitslip_rollover) then
|
| 18184 |
|
|
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
|
| 18185 |
|
|
slip_count <= 0;
|
| 18186 |
|
|
bslipmax_tmp := '0';
|
| 18187 |
|
|
else
|
| 18188 |
|
|
slip_count <= slip_count + 1;
|
| 18189 |
|
|
if ((slip_count + 1) = bitslip_rollover) then
|
| 18190 |
|
|
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
|
| 18191 |
|
|
bslipmax_tmp := '1';
|
| 18192 |
|
|
end if;
|
| 18193 |
|
|
end if;
|
| 18194 |
|
|
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
|
| 18195 |
|
|
start_corrupt_bits <= '0';
|
| 18196 |
|
|
num_corrupt_bits <= 0;
|
| 18197 |
|
|
end if;
|
| 18198 |
|
|
end if;
|
| 18199 |
|
|
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
|
| 18200 |
|
|
bitslip_arr(0) <= datain_in;
|
| 18201 |
|
|
for i in 0 to (bitslip_rollover - 1) loop
|
| 18202 |
|
|
bitslip_arr(i + 1) <= bitslip_arr(i);
|
| 18203 |
|
|
end loop;
|
| 18204 |
|
|
|
| 18205 |
|
|
if (start_corrupt_bits = '1') then
|
| 18206 |
|
|
num_corrupt_bits <= num_corrupt_bits + 1;
|
| 18207 |
|
|
end if;
|
| 18208 |
|
|
if (num_corrupt_bits+1 = 3) then
|
| 18209 |
|
|
start_corrupt_bits <= '0';
|
| 18210 |
|
|
end if;
|
| 18211 |
|
|
end if;
|
| 18212 |
|
|
-- end if;
|
| 18213 |
|
|
|
| 18214 |
|
|
----------------------
|
| 18215 |
|
|
-- Path Delay Section
|
| 18216 |
|
|
----------------------
|
| 18217 |
|
|
VitalPathDelay01 (
|
| 18218 |
|
|
Outsignal => bslipmax,
|
| 18219 |
|
|
OutsignalName => "BSLIPMAX",
|
| 18220 |
|
|
OutTemp => bslipmax_tmp,
|
| 18221 |
|
|
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
|
| 18222 |
|
|
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
|
| 18223 |
|
|
GlitchData => bslipmax_VitalGlitchData,
|
| 18224 |
|
|
Mode => DefGlitchMode,
|
| 18225 |
|
|
XOn => XOn,
|
| 18226 |
|
|
MsgOn => MsgOn );
|
| 18227 |
|
|
end process;
|
| 18228 |
|
|
|
| 18229 |
|
|
slip_data <= bitslip_arr(slip_count);
|
| 18230 |
|
|
|
| 18231 |
|
|
dataoutreg : stratixiii_lvds_reg
|
| 18232 |
|
|
PORT MAP ( d => slip_data,
|
| 18233 |
|
|
clk => clk0_in,
|
| 18234 |
|
|
ena => vcc,
|
| 18235 |
|
|
clrn => vcc,
|
| 18236 |
|
|
prn => vcc,
|
| 18237 |
|
|
q => dataout_tmp
|
| 18238 |
|
|
);
|
| 18239 |
|
|
|
| 18240 |
|
|
dataout <= dataout_tmp when start_corrupt_bits = '0' else
|
| 18241 |
|
|
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
|
| 18242 |
|
|
dataout_tmp;
|
| 18243 |
|
|
|
| 18244 |
|
|
END vital_arm_lvds_rx_bitslip;
|
| 18245 |
|
|
|
| 18246 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 18247 |
|
|
--
|
| 18248 |
|
|
-- Module Name : stratixiii_lvds_rx_deser
|
| 18249 |
|
|
--
|
| 18250 |
|
|
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
|
| 18251 |
|
|
-- DESERIALIZER. This module receives serial data and outputs
|
| 18252 |
|
|
-- parallel data word of width = channel width
|
| 18253 |
|
|
--
|
| 18254 |
|
|
--////////////////////////////////////////////////////////////////////////////
|
| 18255 |
|
|
|
| 18256 |
|
|
LIBRARY IEEE;
|
| 18257 |
|
|
USE ieee.std_logic_1164.all;
|
| 18258 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 18259 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 18260 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 18261 |
|
|
|
| 18262 |
|
|
ENTITY stratixiii_lvds_rx_deser IS
|
| 18263 |
|
|
GENERIC ( channel_width : integer := 4;
|
| 18264 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 18265 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 18266 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 18267 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 18268 |
|
|
InstancePath : String := "*";
|
| 18269 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 18270 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01;
|
| 18271 |
|
|
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
|
| 18272 |
|
|
);
|
| 18273 |
|
|
|
| 18274 |
|
|
PORT ( clk : IN std_logic := '0';
|
| 18275 |
|
|
datain : IN std_logic := '0';
|
| 18276 |
|
|
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
|
| 18277 |
|
|
devclrn : IN std_logic := '1';
|
| 18278 |
|
|
devpor : IN std_logic := '1'
|
| 18279 |
|
|
);
|
| 18280 |
|
|
|
| 18281 |
|
|
END stratixiii_lvds_rx_deser;
|
| 18282 |
|
|
|
| 18283 |
|
|
ARCHITECTURE vital_arm_lvds_rx_deser OF stratixiii_lvds_rx_deser IS
|
| 18284 |
|
|
|
| 18285 |
|
|
-- INTERNAL SIGNALS
|
| 18286 |
|
|
signal clk_ipd : std_logic;
|
| 18287 |
|
|
signal datain_ipd : std_logic;
|
| 18288 |
|
|
|
| 18289 |
|
|
begin
|
| 18290 |
|
|
|
| 18291 |
|
|
----------------------
|
| 18292 |
|
|
-- INPUT PATH DELAYs
|
| 18293 |
|
|
----------------------
|
| 18294 |
|
|
WireDelay : block
|
| 18295 |
|
|
begin
|
| 18296 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 18297 |
|
|
VitalWireDelay (datain_ipd, datain, tipd_datain);
|
| 18298 |
|
|
end block;
|
| 18299 |
|
|
|
| 18300 |
|
|
VITAL: process (clk_ipd, devpor, devclrn)
|
| 18301 |
|
|
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
|
| 18302 |
|
|
variable i : integer := 0;
|
| 18303 |
|
|
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
|
| 18304 |
|
|
variable CQDelay : TIME := 0 ns;
|
| 18305 |
|
|
begin
|
| 18306 |
|
|
if (devclrn = '0' or devpor = '0') then
|
| 18307 |
|
|
dataout_tmp := (OTHERS => '0');
|
| 18308 |
|
|
else
|
| 18309 |
|
|
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
|
| 18310 |
|
|
for i in channel_width - 1 DOWNTO 1 loop
|
| 18311 |
|
|
dataout_tmp(i) := dataout_tmp(i - 1);
|
| 18312 |
|
|
end loop;
|
| 18313 |
|
|
dataout_tmp(0) := datain_ipd;
|
| 18314 |
|
|
end if;
|
| 18315 |
|
|
end if;
|
| 18316 |
|
|
|
| 18317 |
|
|
----------------------
|
| 18318 |
|
|
-- Path Delay Section
|
| 18319 |
|
|
----------------------
|
| 18320 |
|
|
|
| 18321 |
|
|
CQDelay := SelectDelay (
|
| 18322 |
|
|
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
|
| 18323 |
|
|
);
|
| 18324 |
|
|
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
|
| 18325 |
|
|
end process;
|
| 18326 |
|
|
|
| 18327 |
|
|
END vital_arm_lvds_rx_deser;
|
| 18328 |
|
|
|
| 18329 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 18330 |
|
|
--
|
| 18331 |
|
|
-- Module Name : stratixiii_lvds_rx_parallel_reg
|
| 18332 |
|
|
--
|
| 18333 |
|
|
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
|
| 18334 |
|
|
-- PARALLEL REGISTER. The data width equals max. channel width,
|
| 18335 |
|
|
-- which is 10.
|
| 18336 |
|
|
--
|
| 18337 |
|
|
--////////////////////////////////////////////////////////////////////////////
|
| 18338 |
|
|
|
| 18339 |
|
|
LIBRARY IEEE;
|
| 18340 |
|
|
USE ieee.std_logic_1164.all;
|
| 18341 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 18342 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 18343 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 18344 |
|
|
|
| 18345 |
|
|
ENTITY stratixiii_lvds_rx_parallel_reg IS
|
| 18346 |
|
|
GENERIC ( channel_width : integer := 4;
|
| 18347 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 18348 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 18349 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 18350 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 18351 |
|
|
InstancePath : String := "*";
|
| 18352 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 18353 |
|
|
tipd_enable : VitalDelayType01 := DefpropDelay01;
|
| 18354 |
|
|
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
|
| 18355 |
|
|
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
|
| 18356 |
|
|
);
|
| 18357 |
|
|
PORT ( clk : IN std_logic;
|
| 18358 |
|
|
enable : IN std_logic := '1';
|
| 18359 |
|
|
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
|
| 18360 |
|
|
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
|
| 18361 |
|
|
devclrn : IN std_logic := '1';
|
| 18362 |
|
|
devpor : IN std_logic := '1'
|
| 18363 |
|
|
);
|
| 18364 |
|
|
|
| 18365 |
|
|
END stratixiii_lvds_rx_parallel_reg;
|
| 18366 |
|
|
|
| 18367 |
|
|
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF stratixiii_lvds_rx_parallel_reg IS
|
| 18368 |
|
|
-- INTERNAL SIGNALS
|
| 18369 |
|
|
signal clk_ipd : std_logic;
|
| 18370 |
|
|
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
|
| 18371 |
|
|
signal enable_ipd : std_logic;
|
| 18372 |
|
|
|
| 18373 |
|
|
begin
|
| 18374 |
|
|
|
| 18375 |
|
|
----------------------
|
| 18376 |
|
|
-- INPUT PATH DELAYs
|
| 18377 |
|
|
----------------------
|
| 18378 |
|
|
WireDelay : block
|
| 18379 |
|
|
begin
|
| 18380 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 18381 |
|
|
VitalWireDelay (enable_ipd, enable, tipd_enable);
|
| 18382 |
|
|
loopbits : FOR i in datain'RANGE GENERATE
|
| 18383 |
|
|
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
|
| 18384 |
|
|
END GENERATE;
|
| 18385 |
|
|
end block;
|
| 18386 |
|
|
|
| 18387 |
|
|
VITAL: process (clk_ipd, devpor, devclrn)
|
| 18388 |
|
|
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
|
| 18389 |
|
|
variable i : integer := 0;
|
| 18390 |
|
|
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
|
| 18391 |
|
|
variable CQDelay : TIME := 0 ns;
|
| 18392 |
|
|
begin
|
| 18393 |
|
|
if ((devpor = '0') or (devclrn = '0')) then
|
| 18394 |
|
|
dataout_tmp := (OTHERS => '0');
|
| 18395 |
|
|
else
|
| 18396 |
|
|
if (clk_ipd'event and clk_ipd = '1') then
|
| 18397 |
|
|
if (enable_ipd = '1') then
|
| 18398 |
|
|
dataout_tmp := datain_ipd;
|
| 18399 |
|
|
end if;
|
| 18400 |
|
|
end if;
|
| 18401 |
|
|
end if;
|
| 18402 |
|
|
|
| 18403 |
|
|
----------------------
|
| 18404 |
|
|
-- Path Delay Section
|
| 18405 |
|
|
----------------------
|
| 18406 |
|
|
|
| 18407 |
|
|
CQDelay := SelectDelay (
|
| 18408 |
|
|
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
|
| 18409 |
|
|
);
|
| 18410 |
|
|
dataout <= dataout_tmp AFTER CQDelay;
|
| 18411 |
|
|
end process;
|
| 18412 |
|
|
END vital_arm_lvds_rx_parallel_reg;
|
| 18413 |
|
|
|
| 18414 |
|
|
-------------------------------------------------------------------------------
|
| 18415 |
|
|
--
|
| 18416 |
|
|
-- Module Name : stratixiii_pclk_divider
|
| 18417 |
|
|
--
|
| 18418 |
|
|
-- Description : Simulation model for a clock divider
|
| 18419 |
|
|
-- output clock is divided by value specified
|
| 18420 |
|
|
-- in the parameter clk_divide_by
|
| 18421 |
|
|
--
|
| 18422 |
|
|
-------------------------------------------------------------------------------
|
| 18423 |
|
|
|
| 18424 |
|
|
LIBRARY IEEE;
|
| 18425 |
|
|
USE ieee.std_logic_1164.all;
|
| 18426 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 18427 |
|
|
|
| 18428 |
|
|
ENTITY stratixiii_pclk_divider IS
|
| 18429 |
|
|
GENERIC (
|
| 18430 |
|
|
clk_divide_by : integer := 1);
|
| 18431 |
|
|
PORT (
|
| 18432 |
|
|
clkin : IN std_logic;
|
| 18433 |
|
|
lloaden : OUT std_logic;
|
| 18434 |
|
|
clkout : OUT std_logic);
|
| 18435 |
|
|
END stratixiii_pclk_divider;
|
| 18436 |
|
|
|
| 18437 |
|
|
ARCHITECTURE arch OF stratixiii_pclk_divider IS
|
| 18438 |
|
|
|
| 18439 |
|
|
SIGNAL lloaden_tmp : std_logic := '0';
|
| 18440 |
|
|
SIGNAL clkout_tmp : std_logic := '0';
|
| 18441 |
|
|
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
|
| 18442 |
|
|
|
| 18443 |
|
|
BEGIN
|
| 18444 |
|
|
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
|
| 18445 |
|
|
lloaden <= lloaden_tmp;
|
| 18446 |
|
|
PROCESS(clkin)
|
| 18447 |
|
|
variable count : std_logic := '0';
|
| 18448 |
|
|
variable start : std_logic := '0';
|
| 18449 |
|
|
variable prev_load : std_logic := '0';
|
| 18450 |
|
|
BEGIN
|
| 18451 |
|
|
|
| 18452 |
|
|
IF(clkin = '1') THEN
|
| 18453 |
|
|
count := '1';
|
| 18454 |
|
|
END IF;
|
| 18455 |
|
|
if( count = '1') then
|
| 18456 |
|
|
IF (cnt < clk_divide_by) THEN
|
| 18457 |
|
|
clkout_tmp <= '0';
|
| 18458 |
|
|
cnt <= cnt + "00001";
|
| 18459 |
|
|
ELSE
|
| 18460 |
|
|
IF (cnt = (2 * clk_divide_by - 1)) THEN
|
| 18461 |
|
|
cnt <= "00000";
|
| 18462 |
|
|
ELSE
|
| 18463 |
|
|
clkout_tmp <= '1';
|
| 18464 |
|
|
cnt <= cnt + "00001";
|
| 18465 |
|
|
END IF;
|
| 18466 |
|
|
END IF;
|
| 18467 |
|
|
end if;
|
| 18468 |
|
|
END PROCESS;
|
| 18469 |
|
|
|
| 18470 |
|
|
process( clkin, cnt )
|
| 18471 |
|
|
begin
|
| 18472 |
|
|
if( cnt =( 2*clk_divide_by -2) )then
|
| 18473 |
|
|
lloaden_tmp <= '1';
|
| 18474 |
|
|
else
|
| 18475 |
|
|
if(cnt = 0)then
|
| 18476 |
|
|
lloaden_tmp <= '0';
|
| 18477 |
|
|
end if;
|
| 18478 |
|
|
end if;
|
| 18479 |
|
|
end process;
|
| 18480 |
|
|
|
| 18481 |
|
|
END arch;
|
| 18482 |
|
|
|
| 18483 |
|
|
-------------------------------------------------------------------------------
|
| 18484 |
|
|
--
|
| 18485 |
|
|
-- Module Name : stratixiii_select_ini_phase_dpaclk
|
| 18486 |
|
|
--
|
| 18487 |
|
|
-- Description : Simulation model for selecting the initial phase of the dpa clock
|
| 18488 |
|
|
--
|
| 18489 |
|
|
--
|
| 18490 |
|
|
-------------------------------------------------------------------------------
|
| 18491 |
|
|
|
| 18492 |
|
|
LIBRARY ieee;
|
| 18493 |
|
|
USE ieee.std_logic_1164.all;
|
| 18494 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 18495 |
|
|
USE IEEE.std_logic_arith.ALL;
|
| 18496 |
|
|
|
| 18497 |
|
|
|
| 18498 |
|
|
ENTITY stratixiii_select_ini_phase_dpaclk IS
|
| 18499 |
|
|
GENERIC(
|
| 18500 |
|
|
initial_phase_select : integer := 0
|
| 18501 |
|
|
);
|
| 18502 |
|
|
PORT (
|
| 18503 |
|
|
|
| 18504 |
|
|
clkin : IN STD_LOGIC;
|
| 18505 |
|
|
loaden : IN STD_LOGIC;
|
| 18506 |
|
|
enable : IN STD_LOGIC;
|
| 18507 |
|
|
clkout : OUT STD_LOGIC;
|
| 18508 |
|
|
loadenout : OUT STD_LOGIC
|
| 18509 |
|
|
);
|
| 18510 |
|
|
END stratixiii_select_ini_phase_dpaclk;
|
| 18511 |
|
|
|
| 18512 |
|
|
ARCHITECTURE trans OF stratixiii_select_ini_phase_dpaclk IS
|
| 18513 |
|
|
|
| 18514 |
|
|
SIGNAL clk_period : time := 0 ps;
|
| 18515 |
|
|
SIGNAL last_clk_period : time := 0 ps;
|
| 18516 |
|
|
SIGNAL last_clkin_edge : time := 0 ps;
|
| 18517 |
|
|
|
| 18518 |
|
|
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
|
| 18519 |
|
|
SIGNAL clk0_tmp : STD_LOGIC;
|
| 18520 |
|
|
SIGNAL clk1_tmp : STD_LOGIC;
|
| 18521 |
|
|
SIGNAL clk2_tmp : STD_LOGIC;
|
| 18522 |
|
|
SIGNAL clk3_tmp : STD_LOGIC;
|
| 18523 |
|
|
SIGNAL clk4_tmp : STD_LOGIC;
|
| 18524 |
|
|
SIGNAL clk5_tmp : STD_LOGIC;
|
| 18525 |
|
|
SIGNAL clk6_tmp : STD_LOGIC;
|
| 18526 |
|
|
SIGNAL clk7_tmp : STD_LOGIC;
|
| 18527 |
|
|
SIGNAL loaden0_tmp : STD_LOGIC;
|
| 18528 |
|
|
SIGNAL loaden1_tmp : STD_LOGIC;
|
| 18529 |
|
|
SIGNAL loaden2_tmp : STD_LOGIC;
|
| 18530 |
|
|
SIGNAL loaden3_tmp : STD_LOGIC;
|
| 18531 |
|
|
SIGNAL loaden4_tmp : STD_LOGIC;
|
| 18532 |
|
|
SIGNAL loaden5_tmp : STD_LOGIC;
|
| 18533 |
|
|
SIGNAL loaden6_tmp : STD_LOGIC;
|
| 18534 |
|
|
SIGNAL loaden7_tmp : STD_LOGIC;
|
| 18535 |
|
|
|
| 18536 |
|
|
SIGNAL clkout_tmp : STD_LOGIC;
|
| 18537 |
|
|
SIGNAL loadenout_tmp : STD_LOGIC;
|
| 18538 |
|
|
|
| 18539 |
|
|
BEGIN
|
| 18540 |
|
|
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
|
| 18541 |
|
|
clk2_tmp when (initial_phase_select = 2) else
|
| 18542 |
|
|
clk3_tmp when (initial_phase_select = 3) else
|
| 18543 |
|
|
clk4_tmp when (initial_phase_select = 4) else
|
| 18544 |
|
|
clk5_tmp when (initial_phase_select = 5) else
|
| 18545 |
|
|
clk6_tmp when (initial_phase_select = 6) else
|
| 18546 |
|
|
clk7_tmp when (initial_phase_select = 7) else
|
| 18547 |
|
|
clk0_tmp;
|
| 18548 |
|
|
|
| 18549 |
|
|
clkout <= clkout_tmp when enable = '1' else clkin;
|
| 18550 |
|
|
|
| 18551 |
|
|
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
|
| 18552 |
|
|
loaden2_tmp when (initial_phase_select = 2) else
|
| 18553 |
|
|
loaden3_tmp when (initial_phase_select = 3) else
|
| 18554 |
|
|
loaden4_tmp when (initial_phase_select = 4) else
|
| 18555 |
|
|
loaden5_tmp when (initial_phase_select = 5) else
|
| 18556 |
|
|
loaden6_tmp when (initial_phase_select = 6) else
|
| 18557 |
|
|
loaden7_tmp when (initial_phase_select = 7) else
|
| 18558 |
|
|
loaden0_tmp;
|
| 18559 |
|
|
|
| 18560 |
|
|
loadenout <= loadenout_tmp when enable = '1' else loaden;
|
| 18561 |
|
|
|
| 18562 |
|
|
|
| 18563 |
|
|
-- Calculate the clock period
|
| 18564 |
|
|
PROCESS
|
| 18565 |
|
|
VARIABLE clk_period_tmp : time := 0 ps;
|
| 18566 |
|
|
BEGIN
|
| 18567 |
|
|
WAIT UNTIL (clkin'EVENT AND clkin = '1');
|
| 18568 |
|
|
IF (first_clkin_edge_detect = '0') THEN
|
| 18569 |
|
|
first_clkin_edge_detect <= '1';
|
| 18570 |
|
|
ELSE
|
| 18571 |
|
|
last_clk_period <= clk_period;
|
| 18572 |
|
|
clk_period_tmp := NOW - last_clkin_edge;
|
| 18573 |
|
|
END IF;
|
| 18574 |
|
|
|
| 18575 |
|
|
last_clkin_edge <= NOW;
|
| 18576 |
|
|
clk_period <= clk_period_tmp;
|
| 18577 |
|
|
END PROCESS;
|
| 18578 |
|
|
|
| 18579 |
|
|
-- Generate the phase shifted signals
|
| 18580 |
|
|
PROCESS (clkin)
|
| 18581 |
|
|
BEGIN
|
| 18582 |
|
|
clk0_tmp <= clkin;
|
| 18583 |
|
|
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
|
| 18584 |
|
|
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
|
| 18585 |
|
|
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
|
| 18586 |
|
|
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
|
| 18587 |
|
|
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
|
| 18588 |
|
|
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
|
| 18589 |
|
|
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
|
| 18590 |
|
|
END PROCESS;
|
| 18591 |
|
|
|
| 18592 |
|
|
PROCESS (loaden)
|
| 18593 |
|
|
BEGIN
|
| 18594 |
|
|
loaden0_tmp <= clkin;
|
| 18595 |
|
|
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
|
| 18596 |
|
|
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
|
| 18597 |
|
|
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
|
| 18598 |
|
|
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
|
| 18599 |
|
|
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
|
| 18600 |
|
|
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
|
| 18601 |
|
|
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
|
| 18602 |
|
|
END PROCESS;
|
| 18603 |
|
|
|
| 18604 |
|
|
END trans;
|
| 18605 |
|
|
|
| 18606 |
|
|
-------------------------------------------------------------------------------
|
| 18607 |
|
|
--
|
| 18608 |
|
|
-- Module Name : stratixiii_dpa_retime_block
|
| 18609 |
|
|
--
|
| 18610 |
|
|
-- Description : Simulation model for generating the retimed clock,data and loaden.
|
| 18611 |
|
|
-- Each of the signals has 8 different phase shifted versions.
|
| 18612 |
|
|
--
|
| 18613 |
|
|
--
|
| 18614 |
|
|
-------------------------------------------------------------------------------
|
| 18615 |
|
|
|
| 18616 |
|
|
LIBRARY ieee;
|
| 18617 |
|
|
USE ieee.std_logic_1164.all;
|
| 18618 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 18619 |
|
|
USE IEEE.std_logic_arith.ALL;
|
| 18620 |
|
|
|
| 18621 |
|
|
|
| 18622 |
|
|
ENTITY stratixiii_dpa_retime_block IS
|
| 18623 |
|
|
PORT (
|
| 18624 |
|
|
|
| 18625 |
|
|
clkin : IN STD_LOGIC;
|
| 18626 |
|
|
datain : IN STD_LOGIC;
|
| 18627 |
|
|
reset : IN STD_LOGIC;
|
| 18628 |
|
|
|
| 18629 |
|
|
clk0 : OUT STD_LOGIC;
|
| 18630 |
|
|
clk1 : OUT STD_LOGIC;
|
| 18631 |
|
|
clk2 : OUT STD_LOGIC;
|
| 18632 |
|
|
clk3 : OUT STD_LOGIC;
|
| 18633 |
|
|
clk4 : OUT STD_LOGIC;
|
| 18634 |
|
|
clk5 : OUT STD_LOGIC;
|
| 18635 |
|
|
clk6 : OUT STD_LOGIC;
|
| 18636 |
|
|
clk7 : OUT STD_LOGIC;
|
| 18637 |
|
|
data0 : OUT STD_LOGIC;
|
| 18638 |
|
|
data1 : OUT STD_LOGIC;
|
| 18639 |
|
|
data2 : OUT STD_LOGIC;
|
| 18640 |
|
|
data3 : OUT STD_LOGIC;
|
| 18641 |
|
|
data4 : OUT STD_LOGIC;
|
| 18642 |
|
|
data5 : OUT STD_LOGIC;
|
| 18643 |
|
|
data6 : OUT STD_LOGIC;
|
| 18644 |
|
|
data7 : OUT STD_LOGIC;
|
| 18645 |
|
|
lock : OUT STD_LOGIC
|
| 18646 |
|
|
);
|
| 18647 |
|
|
END stratixiii_dpa_retime_block;
|
| 18648 |
|
|
|
| 18649 |
|
|
ARCHITECTURE trans OF stratixiii_dpa_retime_block IS
|
| 18650 |
|
|
|
| 18651 |
|
|
SIGNAL clk_period : time := 0 ps;
|
| 18652 |
|
|
SIGNAL last_clk_period : time := 0 ps;
|
| 18653 |
|
|
SIGNAL last_clkin_edge : time := 0 ps;
|
| 18654 |
|
|
|
| 18655 |
|
|
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
|
| 18656 |
|
|
SIGNAL clk0_tmp : STD_LOGIC;
|
| 18657 |
|
|
SIGNAL clk1_tmp : STD_LOGIC;
|
| 18658 |
|
|
SIGNAL clk2_tmp : STD_LOGIC;
|
| 18659 |
|
|
SIGNAL clk3_tmp : STD_LOGIC;
|
| 18660 |
|
|
SIGNAL clk4_tmp : STD_LOGIC;
|
| 18661 |
|
|
SIGNAL clk5_tmp : STD_LOGIC;
|
| 18662 |
|
|
SIGNAL clk6_tmp : STD_LOGIC;
|
| 18663 |
|
|
SIGNAL clk7_tmp : STD_LOGIC;
|
| 18664 |
|
|
SIGNAL data0_tmp : STD_LOGIC;
|
| 18665 |
|
|
SIGNAL data1_tmp : STD_LOGIC;
|
| 18666 |
|
|
SIGNAL data2_tmp : STD_LOGIC;
|
| 18667 |
|
|
SIGNAL data3_tmp : STD_LOGIC;
|
| 18668 |
|
|
SIGNAL data4_tmp : STD_LOGIC;
|
| 18669 |
|
|
SIGNAL data5_tmp : STD_LOGIC;
|
| 18670 |
|
|
SIGNAL data6_tmp : STD_LOGIC;
|
| 18671 |
|
|
SIGNAL data7_tmp : STD_LOGIC;
|
| 18672 |
|
|
SIGNAL lock_tmp : STD_LOGIC;
|
| 18673 |
|
|
BEGIN
|
| 18674 |
|
|
|
| 18675 |
|
|
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
|
| 18676 |
|
|
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
|
| 18677 |
|
|
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
|
| 18678 |
|
|
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
|
| 18679 |
|
|
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
|
| 18680 |
|
|
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
|
| 18681 |
|
|
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
|
| 18682 |
|
|
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
|
| 18683 |
|
|
|
| 18684 |
|
|
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
|
| 18685 |
|
|
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
|
| 18686 |
|
|
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
|
| 18687 |
|
|
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
|
| 18688 |
|
|
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
|
| 18689 |
|
|
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
|
| 18690 |
|
|
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
|
| 18691 |
|
|
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
|
| 18692 |
|
|
|
| 18693 |
|
|
|
| 18694 |
|
|
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
|
| 18695 |
|
|
|
| 18696 |
|
|
-- Calculate the clock period
|
| 18697 |
|
|
PROCESS
|
| 18698 |
|
|
VARIABLE clk_period_tmp : time := 0 ps;
|
| 18699 |
|
|
BEGIN
|
| 18700 |
|
|
WAIT UNTIL (clkin'EVENT AND clkin = '1');
|
| 18701 |
|
|
IF (first_clkin_edge_detect = '0') THEN
|
| 18702 |
|
|
first_clkin_edge_detect <= '1';
|
| 18703 |
|
|
ELSE
|
| 18704 |
|
|
last_clk_period <= clk_period;
|
| 18705 |
|
|
clk_period_tmp := NOW - last_clkin_edge;
|
| 18706 |
|
|
END IF;
|
| 18707 |
|
|
|
| 18708 |
|
|
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
|
| 18709 |
|
|
lock_tmp <= '1';
|
| 18710 |
|
|
ELSE
|
| 18711 |
|
|
lock_tmp <= '0';
|
| 18712 |
|
|
END IF;
|
| 18713 |
|
|
|
| 18714 |
|
|
last_clkin_edge <= NOW;
|
| 18715 |
|
|
clk_period <= clk_period_tmp;
|
| 18716 |
|
|
END PROCESS;
|
| 18717 |
|
|
|
| 18718 |
|
|
-- Generate the phase shifted signals
|
| 18719 |
|
|
PROCESS (clkin)
|
| 18720 |
|
|
BEGIN
|
| 18721 |
|
|
clk0_tmp <= clkin;
|
| 18722 |
|
|
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
|
| 18723 |
|
|
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
|
| 18724 |
|
|
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
|
| 18725 |
|
|
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
|
| 18726 |
|
|
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
|
| 18727 |
|
|
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
|
| 18728 |
|
|
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
|
| 18729 |
|
|
END PROCESS;
|
| 18730 |
|
|
|
| 18731 |
|
|
PROCESS (datain)
|
| 18732 |
|
|
BEGIN
|
| 18733 |
|
|
data0_tmp <= datain;
|
| 18734 |
|
|
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
|
| 18735 |
|
|
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
|
| 18736 |
|
|
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
|
| 18737 |
|
|
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
|
| 18738 |
|
|
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
|
| 18739 |
|
|
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
|
| 18740 |
|
|
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
|
| 18741 |
|
|
END PROCESS;
|
| 18742 |
|
|
|
| 18743 |
|
|
END trans;
|
| 18744 |
|
|
|
| 18745 |
|
|
-------------------------------------------------------------------------------
|
| 18746 |
|
|
--
|
| 18747 |
|
|
-- Module Name : stratixiii_dpa_block
|
| 18748 |
|
|
--
|
| 18749 |
|
|
-- Description : Simulation model for selecting the retimed data, clock and loaden
|
| 18750 |
|
|
-- depending on teh PPM varaiation and direction of shift.
|
| 18751 |
|
|
--
|
| 18752 |
|
|
-------------------------------------------------------------------------------
|
| 18753 |
|
|
|
| 18754 |
|
|
|
| 18755 |
|
|
LIBRARY ieee;
|
| 18756 |
|
|
USE ieee.std_logic_1164.all;
|
| 18757 |
|
|
-- USE ieee.std_logic_unsigned.all;
|
| 18758 |
|
|
USE work.stratixiii_dpa_retime_block;
|
| 18759 |
|
|
library grlib;
|
| 18760 |
|
|
use grlib.stdlib.all;
|
| 18761 |
|
|
|
| 18762 |
|
|
ENTITY stratixiii_dpa_block IS
|
| 18763 |
|
|
GENERIC (
|
| 18764 |
|
|
net_ppm_variation : INTEGER := 0;
|
| 18765 |
|
|
is_negative_ppm_drift : STRING := "off";
|
| 18766 |
|
|
enable_soft_cdr_mode: STRING := "on"
|
| 18767 |
|
|
);
|
| 18768 |
|
|
PORT (
|
| 18769 |
|
|
|
| 18770 |
|
|
clkin : IN STD_LOGIC;
|
| 18771 |
|
|
dpareset : IN STD_LOGIC;
|
| 18772 |
|
|
dpahold : IN STD_LOGIC;
|
| 18773 |
|
|
datain : IN STD_LOGIC;
|
| 18774 |
|
|
|
| 18775 |
|
|
clkout : OUT STD_LOGIC;
|
| 18776 |
|
|
dataout : OUT STD_LOGIC;
|
| 18777 |
|
|
dpalock : OUT STD_LOGIC
|
| 18778 |
|
|
);
|
| 18779 |
|
|
END stratixiii_dpa_block;
|
| 18780 |
|
|
|
| 18781 |
|
|
ARCHITECTURE trans OF stratixiii_dpa_block IS
|
| 18782 |
|
|
COMPONENT stratixiii_dpa_retime_block IS
|
| 18783 |
|
|
PORT (
|
| 18784 |
|
|
clkin : IN STD_LOGIC;
|
| 18785 |
|
|
datain : IN STD_LOGIC;
|
| 18786 |
|
|
reset : IN STD_LOGIC;
|
| 18787 |
|
|
clk0 : OUT STD_LOGIC;
|
| 18788 |
|
|
clk1 : OUT STD_LOGIC;
|
| 18789 |
|
|
clk2 : OUT STD_LOGIC;
|
| 18790 |
|
|
clk3 : OUT STD_LOGIC;
|
| 18791 |
|
|
clk4 : OUT STD_LOGIC;
|
| 18792 |
|
|
clk5 : OUT STD_LOGIC;
|
| 18793 |
|
|
clk6 : OUT STD_LOGIC;
|
| 18794 |
|
|
clk7 : OUT STD_LOGIC;
|
| 18795 |
|
|
data0 : OUT STD_LOGIC;
|
| 18796 |
|
|
data1 : OUT STD_LOGIC;
|
| 18797 |
|
|
data2 : OUT STD_LOGIC;
|
| 18798 |
|
|
data3 : OUT STD_LOGIC;
|
| 18799 |
|
|
data4 : OUT STD_LOGIC;
|
| 18800 |
|
|
data5 : OUT STD_LOGIC;
|
| 18801 |
|
|
data6 : OUT STD_LOGIC;
|
| 18802 |
|
|
data7 : OUT STD_LOGIC;
|
| 18803 |
|
|
lock : OUT STD_LOGIC
|
| 18804 |
|
|
);
|
| 18805 |
|
|
END COMPONENT;
|
| 18806 |
|
|
|
| 18807 |
|
|
|
| 18808 |
|
|
SIGNAL clk0_tmp : STD_LOGIC;
|
| 18809 |
|
|
SIGNAL clk1_tmp : STD_LOGIC;
|
| 18810 |
|
|
SIGNAL clk2_tmp : STD_LOGIC;
|
| 18811 |
|
|
SIGNAL clk3_tmp : STD_LOGIC;
|
| 18812 |
|
|
SIGNAL clk4_tmp : STD_LOGIC;
|
| 18813 |
|
|
SIGNAL clk5_tmp : STD_LOGIC;
|
| 18814 |
|
|
SIGNAL clk6_tmp : STD_LOGIC;
|
| 18815 |
|
|
SIGNAL clk7_tmp : STD_LOGIC;
|
| 18816 |
|
|
SIGNAL data0_tmp : STD_LOGIC;
|
| 18817 |
|
|
SIGNAL data1_tmp : STD_LOGIC;
|
| 18818 |
|
|
SIGNAL data2_tmp : STD_LOGIC;
|
| 18819 |
|
|
SIGNAL data3_tmp : STD_LOGIC;
|
| 18820 |
|
|
SIGNAL data4_tmp : STD_LOGIC;
|
| 18821 |
|
|
SIGNAL data5_tmp : STD_LOGIC;
|
| 18822 |
|
|
SIGNAL data6_tmp : STD_LOGIC;
|
| 18823 |
|
|
SIGNAL data7_tmp : STD_LOGIC;
|
| 18824 |
|
|
|
| 18825 |
|
|
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
|
| 18826 |
|
|
SIGNAL clkout_tmp : STD_LOGIC;
|
| 18827 |
|
|
SIGNAL dataout_tmp : STD_LOGIC;
|
| 18828 |
|
|
|
| 18829 |
|
|
SIGNAL counter_reset_value : INTEGER ;
|
| 18830 |
|
|
SIGNAL count_value : INTEGER ;
|
| 18831 |
|
|
SIGNAL i : INTEGER := 0;
|
| 18832 |
|
|
SIGNAL dpalock_xhdl0 : STD_LOGIC;
|
| 18833 |
|
|
|
| 18834 |
|
|
BEGIN
|
| 18835 |
|
|
-- Drive referenced outputs
|
| 18836 |
|
|
dpalock <= dpalock_xhdl0;
|
| 18837 |
|
|
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
|
| 18838 |
|
|
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
|
| 18839 |
|
|
|
| 18840 |
|
|
data_clock_retime : stratixiii_dpa_retime_block
|
| 18841 |
|
|
PORT MAP (
|
| 18842 |
|
|
clkin => clkin,
|
| 18843 |
|
|
datain => datain,
|
| 18844 |
|
|
reset => dpareset,
|
| 18845 |
|
|
clk0 => clk0_tmp,
|
| 18846 |
|
|
clk1 => clk1_tmp,
|
| 18847 |
|
|
clk2 => clk2_tmp,
|
| 18848 |
|
|
clk3 => clk3_tmp,
|
| 18849 |
|
|
clk4 => clk4_tmp,
|
| 18850 |
|
|
clk5 => clk5_tmp,
|
| 18851 |
|
|
clk6 => clk6_tmp,
|
| 18852 |
|
|
clk7 => clk7_tmp,
|
| 18853 |
|
|
data0 => data0_tmp,
|
| 18854 |
|
|
data1 => data1_tmp,
|
| 18855 |
|
|
data2 => data2_tmp,
|
| 18856 |
|
|
data3 => data3_tmp,
|
| 18857 |
|
|
data4 => data4_tmp,
|
| 18858 |
|
|
data5 => data5_tmp,
|
| 18859 |
|
|
data6 => data6_tmp,
|
| 18860 |
|
|
data7 => data7_tmp,
|
| 18861 |
|
|
lock => dpalock_xhdl0
|
| 18862 |
|
|
);
|
| 18863 |
|
|
|
| 18864 |
|
|
PROCESS (clkin, dpareset, dpahold)
|
| 18865 |
|
|
variable initial : boolean := true;
|
| 18866 |
|
|
BEGIN
|
| 18867 |
|
|
if(initial) then
|
| 18868 |
|
|
if(net_ppm_variation = 0) then
|
| 18869 |
|
|
counter_reset_value <= 1;
|
| 18870 |
|
|
count_value <= 1;
|
| 18871 |
|
|
initial := false;
|
| 18872 |
|
|
else
|
| 18873 |
|
|
counter_reset_value <= 1000000 / (net_ppm_variation * 8);
|
| 18874 |
|
|
count_value <= 1000000 / (net_ppm_variation * 8);
|
| 18875 |
|
|
initial := false;
|
| 18876 |
|
|
end if;
|
| 18877 |
|
|
end if;
|
| 18878 |
|
|
|
| 18879 |
|
|
IF (clkin'EVENT AND clkin = '1') THEN
|
| 18880 |
|
|
IF(net_ppm_variation = 0) THEN
|
| 18881 |
|
|
select_xhdl1 <= "000";
|
| 18882 |
|
|
ELSE
|
| 18883 |
|
|
IF (dpareset = '1') THEN
|
| 18884 |
|
|
i <= 0;
|
| 18885 |
|
|
select_xhdl1 <= "000";
|
| 18886 |
|
|
ELSE
|
| 18887 |
|
|
IF (dpahold = '0') THEN
|
| 18888 |
|
|
IF (i < count_value) THEN
|
| 18889 |
|
|
i <= i + 1;
|
| 18890 |
|
|
ELSE
|
| 18891 |
|
|
select_xhdl1 <= select_xhdl1 + "001";
|
| 18892 |
|
|
i <= 0;
|
| 18893 |
|
|
END IF;
|
| 18894 |
|
|
END IF;
|
| 18895 |
|
|
END IF;
|
| 18896 |
|
|
END IF;
|
| 18897 |
|
|
END IF;
|
| 18898 |
|
|
END PROCESS;
|
| 18899 |
|
|
|
| 18900 |
|
|
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
|
| 18901 |
|
|
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
|
| 18902 |
|
|
BEGIN
|
| 18903 |
|
|
if (select_xhdl1 = "000") then
|
| 18904 |
|
|
clkout_tmp <= clk0_tmp;
|
| 18905 |
|
|
dataout_tmp <= data0_tmp;
|
| 18906 |
|
|
|
| 18907 |
|
|
elsif (select_xhdl1 = "001") then
|
| 18908 |
|
|
if( is_negative_ppm_drift = "off")then
|
| 18909 |
|
|
clkout_tmp <= clk1_tmp;
|
| 18910 |
|
|
dataout_tmp <= data1_tmp;
|
| 18911 |
|
|
else
|
| 18912 |
|
|
clkout_tmp <= clk7_tmp;
|
| 18913 |
|
|
dataout_tmp <= data7_tmp;
|
| 18914 |
|
|
end if;
|
| 18915 |
|
|
|
| 18916 |
|
|
elsif (select_xhdl1 = "010") then
|
| 18917 |
|
|
if( is_negative_ppm_drift = "off")then
|
| 18918 |
|
|
clkout_tmp <= clk2_tmp;
|
| 18919 |
|
|
dataout_tmp <= data2_tmp;
|
| 18920 |
|
|
else
|
| 18921 |
|
|
clkout_tmp <= clk6_tmp;
|
| 18922 |
|
|
dataout_tmp <= data6_tmp;
|
| 18923 |
|
|
end if;
|
| 18924 |
|
|
|
| 18925 |
|
|
elsif (select_xhdl1 = "011")then
|
| 18926 |
|
|
if( is_negative_ppm_drift = "off")then
|
| 18927 |
|
|
clkout_tmp <= clk3_tmp;
|
| 18928 |
|
|
dataout_tmp <= data3_tmp;
|
| 18929 |
|
|
else
|
| 18930 |
|
|
clkout_tmp <= clk5_tmp;
|
| 18931 |
|
|
dataout_tmp <= data5_tmp;
|
| 18932 |
|
|
end if;
|
| 18933 |
|
|
|
| 18934 |
|
|
elsif (select_xhdl1 = "100")then
|
| 18935 |
|
|
clkout_tmp <= clk4_tmp;
|
| 18936 |
|
|
dataout_tmp <= data4_tmp;
|
| 18937 |
|
|
|
| 18938 |
|
|
elsif (select_xhdl1 = "101")then
|
| 18939 |
|
|
if( is_negative_ppm_drift = "off")then
|
| 18940 |
|
|
clkout_tmp <= clk5_tmp;
|
| 18941 |
|
|
dataout_tmp <= data5_tmp;
|
| 18942 |
|
|
else
|
| 18943 |
|
|
clkout_tmp <= clk3_tmp;
|
| 18944 |
|
|
dataout_tmp <= data3_tmp;
|
| 18945 |
|
|
end if;
|
| 18946 |
|
|
|
| 18947 |
|
|
elsif (select_xhdl1 = "110") then
|
| 18948 |
|
|
if( is_negative_ppm_drift = "off")then
|
| 18949 |
|
|
clkout_tmp <= clk6_tmp;
|
| 18950 |
|
|
dataout_tmp <= data6_tmp;
|
| 18951 |
|
|
else
|
| 18952 |
|
|
clkout_tmp <= clk2_tmp;
|
| 18953 |
|
|
dataout_tmp <= data2_tmp;
|
| 18954 |
|
|
end if;
|
| 18955 |
|
|
|
| 18956 |
|
|
elsif (select_xhdl1 = "111")then
|
| 18957 |
|
|
if( is_negative_ppm_drift = "off")then
|
| 18958 |
|
|
clkout_tmp <= clk7_tmp;
|
| 18959 |
|
|
dataout_tmp <= data7_tmp;
|
| 18960 |
|
|
else
|
| 18961 |
|
|
clkout_tmp <= clk1_tmp;
|
| 18962 |
|
|
dataout_tmp <= data1_tmp;
|
| 18963 |
|
|
end if;
|
| 18964 |
|
|
else
|
| 18965 |
|
|
clkout_tmp <= clk0_tmp;
|
| 18966 |
|
|
dataout_tmp <= data0_tmp;
|
| 18967 |
|
|
end if;
|
| 18968 |
|
|
END PROCESS;
|
| 18969 |
|
|
|
| 18970 |
|
|
END trans;
|
| 18971 |
|
|
|
| 18972 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 18973 |
|
|
--
|
| 18974 |
|
|
-- Module Name : stratixiii_lvds_receiver
|
| 18975 |
|
|
--
|
| 18976 |
|
|
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
|
| 18977 |
|
|
-- atom. This module instantiates the following sub-modules :
|
| 18978 |
|
|
-- 1) stratixiii_lvds_rx_fifo
|
| 18979 |
|
|
-- 2) stratixiii_lvds_rx_bitslip
|
| 18980 |
|
|
-- 3) DFFEs for the LOADEN signals
|
| 18981 |
|
|
-- 4) stratixiii_lvds_rx_parallel_reg
|
| 18982 |
|
|
-- 5) stratixiii_pclk_divider
|
| 18983 |
|
|
-- 6) stratixiii_select_ini_phase_dpaclk
|
| 18984 |
|
|
-- 7) stratixiii_dpa_block
|
| 18985 |
|
|
--
|
| 18986 |
|
|
--/////////////////////////////////////////////////////////////////////////////
|
| 18987 |
|
|
|
| 18988 |
|
|
LIBRARY IEEE;
|
| 18989 |
|
|
USE ieee.std_logic_1164.all;
|
| 18990 |
|
|
USE IEEE.VITAL_Timing.all;
|
| 18991 |
|
|
USE IEEE.VITAL_Primitives.all;
|
| 18992 |
|
|
USE work.stratixiii_atom_pack.all;
|
| 18993 |
|
|
USE work.stratixiii_lvds_rx_bitslip;
|
| 18994 |
|
|
USE work.stratixiii_lvds_rx_fifo;
|
| 18995 |
|
|
USE work.stratixiii_lvds_rx_deser;
|
| 18996 |
|
|
USE work.stratixiii_lvds_rx_parallel_reg;
|
| 18997 |
|
|
USE work.stratixiii_lvds_reg;
|
| 18998 |
|
|
USE work.stratixiii_pclk_divider;
|
| 18999 |
|
|
USE work.stratixiii_select_ini_phase_dpaclk;
|
| 19000 |
|
|
USE work.stratixiii_dpa_block;
|
| 19001 |
|
|
|
| 19002 |
|
|
ENTITY stratixiii_lvds_receiver IS
|
| 19003 |
|
|
GENERIC ( channel_width : integer := 10;
|
| 19004 |
|
|
data_align_rollover : integer := 2;
|
| 19005 |
|
|
enable_dpa : string := "off";
|
| 19006 |
|
|
lose_lock_on_one_change : string := "off";
|
| 19007 |
|
|
reset_fifo_at_first_lock : string := "on";
|
| 19008 |
|
|
align_to_rising_edge_only : string := "on";
|
| 19009 |
|
|
use_serial_feedback_input : string := "off";
|
| 19010 |
|
|
dpa_debug : string := "off";
|
| 19011 |
|
|
enable_soft_cdr : string := "off";
|
| 19012 |
|
|
dpa_output_clock_phase_shift : INTEGER := 0 ;
|
| 19013 |
|
|
enable_dpa_initial_phase_selection : string := "off";
|
| 19014 |
|
|
dpa_initial_phase_value : INTEGER := 0;
|
| 19015 |
|
|
enable_dpa_align_to_rising_edge_only : string := "off";
|
| 19016 |
|
|
net_ppm_variation : INTEGER := 0;
|
| 19017 |
|
|
is_negative_ppm_drift : string := "off";
|
| 19018 |
|
|
rx_input_path_delay_engineering_bits : INTEGER := -1;
|
| 19019 |
|
|
x_on_bitslip : string := "on";
|
| 19020 |
|
|
lpm_type : string := "stratixiii_lvds_receiver";
|
| 19021 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 19022 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 19023 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 19024 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 19025 |
|
|
InstancePath : String := "*";
|
| 19026 |
|
|
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
|
| 19027 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01;
|
| 19028 |
|
|
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
|
| 19029 |
|
|
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
|
| 19030 |
|
|
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
|
| 19031 |
|
|
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
|
| 19032 |
|
|
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
|
| 19033 |
|
|
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
|
| 19034 |
|
|
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
|
| 19035 |
|
|
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
|
| 19036 |
|
|
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
|
| 19037 |
|
|
);
|
| 19038 |
|
|
PORT ( clk0 : IN std_logic;
|
| 19039 |
|
|
datain : IN std_logic := '0';
|
| 19040 |
|
|
enable0 : IN std_logic := '0';
|
| 19041 |
|
|
dpareset : IN std_logic := '0';
|
| 19042 |
|
|
dpahold : IN std_logic := '0';
|
| 19043 |
|
|
dpaswitch : IN std_logic := '0';
|
| 19044 |
|
|
fiforeset : IN std_logic := '0';
|
| 19045 |
|
|
bitslip : IN std_logic := '0';
|
| 19046 |
|
|
bitslipreset : IN std_logic := '0';
|
| 19047 |
|
|
serialfbk : IN std_logic := '0';
|
| 19048 |
|
|
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
|
| 19049 |
|
|
dpalock : OUT std_logic;
|
| 19050 |
|
|
bitslipmax : OUT std_logic;
|
| 19051 |
|
|
serialdataout : OUT std_logic;
|
| 19052 |
|
|
postdpaserialdataout : OUT std_logic;
|
| 19053 |
|
|
divfwdclk : OUT std_logic;
|
| 19054 |
|
|
dpaclkout : OUT std_logic;
|
| 19055 |
|
|
devclrn : IN std_logic := '1';
|
| 19056 |
|
|
devpor : IN std_logic := '1'
|
| 19057 |
|
|
);
|
| 19058 |
|
|
|
| 19059 |
|
|
END stratixiii_lvds_receiver;
|
| 19060 |
|
|
|
| 19061 |
|
|
ARCHITECTURE vital_arm_lvds_receiver OF stratixiii_lvds_receiver IS
|
| 19062 |
|
|
|
| 19063 |
|
|
COMPONENT stratixiii_lvds_rx_bitslip
|
| 19064 |
|
|
GENERIC ( channel_width : integer := 10;
|
| 19065 |
|
|
bitslip_rollover : integer := 12;
|
| 19066 |
|
|
x_on_bitslip : string := "on";
|
| 19067 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 19068 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 19069 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 19070 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 19071 |
|
|
InstancePath : String := "*";
|
| 19072 |
|
|
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
|
| 19073 |
|
|
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
|
| 19074 |
|
|
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
|
| 19075 |
|
|
tipd_datain : VitalDelayType01 := DefpropDelay01;
|
| 19076 |
|
|
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
|
| 19077 |
|
|
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
|
| 19078 |
|
|
);
|
| 19079 |
|
|
PORT ( clk0 : IN std_logic := '0';
|
| 19080 |
|
|
bslipcntl : IN std_logic := '0';
|
| 19081 |
|
|
bsliprst : IN std_logic := '0';
|
| 19082 |
|
|
datain : IN std_logic := '0';
|
| 19083 |
|
|
bslipmax : OUT std_logic;
|
| 19084 |
|
|
dataout : OUT std_logic
|
| 19085 |
|
|
);
|
| 19086 |
|
|
END COMPONENT;
|
| 19087 |
|
|
|
| 19088 |
|
|
COMPONENT stratixiii_lvds_rx_fifo
|
| 19089 |
|
|
GENERIC ( channel_width : integer := 10
|
| 19090 |
|
|
);
|
| 19091 |
|
|
PORT ( wclk : IN std_logic := '0';
|
| 19092 |
|
|
rclk : IN std_logic := '0';
|
| 19093 |
|
|
fiforst : IN std_logic := '0';
|
| 19094 |
|
|
dparst : IN std_logic := '0';
|
| 19095 |
|
|
datain : IN std_logic := '0';
|
| 19096 |
|
|
dataout : OUT std_logic
|
| 19097 |
|
|
);
|
| 19098 |
|
|
END COMPONENT;
|
| 19099 |
|
|
|
| 19100 |
|
|
COMPONENT stratixiii_lvds_rx_deser
|
| 19101 |
|
|
GENERIC ( channel_width : integer := 4
|
| 19102 |
|
|
);
|
| 19103 |
|
|
PORT ( clk : IN std_logic;
|
| 19104 |
|
|
datain : IN std_logic;
|
| 19105 |
|
|
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
|
| 19106 |
|
|
devclrn : IN std_logic := '1';
|
| 19107 |
|
|
devpor : IN std_logic := '1'
|
| 19108 |
|
|
);
|
| 19109 |
|
|
END COMPONENT;
|
| 19110 |
|
|
|
| 19111 |
|
|
COMPONENT stratixiii_lvds_rx_parallel_reg
|
| 19112 |
|
|
GENERIC ( channel_width : integer := 4
|
| 19113 |
|
|
);
|
| 19114 |
|
|
PORT ( clk : IN std_logic;
|
| 19115 |
|
|
enable : IN std_logic := '1';
|
| 19116 |
|
|
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
|
| 19117 |
|
|
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
|
| 19118 |
|
|
devclrn : IN std_logic := '1';
|
| 19119 |
|
|
devpor : IN std_logic := '1'
|
| 19120 |
|
|
);
|
| 19121 |
|
|
END COMPONENT;
|
| 19122 |
|
|
|
| 19123 |
|
|
COMPONENT stratixiii_lvds_reg
|
| 19124 |
|
|
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
|
| 19125 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 19126 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
| 19127 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
| 19128 |
|
|
InstancePath : String := "*";
|
| 19129 |
|
|
tipd_clk : VitalDelayType01 := DefpropDelay01;
|
| 19130 |
|
|
tipd_ena : VitalDelayType01 := DefpropDelay01;
|
| 19131 |
|
|
tipd_d : VitalDelayType01 := DefpropDelay01;
|
| 19132 |
|
|
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
|
| 19133 |
|
|
);
|
| 19134 |
|
|
PORT ( q : OUT std_logic;
|
| 19135 |
|
|
clk : IN std_logic;
|
| 19136 |
|
|
ena : IN std_logic := '1';
|
| 19137 |
|
|
d : IN std_logic;
|
| 19138 |
|
|
clrn : IN std_logic := '1';
|
| 19139 |
|
|
prn : IN std_logic := '1'
|
| 19140 |
|
|
);
|
| 19141 |
|
|
END COMPONENT;
|
| 19142 |
|
|
|
| 19143 |
|
|
COMPONENT stratixiii_pclk_divider
|
| 19144 |
|
|
GENERIC (
|
| 19145 |
|
|
clk_divide_by : integer := 1);
|
| 19146 |
|
|
PORT (
|
| 19147 |
|
|
clkin : IN std_logic;
|
| 19148 |
|
|
lloaden : OUT std_logic;
|
| 19149 |
|
|
clkout : OUT std_logic);
|
| 19150 |
|
|
END COMPONENT;
|
| 19151 |
|
|
|
| 19152 |
|
|
|
| 19153 |
|
|
COMPONENT stratixiii_select_ini_phase_dpaclk
|
| 19154 |
|
|
GENERIC(
|
| 19155 |
|
|
initial_phase_select : integer := 0
|
| 19156 |
|
|
);
|
| 19157 |
|
|
PORT (
|
| 19158 |
|
|
|
| 19159 |
|
|
clkin : IN STD_LOGIC;
|
| 19160 |
|
|
loaden : IN STD_LOGIC;
|
| 19161 |
|
|
enable : IN STD_LOGIC;
|
| 19162 |
|
|
loadenout : OUT STD_LOGIC;
|
| 19163 |
|
|
clkout : OUT STD_LOGIC
|
| 19164 |
|
|
);
|
| 19165 |
|
|
END COMPONENT;
|
| 19166 |
|
|
|
| 19167 |
|
|
|
| 19168 |
|
|
COMPONENT stratixiii_dpa_block
|
| 19169 |
|
|
GENERIC (
|
| 19170 |
|
|
net_ppm_variation : INTEGER := 0;
|
| 19171 |
|
|
is_negative_ppm_drift : STRING := "off";
|
| 19172 |
|
|
enable_soft_cdr_mode: STRING := "on"
|
| 19173 |
|
|
);
|
| 19174 |
|
|
PORT (
|
| 19175 |
|
|
clkin : IN STD_LOGIC;
|
| 19176 |
|
|
dpareset : IN STD_LOGIC;
|
| 19177 |
|
|
dpahold : IN STD_LOGIC;
|
| 19178 |
|
|
datain : IN STD_LOGIC;
|
| 19179 |
|
|
|
| 19180 |
|
|
clkout : OUT STD_LOGIC;
|
| 19181 |
|
|
dataout : OUT STD_LOGIC;
|
| 19182 |
|
|
dpalock : OUT STD_LOGIC
|
| 19183 |
|
|
);
|
| 19184 |
|
|
END COMPONENT;
|
| 19185 |
|
|
|
| 19186 |
|
|
-- INTERNAL SIGNALS
|
| 19187 |
|
|
signal bitslip_ipd : std_logic;
|
| 19188 |
|
|
signal bitslipreset_ipd : std_logic;
|
| 19189 |
|
|
signal clk0_ipd : std_logic;
|
| 19190 |
|
|
signal datain_ipd : std_logic;
|
| 19191 |
|
|
signal dpahold_ipd : std_logic;
|
| 19192 |
|
|
signal dpareset_ipd : std_logic;
|
| 19193 |
|
|
signal dpaswitch_ipd : std_logic;
|
| 19194 |
|
|
signal enable0_ipd : std_logic;
|
| 19195 |
|
|
signal fiforeset_ipd : std_logic;
|
| 19196 |
|
|
signal serialfbk_ipd : std_logic;
|
| 19197 |
|
|
|
| 19198 |
|
|
signal fifo_wclk : std_logic;
|
| 19199 |
|
|
signal fifo_rclk : std_logic;
|
| 19200 |
|
|
signal fifo_datain : std_logic;
|
| 19201 |
|
|
signal fifo_dataout : std_logic;
|
| 19202 |
|
|
signal fifo_reset : std_logic;
|
| 19203 |
|
|
signal slip_datain : std_logic;
|
| 19204 |
|
|
signal slip_dataout : std_logic;
|
| 19205 |
|
|
signal bitslip_reset : std_logic;
|
| 19206 |
|
|
-- wire deser_dataout;
|
| 19207 |
|
|
signal dpa_clk : std_logic;
|
| 19208 |
|
|
signal dpa_rst : std_logic;
|
| 19209 |
|
|
signal datain_reg : std_logic;
|
| 19210 |
|
|
signal datain_reg_neg : std_logic;
|
| 19211 |
|
|
signal datain_reg_tmp : std_logic;
|
| 19212 |
|
|
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
|
| 19213 |
|
|
signal reset_fifo : std_logic;
|
| 19214 |
|
|
signal gnd : std_logic := '0';
|
| 19215 |
|
|
signal vcc : std_logic := '1';
|
| 19216 |
|
|
signal in_reg_data : std_logic;
|
| 19217 |
|
|
signal slip_datain_tmp : std_logic;
|
| 19218 |
|
|
signal s_bitslip_clk : std_logic;
|
| 19219 |
|
|
signal loaden : std_logic;
|
| 19220 |
|
|
signal ini_dpa_clk : std_logic;
|
| 19221 |
|
|
signal ini_dpa_load : std_logic;
|
| 19222 |
|
|
signal ini_phase_select_enable : std_logic;
|
| 19223 |
|
|
signal dpa_clk_shift : std_logic;
|
| 19224 |
|
|
signal dpa_data_shift : std_logic;
|
| 19225 |
|
|
signal lloaden : std_logic;
|
| 19226 |
|
|
signal lock_tmp : std_logic;
|
| 19227 |
|
|
signal divfwdclk_tmp : std_logic;
|
| 19228 |
|
|
signal dpa_is_locked : std_logic;
|
| 19229 |
|
|
signal dpareg0_out : std_logic;
|
| 19230 |
|
|
signal dpareg1_out : std_logic;
|
| 19231 |
|
|
|
| 19232 |
|
|
signal xhdl_12 : std_logic;
|
| 19233 |
|
|
signal rxload : std_logic;
|
| 19234 |
|
|
|
| 19235 |
|
|
|
| 19236 |
|
|
begin
|
| 19237 |
|
|
|
| 19238 |
|
|
WireDelay : block
|
| 19239 |
|
|
begin
|
| 19240 |
|
|
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
|
| 19241 |
|
|
VitalWireDelay (datain_ipd, datain, tipd_datain);
|
| 19242 |
|
|
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
|
| 19243 |
|
|
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
|
| 19244 |
|
|
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
|
| 19245 |
|
|
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
|
| 19246 |
|
|
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
|
| 19247 |
|
|
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
|
| 19248 |
|
|
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
|
| 19249 |
|
|
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
|
| 19250 |
|
|
end block;
|
| 19251 |
|
|
|
| 19252 |
|
|
process (clk0_ipd, dpareset_ipd,lock_tmp )
|
| 19253 |
|
|
variable dpalock_VitalGlitchData : VitalGlitchDataType;
|
| 19254 |
|
|
variable initial : boolean := true;
|
| 19255 |
|
|
begin
|
| 19256 |
|
|
if (initial) then
|
| 19257 |
|
|
|
| 19258 |
|
|
if (reset_fifo_at_first_lock = "on") then
|
| 19259 |
|
|
reset_fifo <= '1';
|
| 19260 |
|
|
else
|
| 19261 |
|
|
reset_fifo <= '0';
|
| 19262 |
|
|
end if;
|
| 19263 |
|
|
|
| 19264 |
|
|
initial := false;
|
| 19265 |
|
|
end if;
|
| 19266 |
|
|
|
| 19267 |
|
|
----------------------
|
| 19268 |
|
|
-- Path Delay Section
|
| 19269 |
|
|
----------------------
|
| 19270 |
|
|
VitalPathDelay01 (
|
| 19271 |
|
|
OutSignal => dpalock,
|
| 19272 |
|
|
OutSignalName => "DPALOCK",
|
| 19273 |
|
|
OutTemp => dpa_is_locked,
|
| 19274 |
|
|
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
|
| 19275 |
|
|
GlitchData => dpalock_VitalGlitchData,
|
| 19276 |
|
|
Mode => DefGlitchMode,
|
| 19277 |
|
|
XOn => XOn,
|
| 19278 |
|
|
MsgOn => MsgOn );
|
| 19279 |
|
|
if(lock_tmp = '1') then
|
| 19280 |
|
|
reset_fifo <= '0';
|
| 19281 |
|
|
else
|
| 19282 |
|
|
reset_fifo <= '1';
|
| 19283 |
|
|
end if;
|
| 19284 |
|
|
end process;
|
| 19285 |
|
|
|
| 19286 |
|
|
|
| 19287 |
|
|
xhdl_12 <= devclrn OR devpor;
|
| 19288 |
|
|
|
| 19289 |
|
|
-- input register in non-DPA mode for sampling incoming data
|
| 19290 |
|
|
in_reg : stratixiii_lvds_reg
|
| 19291 |
|
|
PORT MAP ( d => in_reg_data,
|
| 19292 |
|
|
clk => clk0_ipd,
|
| 19293 |
|
|
ena => vcc,
|
| 19294 |
|
|
clrn => xhdl_12,
|
| 19295 |
|
|
prn => vcc,
|
| 19296 |
|
|
q => datain_reg
|
| 19297 |
|
|
);
|
| 19298 |
|
|
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
|
| 19299 |
|
|
|
| 19300 |
|
|
neg_reg : stratixiii_lvds_reg
|
| 19301 |
|
|
PORT MAP ( d => in_reg_data,
|
| 19302 |
|
|
clk => clk0_ipd,
|
| 19303 |
|
|
ena => vcc,
|
| 19304 |
|
|
clrn => xhdl_12,
|
| 19305 |
|
|
prn => vcc,
|
| 19306 |
|
|
q => datain_reg_neg
|
| 19307 |
|
|
);
|
| 19308 |
|
|
|
| 19309 |
|
|
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
|
| 19310 |
|
|
|
| 19311 |
|
|
-- dpa initial phase select
|
| 19312 |
|
|
ini_clk_phase_select: stratixiii_select_ini_phase_dpaclk
|
| 19313 |
|
|
GENERIC MAP(
|
| 19314 |
|
|
initial_phase_select => dpa_initial_phase_value
|
| 19315 |
|
|
)
|
| 19316 |
|
|
PORT MAP(
|
| 19317 |
|
|
clkin => clk0_ipd,
|
| 19318 |
|
|
loaden => enable0_ipd,
|
| 19319 |
|
|
enable => ini_phase_select_enable,
|
| 19320 |
|
|
loadenout=>ini_dpa_load,
|
| 19321 |
|
|
clkout => ini_dpa_clk
|
| 19322 |
|
|
);
|
| 19323 |
|
|
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
|
| 19324 |
|
|
|
| 19325 |
|
|
-- DPA circuitary
|
| 19326 |
|
|
dpareg0 : stratixiii_lvds_reg
|
| 19327 |
|
|
PORT MAP ( d => in_reg_data,
|
| 19328 |
|
|
clk => ini_dpa_clk,
|
| 19329 |
|
|
clrn => vcc,
|
| 19330 |
|
|
prn => vcc,
|
| 19331 |
|
|
ena => vcc,
|
| 19332 |
|
|
q => dpareg0_out
|
| 19333 |
|
|
);
|
| 19334 |
|
|
|
| 19335 |
|
|
dpareg1 : stratixiii_lvds_reg
|
| 19336 |
|
|
PORT MAP ( d => dpareg0_out,
|
| 19337 |
|
|
clk => ini_dpa_clk,
|
| 19338 |
|
|
clrn => vcc,
|
| 19339 |
|
|
prn => vcc,
|
| 19340 |
|
|
ena => vcc,
|
| 19341 |
|
|
q => dpareg1_out
|
| 19342 |
|
|
);
|
| 19343 |
|
|
dpa_circuit: stratixiii_dpa_block
|
| 19344 |
|
|
GENERIC MAP(
|
| 19345 |
|
|
net_ppm_variation => net_ppm_variation,
|
| 19346 |
|
|
is_negative_ppm_drift => is_negative_ppm_drift,
|
| 19347 |
|
|
enable_soft_cdr_mode => enable_soft_cdr
|
| 19348 |
|
|
)
|
| 19349 |
|
|
PORT MAP(
|
| 19350 |
|
|
clkin => ini_dpa_clk,
|
| 19351 |
|
|
dpareset => dpareset_ipd,
|
| 19352 |
|
|
dpahold => dpahold_ipd,
|
| 19353 |
|
|
datain => dpareg1_out,
|
| 19354 |
|
|
clkout => dpa_clk_shift,
|
| 19355 |
|
|
dataout => dpa_data_shift,
|
| 19356 |
|
|
dpalock => lock_tmp
|
| 19357 |
|
|
);
|
| 19358 |
|
|
|
| 19359 |
|
|
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
|
| 19360 |
|
|
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
|
| 19361 |
|
|
|
| 19362 |
|
|
-- PCLK and lloaden generation
|
| 19363 |
|
|
clk_forward: stratixiii_pclk_divider
|
| 19364 |
|
|
GENERIC MAP (
|
| 19365 |
|
|
clk_divide_by => channel_width )
|
| 19366 |
|
|
PORT MAP(
|
| 19367 |
|
|
clkin => dpa_clk,
|
| 19368 |
|
|
lloaden => lloaden,
|
| 19369 |
|
|
clkout => divfwdclk_tmp
|
| 19370 |
|
|
);
|
| 19371 |
|
|
|
| 19372 |
|
|
-- FIFO
|
| 19373 |
|
|
s_fifo : stratixiii_lvds_rx_fifo
|
| 19374 |
|
|
GENERIC MAP ( channel_width => channel_width
|
| 19375 |
|
|
)
|
| 19376 |
|
|
PORT MAP ( wclk => fifo_wclk,
|
| 19377 |
|
|
rclk => fifo_rclk,
|
| 19378 |
|
|
fiforst => fifo_reset,
|
| 19379 |
|
|
dparst => dpa_rst,
|
| 19380 |
|
|
datain => fifo_datain,
|
| 19381 |
|
|
dataout => fifo_dataout
|
| 19382 |
|
|
);
|
| 19383 |
|
|
|
| 19384 |
|
|
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
|
| 19385 |
|
|
fifo_wclk <= dpa_clk ;
|
| 19386 |
|
|
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
|
| 19387 |
|
|
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
|
| 19388 |
|
|
|
| 19389 |
|
|
-- Bit Slip
|
| 19390 |
|
|
s_bslip : stratixiii_lvds_rx_bitslip
|
| 19391 |
|
|
GENERIC MAP ( bitslip_rollover => data_align_rollover,
|
| 19392 |
|
|
channel_width => channel_width,
|
| 19393 |
|
|
x_on_bitslip => x_on_bitslip
|
| 19394 |
|
|
)
|
| 19395 |
|
|
PORT MAP ( clk0 => s_bitslip_clk,
|
| 19396 |
|
|
bslipcntl => bitslip_ipd,
|
| 19397 |
|
|
bsliprst => bitslip_reset,
|
| 19398 |
|
|
datain => slip_datain,
|
| 19399 |
|
|
bslipmax => bitslipmax,
|
| 19400 |
|
|
dataout => slip_dataout
|
| 19401 |
|
|
);
|
| 19402 |
|
|
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
|
| 19403 |
|
|
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
|
| 19404 |
|
|
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
|
| 19405 |
|
|
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
|
| 19406 |
|
|
|
| 19407 |
|
|
-- DESERIALISER
|
| 19408 |
|
|
rxload_reg : stratixiii_lvds_reg
|
| 19409 |
|
|
PORT MAP ( d => loaden,
|
| 19410 |
|
|
clk => s_bitslip_clk,
|
| 19411 |
|
|
ena => vcc,
|
| 19412 |
|
|
clrn => vcc,
|
| 19413 |
|
|
prn => vcc,
|
| 19414 |
|
|
q => rxload
|
| 19415 |
|
|
);
|
| 19416 |
|
|
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
|
| 19417 |
|
|
|
| 19418 |
|
|
s_deser : stratixiii_lvds_rx_deser
|
| 19419 |
|
|
GENERIC MAP (channel_width => channel_width
|
| 19420 |
|
|
)
|
| 19421 |
|
|
PORT MAP (clk => s_bitslip_clk,
|
| 19422 |
|
|
datain => slip_dataout,
|
| 19423 |
|
|
devclrn => devclrn,
|
| 19424 |
|
|
devpor => devpor,
|
| 19425 |
|
|
dataout => deser_dataout
|
| 19426 |
|
|
);
|
| 19427 |
|
|
|
| 19428 |
|
|
output_reg : stratixiii_lvds_rx_parallel_reg
|
| 19429 |
|
|
GENERIC MAP ( channel_width => channel_width
|
| 19430 |
|
|
)
|
| 19431 |
|
|
PORT MAP ( clk => s_bitslip_clk,
|
| 19432 |
|
|
enable => rxload,
|
| 19433 |
|
|
datain => deser_dataout,
|
| 19434 |
|
|
devpor => devpor,
|
| 19435 |
|
|
devclrn => devclrn,
|
| 19436 |
|
|
dataout => dataout
|
| 19437 |
|
|
);
|
| 19438 |
|
|
|
| 19439 |
|
|
dpa_is_locked <= lock_tmp when (enable_dpa = "on") else gnd;
|
| 19440 |
|
|
dpaclkout <= dpa_clk_shift;
|
| 19441 |
|
|
postdpaserialdataout <= dpa_data_shift ;
|
| 19442 |
|
|
serialdataout <= datain_ipd;
|
| 19443 |
|
|
divfwdclk <= divfwdclk_tmp ;
|
| 19444 |
|
|
|
| 19445 |
|
|
END vital_arm_lvds_receiver;
|
| 19446 |
|
|
----------------------------------------------------------------------------------
|
| 19447 |
|
|
--Module Name: stratixiii_pseudo_diff_out --
|
| 19448 |
|
|
--Description: Simulation model for Stratix III Pseudo Differential --
|
| 19449 |
|
|
-- Output Buffer --
|
| 19450 |
|
|
----------------------------------------------------------------------------------
|
| 19451 |
|
|
|
| 19452 |
|
|
|
| 19453 |
|
|
LIBRARY IEEE;
|
| 19454 |
|
|
use IEEE.std_logic_1164.all;
|
| 19455 |
|
|
use IEEE.std_logic_arith.all;
|
| 19456 |
|
|
use IEEE.VITAL_Timing.all;
|
| 19457 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 19458 |
|
|
use work.stratixiii_atom_pack.all;
|
| 19459 |
|
|
|
| 19460 |
|
|
ENTITY stratixiii_pseudo_diff_out IS
|
| 19461 |
|
|
GENERIC (
|
| 19462 |
|
|
tipd_i : VitalDelayType01 := DefPropDelay01;
|
| 19463 |
|
|
tpd_i_o : VitalDelayType01 := DefPropDelay01;
|
| 19464 |
|
|
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
|
| 19465 |
|
|
XOn : Boolean := DefGlitchXOn;
|
| 19466 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
| 19467 |
|
|
lpm_type : string := "stratixiii_pseudo_diff_out"
|
| 19468 |
|
|
);
|
| 19469 |
|
|
PORT (
|
| 19470 |
|
|
i : IN std_logic := '0';
|
| 19471 |
|
|
o : OUT std_logic;
|
| 19472 |
|
|
obar : OUT std_logic
|
| 19473 |
|
|
);
|
| 19474 |
|
|
END stratixiii_pseudo_diff_out;
|
| 19475 |
|
|
|
| 19476 |
|
|
ARCHITECTURE arch OF stratixiii_pseudo_diff_out IS
|
| 19477 |
|
|
SIGNAL i_ipd : std_logic ;
|
| 19478 |
|
|
SIGNAL o_tmp : std_logic ;
|
| 19479 |
|
|
SIGNAL obar_tmp : std_logic;
|
| 19480 |
|
|
|
| 19481 |
|
|
BEGIN
|
| 19482 |
|
|
WireDelay : block
|
| 19483 |
|
|
begin
|
| 19484 |
|
|
VitalWireDelay (i_ipd, i, tipd_i);
|
| 19485 |
|
|
end block;
|
| 19486 |
|
|
|
| 19487 |
|
|
PROCESS( i_ipd)
|
| 19488 |
|
|
BEGIN
|
| 19489 |
|
|
IF (i_ipd = '0') THEN
|
| 19490 |
|
|
o_tmp <= '0';
|
| 19491 |
|
|
obar_tmp <= '1';
|
| 19492 |
|
|
ELSE
|
| 19493 |
|
|
IF (i_ipd = '1') THEN
|
| 19494 |
|
|
o_tmp <= '1';
|
| 19495 |
|
|
obar_tmp <= '0';
|
| 19496 |
|
|
ELSE
|
| 19497 |
|
|
o_tmp <= i_ipd;
|
| 19498 |
|
|
obar_tmp <= i_ipd;
|
| 19499 |
|
|
END IF;
|
| 19500 |
|
|
END IF;
|
| 19501 |
|
|
END PROCESS;
|
| 19502 |
|
|
|
| 19503 |
|
|
---------------------
|
| 19504 |
|
|
-- Path Delay Section
|
| 19505 |
|
|
----------------------
|
| 19506 |
|
|
PROCESS( o_tmp,obar_tmp)
|
| 19507 |
|
|
variable o_VitalGlitchData : VitalGlitchDataType;
|
| 19508 |
|
|
variable obar_VitalGlitchData : VitalGlitchDataType;
|
| 19509 |
|
|
BEGIN
|
| 19510 |
|
|
VitalPathDelay01 (
|
| 19511 |
|
|
OutSignal => o,
|
| 19512 |
|
|
OutSignalName => "o",
|
| 19513 |
|
|
OutTemp => o_tmp,
|
| 19514 |
|
|
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
|
| 19515 |
|
|
GlitchData => o_VitalGlitchData,
|
| 19516 |
|
|
Mode => DefGlitchMode,
|
| 19517 |
|
|
XOn => XOn,
|
| 19518 |
|
|
MsgOn => MsgOn
|
| 19519 |
|
|
);
|
| 19520 |
|
|
VitalPathDelay01 (
|
| 19521 |
|
|
OutSignal => obar,
|
| 19522 |
|
|
OutSignalName => "obar",
|
| 19523 |
|
|
OutTemp => obar_tmp,
|
| 19524 |
|
|
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
|
| 19525 |
|
|
GlitchData => obar_VitalGlitchData,
|
| 19526 |
|
|
Mode => DefGlitchMode,
|
| 19527 |
|
|
XOn => XOn,
|
| 19528 |
|
|
MsgOn => MsgOn
|
| 19529 |
|
|
);
|
| 19530 |
|
|
END PROCESS;
|
| 19531 |
|
|
END arch;
|
| 19532 |
|
|
--------------------------------------------------------------
|
| 19533 |
|
|
--
|
| 19534 |
|
|
-- Entity Name : stratixiii_bias_logic
|
| 19535 |
|
|
--
|
| 19536 |
|
|
-- Description : STRATIXIII Bias Block's Logic Block
|
| 19537 |
|
|
-- VHDL simulation model
|
| 19538 |
|
|
--
|
| 19539 |
|
|
--------------------------------------------------------------
|
| 19540 |
|
|
LIBRARY IEEE;
|
| 19541 |
|
|
use IEEE.VITAL_Timing.all;
|
| 19542 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 19543 |
|
|
use IEEE.std_logic_1164.all;
|
| 19544 |
|
|
use work.stratixiii_atom_pack.all;
|
| 19545 |
|
|
|
| 19546 |
|
|
ENTITY stratixiii_bias_logic IS
|
| 19547 |
|
|
GENERIC (
|
| 19548 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 19549 |
|
|
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
|
| 19550 |
|
|
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
|
| 19551 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 19552 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 19553 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 19554 |
|
|
XOnChecks: Boolean := DefXOnChecks
|
| 19555 |
|
|
);
|
| 19556 |
|
|
PORT (
|
| 19557 |
|
|
clk : in std_logic := '0';
|
| 19558 |
|
|
shiftnld : in std_logic := '0';
|
| 19559 |
|
|
captnupdt : in std_logic := '0';
|
| 19560 |
|
|
mainclk : out std_logic := '0';
|
| 19561 |
|
|
updateclk : out std_logic := '0';
|
| 19562 |
|
|
capture : out std_logic := '0';
|
| 19563 |
|
|
update : out std_logic := '0'
|
| 19564 |
|
|
);
|
| 19565 |
|
|
|
| 19566 |
|
|
attribute VITAL_LEVEL0 of stratixiii_bias_logic : ENTITY IS TRUE;
|
| 19567 |
|
|
end stratixiii_bias_logic;
|
| 19568 |
|
|
|
| 19569 |
|
|
ARCHITECTURE vital_bias_logic of stratixiii_bias_logic IS
|
| 19570 |
|
|
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
|
| 19571 |
|
|
signal clk_ipd : std_logic := '0';
|
| 19572 |
|
|
signal shiftnld_ipd : std_logic := '0';
|
| 19573 |
|
|
signal captnupdt_ipd : std_logic := '0';
|
| 19574 |
|
|
begin
|
| 19575 |
|
|
|
| 19576 |
|
|
WireDelay : block
|
| 19577 |
|
|
begin
|
| 19578 |
|
|
VitalWireDelay (clk_ipd, clk, tipd_clk);
|
| 19579 |
|
|
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
|
| 19580 |
|
|
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
|
| 19581 |
|
|
end block;
|
| 19582 |
|
|
|
| 19583 |
|
|
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
|
| 19584 |
|
|
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
|
| 19585 |
|
|
begin
|
| 19586 |
|
|
select_tmp := captnupdt_ipd & shiftnld_ipd;
|
| 19587 |
|
|
case select_tmp IS
|
| 19588 |
|
|
when "10"|"11" =>
|
| 19589 |
|
|
mainclk <= '0';
|
| 19590 |
|
|
updateclk <= clk_ipd;
|
| 19591 |
|
|
capture <= '1';
|
| 19592 |
|
|
update <= '0';
|
| 19593 |
|
|
when "01" =>
|
| 19594 |
|
|
mainclk <= '0';
|
| 19595 |
|
|
updateclk <= clk_ipd;
|
| 19596 |
|
|
capture <= '0';
|
| 19597 |
|
|
update <= '0';
|
| 19598 |
|
|
when "00" =>
|
| 19599 |
|
|
mainclk <= clk_ipd;
|
| 19600 |
|
|
updateclk <= '0';
|
| 19601 |
|
|
capture <= '0';
|
| 19602 |
|
|
update <= '1';
|
| 19603 |
|
|
when others =>
|
| 19604 |
|
|
mainclk <= '0';
|
| 19605 |
|
|
updateclk <= '0';
|
| 19606 |
|
|
capture <= '0';
|
| 19607 |
|
|
update <= '0';
|
| 19608 |
|
|
end case;
|
| 19609 |
|
|
end process;
|
| 19610 |
|
|
|
| 19611 |
|
|
end vital_bias_logic;
|
| 19612 |
|
|
|
| 19613 |
|
|
--------------------------------------------------------------
|
| 19614 |
|
|
--
|
| 19615 |
|
|
-- Entity Name : stratixiii_bias_generator
|
| 19616 |
|
|
--
|
| 19617 |
|
|
-- Description : STRATIXIII Bias Generator VHDL simulation model
|
| 19618 |
|
|
--
|
| 19619 |
|
|
--------------------------------------------------------------
|
| 19620 |
|
|
LIBRARY IEEE;
|
| 19621 |
|
|
use IEEE.VITAL_Timing.all;
|
| 19622 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 19623 |
|
|
use IEEE.std_logic_1164.all;
|
| 19624 |
|
|
use work.stratixiii_atom_pack.all;
|
| 19625 |
|
|
|
| 19626 |
|
|
ENTITY stratixiii_bias_generator IS
|
| 19627 |
|
|
GENERIC (
|
| 19628 |
|
|
tipd_din : VitalDelayType01 := DefPropDelay01;
|
| 19629 |
|
|
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
|
| 19630 |
|
|
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
|
| 19631 |
|
|
tipd_update : VitalDelayType01 := DefPropDelay01;
|
| 19632 |
|
|
tipd_capture : VitalDelayType01 := DefPropDelay01;
|
| 19633 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 19634 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 19635 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 19636 |
|
|
XOnChecks: Boolean := DefXOnChecks
|
| 19637 |
|
|
);
|
| 19638 |
|
|
PORT (
|
| 19639 |
|
|
din : in std_logic := '0';
|
| 19640 |
|
|
mainclk : in std_logic := '0';
|
| 19641 |
|
|
updateclk : in std_logic := '0';
|
| 19642 |
|
|
capture : in std_logic := '0';
|
| 19643 |
|
|
update : in std_logic := '0';
|
| 19644 |
|
|
dout : out std_logic := '0'
|
| 19645 |
|
|
);
|
| 19646 |
|
|
|
| 19647 |
|
|
attribute VITAL_LEVEL0 of stratixiii_bias_generator : ENTITY IS TRUE;
|
| 19648 |
|
|
end stratixiii_bias_generator;
|
| 19649 |
|
|
|
| 19650 |
|
|
ARCHITECTURE vital_bias_generator of stratixiii_bias_generator IS
|
| 19651 |
|
|
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
|
| 19652 |
|
|
CONSTANT TOTAL_REG : integer := 252;
|
| 19653 |
|
|
signal din_ipd : std_logic := '0';
|
| 19654 |
|
|
signal mainclk_ipd : std_logic := '0';
|
| 19655 |
|
|
signal updateclk_ipd : std_logic := '0';
|
| 19656 |
|
|
signal update_ipd : std_logic := '0';
|
| 19657 |
|
|
signal capture_ipd : std_logic := '0';
|
| 19658 |
|
|
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
|
| 19659 |
|
|
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
|
| 19660 |
|
|
signal dout_tmp : std_logic := '0';
|
| 19661 |
|
|
signal i : integer := 0;
|
| 19662 |
|
|
|
| 19663 |
|
|
begin
|
| 19664 |
|
|
|
| 19665 |
|
|
WireDelay : block
|
| 19666 |
|
|
begin
|
| 19667 |
|
|
VitalWireDelay (din_ipd, din, tipd_din);
|
| 19668 |
|
|
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
|
| 19669 |
|
|
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
|
| 19670 |
|
|
VitalWireDelay (update_ipd, update, tipd_update);
|
| 19671 |
|
|
VitalWireDelay (capture_ipd, capture, tipd_capture);
|
| 19672 |
|
|
end block;
|
| 19673 |
|
|
|
| 19674 |
|
|
process (mainclk_ipd)
|
| 19675 |
|
|
begin
|
| 19676 |
|
|
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
|
| 19677 |
|
|
if ((capture_ipd = '0') AND (update_ipd = '1')) then
|
| 19678 |
|
|
for i in 0 to (TOTAL_REG - 1)
|
| 19679 |
|
|
loop
|
| 19680 |
|
|
generator_reg(i) <= update_reg(i);
|
| 19681 |
|
|
end loop;
|
| 19682 |
|
|
end if;
|
| 19683 |
|
|
end if;
|
| 19684 |
|
|
end process;
|
| 19685 |
|
|
|
| 19686 |
|
|
process (updateclk_ipd)
|
| 19687 |
|
|
begin
|
| 19688 |
|
|
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
|
| 19689 |
|
|
dout_tmp <= update_reg(TOTAL_REG - 1);
|
| 19690 |
|
|
|
| 19691 |
|
|
if ((capture_ipd = '0') AND (update_ipd = '0')) then
|
| 19692 |
|
|
for i in 1 to (TOTAL_REG - 1)
|
| 19693 |
|
|
loop
|
| 19694 |
|
|
update_reg(i) <= update_reg(i - 1);
|
| 19695 |
|
|
end loop;
|
| 19696 |
|
|
update_reg(0) <= din_ipd;
|
| 19697 |
|
|
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
|
| 19698 |
|
|
for i in 1 to (TOTAL_REG - 1)
|
| 19699 |
|
|
loop
|
| 19700 |
|
|
update_reg(i) <= generator_reg(i);
|
| 19701 |
|
|
end loop;
|
| 19702 |
|
|
end if;
|
| 19703 |
|
|
end if;
|
| 19704 |
|
|
end process;
|
| 19705 |
|
|
|
| 19706 |
|
|
dout <= dout_tmp;
|
| 19707 |
|
|
|
| 19708 |
|
|
end vital_bias_generator;
|
| 19709 |
|
|
|
| 19710 |
|
|
--------------------------------------------------------------
|
| 19711 |
|
|
--
|
| 19712 |
|
|
-- Entity Name : stratixiii_bias_block
|
| 19713 |
|
|
--
|
| 19714 |
|
|
-- Description : STRATIXIII Bias Block VHDL simulation model
|
| 19715 |
|
|
--
|
| 19716 |
|
|
--------------------------------------------------------------
|
| 19717 |
|
|
LIBRARY IEEE;
|
| 19718 |
|
|
use IEEE.VITAL_Timing.all;
|
| 19719 |
|
|
use IEEE.VITAL_Primitives.all;
|
| 19720 |
|
|
use IEEE.std_logic_1164.all;
|
| 19721 |
|
|
use work.stratixiii_atom_pack.all;
|
| 19722 |
|
|
|
| 19723 |
|
|
ENTITY stratixiii_bias_block IS
|
| 19724 |
|
|
GENERIC (
|
| 19725 |
|
|
lpm_type : string := "stratixiii_bias_block";
|
| 19726 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 19727 |
|
|
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
|
| 19728 |
|
|
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
|
| 19729 |
|
|
tipd_din : VitalDelayType01 := DefPropDelay01;
|
| 19730 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 19731 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 19732 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 19733 |
|
|
XOnChecks: Boolean := DefXOnChecks
|
| 19734 |
|
|
);
|
| 19735 |
|
|
PORT (
|
| 19736 |
|
|
clk : in std_logic := '0';
|
| 19737 |
|
|
shiftnld : in std_logic := '0';
|
| 19738 |
|
|
captnupdt : in std_logic := '0';
|
| 19739 |
|
|
din : in std_logic := '0';
|
| 19740 |
|
|
dout : out std_logic := '0'
|
| 19741 |
|
|
);
|
| 19742 |
|
|
|
| 19743 |
|
|
attribute VITAL_LEVEL0 of stratixiii_bias_block : ENTITY IS TRUE;
|
| 19744 |
|
|
end stratixiii_bias_block;
|
| 19745 |
|
|
|
| 19746 |
|
|
ARCHITECTURE vital_bias_block of stratixiii_bias_block IS
|
| 19747 |
|
|
|
| 19748 |
|
|
COMPONENT stratixiii_bias_logic
|
| 19749 |
|
|
GENERIC (
|
| 19750 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
| 19751 |
|
|
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
|
| 19752 |
|
|
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
|
| 19753 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 19754 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 19755 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 19756 |
|
|
XOnChecks: Boolean := DefXOnChecks
|
| 19757 |
|
|
);
|
| 19758 |
|
|
PORT (
|
| 19759 |
|
|
clk : in std_logic := '0';
|
| 19760 |
|
|
shiftnld : in std_logic := '0';
|
| 19761 |
|
|
captnupdt : in std_logic := '0';
|
| 19762 |
|
|
mainclk : out std_logic := '0';
|
| 19763 |
|
|
updateclk : out std_logic := '0';
|
| 19764 |
|
|
capture : out std_logic := '0';
|
| 19765 |
|
|
update : out std_logic := '0'
|
| 19766 |
|
|
);
|
| 19767 |
|
|
end COMPONENT;
|
| 19768 |
|
|
|
| 19769 |
|
|
COMPONENT stratixiii_bias_generator
|
| 19770 |
|
|
GENERIC (
|
| 19771 |
|
|
tipd_din : VitalDelayType01 := DefPropDelay01;
|
| 19772 |
|
|
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
|
| 19773 |
|
|
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
|
| 19774 |
|
|
tipd_update : VitalDelayType01 := DefPropDelay01;
|
| 19775 |
|
|
tipd_capture : VitalDelayType01 := DefPropDelay01;
|
| 19776 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
| 19777 |
|
|
XOn: Boolean := DefGlitchXOn;
|
| 19778 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
| 19779 |
|
|
XOnChecks: Boolean := DefXOnChecks
|
| 19780 |
|
|
);
|
| 19781 |
|
|
PORT (
|
| 19782 |
|
|
din : in std_logic := '0';
|
| 19783 |
|
|
mainclk : in std_logic := '0';
|
| 19784 |
|
|
updateclk : in std_logic := '0';
|
| 19785 |
|
|
capture : in std_logic := '0';
|
| 19786 |
|
|
update : in std_logic := '0';
|
| 19787 |
|
|
dout : out std_logic := '0'
|
| 19788 |
|
|
);
|
| 19789 |
|
|
end COMPONENT;
|
| 19790 |
|
|
|
| 19791 |
|
|
signal mainclk_wire : std_logic := '0';
|
| 19792 |
|
|
signal updateclk_wire : std_logic := '0';
|
| 19793 |
|
|
signal capture_wire : std_logic := '0';
|
| 19794 |
|
|
signal update_wire : std_logic := '0';
|
| 19795 |
|
|
|
| 19796 |
|
|
begin
|
| 19797 |
|
|
|
| 19798 |
|
|
logic_block : stratixiii_bias_logic
|
| 19799 |
|
|
PORT MAP (
|
| 19800 |
|
|
clk => clk,
|
| 19801 |
|
|
shiftnld => shiftnld,
|
| 19802 |
|
|
captnupdt => captnupdt,
|
| 19803 |
|
|
mainclk => mainclk_wire,
|
| 19804 |
|
|
updateclk => updateclk_wire,
|
| 19805 |
|
|
capture => capture_wire,
|
| 19806 |
|
|
update => update_wire
|
| 19807 |
|
|
);
|
| 19808 |
|
|
|
| 19809 |
|
|
bias_generator : stratixiii_bias_generator
|
| 19810 |
|
|
PORT MAP (
|
| 19811 |
|
|
din => din,
|
| 19812 |
|
|
mainclk => mainclk_wire,
|
| 19813 |
|
|
updateclk => updateclk_wire,
|
| 19814 |
|
|
capture => capture_wire,
|
| 19815 |
|
|
update => update_wire,
|
| 19816 |
|
|
dout => dout
|
| 19817 |
|
|
);
|
| 19818 |
|
|
|
| 19819 |
|
|
end vital_bias_block;
|
| 19820 |
|
|
-------------------------------------------------------------------
|
| 19821 |
|
|
--
|
| 19822 |
|
|
-- Entity Name : stratixiii_tsdblock
|
| 19823 |
|
|
--
|
| 19824 |
|
|
-- Description : Stratix III TSDBLOCK VHDL Simulation model
|
| 19825 |
|
|
--
|
| 19826 |
|
|
-------------------------------------------------------------------
|
| 19827 |
|
|
LIBRARY IEEE;
|
| 19828 |
|
|
use IEEE.std_logic_1164.all;
|
| 19829 |
|
|
use work.stratixiii_atom_pack.all;
|
| 19830 |
|
|
|
| 19831 |
|
|
entity stratixiii_tsdblock is
|
| 19832 |
|
|
generic (
|
| 19833 |
|
|
poi_cal_temperature : integer := 85;
|
| 19834 |
|
|
clock_divider_enable : string := "on";
|
| 19835 |
|
|
clock_divider_value : integer := 40;
|
| 19836 |
|
|
sim_tsdcalo : integer := 0;
|
| 19837 |
|
|
lpm_type : string := "stratixiii_tsdblock"
|
| 19838 |
|
|
);
|
| 19839 |
|
|
port (
|
| 19840 |
|
|
offset : in std_logic_vector(5 downto 0);
|
| 19841 |
|
|
clk : in std_logic;
|
| 19842 |
|
|
ce : in std_logic;
|
| 19843 |
|
|
clr : in std_logic;
|
| 19844 |
|
|
tsdcalo : out std_logic_vector(7 downto 0);
|
| 19845 |
|
|
tsdcaldone : out std_logic;
|
| 19846 |
|
|
fdbkctrlfromcore : in std_logic := '0';
|
| 19847 |
|
|
compouttest : in std_logic := '0';
|
| 19848 |
|
|
tsdcompout : out std_logic;
|
| 19849 |
|
|
offsetout : out std_logic_vector(5 downto 0)
|
| 19850 |
|
|
);
|
| 19851 |
|
|
end stratixiii_tsdblock;
|
| 19852 |
|
|
|
| 19853 |
|
|
architecture architecture_tsdblock of stratixiii_tsdblock is
|
| 19854 |
|
|
begin
|
| 19855 |
|
|
|
| 19856 |
|
|
end architecture_tsdblock; -- end of stratixiii_tsdblock
|
