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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [umc18/] [components/] [umc_components.vhd] - Blame information for rev 2

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1 2 dimamali 
------------------------------------------------------------------------------
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--  This file is a part of the GRLIB VHDL IP LIBRARY
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--  Copyright (C) 2003, Gaisler Research
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--
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--  This program is free software; you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation; either version 2 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program; if not, write to the Free Software
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--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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-----------------------------------------------------------------------------
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-- Package:     umc_components
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-- File:        umc_components.vhd
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-- Author:      Jiri Gaisler - Gaisler Research
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-- Description: UMC 0.18 component declarations
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package umc_components is
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  -- input pad
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  component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
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  -- input pad with pull-up
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  component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
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  -- input pad with pull-down
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  component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
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  -- schmitt input pad
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  component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
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  -- output pads
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  component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
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  component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
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  component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
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  -- tri-state output pads
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  component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
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  component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
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  component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
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  -- bidirectional pads
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  component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
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  component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
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  component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
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  component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
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  component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
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  component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
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  -- single-port memory
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  component SRAM_2048wx32b is
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  port (
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        a    : in  std_logic_vector(10 downto 0);
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        data : in  std_logic_vector(31 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(31 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_1024wx32b is
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  port (
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        a    : in  std_logic_vector(9 downto 0);
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        data : in  std_logic_vector(31 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(31 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_512wx32b is
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  port (
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        a    : in  std_logic_vector(8 downto 0);
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        data : in  std_logic_vector(31 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(31 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_256wx32b is
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  port (
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        a    : in  std_logic_vector(7 downto 0);
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        data : in  std_logic_vector(31 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(31 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_128wx32b is
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  port (
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        a    : in  std_logic_vector(6 downto 0);
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        data : in  std_logic_vector(31 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(31 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_64wx32b is
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  port (
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        a    : in  std_logic_vector(5 downto 0);
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        data : in  std_logic_vector(31 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(31 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_32wx32b is
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  port (
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        a    : in  std_logic_vector(4 downto 0);
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        data : in  std_logic_vector(31 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(31 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_2048wx40b is
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  port (
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        a    : in  std_logic_vector(10 downto 0);
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        data : in  std_logic_vector(39 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(39 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_1024wx40b is
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  port (
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        a    : in  std_logic_vector(9 downto 0);
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        data : in  std_logic_vector(39 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(39 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_512wx40b is
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  port (
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        a    : in  std_logic_vector(8 downto 0);
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        data : in  std_logic_vector(39 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(39 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_256wx40b is
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  port (
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        a    : in  std_logic_vector(7 downto 0);
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        data : in  std_logic_vector(39 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(39 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_128wx40b is
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  port (
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        a    : in  std_logic_vector(6 downto 0);
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        data : in  std_logic_vector(39 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(39 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_64wx40b is
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  port (
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        a    : in  std_logic_vector(5 downto 0);
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        data : in  std_logic_vector(39 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(39 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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  component SRAM_32wx40b is
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  port (
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        a    : in  std_logic_vector(4 downto 0);
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        data : in  std_logic_vector(39 downto 0);
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        csn  : in  std_logic;
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        wen  : in  std_logic;
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        oen  : in  std_logic;
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        q    : out std_logic_vector(39 downto 0);
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        clk  : in  std_logic
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       );
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  end component;
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end;
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