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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [umc18/] [components/] [umc_simprims.vhd] - Blame information for rev 2

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------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Package:     umc_simprims
-- File:        umc_simprims.vhd
-- Author:      Jiri Gaisler - Gaisler Research
-- Description: Simple UMC 0.18 simulation models
------------------------------------------------------------------------------
 
-- pragma translate_off
 
-- input pad
 
library ieee;
use ieee.std_logic_1164.all;
 
entity ICMT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3V is begin Z <= to_X01(A) after 1 ns; end;
 
-- input pad with pull-up
 
library ieee;
use ieee.std_logic_1164.all;
 
entity ICMT3VPU is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPU is begin
  Z <= to_X01(A) after 1 ns; --A <= 'H';
end;
 
-- input pad with pull-down
 
library ieee;
use ieee.std_logic_1164.all;
 
entity ICMT3VPD is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPD is begin
  Z <= to_X01(A) after 1 ns; --A <= 'L';
end;
 
-- schmitt input pad
 
library ieee;
use ieee.std_logic_1164.all;
 
entity ISTRT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ISTRT3V is begin Z <= to_X01(A) after 1 ns; end;
 
-- output pads
 
library ieee;
use ieee.std_logic_1164.all;
 
entity OCM3V4 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V4 is begin Z <= to_X01(A) after 3 ns; end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity OCM3V12 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V12 is begin Z <= to_X01(A) after 2 ns; end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity OCM3V24 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V24 is begin Z <= to_X01(A) after 1 ns; end;
 
 
-- tri-state output pads
 
library ieee;
use ieee.std_logic_1164.all;
 
entity OCMTR4 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR4 is begin
  Z <= to_X01(A) after 3 ns when to_X01(en) = '1' else
             'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity OCMTR12 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR12 is begin
  Z <= to_X01(A) after 2 ns when to_X01(en) = '1' else
             'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity OCMTR24 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR24 is begin
  Z <= to_X01(A) after 1 ns when to_X01(en) = '1' else
             'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
end;
 
-- bidirectional pads
 
library ieee;
use ieee.std_logic_1164.all;
 
entity BICM3V4 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V4 is begin
  IO <= to_X01(A) after 3 ns when to_X01(en) = '1' else
             'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
  Z <= to_X01(IO) after 1 ns;
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity BICM3V12 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V12 is begin
  IO <= to_X01(A) after 2 ns when to_X01(en) = '1' else
             'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
  Z <= to_X01(IO) after 1 ns;
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity BICM3V24 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V24 is begin
  IO <= to_X01(A) after 1 ns when to_X01(en) = '1' else
             'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
  Z <= to_X01(IO) after 1 ns;
end;
 
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Receiver is port(  A, AN : in std_logic; Z : out std_logic); end;
architecture struct of LVDS_Receiver is
signal yn : std_ulogic := '0';
begin
  yn <= to_X01(A) after 1 ns when to_x01(A xor AN) = '1' else yn after 1 ns;
  Z <= yn;
end;
 
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Driver is port (A, Vref, HI : in std_logic; Z, ZN : out std_logic ); end;
architecture struct of LVDS_Driver is begin
  Z <= A after 1 ns;
  ZN <= not A after 1 ns;
end;
 
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Biasmodule is port ( RefR : in std_logic; Vref, HI : out std_logic); end;
architecture struct of LVDS_Biasmodule is begin end;
 
-- single-port memory
 
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
 
entity UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of UMC_SIM_SRAM is
subtype memword is std_logic_vector(dbits-1 downto 0);
type mem_type is array (0 to 2**abits-1) of memword;
signal qint : memword;
begin
  m : process(clk)
  variable mem : mem_type;
  begin
    if rising_edge(clk) then
      qint <= (others => 'X');
      if to_X01(wen) = '0' then mem(conv_integer(a)) := data;
      elsif to_X01(wen) = '1' then qint <= mem(conv_integer(a)); end if;
    end if;
  end process;
 
  q <= qint when to_X01(oen) = '0' else
        (others => 'Z') when to_X01(oen) = '1' else (others => 'X');
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_2048wx32b is
  port (
        a    : in  std_logic_vector(10 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_2048wx32b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (11, 32) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_1024wx32b is
  port (
        a    : in  std_logic_vector(9 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_1024wx32b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (10, 32) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_512wx32b is
  port (
        a    : in  std_logic_vector(8 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_512wx32b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (9, 32) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_256wx32b is
  port (
        a    : in  std_logic_vector(7 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_256wx32b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (8, 32) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_128wx32b is
  port (
        a    : in  std_logic_vector(6 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_128wx32b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (7, 32) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_64wx32b is
  port (
        a    : in  std_logic_vector(5 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_64wx32b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (6, 32) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_32wx32b is
  port (
        a    : in  std_logic_vector(4 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_32wx32b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (5, 32) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_2048wx40b is
  port (
        a    : in  std_logic_vector(10 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_2048wx40b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (11, 40) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_1024wx40b is
  port (
        a    : in  std_logic_vector(9 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_1024wx40b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (10, 40) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_512wx40b is
  port (
        a    : in  std_logic_vector(8 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_512wx40b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (9, 40) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_256wx40b is
  port (
        a    : in  std_logic_vector(7 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_256wx40b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (8, 40) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_128wx40b is
  port (
        a    : in  std_logic_vector(6 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_128wx40b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (7, 40) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_64wx40b is
  port (
        a    : in  std_logic_vector(5 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_64wx40b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (6, 40) port map (a, data, csn, wen, oen, q, clk);
end;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SRAM_32wx40b is
  port (
        a    : in  std_logic_vector(4 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
end;
architecture behav of SRAM_32wx40b is
  component UMC_SIM_SRAM is
  generic (abits, dbits : integer := 8);
  port (
        a    : in  std_logic_vector(abits-1 downto 0);
        data : in  std_logic_vector(dbits-1 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(dbits-1 downto 0);
        clk  : in  std_logic
       );
  end component;
begin
 m : UMC_SIM_SRAM generic map (5, 40) port map (a, data, csn, wen, oen, q, clk);
end;
 
-- pragma translate_on

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [umc18/] [components/] [umc_simprims.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Package: umc_simprims`
20			`-- File: umc_simprims.vhd`
21			`-- Author: Jiri Gaisler - Gaisler Research`
22			`-- Description: Simple UMC 0.18 simulation models`
23			`------------------------------------------------------------------------------`
24
25			`-- pragma translate_off`
26
27			`-- input pad`
28
29			`library ieee;`
30			`use ieee.std_logic_1164.all;`
31
32			`entity ICMT3V is port( A : in std_logic; Z : out std_logic); end ;`
33			`architecture behav of ICMT3V is begin Z <= to_X01(A) after 1 ns; end;`
34
35			`-- input pad with pull-up`
36
37			`library ieee;`
38			`use ieee.std_logic_1164.all;`
39
40			`entity ICMT3VPU is port( A : in std_logic; Z : out std_logic); end ;`
41			`architecture behav of ICMT3VPU is begin`
42			`Z <= to_X01(A) after 1 ns; --A <= 'H';`
43			`end;`
44
45			`-- input pad with pull-down`
46
47			`library ieee;`
48			`use ieee.std_logic_1164.all;`
49
50			`entity ICMT3VPD is port( A : in std_logic; Z : out std_logic); end ;`
51			`architecture behav of ICMT3VPD is begin`
52			`Z <= to_X01(A) after 1 ns; --A <= 'L';`
53			`end;`
54
55			`-- schmitt input pad`
56
57			`library ieee;`
58			`use ieee.std_logic_1164.all;`
59
60			`entity ISTRT3V is port( A : in std_logic; Z : out std_logic); end ;`
61			`architecture behav of ISTRT3V is begin Z <= to_X01(A) after 1 ns; end;`
62
63			`-- output pads`
64
65			`library ieee;`
66			`use ieee.std_logic_1164.all;`
67
68			`entity OCM3V4 is port( Z : out std_logic; A : in std_logic); end;`
69			`architecture behav of OCM3V4 is begin Z <= to_X01(A) after 3 ns; end;`
70
71			`library ieee;`
72			`use ieee.std_logic_1164.all;`
73
74			`entity OCM3V12 is port( Z : out std_logic; A : in std_logic); end;`
75			`architecture behav of OCM3V12 is begin Z <= to_X01(A) after 2 ns; end;`
76
77			`library ieee;`
78			`use ieee.std_logic_1164.all;`
79
80			`entity OCM3V24 is port( Z : out std_logic; A : in std_logic); end;`
81			`architecture behav of OCM3V24 is begin Z <= to_X01(A) after 1 ns; end;`
82
83
84			`-- tri-state output pads`
85
86			`library ieee;`
87			`use ieee.std_logic_1164.all;`
88
89			`entity OCMTR4 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;`
90			`architecture behav of OCMTR4 is begin`
91			`Z <= to_X01(A) after 3 ns when to_X01(en) = '1' else`
92			`'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;`
93			`end;`
94
95			`library ieee;`
96			`use ieee.std_logic_1164.all;`
97
98			`entity OCMTR12 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;`
99			`architecture behav of OCMTR12 is begin`
100			`Z <= to_X01(A) after 2 ns when to_X01(en) = '1' else`
101			`'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;`
102			`end;`
103
104			`library ieee;`
105			`use ieee.std_logic_1164.all;`
106
107			`entity OCMTR24 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;`
108			`architecture behav of OCMTR24 is begin`
109			`Z <= to_X01(A) after 1 ns when to_X01(en) = '1' else`
110			`'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;`
111			`end;`
112
113			`-- bidirectional pads`
114
115			`library ieee;`
116			`use ieee.std_logic_1164.all;`
117
118			`entity BICM3V4 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;`
119			`architecture behav of BICM3V4 is begin`
120			`IO <= to_X01(A) after 3 ns when to_X01(en) = '1' else`
121			`'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;`
122			`Z <= to_X01(IO) after 1 ns;`
123			`end;`
124
125			`library ieee;`
126			`use ieee.std_logic_1164.all;`
127
128			`entity BICM3V12 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;`
129			`architecture behav of BICM3V12 is begin`
130			`IO <= to_X01(A) after 2 ns when to_X01(en) = '1' else`
131			`'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;`
132			`Z <= to_X01(IO) after 1 ns;`
133			`end;`
134
135			`library ieee;`
136			`use ieee.std_logic_1164.all;`
137
138			`entity BICM3V24 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;`
139			`architecture behav of BICM3V24 is begin`
140			`IO <= to_X01(A) after 1 ns when to_X01(en) = '1' else`
141			`'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;`
142			`Z <= to_X01(IO) after 1 ns;`
143			`end;`
144
145			`library ieee;`
146			`use ieee.std_logic_1164.all;`
147			`entity LVDS_Receiver is port( A, AN : in std_logic; Z : out std_logic); end;`
148			`architecture struct of LVDS_Receiver is`
149			`signal yn : std_ulogic := '0';`
150			`begin`
151			`yn <= to_X01(A) after 1 ns when to_x01(A xor AN) = '1' else yn after 1 ns;`
152			`Z <= yn;`
153			`end;`
154
155			`library ieee;`
156			`use ieee.std_logic_1164.all;`
157			`entity LVDS_Driver is port (A, Vref, HI : in std_logic; Z, ZN : out std_logic ); end;`
158			`architecture struct of LVDS_Driver is begin`
159			`Z <= A after 1 ns;`
160			`ZN <= not A after 1 ns;`
161			`end;`
162
163			`library ieee;`
164			`use ieee.std_logic_1164.all;`
165			`entity LVDS_Biasmodule is port ( RefR : in std_logic; Vref, HI : out std_logic); end;`
166			`architecture struct of LVDS_Biasmodule is begin end;`
167
168			`-- single-port memory`
169
170			`library ieee;`
171			`use ieee.std_logic_1164.all;`
172			`library grlib;`
173			`use grlib.stdlib.all;`
174
175			`entity UMC_SIM_SRAM is`
176			`generic (abits, dbits : integer := 8);`
177			`port (`
178			`a : in std_logic_vector(abits-1 downto 0);`
179			`data : in std_logic_vector(dbits-1 downto 0);`
180			`csn : in std_logic;`
181			`wen : in std_logic;`
182			`oen : in std_logic;`
183			`q : out std_logic_vector(dbits-1 downto 0);`
184			`clk : in std_logic`
185			`);`
186			`end;`
187			`architecture behav of UMC_SIM_SRAM is`
188			`subtype memword is std_logic_vector(dbits-1 downto 0);`
189			`type mem_type is array (0 to 2**abits-1) of memword;`
190			`signal qint : memword;`
191			`begin`
192			`m : process(clk)`
193			`variable mem : mem_type;`
194			`begin`
195			`if rising_edge(clk) then`
196			`qint <= (others => 'X');`
197			`if to_X01(wen) = '0' then mem(conv_integer(a)) := data;`
198			`elsif to_X01(wen) = '1' then qint <= mem(conv_integer(a)); end if;`
199			`end if;`
200			`end process;`
201
202			`q <= qint when to_X01(oen) = '0' else`
203			`(others => 'Z') when to_X01(oen) = '1' else (others => 'X');`
204			`end;`
205
206			`library ieee;`
207			`use ieee.std_logic_1164.all;`
208
209			`entity SRAM_2048wx32b is`
210			`port (`
211			`a : in std_logic_vector(10 downto 0);`
212			`data : in std_logic_vector(31 downto 0);`
213			`csn : in std_logic;`
214			`wen : in std_logic;`
215			`oen : in std_logic;`
216			`q : out std_logic_vector(31 downto 0);`
217			`clk : in std_logic`
218			`);`
219			`end;`
220			`architecture behav of SRAM_2048wx32b is`
221			`component UMC_SIM_SRAM is`
222			`generic (abits, dbits : integer := 8);`
223			`port (`
224			`a : in std_logic_vector(abits-1 downto 0);`
225			`data : in std_logic_vector(dbits-1 downto 0);`
226			`csn : in std_logic;`
227			`wen : in std_logic;`
228			`oen : in std_logic;`
229			`q : out std_logic_vector(dbits-1 downto 0);`
230			`clk : in std_logic`
231			`);`
232			`end component;`
233			`begin`
234			`m : UMC_SIM_SRAM generic map (11, 32) port map (a, data, csn, wen, oen, q, clk);`
235			`end;`
236
237			`library ieee;`
238			`use ieee.std_logic_1164.all;`
239
240			`entity SRAM_1024wx32b is`
241			`port (`
242			`a : in std_logic_vector(9 downto 0);`
243			`data : in std_logic_vector(31 downto 0);`
244			`csn : in std_logic;`
245			`wen : in std_logic;`
246			`oen : in std_logic;`
247			`q : out std_logic_vector(31 downto 0);`
248			`clk : in std_logic`
249			`);`
250			`end;`
251			`architecture behav of SRAM_1024wx32b is`
252			`component UMC_SIM_SRAM is`
253			`generic (abits, dbits : integer := 8);`
254			`port (`
255			`a : in std_logic_vector(abits-1 downto 0);`
256			`data : in std_logic_vector(dbits-1 downto 0);`
257			`csn : in std_logic;`
258			`wen : in std_logic;`
259			`oen : in std_logic;`
260			`q : out std_logic_vector(dbits-1 downto 0);`
261			`clk : in std_logic`
262			`);`
263			`end component;`
264			`begin`
265			`m : UMC_SIM_SRAM generic map (10, 32) port map (a, data, csn, wen, oen, q, clk);`
266			`end;`
267
268			`library ieee;`
269			`use ieee.std_logic_1164.all;`
270
271			`entity SRAM_512wx32b is`
272			`port (`
273			`a : in std_logic_vector(8 downto 0);`
274			`data : in std_logic_vector(31 downto 0);`
275			`csn : in std_logic;`
276			`wen : in std_logic;`
277			`oen : in std_logic;`
278			`q : out std_logic_vector(31 downto 0);`
279			`clk : in std_logic`
280			`);`
281			`end;`
282			`architecture behav of SRAM_512wx32b is`
283			`component UMC_SIM_SRAM is`
284			`generic (abits, dbits : integer := 8);`
285			`port (`
286			`a : in std_logic_vector(abits-1 downto 0);`
287			`data : in std_logic_vector(dbits-1 downto 0);`
288			`csn : in std_logic;`
289			`wen : in std_logic;`
290			`oen : in std_logic;`
291			`q : out std_logic_vector(dbits-1 downto 0);`
292			`clk : in std_logic`
293			`);`
294			`end component;`
295			`begin`
296			`m : UMC_SIM_SRAM generic map (9, 32) port map (a, data, csn, wen, oen, q, clk);`
297			`end;`
298
299			`library ieee;`
300			`use ieee.std_logic_1164.all;`
301
302			`entity SRAM_256wx32b is`
303			`port (`
304			`a : in std_logic_vector(7 downto 0);`
305			`data : in std_logic_vector(31 downto 0);`
306			`csn : in std_logic;`
307			`wen : in std_logic;`
308			`oen : in std_logic;`
309			`q : out std_logic_vector(31 downto 0);`
310			`clk : in std_logic`
311			`);`
312			`end;`
313			`architecture behav of SRAM_256wx32b is`
314			`component UMC_SIM_SRAM is`
315			`generic (abits, dbits : integer := 8);`
316			`port (`
317			`a : in std_logic_vector(abits-1 downto 0);`
318			`data : in std_logic_vector(dbits-1 downto 0);`
319			`csn : in std_logic;`
320			`wen : in std_logic;`
321			`oen : in std_logic;`
322			`q : out std_logic_vector(dbits-1 downto 0);`
323			`clk : in std_logic`
324			`);`
325			`end component;`
326			`begin`
327			`m : UMC_SIM_SRAM generic map (8, 32) port map (a, data, csn, wen, oen, q, clk);`
328			`end;`
329
330			`library ieee;`
331			`use ieee.std_logic_1164.all;`
332
333			`entity SRAM_128wx32b is`
334			`port (`
335			`a : in std_logic_vector(6 downto 0);`
336			`data : in std_logic_vector(31 downto 0);`
337			`csn : in std_logic;`
338			`wen : in std_logic;`
339			`oen : in std_logic;`
340			`q : out std_logic_vector(31 downto 0);`
341			`clk : in std_logic`
342			`);`
343			`end;`
344			`architecture behav of SRAM_128wx32b is`
345			`component UMC_SIM_SRAM is`
346			`generic (abits, dbits : integer := 8);`
347			`port (`
348			`a : in std_logic_vector(abits-1 downto 0);`
349			`data : in std_logic_vector(dbits-1 downto 0);`
350			`csn : in std_logic;`
351			`wen : in std_logic;`
352			`oen : in std_logic;`
353			`q : out std_logic_vector(dbits-1 downto 0);`
354			`clk : in std_logic`
355			`);`
356			`end component;`
357			`begin`
358			`m : UMC_SIM_SRAM generic map (7, 32) port map (a, data, csn, wen, oen, q, clk);`
359			`end;`
360
361			`library ieee;`
362			`use ieee.std_logic_1164.all;`
363
364			`entity SRAM_64wx32b is`
365			`port (`
366			`a : in std_logic_vector(5 downto 0);`
367			`data : in std_logic_vector(31 downto 0);`
368			`csn : in std_logic;`
369			`wen : in std_logic;`
370			`oen : in std_logic;`
371			`q : out std_logic_vector(31 downto 0);`
372			`clk : in std_logic`
373			`);`
374			`end;`
375			`architecture behav of SRAM_64wx32b is`
376			`component UMC_SIM_SRAM is`
377			`generic (abits, dbits : integer := 8);`
378			`port (`
379			`a : in std_logic_vector(abits-1 downto 0);`
380			`data : in std_logic_vector(dbits-1 downto 0);`
381			`csn : in std_logic;`
382			`wen : in std_logic;`
383			`oen : in std_logic;`
384			`q : out std_logic_vector(dbits-1 downto 0);`
385			`clk : in std_logic`
386			`);`
387			`end component;`
388			`begin`
389			`m : UMC_SIM_SRAM generic map (6, 32) port map (a, data, csn, wen, oen, q, clk);`
390			`end;`
391
392			`library ieee;`
393			`use ieee.std_logic_1164.all;`
394
395			`entity SRAM_32wx32b is`
396			`port (`
397			`a : in std_logic_vector(4 downto 0);`
398			`data : in std_logic_vector(31 downto 0);`
399			`csn : in std_logic;`
400			`wen : in std_logic;`
401			`oen : in std_logic;`
402			`q : out std_logic_vector(31 downto 0);`
403			`clk : in std_logic`
404			`);`
405			`end;`
406			`architecture behav of SRAM_32wx32b is`
407			`component UMC_SIM_SRAM is`
408			`generic (abits, dbits : integer := 8);`
409			`port (`
410			`a : in std_logic_vector(abits-1 downto 0);`
411			`data : in std_logic_vector(dbits-1 downto 0);`
412			`csn : in std_logic;`
413			`wen : in std_logic;`
414			`oen : in std_logic;`
415			`q : out std_logic_vector(dbits-1 downto 0);`
416			`clk : in std_logic`
417			`);`
418			`end component;`
419			`begin`
420			`m : UMC_SIM_SRAM generic map (5, 32) port map (a, data, csn, wen, oen, q, clk);`
421			`end;`
422
423			`library ieee;`
424			`use ieee.std_logic_1164.all;`
425
426			`entity SRAM_2048wx40b is`
427			`port (`
428			`a : in std_logic_vector(10 downto 0);`
429			`data : in std_logic_vector(39 downto 0);`
430			`csn : in std_logic;`
431			`wen : in std_logic;`
432			`oen : in std_logic;`
433			`q : out std_logic_vector(39 downto 0);`
434			`clk : in std_logic`
435			`);`
436			`end;`
437			`architecture behav of SRAM_2048wx40b is`
438			`component UMC_SIM_SRAM is`
439			`generic (abits, dbits : integer := 8);`
440			`port (`
441			`a : in std_logic_vector(abits-1 downto 0);`
442			`data : in std_logic_vector(dbits-1 downto 0);`
443			`csn : in std_logic;`
444			`wen : in std_logic;`
445			`oen : in std_logic;`
446			`q : out std_logic_vector(dbits-1 downto 0);`
447			`clk : in std_logic`
448			`);`
449			`end component;`
450			`begin`
451			`m : UMC_SIM_SRAM generic map (11, 40) port map (a, data, csn, wen, oen, q, clk);`
452			`end;`
453
454			`library ieee;`
455			`use ieee.std_logic_1164.all;`
456
457			`entity SRAM_1024wx40b is`
458			`port (`
459			`a : in std_logic_vector(9 downto 0);`
460			`data : in std_logic_vector(39 downto 0);`
461			`csn : in std_logic;`
462			`wen : in std_logic;`
463			`oen : in std_logic;`
464			`q : out std_logic_vector(39 downto 0);`
465			`clk : in std_logic`
466			`);`
467			`end;`
468			`architecture behav of SRAM_1024wx40b is`
469			`component UMC_SIM_SRAM is`
470			`generic (abits, dbits : integer := 8);`
471			`port (`
472			`a : in std_logic_vector(abits-1 downto 0);`
473			`data : in std_logic_vector(dbits-1 downto 0);`
474			`csn : in std_logic;`
475			`wen : in std_logic;`
476			`oen : in std_logic;`
477			`q : out std_logic_vector(dbits-1 downto 0);`
478			`clk : in std_logic`
479			`);`
480			`end component;`
481			`begin`
482			`m : UMC_SIM_SRAM generic map (10, 40) port map (a, data, csn, wen, oen, q, clk);`
483			`end;`
484
485			`library ieee;`
486			`use ieee.std_logic_1164.all;`
487
488			`entity SRAM_512wx40b is`
489			`port (`
490			`a : in std_logic_vector(8 downto 0);`
491			`data : in std_logic_vector(39 downto 0);`
492			`csn : in std_logic;`
493			`wen : in std_logic;`
494			`oen : in std_logic;`
495			`q : out std_logic_vector(39 downto 0);`
496			`clk : in std_logic`
497			`);`
498			`end;`
499			`architecture behav of SRAM_512wx40b is`
500			`component UMC_SIM_SRAM is`
501			`generic (abits, dbits : integer := 8);`
502			`port (`
503			`a : in std_logic_vector(abits-1 downto 0);`
504			`data : in std_logic_vector(dbits-1 downto 0);`
505			`csn : in std_logic;`
506			`wen : in std_logic;`
507			`oen : in std_logic;`
508			`q : out std_logic_vector(dbits-1 downto 0);`
509			`clk : in std_logic`
510			`);`
511			`end component;`
512			`begin`
513			`m : UMC_SIM_SRAM generic map (9, 40) port map (a, data, csn, wen, oen, q, clk);`
514			`end;`
515
516			`library ieee;`
517			`use ieee.std_logic_1164.all;`
518
519			`entity SRAM_256wx40b is`
520			`port (`
521			`a : in std_logic_vector(7 downto 0);`
522			`data : in std_logic_vector(39 downto 0);`
523			`csn : in std_logic;`
524			`wen : in std_logic;`
525			`oen : in std_logic;`
526			`q : out std_logic_vector(39 downto 0);`
527			`clk : in std_logic`
528			`);`
529			`end;`
530			`architecture behav of SRAM_256wx40b is`
531			`component UMC_SIM_SRAM is`
532			`generic (abits, dbits : integer := 8);`
533			`port (`
534			`a : in std_logic_vector(abits-1 downto 0);`
535			`data : in std_logic_vector(dbits-1 downto 0);`
536			`csn : in std_logic;`
537			`wen : in std_logic;`
538			`oen : in std_logic;`
539			`q : out std_logic_vector(dbits-1 downto 0);`
540			`clk : in std_logic`
541			`);`
542			`end component;`
543			`begin`
544			`m : UMC_SIM_SRAM generic map (8, 40) port map (a, data, csn, wen, oen, q, clk);`
545			`end;`
546
547			`library ieee;`
548			`use ieee.std_logic_1164.all;`
549
550			`entity SRAM_128wx40b is`
551			`port (`
552			`a : in std_logic_vector(6 downto 0);`
553			`data : in std_logic_vector(39 downto 0);`
554			`csn : in std_logic;`
555			`wen : in std_logic;`
556			`oen : in std_logic;`
557			`q : out std_logic_vector(39 downto 0);`
558			`clk : in std_logic`
559			`);`
560			`end;`
561			`architecture behav of SRAM_128wx40b is`
562			`component UMC_SIM_SRAM is`
563			`generic (abits, dbits : integer := 8);`
564			`port (`
565			`a : in std_logic_vector(abits-1 downto 0);`
566			`data : in std_logic_vector(dbits-1 downto 0);`
567			`csn : in std_logic;`
568			`wen : in std_logic;`
569			`oen : in std_logic;`
570			`q : out std_logic_vector(dbits-1 downto 0);`
571			`clk : in std_logic`
572			`);`
573			`end component;`
574			`begin`
575			`m : UMC_SIM_SRAM generic map (7, 40) port map (a, data, csn, wen, oen, q, clk);`
576			`end;`
577
578			`library ieee;`
579			`use ieee.std_logic_1164.all;`
580
581			`entity SRAM_64wx40b is`
582			`port (`
583			`a : in std_logic_vector(5 downto 0);`
584			`data : in std_logic_vector(39 downto 0);`
585			`csn : in std_logic;`
586			`wen : in std_logic;`
587			`oen : in std_logic;`
588			`q : out std_logic_vector(39 downto 0);`
589			`clk : in std_logic`
590			`);`
591			`end;`
592			`architecture behav of SRAM_64wx40b is`
593			`component UMC_SIM_SRAM is`
594			`generic (abits, dbits : integer := 8);`
595			`port (`
596			`a : in std_logic_vector(abits-1 downto 0);`
597			`data : in std_logic_vector(dbits-1 downto 0);`
598			`csn : in std_logic;`
599			`wen : in std_logic;`
600			`oen : in std_logic;`
601			`q : out std_logic_vector(dbits-1 downto 0);`
602			`clk : in std_logic`
603			`);`
604			`end component;`
605			`begin`
606			`m : UMC_SIM_SRAM generic map (6, 40) port map (a, data, csn, wen, oen, q, clk);`
607			`end;`
608
609			`library ieee;`
610			`use ieee.std_logic_1164.all;`
611
612			`entity SRAM_32wx40b is`
613			`port (`
614			`a : in std_logic_vector(4 downto 0);`
615			`data : in std_logic_vector(39 downto 0);`
616			`csn : in std_logic;`
617			`wen : in std_logic;`
618			`oen : in std_logic;`
619			`q : out std_logic_vector(39 downto 0);`
620			`clk : in std_logic`
621			`);`
622			`end;`
623			`architecture behav of SRAM_32wx40b is`
624			`component UMC_SIM_SRAM is`
625			`generic (abits, dbits : integer := 8);`
626			`port (`
627			`a : in std_logic_vector(abits-1 downto 0);`
628			`data : in std_logic_vector(dbits-1 downto 0);`
629			`csn : in std_logic;`
630			`wen : in std_logic;`
631			`oen : in std_logic;`
632			`q : out std_logic_vector(dbits-1 downto 0);`
633			`clk : in std_logic`
634			`);`
635			`end component;`
636			`begin`
637			`m : UMC_SIM_SRAM generic map (5, 40) port map (a, data, csn, wen, oen, q, clk);`
638			`end;`
639
640			`-- pragma translate_on`