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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [virage/] [vcomponents/] [virage_vcomponents.vhd] - Blame information for rev 2

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1 2 dimamali 
------------------------------------------------------------------------------
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--  This file is a part of the GRLIB VHDL IP LIBRARY
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--  Copyright (C) 2003, Gaisler Research
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--
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--  This program is free software; you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation; either version 2 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program; if not, write to the Free Software
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--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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-----------------------------------------------------------------------------
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-- Package:     virage_vcomponents
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-- File:        virage_vcomponents.vhd
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-- Author:      Jiri Gaisler, Gaisler Research
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-- Description: Simple simulation models for ACTEL RAM and pads
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package virage_vcomponents is
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  component hdss1_128x32cm4sw0b
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  port (
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    addr, taddr : in std_logic_vector(6 downto 0);
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    clk         : in std_logic;
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    di, tdi     : in std_logic_vector(31 downto 0);
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    do          : out std_logic_vector(31 downto 0);
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    me, oe, we, tme, twe, awt, biste, toe : in std_logic
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  );
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  end component;
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  component hdss1_256x32cm4sw0b
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  port (
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    addr, taddr : in std_logic_vector(7 downto 0);
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    clk         : in std_logic;
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    di, tdi     : in std_logic_vector(31 downto 0);
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    do          : out std_logic_vector(31 downto 0);
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    me, oe, we, tme, twe, awt, biste, toe : in std_logic
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  );
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  end component;
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  component hdss1_512x32cm4sw0b
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  port (
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    addr, taddr : in std_logic_vector(8 downto 0);
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    clk         : in std_logic;
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    di, tdi     : in std_logic_vector(31 downto 0);
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    do          : out std_logic_vector(31 downto 0);
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    me, oe, we, tme, twe, awt, biste, toe : in std_logic
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  );
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  end component;
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  component hdss1_1024x32cm4sw0b
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  port (
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    addr, taddr : in std_logic_vector(9 downto 0);
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    clk         : in std_logic;
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    di, tdi     : in std_logic_vector(31 downto 0);
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    do          : out std_logic_vector(31 downto 0);
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    me, oe, we, tme, twe, awt, biste, toe : in std_logic
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  );
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  end component;
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  component hdss1_2048x32cm8sw0b
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  port (
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    addr, taddr : in std_logic_vector(10 downto 0);
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    clk         : in std_logic;
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    di, tdi     : in std_logic_vector(31 downto 0);
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    do          : out std_logic_vector(31 downto 0);
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    me, oe, we, tme, twe, awt, biste, toe : in std_logic
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  );
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  end component;
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  component hdss1_4096x36cm8sw0b is
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  port (
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    addr, taddr : in std_logic_vector(11 downto 0);
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    clk         : in std_logic;
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    di, tdi     : in std_logic_vector(35 downto 0);
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    do          : out std_logic_vector(35 downto 0);
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    me, oe, we, tme, twe, awt, biste, toe : in std_logic
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  );
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  end component;
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  component hdss1_16384x8cm16sw0 is
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  port (
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    addr        : in std_logic_vector(13 downto 0);
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    clk         : in std_logic;
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    di          : in std_logic_vector(7 downto 0);
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    do          : out std_logic_vector(7 downto 0);
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    me, oe, we  : in std_logic
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  );
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  end component;
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  component rfss2_136x32cm2sw0b
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  port (
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    addra, taddra : in std_logic_vector(7 downto 0);
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    addrb, taddrb : in std_logic_vector(7 downto 0);
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    clka, clkb    : in std_logic;
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    dia, tdia     : in std_logic_vector(31 downto 0);
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    dob      : out std_logic_vector(31 downto 0);
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    mea, wea, tmea, twea, bistea : in std_logic;
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    meb, oeb, tmeb,  awtb, bisteb, toeb : in std_logic
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  );
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  end component;
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  component rfss2_168x32cm2sw0b
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  port (
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    addra, taddra : in std_logic_vector(7 downto 0);
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    addrb, taddrb : in std_logic_vector(7 downto 0);
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    clka, clkb    : in std_logic;
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    dia, tdia     : in std_logic_vector(31 downto 0);
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    dob      : out std_logic_vector(31 downto 0);
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    mea, wea, tmea, twea, bistea : in std_logic;
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    meb, oeb, tmeb,  awtb, bisteb, toeb : in std_logic
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  );
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  end component;
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  component hdss2_64x32cm4sw0b
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  port (
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    addra, taddra : in std_logic_vector(5 downto 0);
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    addrb, taddrb : in std_logic_vector(5 downto 0);
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    clka, clkb    : in std_logic;
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    dia, tdia     : in std_logic_vector(31 downto 0);
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    dib, tdib     : in std_logic_vector(31 downto 0);
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    doa, dob      : out std_logic_vector(31 downto 0);
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    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
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    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
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  );
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  end component;
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  component hdss2_128x32cm4sw0b
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  port (
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    addra, taddra : in std_logic_vector(6 downto 0);
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    addrb, taddrb : in std_logic_vector(6 downto 0);
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    clka, clkb    : in std_logic;
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    dia, tdia     : in std_logic_vector(31 downto 0);
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    dib, tdib     : in std_logic_vector(31 downto 0);
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    doa, dob      : out std_logic_vector(31 downto 0);
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    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
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    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
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  );
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  end component;
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  component hdss2_256x32cm4sw0b
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  port (
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    addra, taddra : in std_logic_vector(7 downto 0);
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    addrb, taddrb : in std_logic_vector(7 downto 0);
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    clka, clkb    : in std_logic;
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    dia, tdia     : in std_logic_vector(31 downto 0);
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    dib, tdib     : in std_logic_vector(31 downto 0);
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    doa, dob      : out std_logic_vector(31 downto 0);
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    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
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    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
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  );
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  end component;
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  component hdss2_512x32cm4sw0b
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  port (
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    addra, taddra : in std_logic_vector(8 downto 0);
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    addrb, taddrb : in std_logic_vector(8 downto 0);
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    clka, clkb    : in std_logic;
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    dia, tdia     : in std_logic_vector(31 downto 0);
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    dib, tdib     : in std_logic_vector(31 downto 0);
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    doa, dob      : out std_logic_vector(31 downto 0);
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    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
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    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
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  );
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  end component;
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  component hdss2_512x38cm4sw0b
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  port (
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    addra, taddra : in std_logic_vector(8 downto 0);
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    addrb, taddrb : in std_logic_vector(8 downto 0);
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    clka, clkb    : in std_logic;
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    dia, tdia     : in std_logic_vector(37 downto 0);
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    dib, tdib     : in std_logic_vector(37 downto 0);
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    doa, dob      : out std_logic_vector(37 downto 0);
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    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
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    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
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  );
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  end component;
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end;

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