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dimamali |
library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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-- pragma translate_off
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-- pragma translate_on
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library techmap;
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use techmap.gencomp.all;
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------------------------------------------------------------------
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-- CYCLONEIII DDR PHY --------------------------------------------
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------------------------------------------------------------------
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entity cycloneiii_ddr_phy is
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2; rskew : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- system clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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addr : in std_logic_vector (13 downto 0); -- data mask
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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oen : in std_ulogic;
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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rasn : in std_ulogic;
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casn : in std_ulogic;
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wen : in std_ulogic;
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csn : in std_logic_vector(1 downto 0);
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cke : in std_logic_vector(1 downto 0)
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);
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end;
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architecture rtl of cycloneiii_ddr_phy is
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component apll IS
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generic (
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freq : integer := 200;
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mult : integer := 8;
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div : integer := 5;
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rskew : integer := 0
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);
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PORT
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(
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areset : IN STD_LOGIC := '0';
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inclk0 : IN STD_LOGIC := '0';
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phasestep : IN STD_LOGIC := '0';
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phaseupdown : IN STD_LOGIC := '0';
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scanclk : IN STD_LOGIC := '1';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC ;
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c3 : OUT STD_LOGIC ;
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c4 : OUT STD_LOGIC ;
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locked : OUT STD_LOGIC;
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phasedone : out std_logic
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);
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END component;
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component aclkout is
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port(
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clk : in std_logic;
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ddr_clk : out std_logic;
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ddr_clkn: out std_logic
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);
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end component;
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component actrlout is
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generic(
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power_up : string := "high"
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);
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port(
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clk : in std_logic;
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i : in std_logic;
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o : out std_logic
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);
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end component;
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component adqsout is
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port(
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clk : in std_logic; -- clk90
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dqs : in std_logic;
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dqs_oe : in std_logic;
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dqs_oct : in std_logic; -- gnd = disable
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dqs_pad : out std_logic; -- DQS pad
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dqsn_pad : out std_logic -- DQSN pad
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);
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end component;
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component adqsin is
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port(
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dqs_pad : in std_logic; -- DQS pad
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dqsn_pad : in std_logic; -- DQSN pad
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dqs : out std_logic
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);
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end component;
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component admout is
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port(
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clk : in std_logic; -- clk0
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dm_h : in std_logic;
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dm_l : in std_logic;
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dm_pad : out std_logic -- DQ pad
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);
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end component;
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component adqin is
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port(
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clk : in std_logic;
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dq_pad : in std_logic; -- DQ pad
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dq_h : out std_logic;
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dq_l : out std_logic;
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config_clk : in std_logic;
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config_clken : in std_logic;
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config_datain : in std_logic;
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config_update : in std_logic
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);
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end component;
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component adqout is
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port(
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clk : in std_logic; -- clk0
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clk_oct : in std_logic; -- clk90
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dq_h : in std_logic;
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dq_l : in std_logic;
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dq_oe : in std_logic;
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dq_oct : in std_logic; -- gnd = disable
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dq_pad : out std_logic -- DQ pad
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);
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end component;
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signal reset : std_logic;
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signal vcc, gnd, oe : std_ulogic;
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signal locked, vlockl, lockl : std_ulogic;
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signal clk0r, clk90r, clk180r, clk270r, rclk : std_ulogic;
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signal ckel, ckel2 : std_logic_vector(1 downto 0);
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signal dqsin, dqsin_reg : std_logic_vector (7 downto 0); -- ddr dqs
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signal dqsn : std_logic_vector(dbits/8-1 downto 0);
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signal dqsoenr : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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signal delayrst : std_logic_vector(3 downto 0);
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signal phasedone : std_logic;
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signal dqinl,dqinl2,dqinl3 : std_logic_vector (dbits-1 downto 0); -- ddr data
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signal dqsin_tmp : std_logic;
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type phy_r_type is record
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delay : std_logic_vector(3 downto 0);
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count : std_logic_vector(3 downto 0);
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update : std_logic;
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sdata : std_logic;
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enable : std_logic;
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update_delay : std_logic;
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end record;
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type phy_r_type_arr is array (7 downto 0) of phy_r_type;
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signal r,rin : phy_r_type_arr;
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signal rp : std_logic_vector(3 downto 0);
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constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
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attribute keep : boolean;
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attribute syn_keep : boolean;
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attribute syn_preserve : boolean;
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attribute syn_keep of dqsn : signal is true;
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attribute syn_preserve of dqsn : signal is true;
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attribute syn_keep of dqsoenr : signal is true;
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attribute syn_preserve of dqsoenr : signal is true;
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attribute syn_keep of dqsin_reg : signal is true;
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attribute syn_preserve of dqsin_reg : signal is true;
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begin
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-----------------------------------------------------------------------------------
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-- Clock generation
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-----------------------------------------------------------------------------------
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oe <= not oen;
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vcc <= '1'; gnd <= '0';
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reset <= not rst;
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-- Optional DDR clock multiplication
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pll0 : apll
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generic map(
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freq => MHz,
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mult => clk_mul,
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div => clk_div,
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rskew => rskew
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)
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port map(
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areset => reset,
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inclk0 => clk,
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phasestep => rp(1),
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phaseupdown => rp(3),
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scanclk => clk0r,
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c0 => clk0r,
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c1 => clk90r,
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c2 => open, --clk180r,
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c3 => open, --clk270r,
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c4 => rclk,
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locked => lockl,
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phasedone => phasedone
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);
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clk180r <= not clk0r;
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clk270r <= not clk90r;
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clkout <= clk0r;
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-----------------------------------------------------------------------------------
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-- Lock delay
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-----------------------------------------------------------------------------------
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rdel : if rstdelay /= 0 generate
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rcnt : process (clk0r)
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variable cnt : std_logic_vector(15 downto 0);
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variable vlock, co : std_ulogic;
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begin
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if rising_edge(clk0r) then
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co := cnt(15);
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vlockl <= vlock;
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if lockl = '0' then
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cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
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-- cnt(0) := dqsin_reg(7) or dqsin_reg(6) or dqsin_reg(5) or dqsin_reg(4) or -- dummy use of dqsin
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-- dqsin_reg(3) or dqsin_reg(2) or dqsin_reg(1) or dqsin_reg(0);
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else
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if vlock = '0' then
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cnt := cnt -1; vlock := cnt(15) and not co;
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end if;
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end if;
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end if;
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if lockl = '0' then
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vlock := '0';
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end if;
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end process;
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end generate;
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locked <= lockl when rstdelay = 0 else vlockl;
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lock <= locked;
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-----------------------------------------------------------------------------------
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-- Generate external DDR clock
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-----------------------------------------------------------------------------------
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ddrclocks : for i in 0 to 2 generate
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ddrclk_pad : aclkout port map(clk => clk90r, ddr_clk => ddr_clk(i), ddr_clkn => ddr_clkb(i));
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end generate;
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-----------------------------------------------------------------------------------
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-- DDR single-edge control signals
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-----------------------------------------------------------------------------------
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-- CSN and CKE
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ddrbanks : for i in 0 to 1 generate
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ddr_csn_pad : actrlout port map(clk =>clk180r , i => csn(i), o => ddr_csb(i));
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ckel(i) <= cke(i) and locked;
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ddr_cke_pad : actrlout generic map(power_up => "low")
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port map(clk =>clk0r , i => ckel(i), o => ddr_cke(i));
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end generate;
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-- RAS
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ddr_rasn_pad : actrlout port map(clk =>clk180r , i => rasn, o => ddr_rasb);
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-- CAS
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ddr_casn_pad : actrlout port map(clk =>clk180r , i => casn, o => ddr_casb);
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-- WEN
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ddr_wen_pad : actrlout port map(clk =>clk180r , i => wen, o => ddr_web);
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-- BA
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bagen : for i in 0 to 1 generate
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ddr_ba_pad : actrlout port map(clk =>clk180r , i => ba(i), o => ddr_ba(i));
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end generate;
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-- ADDRESS
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dagen : for i in 0 to 13 generate
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ddr_ad_pad : actrlout port map(clk =>clk180r , i => addr(i), o => ddr_ad(i));
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end generate;
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-----------------------------------------------------------------------------------
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-- DQS generation
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-----------------------------------------------------------------------------------
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dqsgen : for i in 0 to dbits/8-1 generate
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doen : process(clk180r)
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begin if rising_edge(clk180r) then dqsoenr(i) <= dqsoen; end if; end process;
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dsqreg : process(clk180r)
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begin if rising_edge(clk180r) then dqsn(i) <= oe; end if; end process;
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dqs_out_pad : adqsout port map(
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clk => clk90r, -- clk90
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dqs => dqsn(i),
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dqs_oe => dqsoenr(i),
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dqs_oct => gnd, -- gnd = disable
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dqs_pad => ddr_dqs(i) -- DQS pad
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);
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-- dqs_in_pad : adqsin port map(
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-- dqs_pad => ddr_dqs(i),
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-- dqsn_pad => ddr_dqsn(i),
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-- dqs => dqsin(i)
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-- );
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-- -- Dummy procces to sample dqsin
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-- process(clk0r)
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-- begin
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-- if rising_edge(clk0r) then
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-- dqsin_reg(i) <= dqsin(i);
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-- end if;
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-- end process;
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end generate;
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-----------------------------------------------------------------------------------
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-- DQM generation
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-----------------------------------------------------------------------------------
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dmgen : for i in 0 to dbits/8-1 generate
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ddr_dm_pad : admout port map(
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clk => clk0r, -- clk0
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dm_h => dm(i+dbits/8),
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dm_l => dm(i),
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dm_pad => ddr_dm(i) -- DQ pad
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);
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end generate;
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-----------------------------------------------------------------------------------
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-- Data bus
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-----------------------------------------------------------------------------------
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ddgen : for i in 0 to dbits-1 generate
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-- DQ Input
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dq_in_pad : adqin port map(
|
353 |
|
|
clk => rclk,--clk0r,
|
354 |
|
|
dq_pad => ddr_dq(i), -- DQ pad
|
355 |
|
|
dq_h => dqin(i), --dqinl(i),
|
356 |
|
|
dq_l => dqin(i+dbits),--dqin(i),
|
357 |
|
|
config_clk => clk0r,
|
358 |
|
|
config_clken => r(i/8).enable,--io_config_clkena,
|
359 |
|
|
config_datain => r(i/8).sdata,--io_config_datain,
|
360 |
|
|
config_update => r(i/8).update_delay--io_config_update
|
361 |
|
|
);
|
362 |
|
|
--dinq1 : process (clk0r)
|
363 |
|
|
--begin if rising_edge(clk0r) then dqin(i+dbits) <= dqinl(i); end if; end process;
|
364 |
|
|
|
365 |
|
|
-- DQ Output
|
366 |
|
|
dq_out_pad : adqout port map(
|
367 |
|
|
clk => clk0r, -- clk0
|
368 |
|
|
clk_oct => clk90r, -- clk90
|
369 |
|
|
dq_h => dqout(i+dbits),
|
370 |
|
|
dq_l => dqout(i),
|
371 |
|
|
dq_oe => oen,
|
372 |
|
|
dq_oct => gnd, -- gnd = disable
|
373 |
|
|
dq_pad => ddr_dq(i) -- DQ pad
|
374 |
|
|
);
|
375 |
|
|
end generate;
|
376 |
|
|
|
377 |
|
|
-----------------------------------------------------------------------------------
|
378 |
|
|
-- DEBUG
|
379 |
|
|
-----------------------------------------------------------------------------------
|
380 |
|
|
--debug(66 downto 59) <= dqsin_reg(7 downto 0);
|
381 |
|
|
--debug(58 downto 27) <= dqinl3(15 downto 0) & dqinl2(15 downto 0);
|
382 |
|
|
--debug(26 downto 25) <= dm(1 downto 0);
|
383 |
|
|
--debug(24 downto 11) <= addr(13 downto 0);
|
384 |
|
|
--debug(10) <= wen;
|
385 |
|
|
--debug(9) <= casn;
|
386 |
|
|
--debug(8) <= rasn;
|
387 |
|
|
----debug(7 downto 0);
|
388 |
|
|
--debug(3) <= rasn and not wen and not casn; -- write
|
389 |
|
|
--debug(2) <= rasn and wen and not casn; -- read
|
390 |
|
|
--debug(1) <= not rasn and wen and casn; -- act
|
391 |
|
|
--debug(0) <= clk0r;
|
392 |
|
|
|
393 |
|
|
-----------------------------------------------------------------------------------
|
394 |
|
|
-- Delay control
|
395 |
|
|
-----------------------------------------------------------------------------------
|
396 |
|
|
|
397 |
|
|
-- delay_control : for i in 0 to dbits/8-1 generate
|
398 |
|
|
|
399 |
|
|
-- process(r(i),cal_en(i), cal_inc(i), delayrst(3))
|
400 |
|
|
-- variable v : phy_r_type;
|
401 |
|
|
-- variable data : std_logic_vector(0 to 3);
|
402 |
|
|
-- begin
|
403 |
|
|
-- v := r(i);
|
404 |
|
|
-- data := r(i).delay;
|
405 |
|
|
-- v.update_delay := '0';
|
406 |
|
|
-- if cal_en(i) = '1' then
|
407 |
|
|
-- if cal_inc(i) = '1' then
|
408 |
|
|
-- v.delay := r(i).delay + 1;
|
409 |
|
|
-- else
|
410 |
|
|
-- v.delay := r(i).delay - 1;
|
411 |
|
|
-- end if;
|
412 |
|
|
-- v.update := '1';
|
413 |
|
|
-- v.count := (others => '0');
|
414 |
|
|
-- end if;
|
415 |
|
|
--
|
416 |
|
|
-- if r(i).update = '1' then
|
417 |
|
|
-- v.enable := '1';
|
418 |
|
|
-- v.sdata := '0';
|
419 |
|
|
--
|
420 |
|
|
-- if r(i).count <= "1011" then
|
421 |
|
|
-- v.count := r(i).count + 1;
|
422 |
|
|
-- end if;
|
423 |
|
|
--
|
424 |
|
|
-- if r(i).count <= "0011" then
|
425 |
|
|
-- v.sdata := data(conv_integer(r(i).count));
|
426 |
|
|
-- end if;
|
427 |
|
|
--
|
428 |
|
|
-- if r(i).count = "1011" then
|
429 |
|
|
-- v.update_delay := '1';
|
430 |
|
|
-- v.enable := '0';
|
431 |
|
|
-- v.update := '0';
|
432 |
|
|
-- end if;
|
433 |
|
|
-- end if;
|
434 |
|
|
--
|
435 |
|
|
-- if delayrst(3) = '0' then
|
436 |
|
|
-- v.delay := (others => '0');
|
437 |
|
|
-- v.count := (others => '0');
|
438 |
|
|
-- v.update := '0';
|
439 |
|
|
-- v.enable := '0';
|
440 |
|
|
-- end if;
|
441 |
|
|
--
|
442 |
|
|
-- rin(i) <= v;
|
443 |
|
|
-- end process;
|
444 |
|
|
--
|
445 |
|
|
-- end generate;
|
446 |
|
|
|
447 |
|
|
-- process(clk0r)
|
448 |
|
|
-- begin
|
449 |
|
|
-- if locked = '0' then
|
450 |
|
|
-- delayrst <= (others => '0');
|
451 |
|
|
-- elsif rising_edge(clk0r) then
|
452 |
|
|
-- delayrst <= delayrst(2 downto 0) & '1';
|
453 |
|
|
-- r <= rin;
|
454 |
|
|
-- -- PLL phase config
|
455 |
|
|
-- rp(0) <= cal_pll(0); rp(1) <= cal_pll(0) or rp(0);
|
456 |
|
|
-- rp(2) <= cal_pll(1); rp(3) <= cal_pll(1) or rp(2);
|
457 |
|
|
-- end if;
|
458 |
|
|
-- end process;
|
459 |
|
|
|
460 |
|
|
end;
|
461 |
|
|
|
462 |
|
|
|
463 |
|
|
|