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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [ec/] [memory_ec.vhd] - Blame information for rev 2

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1 2 dimamali 
------------------------------------------------------------------------------
2 
--  This file is a part of the GRLIB VHDL IP LIBRARY
3 
--  Copyright (C) 2003, Gaisler Research
4 
--
5 
--  This program is free software; you can redistribute it and/or modify
6 
--  it under the terms of the GNU General Public License as published by
7 
--  the Free Software Foundation; either version 2 of the License, or
8 
--  (at your option) any later version.
9 
--
10 
--  This program is distributed in the hope that it will be useful,
11 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
--  GNU General Public License for more details.
14 
--
15 
--  You should have received a copy of the GNU General Public License
16 
--  along with this program; if not, write to the Free Software
17 
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18 
-----------------------------------------------------------------------------
19 
-- Entity:  various
20 
-- File:    mem_ec_gen.vhd
21 
-- Author:  Jiri Gaisler - Gaisler Research
22 
-- Description: Memory generators for Lattice XP/EC/ECP RAM blocks
23 
------------------------------------------------------------------------------
24 
 
25 
library ieee;
26 
use ieee.std_logic_1164.all;
27 
-- pragma translate_off
28 
library ec;
29 
use ec.dp8ka;
30 
-- pragma translate_on
31 
 
32 
entity EC_RAMB8_S1_S1 is
33 
    port (
34 
        DataInA: in  std_logic_vector(0 downto 0);
35 
        DataInB: in  std_logic_vector(0 downto 0);
36 
        AddressA: in  std_logic_vector(12 downto 0);
37 
        AddressB: in  std_logic_vector(12 downto 0);
38 
        ClockA: in  std_logic;
39 
        ClockB: in  std_logic;
40 
        ClockEnA: in  std_logic;
41 
        ClockEnB: in  std_logic;
42 
        WrA: in  std_logic;
43 
        WrB: in  std_logic;
44 
        QA: out  std_logic_vector(0 downto 0);
45 
        QB: out  std_logic_vector(0 downto 0));
46 
end;
47 
 
48 
architecture Structure of EC_RAMB8_S1_S1 is
49 
  COMPONENT dp8ka
50 
  GENERIC(
51 
        DATA_WIDTH_A : in Integer := 18;
52 
        DATA_WIDTH_B : in Integer := 18;
53 
        REGMODE_A    : String  := "NOREG";
54 
        REGMODE_B    : String  := "NOREG";
55 
        RESETMODE    : String  := "ASYNC";
56 
        CSDECODE_A   : String  := "000";
57 
        CSDECODE_B   : String  := "000";
58 
        WRITEMODE_A  : String  := "NORMAL";
59 
        WRITEMODE_B  : String  := "NORMAL";
60 
        GSR : String  := "ENABLED";
61 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
62 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
63 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
64 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
65 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
66 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
67 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
68 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
69 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
70 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
71 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
72 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
73 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
74 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
75 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
76 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
77 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
78 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
79 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
80 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
81 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
82 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
83 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
84 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
85 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
86 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
87 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
88 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
89 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
90 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
91 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
92 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
93 
  );
94 
  PORT(
95 
        dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8            : in std_logic := 'X';
96 
        dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17    : in std_logic := 'X';
97 
        ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8            : in std_logic := 'X';
98 
        ada9, ada10, ada11, ada12                                       : in std_logic := 'X';
99 
        cea, clka, wea, csa0, csa1, csa2, rsta                         : in std_logic := 'X';
100 
        dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8            : in std_logic := 'X';
101 
        dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17    : in std_logic := 'X';
102 
        adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8            : in std_logic := 'X';
103 
        adb9, adb10, adb11, adb12                                       : in std_logic := 'X';
104 
        ceb, clkb, web, csb0, csb1, csb2, rstb                         : in std_logic := 'X';
105 
 
106 
        doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8            : out std_logic := 'X';
107 
        doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17    : out std_logic := 'X';
108 
        dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8            : out std_logic := 'X';
109 
        dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17    : out std_logic := 'X'
110 
  );
111 
  END COMPONENT;
112 
 
113 
signal vcc, gnd : std_ulogic;
114 
begin
115 
  vcc <= '1'; gnd <= '0';
116 
  u0: DP8KA
117 
        generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
118 
          WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
119 
          GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
120 
          REGMODE_A=>"NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 1)
121 
        port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
122 
            CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
123 
            CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
124 
            CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
125 
            DIA0=>gnd, DIA1=>gnd, DIA2=>gnd,
126 
            DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
127 
            DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
128 
            DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(0),
129 
            DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
130 
            DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
131 
            ADA0=>AddressA(0), ADA1=>AddressA(1), ADA2=>AddressA(2),
132 
            ADA3=>AddressA(3), ADA4=>AddressA(4), ADA5=>AddressA(5),
133 
            ADA6=>AddressA(6), ADA7=>AddressA(7), ADA8=>AddressA(8),
134 
            ADA9=>AddressA(9), ADA10=>AddressA(10), ADA11=>AddressA(11),
135 
            ADA12=>AddressA(12), DIB0=>gnd, DIB1=>gnd,
136 
            DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
137 
            DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
138 
            DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
139 
            DIB11=>DataInB(0), DIB12=>gnd, DIB13=>gnd,
140 
            DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
141 
            DIB17=>gnd, ADB0=>AddressB(0), ADB1=>AddressB(1),
142 
            ADB2=>AddressB(2), ADB3=>AddressB(3), ADB4=>AddressB(4),
143 
            ADB5=>AddressB(5), ADB6=>AddressB(6), ADB7=>AddressB(7),
144 
            ADB8=>AddressB(8), ADB9=>AddressB(9), ADB10=>AddressB(10),
145 
            ADB11=>AddressB(11), ADB12=>AddressB(12), DOA0=>QA(0),
146 
            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
147 
            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
148 
            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
149 
            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
150 
            DOA17=>open, DOB0=>QB(0), DOB1=>open, DOB2=>open,
151 
            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
152 
            DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
153 
            DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
154 
            DOB15=>open, DOB16=>open, DOB17=>open);
155 
end;
156 
 
157 
library ieee;
158 
use ieee.std_logic_1164.all;
159 
-- pragma translate_off
160 
library ec;
161 
use ec.dp8ka;
162 
-- pragma translate_on
163 
 
164 
entity EC_RAMB8_S2_S2 is
165 
    port (
166 
        DataInA: in  std_logic_vector(1 downto 0);
167 
        DataInB: in  std_logic_vector(1 downto 0);
168 
        AddressA: in  std_logic_vector(11 downto 0);
169 
        AddressB: in  std_logic_vector(11 downto 0);
170 
        ClockA: in  std_logic;
171 
        ClockB: in  std_logic;
172 
        ClockEnA: in  std_logic;
173 
        ClockEnB: in  std_logic;
174 
        WrA: in  std_logic;
175 
        WrB: in  std_logic;
176 
        QA: out  std_logic_vector(1 downto 0);
177 
        QB: out  std_logic_vector(1 downto 0));
178 
end;
179 
 
180 
architecture Structure of EC_RAMB8_S2_S2 is
181 
  COMPONENT dp8ka
182 
  GENERIC(
183 
        DATA_WIDTH_A : in Integer := 18;
184 
        DATA_WIDTH_B : in Integer := 18;
185 
        REGMODE_A    : String  := "NOREG";
186 
        REGMODE_B    : String  := "NOREG";
187 
        RESETMODE    : String  := "ASYNC";
188 
        CSDECODE_A   : String  := "000";
189 
        CSDECODE_B   : String  := "000";
190 
        WRITEMODE_A  : String  := "NORMAL";
191 
        WRITEMODE_B  : String  := "NORMAL";
192 
        GSR : String  := "ENABLED";
193 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
194 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
195 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
196 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
197 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
198 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
199 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
200 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
201 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
202 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
203 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
204 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
205 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
206 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
207 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
208 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
209 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
210 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
211 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
212 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
213 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
214 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
215 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
216 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
217 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
218 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
219 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
220 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
221 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
222 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
223 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
224 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
225 
  );
226 
  PORT(
227 
        dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8            : in std_logic := 'X';
228 
        dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17    : in std_logic := 'X';
229 
        ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8            : in std_logic := 'X';
230 
        ada9, ada10, ada11, ada12                                       : in std_logic := 'X';
231 
        cea, clka, wea, csa0, csa1, csa2, rsta                         : in std_logic := 'X';
232 
        dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8            : in std_logic := 'X';
233 
        dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17    : in std_logic := 'X';
234 
        adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8            : in std_logic := 'X';
235 
        adb9, adb10, adb11, adb12                                       : in std_logic := 'X';
236 
        ceb, clkb, web, csb0, csb1, csb2, rstb                         : in std_logic := 'X';
237 
 
238 
        doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8            : out std_logic := 'X';
239 
        doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17    : out std_logic := 'X';
240 
        dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8            : out std_logic := 'X';
241 
        dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17    : out std_logic := 'X'
242 
  );
243 
  END COMPONENT;
244 
 
245 
signal vcc, gnd : std_ulogic;
246 
begin
247 
  vcc <= '1'; gnd <= '0';
248 
  u0: DP8KA
249 
        generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
250 
          WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
251 
          GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
252 
          REGMODE_A=>"NOREG", DATA_WIDTH_B=> 2, DATA_WIDTH_A=> 2)
253 
        port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
254 
            CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
255 
            CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
256 
            CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
257 
            DIA0=>gnd, DIA1=>DataInA(0), DIA2=>gnd,
258 
            DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
259 
            DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
260 
            DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(1),
261 
            DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
262 
            DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
263 
            ADA0=>vcc, ADA1=>AddressA(0), ADA2=>AddressA(1),
264 
            ADA3=>AddressA(2), ADA4=>AddressA(3), ADA5=>AddressA(4),
265 
            ADA6=>AddressA(6), ADA7=>AddressA(6), ADA8=>AddressA(7),
266 
            ADA9=>AddressA(8), ADA10=>AddressA(9), ADA11=>AddressA(10),
267 
            ADA12=>AddressA(11), DIB0=>gnd, DIB1=>DataInB(0),
268 
            DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
269 
            DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
270 
            DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
271 
            DIB11=>DataInB(1), DIB12=>gnd, DIB13=>gnd,
272 
            DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
273 
            DIB17=>gnd, ADB0=>vcc, ADB1=>AddressB(0),
274 
            ADB2=>AddressB(1), ADB3=>AddressB(2), ADB4=>AddressB(3),
275 
            ADB5=>AddressB(4), ADB6=>AddressB(5), ADB7=>AddressB(6),
276 
            ADB8=>AddressB(7), ADB9=>AddressB(8), ADB10=>AddressB(9),
277 
            ADB11=>AddressB(10), ADB12=>AddressB(11), DOA0=>QA(1),
278 
            DOA1=>QA(0), DOA2=>open, DOA3=>open, DOA4=>open,
279 
            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
280 
            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
281 
            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
282 
            DOA17=>open, DOB0=>QB(1), DOB1=>QB(0), DOB2=>open,
283 
            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
284 
            DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
285 
            DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
286 
            DOB15=>open, DOB16=>open, DOB17=>open);
287 
end;
288 
 
289 
library ieee;
290 
use ieee.std_logic_1164.all;
291 
-- pragma translate_off
292 
library ec;
293 
use ec.dp8ka;
294 
-- pragma translate_on
295 
 
296 
entity EC_RAMB8_S4_S4 is
297 
    port (
298 
        DataInA: in  std_logic_vector(3 downto 0);
299 
        DataInB: in  std_logic_vector(3 downto 0);
300 
        AddressA: in  std_logic_vector(10 downto 0);
301 
        AddressB: in  std_logic_vector(10 downto 0);
302 
        ClockA: in  std_logic;
303 
        ClockB: in  std_logic;
304 
        ClockEnA: in  std_logic;
305 
        ClockEnB: in  std_logic;
306 
        WrA: in  std_logic;
307 
        WrB: in  std_logic;
308 
        QA: out  std_logic_vector(3 downto 0);
309 
        QB: out  std_logic_vector(3 downto 0));
310 
end;
311 
 
312 
architecture Structure of EC_RAMB8_S4_S4 is
313 
  COMPONENT dp8ka
314 
  GENERIC(
315 
        DATA_WIDTH_A : in Integer := 18;
316 
        DATA_WIDTH_B : in Integer := 18;
317 
        REGMODE_A    : String  := "NOREG";
318 
        REGMODE_B    : String  := "NOREG";
319 
        RESETMODE    : String  := "ASYNC";
320 
        CSDECODE_A   : String  := "000";
321 
        CSDECODE_B   : String  := "000";
322 
        WRITEMODE_A  : String  := "NORMAL";
323 
        WRITEMODE_B  : String  := "NORMAL";
324 
        GSR : String  := "ENABLED";
325 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
326 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
327 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
328 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
329 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
330 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
331 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
332 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
333 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
334 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
335 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
336 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
337 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
338 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
339 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
340 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
341 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
342 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
343 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
344 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
345 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
346 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
347 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
348 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
349 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
350 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
351 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
352 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
353 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
354 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
355 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
356 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
357 
  );
358 
  PORT(
359 
        dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8            : in std_logic := 'X';
360 
        dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17    : in std_logic := 'X';
361 
        ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8            : in std_logic := 'X';
362 
        ada9, ada10, ada11, ada12                                       : in std_logic := 'X';
363 
        cea, clka, wea, csa0, csa1, csa2, rsta                         : in std_logic := 'X';
364 
        dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8            : in std_logic := 'X';
365 
        dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17    : in std_logic := 'X';
366 
        adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8            : in std_logic := 'X';
367 
        adb9, adb10, adb11, adb12                                       : in std_logic := 'X';
368 
        ceb, clkb, web, csb0, csb1, csb2, rstb                         : in std_logic := 'X';
369 
 
370 
        doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8            : out std_logic := 'X';
371 
        doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17    : out std_logic := 'X';
372 
        dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8            : out std_logic := 'X';
373 
        dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17    : out std_logic := 'X'
374 
  );
375 
  END COMPONENT;
376 
 
377 
signal vcc, gnd : std_ulogic;
378 
begin
379 
  vcc <= '1'; gnd <= '0';
380 
  u0: DP8KA
381 
        generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
382 
          WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
383 
          GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
384 
          REGMODE_A=>"NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 4)
385 
        port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
386 
            CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
387 
            CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
388 
            CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
389 
            DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
390 
            DIA3=>DataInA(3), DIA4=>gnd, DIA5=>gnd,
391 
            DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
392 
            DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
393 
            DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
394 
            DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
395 
            ADA0=>vcc, ADA1=>vcc, ADA2=>AddressA(0),
396 
            ADA3=>AddressA(1), ADA4=>AddressA(2), ADA5=>AddressA(3),
397 
            ADA6=>AddressA(4), ADA7=>AddressA(5), ADA8=>AddressA(6),
398 
            ADA9=>AddressA(7), ADA10=>AddressA(8), ADA11=>AddressA(9),
399 
            ADA12=>AddressA(10), DIB0=>DataInB(0), DIB1=>DataInB(1),
400 
            DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>gnd,
401 
            DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
402 
            DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
403 
            DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
404 
            DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
405 
            DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
406 
            ADB2=>AddressB(0), ADB3=>AddressB(1), ADB4=>AddressB(2),
407 
            ADB5=>AddressB(3), ADB6=>AddressB(4), ADB7=>AddressB(5),
408 
            ADB8=>AddressB(6), ADB9=>AddressB(7), ADB10=>AddressB(8),
409 
            ADB11=>AddressB(9), ADB12=>AddressB(10), DOA0=>QA(0),
410 
            DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>open,
411 
            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
412 
            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
413 
            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
414 
            DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
415 
            DOB3=>QB(3), DOB4=>open, DOB5=>open, DOB6=>open,
416 
            DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
417 
            DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
418 
            DOB15=>open, DOB16=>open, DOB17=>open);
419 
end;
420 
 
421 
library ieee;
422 
use ieee.std_logic_1164.all;
423 
-- pragma translate_off
424 
library ec;
425 
use ec.dp8ka;
426 
-- pragma translate_on
427 
 
428 
entity EC_RAMB8_S9_S9 is
429 
    port (
430 
        DataInA: in  std_logic_vector(8 downto 0);
431 
        DataInB: in  std_logic_vector(8 downto 0);
432 
        AddressA: in  std_logic_vector(9 downto 0);
433 
        AddressB: in  std_logic_vector(9 downto 0);
434 
        ClockA: in  std_logic;
435 
        ClockB: in  std_logic;
436 
        ClockEnA: in  std_logic;
437 
        ClockEnB: in  std_logic;
438 
        WrA: in  std_logic;
439 
        WrB: in  std_logic;
440 
        QA: out  std_logic_vector(8 downto 0);
441 
        QB: out  std_logic_vector(8 downto 0));
442 
end;
443 
 
444 
architecture Structure of EC_RAMB8_S9_S9 is
445 
  COMPONENT dp8ka
446 
  GENERIC(
447 
        DATA_WIDTH_A : in Integer := 18;
448 
        DATA_WIDTH_B : in Integer := 18;
449 
        REGMODE_A    : String  := "NOREG";
450 
        REGMODE_B    : String  := "NOREG";
451 
        RESETMODE    : String  := "ASYNC";
452 
        CSDECODE_A   : String  := "000";
453 
        CSDECODE_B   : String  := "000";
454 
        WRITEMODE_A  : String  := "NORMAL";
455 
        WRITEMODE_B  : String  := "NORMAL";
456 
        GSR : String  := "ENABLED";
457 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
458 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
459 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
460 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
461 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
462 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
463 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
464 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
465 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
466 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
467 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
468 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
469 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
470 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
471 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
472 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
473 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
474 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
475 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
476 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
477 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
478 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
479 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
480 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
481 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
482 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
483 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
484 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
485 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
486 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
487 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
488 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
489 
  );
490 
  PORT(
491 
        dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8            : in std_logic := 'X';
492 
        dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17    : in std_logic := 'X';
493 
        ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8            : in std_logic := 'X';
494 
        ada9, ada10, ada11, ada12                                       : in std_logic := 'X';
495 
        cea, clka, wea, csa0, csa1, csa2, rsta                         : in std_logic := 'X';
496 
        dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8            : in std_logic := 'X';
497 
        dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17    : in std_logic := 'X';
498 
        adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8            : in std_logic := 'X';
499 
        adb9, adb10, adb11, adb12                                       : in std_logic := 'X';
500 
        ceb, clkb, web, csb0, csb1, csb2, rstb                         : in std_logic := 'X';
501 
 
502 
        doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8            : out std_logic := 'X';
503 
        doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17    : out std_logic := 'X';
504 
        dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8            : out std_logic := 'X';
505 
        dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17    : out std_logic := 'X'
506 
  );
507 
  END COMPONENT;
508 
 
509 
signal vcc, gnd : std_ulogic;
510 
begin
511 
  vcc <= '1'; gnd <= '0';
512 
  u0: DP8KA
513 
        generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
514 
          WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
515 
          GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
516 
          REGMODE_A=>"NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9)
517 
        port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
518 
            CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
519 
            CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
520 
            CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
521 
            DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
522 
            DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
523 
            DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
524 
            DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
525 
            DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
526 
            DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
527 
            ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
528 
            ADA3=>AddressA(0), ADA4=>AddressA(1), ADA5=>AddressA(2),
529 
            ADA6=>AddressA(3), ADA7=>AddressA(4), ADA8=>AddressA(5),
530 
            ADA9=>AddressA(6), ADA10=>AddressA(7), ADA11=>AddressA(8),
531 
            ADA12=>AddressA(9), DIB0=>DataInB(0), DIB1=>DataInB(1),
532 
            DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
533 
            DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
534 
            DIB8=>DataInB(8), DIB9=>gnd, DIB10=>gnd,
535 
            DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
536 
            DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
537 
            DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
538 
            ADB2=>gnd, ADB3=>AddressB(0), ADB4=>AddressB(1),
539 
            ADB5=>AddressB(2), ADB6=>AddressB(3), ADB7=>AddressB(4),
540 
            ADB8=>AddressB(5), ADB9=>AddressB(6), ADB10=>AddressB(7),
541 
            ADB11=>AddressB(8), ADB12=>AddressB(9), DOA0=>QA(0),
542 
            DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
543 
            DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
544 
            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
545 
            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
546 
            DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
547 
            DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
548 
            DOB7=>QB(7), DOB8=>QB(8), DOB9=>open, DOB10=>open,
549 
            DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
550 
            DOB15=>open, DOB16=>open, DOB17=>open);
551 
end;
552 
 
553 
 
554 
library ieee;
555 
use ieee.std_logic_1164.all;
556 
-- pragma translate_off
557 
library ec;
558 
use ec.dp8ka;
559 
-- pragma translate_on
560 
 
561 
entity EC_RAMB8_S18_S18 is
562 
    port (
563 
        DataInA: in  std_logic_vector(17 downto 0);
564 
        DataInB: in  std_logic_vector(17 downto 0);
565 
        AddressA: in  std_logic_vector(8 downto 0);
566 
        AddressB: in  std_logic_vector(8 downto 0);
567 
        ClockA: in  std_logic;
568 
        ClockB: in  std_logic;
569 
        ClockEnA: in  std_logic;
570 
        ClockEnB: in  std_logic;
571 
        WrA: in  std_logic;
572 
        WrB: in  std_logic;
573 
        QA: out  std_logic_vector(17 downto 0);
574 
        QB: out  std_logic_vector(17 downto 0));
575 
end;
576 
 
577 
architecture Structure of EC_RAMB8_S18_S18 is
578 
  COMPONENT dp8ka
579 
  GENERIC(
580 
        DATA_WIDTH_A : in Integer := 18;
581 
        DATA_WIDTH_B : in Integer := 18;
582 
        REGMODE_A    : String  := "NOREG";
583 
        REGMODE_B    : String  := "NOREG";
584 
        RESETMODE    : String  := "ASYNC";
585 
        CSDECODE_A   : String  := "000";
586 
        CSDECODE_B   : String  := "000";
587 
        WRITEMODE_A  : String  := "NORMAL";
588 
        WRITEMODE_B  : String  := "NORMAL";
589 
        GSR : String  := "ENABLED";
590 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
591 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
592 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
593 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
594 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
595 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
596 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
597 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
598 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
599 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
600 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
601 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
602 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
603 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
604 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
605 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
606 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
607 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
608 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
609 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
610 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
611 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
612 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
613 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
614 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
615 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
616 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
617 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
618 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
619 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
620 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
621 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
622 
  );
623 
  PORT(
624 
        dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8            : in std_logic := 'X';
625 
        dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17    : in std_logic := 'X';
626 
        ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8            : in std_logic := 'X';
627 
        ada9, ada10, ada11, ada12                                       : in std_logic := 'X';
628 
        cea, clka, wea, csa0, csa1, csa2, rsta                         : in std_logic := 'X';
629 
        dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8            : in std_logic := 'X';
630 
        dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17    : in std_logic := 'X';
631 
        adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8            : in std_logic := 'X';
632 
        adb9, adb10, adb11, adb12                                       : in std_logic := 'X';
633 
        ceb, clkb, web, csb0, csb1, csb2, rstb                         : in std_logic := 'X';
634 
 
635 
        doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8            : out std_logic := 'X';
636 
        doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17    : out std_logic := 'X';
637 
        dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8            : out std_logic := 'X';
638 
        dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17    : out std_logic := 'X'
639 
  );
640 
  END COMPONENT;
641 
 
642 
signal vcc, gnd : std_ulogic;
643 
begin
644 
  vcc <= '1'; gnd <= '0';
645 
  u0: DP8KA
646 
        generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
647 
          WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
648 
          GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
649 
          REGMODE_A=>"NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
650 
        port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
651 
            CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
652 
            CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
653 
            CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
654 
            DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
655 
            DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
656 
            DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
657 
            DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
658 
            DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
659 
            DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
660 
            ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
661 
            ADA3=>gnd, ADA4=>AddressA(0), ADA5=>AddressA(1),
662 
            ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
663 
            ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
664 
            ADA12=>AddressA(8), DIB0=>DataInB(0), DIB1=>DataInB(1),
665 
            DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
666 
            DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
667 
            DIB8=>DataInB(8), DIB9=>DataInB(9), DIB10=>DataInB(10),
668 
            DIB11=>DataInB(11), DIB12=>DataInB(12), DIB13=>DataInB(13),
669 
            DIB14=>DataInB(14), DIB15=>DataInB(15), DIB16=>DataInB(16),
670 
            DIB17=>DataInB(17), ADB0=>vcc, ADB1=>vcc,
671 
            ADB2=>gnd, ADB3=>gnd, ADB4=>AddressB(0),
672 
            ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3),
673 
            ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6),
674 
            ADB11=>AddressB(7), ADB12=>AddressB(8), DOA0=>QA(0),
675 
            DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
676 
            DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
677 
            DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
678 
            DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
679 
            DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
680 
            DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
681 
            DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
682 
            DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
683 
            DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
684 
end;
685 
 
686 
library ieee;
687 
use ieee.std_logic_1164.all;
688 
-- pragma translate_off
689 
library ec;
690 
use ec.sp8ka;
691 
-- pragma translate_on
692 
 
693 
entity EC_RAMB8_S1 is
694 
  port (
695 
   clk, en, we : in std_ulogic;
696 
   address : in std_logic_vector (12 downto 0);
697 
   data : in std_logic_vector (0 downto 0);
698 
   q : out std_logic_vector (0 downto 0));
699 
end;
700 
architecture behav of EC_RAMB8_S1 is
701 
  COMPONENT sp8ka
702 
  GENERIC(
703 
        DATA_WIDTH   : in Integer := 18;
704 
        REGMODE      : String  := "NOREG";
705 
        RESETMODE    : String  := "ASYNC";
706 
        CSDECODE     : String  := "000";
707 
        WRITEMODE    : String  := "NORMAL";
708 
        GSR : String  := "ENABLED";
709 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
710 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
711 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
712 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
713 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
714 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
715 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
716 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
717 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
718 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
719 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
720 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
721 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
722 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
723 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
724 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
725 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
726 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
727 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
728 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
729 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
730 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
731 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
732 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
733 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
734 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
735 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
736 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
737 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
738 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
739 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
740 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
741 
  );
742 
  PORT(
743 
        di0, di1, di2, di3, di4, di5, di6, di7, di8            : in std_logic := 'X';
744 
        di9, di10, di11, di12, di13, di14, di15, di16, di17    : in std_logic := 'X';
745 
        ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8            : in std_logic := 'X';
746 
        ad9, ad10, ad11, ad12                                  : in std_logic := 'X';
747 
        ce, clk, we, cs0, cs1, cs2, rst                        : in std_logic := 'X';
748 
 
749 
        do0, do1, do2, do3, do4, do5, do6, do7, do8            : out std_logic := 'X';
750 
        do9, do10, do11, do12, do13, do14, do15, do16, do17    : out std_logic := 'X'
751 
  );
752 
  END COMPONENT;
753 
signal vcc, gnd : std_ulogic;
754 
begin
755 
 
756 
  vcc <= '1'; gnd <= '0';
757 
    u0: SP8KA
758 
        generic map (CSDECODE=>"000", GSR=>"DISABLED",
759 
           WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
760 
           REGMODE=>"NOREG", DATA_WIDTH=> 1)
761 
        port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
762 
            CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
763 
            DI1=>gnd, DI2=>gnd, DI3=>gnd, DI4=>gnd,
764 
            DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
765 
            DI9=>gnd, DI10=>gnd, DI11=>Data(0),
766 
            DI12=>gnd, DI13=>gnd, DI14=>gnd,
767 
            DI15=>gnd, DI16=>gnd, DI17=>gnd,
768 
            AD0=>Address(0), AD1=>Address(1), AD2=>Address(2),
769 
            AD3=>Address(3), AD4=>Address(4), AD5=>Address(5),
770 
            AD6=>Address(6), AD7=>Address(7), AD8=>Address(8),
771 
            AD9=>Address(9), AD10=>Address(10), AD11=>Address(11),
772 
            AD12=>Address(12), DO0=>Q(0), DO1=>open, DO2=>open, DO3=>open,
773 
            DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
774 
            DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
775 
            DO14=>open, DO15=>open, DO16=>open, DO17=>open);
776 
end;
777 
 
778 
library ieee;
779 
use ieee.std_logic_1164.all;
780 
-- pragma translate_off
781 
library ec;
782 
use ec.sp8ka;
783 
-- pragma translate_on
784 
 
785 
entity EC_RAMB8_S2 is
786 
  port (
787 
   clk, en, we : in std_ulogic;
788 
   address : in std_logic_vector (11 downto 0);
789 
   data : in std_logic_vector (1 downto 0);
790 
   q : out std_logic_vector (1 downto 0));
791 
end;
792 
architecture behav of EC_RAMB8_S2 is
793 
  COMPONENT sp8ka
794 
  GENERIC(
795 
        DATA_WIDTH   : in Integer := 18;
796 
        REGMODE      : String  := "NOREG";
797 
        RESETMODE    : String  := "ASYNC";
798 
        CSDECODE     : String  := "000";
799 
        WRITEMODE    : String  := "NORMAL";
800 
        GSR : String  := "ENABLED";
801 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
802 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
803 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
804 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
805 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
806 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
807 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
808 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
809 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
810 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
811 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
812 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
813 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
814 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
815 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
816 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
817 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
818 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
819 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
820 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
821 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
822 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
823 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
824 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
825 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
826 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
827 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
828 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
829 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
830 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
831 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
832 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
833 
  );
834 
  PORT(
835 
        di0, di1, di2, di3, di4, di5, di6, di7, di8            : in std_logic := 'X';
836 
        di9, di10, di11, di12, di13, di14, di15, di16, di17    : in std_logic := 'X';
837 
        ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8            : in std_logic := 'X';
838 
        ad9, ad10, ad11, ad12                                  : in std_logic := 'X';
839 
        ce, clk, we, cs0, cs1, cs2, rst                        : in std_logic := 'X';
840 
 
841 
        do0, do1, do2, do3, do4, do5, do6, do7, do8            : out std_logic := 'X';
842 
        do9, do10, do11, do12, do13, do14, do15, do16, do17    : out std_logic := 'X'
843 
  );
844 
  END COMPONENT;
845 
signal vcc, gnd : std_ulogic;
846 
begin
847 
 
848 
  vcc <= '1'; gnd <= '0';
849 
    u0: SP8KA
850 
        generic map (CSDECODE=>"000", GSR=>"DISABLED",
851 
           WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
852 
           REGMODE=>"NOREG", DATA_WIDTH=> 2)
853 
        port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
854 
            CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
855 
            DI1=>Data(0), DI2=>gnd, DI3=>gnd, DI4=>gnd,
856 
            DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
857 
            DI9=>gnd, DI10=>gnd, DI11=>Data(1),
858 
            DI12=>gnd, DI13=>gnd, DI14=>gnd,
859 
            DI15=>gnd, DI16=>gnd, DI17=>gnd,
860 
            AD0=>gnd, AD1=>Address(0), AD2=>Address(1),
861 
            AD3=>Address(2), AD4=>Address(3), AD5=>Address(4),
862 
            AD6=>Address(5), AD7=>Address(6), AD8=>Address(7),
863 
            AD9=>Address(8), AD10=>Address(9), AD11=>Address(10),
864 
            AD12=>Address(11), DO0=>Q(1), DO1=>Q(0), DO2=>open, DO3=>open,
865 
            DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
866 
            DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
867 
            DO14=>open, DO15=>open, DO16=>open, DO17=>open);
868 
end;
869 
 
870 
library ieee;
871 
use ieee.std_logic_1164.all;
872 
-- pragma translate_off
873 
library ec;
874 
use ec.sp8ka;
875 
-- pragma translate_on
876 
 
877 
entity EC_RAMB8_S4 is
878 
  port (
879 
   clk, en, we : in std_ulogic;
880 
   address : in std_logic_vector (10 downto 0);
881 
   data : in std_logic_vector (3 downto 0);
882 
   q : out std_logic_vector (3 downto 0));
883 
end;
884 
architecture behav of EC_RAMB8_S4 is
885 
  COMPONENT sp8ka
886 
  GENERIC(
887 
        DATA_WIDTH   : in Integer := 18;
888 
        REGMODE      : String  := "NOREG";
889 
        RESETMODE    : String  := "ASYNC";
890 
        CSDECODE     : String  := "000";
891 
        WRITEMODE    : String  := "NORMAL";
892 
        GSR : String  := "ENABLED";
893 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
894 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
895 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
896 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
897 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
898 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
899 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
900 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
901 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
902 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
903 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
904 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
905 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
906 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
907 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
908 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
909 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
910 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
911 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
912 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
913 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
914 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
915 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
916 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
917 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
918 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
919 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
920 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
921 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
922 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
923 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
924 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
925 
  );
926 
  PORT(
927 
        di0, di1, di2, di3, di4, di5, di6, di7, di8            : in std_logic := 'X';
928 
        di9, di10, di11, di12, di13, di14, di15, di16, di17    : in std_logic := 'X';
929 
        ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8            : in std_logic := 'X';
930 
        ad9, ad10, ad11, ad12                                  : in std_logic := 'X';
931 
        ce, clk, we, cs0, cs1, cs2, rst                        : in std_logic := 'X';
932 
 
933 
        do0, do1, do2, do3, do4, do5, do6, do7, do8            : out std_logic := 'X';
934 
        do9, do10, do11, do12, do13, do14, do15, do16, do17    : out std_logic := 'X'
935 
  );
936 
  END COMPONENT;
937 
signal vcc, gnd : std_ulogic;
938 
begin
939 
 
940 
  vcc <= '1'; gnd <= '0';
941 
    u0: SP8KA
942 
        generic map (CSDECODE=>"000", GSR=>"DISABLED",
943 
           WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
944 
           REGMODE=>"NOREG", DATA_WIDTH=> 4)
945 
        port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
946 
            CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
947 
            DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>gnd,
948 
            DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
949 
            DI9=>gnd, DI10=>gnd, DI11=>gnd,
950 
            DI12=>gnd, DI13=>gnd, DI14=>gnd,
951 
            DI15=>gnd, DI16=>gnd, DI17=>gnd,
952 
            AD0=>gnd, AD1=>gnd, AD2=>Address(0),
953 
            AD3=>Address(1), AD4=>Address(2), AD5=>Address(3),
954 
            AD6=>Address(4), AD7=>Address(5), AD8=>Address(6),
955 
            AD9=>Address(7), AD10=>Address(8), AD11=>Address(9),
956 
            AD12=>Address(10), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
957 
            DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
958 
            DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
959 
            DO14=>open, DO15=>open, DO16=>open, DO17=>open);
960 
end;
961 
 
962 
library ieee;
963 
use ieee.std_logic_1164.all;
964 
-- pragma translate_off
965 
library ec;
966 
use ec.sp8ka;
967 
-- pragma translate_on
968 
 
969 
entity EC_RAMB8_S9 is
970 
  port (
971 
   clk, en, we : in std_ulogic;
972 
   address : in std_logic_vector (9 downto 0);
973 
   data : in std_logic_vector (8 downto 0);
974 
   q : out std_logic_vector (8 downto 0));
975 
end;
976 
architecture behav of EC_RAMB8_S9 is
977 
  COMPONENT sp8ka
978 
  GENERIC(
979 
        DATA_WIDTH   : in Integer := 18;
980 
        REGMODE      : String  := "NOREG";
981 
        RESETMODE    : String  := "ASYNC";
982 
        CSDECODE     : String  := "000";
983 
        WRITEMODE    : String  := "NORMAL";
984 
        GSR : String  := "ENABLED";
985 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
986 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
987 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
988 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
989 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
990 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
991 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
992 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
993 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
994 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
995 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
996 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
997 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
998 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
999 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1000 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1001 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1002 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1003 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1004 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1005 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1006 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1007 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1008 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1009 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1010 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1011 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1012 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1013 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1014 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1015 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1016 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
1017 
  );
1018 
  PORT(
1019 
        di0, di1, di2, di3, di4, di5, di6, di7, di8            : in std_logic := 'X';
1020 
        di9, di10, di11, di12, di13, di14, di15, di16, di17    : in std_logic := 'X';
1021 
        ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8            : in std_logic := 'X';
1022 
        ad9, ad10, ad11, ad12                                  : in std_logic := 'X';
1023 
        ce, clk, we, cs0, cs1, cs2, rst                        : in std_logic := 'X';
1024 
 
1025 
        do0, do1, do2, do3, do4, do5, do6, do7, do8            : out std_logic := 'X';
1026 
        do9, do10, do11, do12, do13, do14, do15, do16, do17    : out std_logic := 'X'
1027 
  );
1028 
  END COMPONENT;
1029 
signal vcc, gnd : std_ulogic;
1030 
begin
1031 
 
1032 
  vcc <= '1'; gnd <= '0';
1033 
    u0: SP8KA
1034 
        generic map (CSDECODE=>"000", GSR=>"DISABLED",
1035 
           WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
1036 
           REGMODE=>"NOREG", DATA_WIDTH=> 9)
1037 
        port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
1038 
            CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
1039 
            DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
1040 
            DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
1041 
            DI9=>gnd, DI10=>gnd, DI11=>gnd,
1042 
            DI12=>gnd, DI13=>gnd, DI14=>gnd,
1043 
            DI15=>gnd, DI16=>gnd, DI17=>gnd,
1044 
            AD0=>gnd, AD1=>gnd, AD2=>gnd,
1045 
            AD3=>Address(0), AD4=>Address(1), AD5=>Address(2),
1046 
            AD6=>Address(3), AD7=>Address(4), AD8=>Address(5),
1047 
            AD9=>Address(6), AD10=>Address(7), AD11=>Address(8),
1048 
            AD12=>Address(9), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
1049 
            DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
1050 
            DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
1051 
            DO14=>open, DO15=>open, DO16=>open, DO17=>open);
1052 
end;
1053 
 
1054 
 
1055 
library ieee;
1056 
use ieee.std_logic_1164.all;
1057 
-- pragma translate_off
1058 
library ec;
1059 
use ec.sp8ka;
1060 
-- pragma translate_on
1061 
 
1062 
entity EC_RAMB8_S18 is
1063 
  port (
1064 
   clk, en, we : in std_ulogic;
1065 
   address : in std_logic_vector (8 downto 0);
1066 
   data : in std_logic_vector (17 downto 0);
1067 
   q : out std_logic_vector (17 downto 0));
1068 
end;
1069 
architecture behav of EC_RAMB8_S18 is
1070 
  COMPONENT sp8ka
1071 
  GENERIC(
1072 
        DATA_WIDTH   : in Integer := 18;
1073 
        REGMODE      : String  := "NOREG";
1074 
        RESETMODE    : String  := "ASYNC";
1075 
        CSDECODE     : String  := "000";
1076 
        WRITEMODE    : String  := "NORMAL";
1077 
        GSR : String  := "ENABLED";
1078 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1079 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1080 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1081 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1082 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1083 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1084 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1085 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1086 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1087 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1088 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1089 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1090 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1091 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1092 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1093 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1094 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1095 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1096 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1097 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1098 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1099 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1100 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1101 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1102 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1103 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1104 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1105 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1106 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1107 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1108 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1109 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
1110 
  );
1111 
  PORT(
1112 
        di0, di1, di2, di3, di4, di5, di6, di7, di8            : in std_logic := 'X';
1113 
        di9, di10, di11, di12, di13, di14, di15, di16, di17    : in std_logic := 'X';
1114 
        ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8            : in std_logic := 'X';
1115 
        ad9, ad10, ad11, ad12                                  : in std_logic := 'X';
1116 
        ce, clk, we, cs0, cs1, cs2, rst                        : in std_logic := 'X';
1117 
 
1118 
        do0, do1, do2, do3, do4, do5, do6, do7, do8            : out std_logic := 'X';
1119 
        do9, do10, do11, do12, do13, do14, do15, do16, do17    : out std_logic := 'X'
1120 
  );
1121 
  END COMPONENT;
1122 
signal vcc, gnd : std_ulogic;
1123 
begin
1124 
 
1125 
  vcc <= '1'; gnd <= '0';
1126 
    u0: SP8KA
1127 
        generic map (CSDECODE=>"000", GSR=>"DISABLED",
1128 
           WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
1129 
           REGMODE=>"NOREG", DATA_WIDTH=> 18)
1130 
        port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
1131 
            CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
1132 
            DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
1133 
            DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
1134 
            DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
1135 
            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
1136 
            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
1137 
            AD0=>gnd, AD1=>gnd, AD2=>gnd,
1138 
            AD3=>gnd, AD4=>Address(0), AD5=>Address(1),
1139 
            AD6=>Address(2), AD7=>Address(3), AD8=>Address(4),
1140 
            AD9=>Address(5), AD10=>Address(6), AD11=>Address(7),
1141 
            AD12=>Address(8), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
1142 
            DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
1143 
            DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), DO13=>Q(13),
1144 
            DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), DO17=>Q(17));
1145 
end;
1146 
 
1147 
 
1148 
library ieee;
1149 
use ieee.std_logic_1164.all;
1150 
-- pragma translate_off
1151 
library ec;
1152 
use ec.dp8ka;
1153 
-- pragma translate_on
1154 
 
1155 
entity EC_RAMB8_S36 is
1156 
  port (
1157 
   clk, en, we : in std_ulogic;
1158 
   address : in std_logic_vector (7 downto 0);
1159 
   data : in std_logic_vector (35 downto 0);
1160 
   q : out std_logic_vector (35 downto 0));
1161 
end;
1162 
architecture behav of EC_RAMB8_S36 is
1163 
  COMPONENT dp8ka
1164 
  GENERIC(
1165 
        DATA_WIDTH_A : in Integer := 18;
1166 
        DATA_WIDTH_B : in Integer := 18;
1167 
        REGMODE_A    : String  := "NOREG";
1168 
        REGMODE_B    : String  := "NOREG";
1169 
        RESETMODE    : String  := "ASYNC";
1170 
        CSDECODE_A   : String  := "000";
1171 
        CSDECODE_B   : String  := "000";
1172 
        WRITEMODE_A  : String  := "NORMAL";
1173 
        WRITEMODE_B  : String  := "NORMAL";
1174 
        GSR : String  := "ENABLED";
1175 
        initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1176 
        initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1177 
        initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1178 
        initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1179 
        initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1180 
        initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1181 
        initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1182 
        initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1183 
        initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1184 
        initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1185 
        initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1186 
        initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1187 
        initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1188 
        initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1189 
        initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1190 
        initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1191 
        initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1192 
        initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1193 
        initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1194 
        initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1195 
        initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1196 
        initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1197 
        initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1198 
        initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1199 
        initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1200 
        initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1201 
        initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1202 
        initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1203 
        initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1204 
        initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1205 
        initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
1206 
        initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
1207 
  );
1208 
  PORT(
1209 
        dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8            : in std_logic := 'X';
1210 
        dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17    : in std_logic := 'X';
1211 
        ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8            : in std_logic := 'X';
1212 
        ada9, ada10, ada11, ada12                                       : in std_logic := 'X';
1213 
        cea, clka, wea, csa0, csa1, csa2, rsta                         : in std_logic := 'X';
1214 
        dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8            : in std_logic := 'X';
1215 
        dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17    : in std_logic := 'X';
1216 
        adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8            : in std_logic := 'X';
1217 
        adb9, adb10, adb11, adb12                                       : in std_logic := 'X';
1218 
        ceb, clkb, web, csb0, csb1, csb2, rstb                         : in std_logic := 'X';
1219 
 
1220 
        doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8            : out std_logic := 'X';
1221 
        doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17    : out std_logic := 'X';
1222 
        dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8            : out std_logic := 'X';
1223 
        dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17    : out std_logic := 'X'
1224 
  );
1225 
  END COMPONENT;
1226 
 
1227 
signal vcc, gnd : std_ulogic;
1228 
begin
1229 
 
1230 
  vcc <= '1'; gnd <= '0';
1231 
 
1232 
    u0: DP8KA
1233 
        generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
1234 
           WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL", GSR=>"DISABLED",
1235 
           RESETMODE=>"ASYNC", REGMODE_B=>"NOREG", REGMODE_A=>"NOREG",
1236 
           DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
1237 
        port map (CEA => en, CLKA => clk, WEA => we, CSA0 => gnd,
1238 
            CSA1=>gnd, CSA2=>gnd, RSTA=> gnd, CEB=> en,
1239 
            CLKB=> clk, WEB=> we, CSB0=>gnd, CSB1=>gnd,
1240 
            CSB2=>gnd, RSTB=>gnd, DIA0=>Data(0), DIA1=>Data(1),
1241 
            DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5),
1242 
            DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9),
1243 
            DIA10=>Data(10), DIA11=>Data(11), DIA12=>Data(12),
1244 
            DIA13=>Data(13), DIA14=>Data(14), DIA15=>Data(15),
1245 
            DIA16=>Data(16), DIA17=>Data(17), ADA0=>vcc,
1246 
            ADA1=>vcc, ADA2=>vcc, ADA3=>vcc,
1247 
            ADA4=>Address(0), ADA5=>Address(1), ADA6=>Address(2),
1248 
            ADA7=>Address(3), ADA8=>Address(4), ADA9=>Address(5),
1249 
            ADA10=>Address(6), ADA11=>Address(7), ADA12=>gnd,
1250 
            DIB0=>Data(18), DIB1=>Data(19), DIB2=>Data(20),
1251 
            DIB3=>Data(21), DIB4=>Data(22), DIB5=>Data(23),
1252 
            DIB6=>Data(24), DIB7=>Data(25), DIB8=>Data(26),
1253 
            DIB9=>Data(27), DIB10=>Data(28), DIB11=>Data(29),
1254 
            DIB12=>Data(30), DIB13=>Data(31), DIB14=>Data(32),
1255 
            DIB15=>Data(33), DIB16=>Data(34), DIB17=>Data(35),
1256 
            ADB0=>vcc, ADB1=>vcc, ADB2=>gnd,
1257 
            ADB3=>gnd, ADB4=>Address(0), ADB5=>Address(1),
1258 
            ADB6=>Address(2), ADB7=>Address(3), ADB8=>Address(4),
1259 
            ADB9=>Address(5), ADB10=>Address(6), ADB11=>Address(7),
1260 
            ADB12=>vcc, DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2),
1261 
            DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7),
1262 
            DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10), DOA11=>Q(11),
1263 
            DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14), DOA15=>Q(15),
1264 
            DOA16=>Q(16), DOA17=>Q(17), DOB0=>Q(18), DOB1=>Q(19),
1265 
            DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23),
1266 
            DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), DOB9=>Q(27),
1267 
            DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), DOB13=>Q(31),
1268 
            DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>Q(35));
1269 
end;
1270 
 
1271 
library ieee;
1272 
use ieee.std_logic_1164.all;
1273 
library techmap;
1274 
 
1275 
entity ec_syncram is
1276 
  generic (abits : integer := 9; dbits : integer := 32);
1277 
  port (
1278 
    clk     : in  std_ulogic;
1279 
    address : in  std_logic_vector (abits -1 downto 0);
1280 
    datain  : in  std_logic_vector (dbits -1 downto 0);
1281 
    dataout : out std_logic_vector (dbits -1 downto 0);
1282 
    enable  : in  std_ulogic;
1283 
    write   : in  std_ulogic
1284 
    );
1285 
end;
1286 
 
1287 
architecture behav of ec_syncram is
1288 
  component EC_RAMB8_S1 port (
1289 
   clk, en, we : in std_ulogic;
1290 
   address : in std_logic_vector (12 downto 0);
1291 
   data : in std_logic_vector (0 downto 0);
1292 
   q : out std_logic_vector (0 downto 0));
1293 
  end component;
1294 
  component EC_RAMB8_S2 port (
1295 
   clk, en, we : in std_ulogic;
1296 
   address : in std_logic_vector (11 downto 0);
1297 
   data : in std_logic_vector (1 downto 0);
1298 
   q : out std_logic_vector (1 downto 0));
1299 
  end component;
1300 
  component EC_RAMB8_S4 port (
1301 
   clk, en, we : in std_ulogic;
1302 
   address : in std_logic_vector (10 downto 0);
1303 
   data : in std_logic_vector (3 downto 0);
1304 
   q : out std_logic_vector (3 downto 0));
1305 
  end component;
1306 
  component EC_RAMB8_S9 port (
1307 
   clk, en, we : in std_ulogic;
1308 
   address : in std_logic_vector (9 downto 0);
1309 
   data : in std_logic_vector (8 downto 0);
1310 
   q : out std_logic_vector (8 downto 0));
1311 
  end component;
1312 
  component EC_RAMB8_S18 port (
1313 
   clk, en, we : in std_ulogic;
1314 
   address : in std_logic_vector (8 downto 0);
1315 
   data : in std_logic_vector (17 downto 0);
1316 
   q : out std_logic_vector (17 downto 0));
1317 
  end component;
1318 
  component EC_RAMB8_S36 port (
1319 
   clk, en, we : in std_ulogic;
1320 
   address : in std_logic_vector (7 downto 0);
1321 
   data : in std_logic_vector (35 downto 0);
1322 
   q : out std_logic_vector (35 downto 0));
1323 
  end component;
1324 
 
1325 
constant DMAX : integer := dbits+36;
1326 
constant AMAX : integer := 13;
1327 
signal gnd : std_ulogic;
1328 
signal do, di : std_logic_vector(DMAX downto 0);
1329 
signal xa, ya : std_logic_vector(AMAX downto 0);
1330 
begin
1331 
  gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
1332 
  di(DMAX downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
1333 
  xa(AMAX downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
1334 
  ya(AMAX downto abits) <= (others => '1');
1335 
 
1336 
  a8 : if (abits <= 8) generate
1337 
    x : for i in 0 to ((dbits-1)/36) generate
1338 
      r : EC_RAMB8_S36 port map ( clk, enable, write, xa(7 downto 0),
1339 
        di((i+1)*36-1 downto i*36), do((i+1)*36-1 downto i*36));
1340 
    end generate;
1341 
  end generate;
1342 
 
1343 
  a9 : if (abits = 9) generate
1344 
    x : for i in 0 to ((dbits-1)/18) generate
1345 
      r : EC_RAMB8_S18 port map ( clk, enable, write, xa(8 downto 0),
1346 
        di((i+1)*18-1 downto i*18), do((i+1)*18-1 downto i*18));
1347 
    end generate;
1348 
  end generate;
1349 
 
1350 
  a10 : if (abits = 10) generate
1351 
    x : for i in 0 to ((dbits-1)/9) generate
1352 
      r : EC_RAMB8_S9 port map ( clk, enable, write, xa(9 downto 0),
1353 
        di((i+1)*9-1 downto i*9), do((i+1)*9-1 downto i*9));
1354 
    end generate;
1355 
  end generate;
1356 
 
1357 
  a11 : if (abits = 11) generate
1358 
    x : for i in 0 to ((dbits-1)/4) generate
1359 
      r : EC_RAMB8_S4 port map ( clk, enable, write, xa(10 downto 0),
1360 
        di((i+1)*4-1 downto i*4), do((i+1)*4-1 downto i*4));
1361 
    end generate;
1362 
  end generate;
1363 
 
1364 
  a12 : if (abits = 12) generate
1365 
    x : for i in 0 to ((dbits-1)/2) generate
1366 
      r : EC_RAMB8_S2 port map ( clk, enable, write, xa(11 downto 0),
1367 
        di((i+1)*2-1 downto i*2), do((i+1)*2-1 downto i*2));
1368 
    end generate;
1369 
  end generate;
1370 
 
1371 
  a13 : if (abits = 13) generate
1372 
    x : for i in 0 to ((dbits-1)/1) generate
1373 
      r : EC_RAMB8_S1 port map ( clk, enable, write, xa(12 downto 0),
1374 
        di((i+1)*1-1 downto i*1), do((i+1)*1-1 downto i*1));
1375 
    end generate;
1376 
  end generate;
1377 
 
1378 
  -- pragma translate_off
1379 
  unsup : if (abits > 13) generate
1380 
    x : process
1381 
    begin
1382 
      assert false
1383 
        report "Lattice EC syncram mapper: unsupported memory configuration!"
1384 
        severity failure;
1385 
      wait;
1386 
    end process;
1387 
  end generate;
1388 
  -- pragma translate_on
1389 
 
1390 
end;
1391 
 
1392 
 
1393 
 
1394 
library ieee;
1395 
use ieee.std_logic_1164.all;
1396 
library techmap;
1397 
 
1398 
entity ec_syncram_dp is
1399 
  generic (
1400 
    abits : integer := 4; dbits : integer := 32
1401 
    );
1402 
  port (
1403 
    clk1     : in  std_ulogic;
1404 
    address1 : in  std_logic_vector((abits -1) downto 0);
1405 
    datain1  : in  std_logic_vector((dbits -1) downto 0);
1406 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
1407 
    enable1  : in  std_ulogic;
1408 
    write1   : in  std_ulogic;
1409 
    clk2     : in  std_ulogic;
1410 
    address2 : in  std_logic_vector((abits -1) downto 0);
1411 
    datain2  : in  std_logic_vector((dbits -1) downto 0);
1412 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
1413 
    enable2  : in  std_ulogic;
1414 
    write2   : in  std_ulogic);
1415 
end;
1416 
 
1417 
architecture behav of ec_syncram_dp is
1418 
  component EC_RAMB8_S1_S1 is port (
1419 
    DataInA, DataInB: in  std_logic_vector(0 downto 0);
1420 
    AddressA, AddressB: in  std_logic_vector(12 downto 0);
1421 
    ClockA, ClockB: in  std_logic;
1422 
    ClockEnA, ClockEnB: in  std_logic;
1423 
    WrA, WrB: in  std_logic;
1424 
    QA, QB: out  std_logic_vector(0 downto 0));
1425 
  end component;
1426 
  component EC_RAMB8_S2_S2 is port (
1427 
    DataInA, DataInB: in  std_logic_vector(1 downto 0);
1428 
    AddressA, AddressB: in  std_logic_vector(11 downto 0);
1429 
    ClockA, ClockB: in  std_logic;
1430 
    ClockEnA, ClockEnB: in  std_logic;
1431 
    WrA, WrB: in  std_logic;
1432 
    QA, QB: out  std_logic_vector(1 downto 0));
1433 
  end component;
1434 
  component EC_RAMB8_S4_S4 is port (
1435 
    DataInA, DataInB: in  std_logic_vector(3 downto 0);
1436 
    AddressA, AddressB: in  std_logic_vector(10 downto 0);
1437 
    ClockA, ClockB: in  std_logic;
1438 
    ClockEnA, ClockEnB: in  std_logic;
1439 
    WrA, WrB: in  std_logic;
1440 
    QA, QB: out  std_logic_vector(3 downto 0));
1441 
  end component;
1442 
  component EC_RAMB8_S9_S9 is port (
1443 
    DataInA, DataInB: in  std_logic_vector(8 downto 0);
1444 
    AddressA, AddressB: in  std_logic_vector(9 downto 0);
1445 
    ClockA, ClockB: in  std_logic;
1446 
    ClockEnA, ClockEnB: in  std_logic;
1447 
    WrA, WrB: in  std_logic;
1448 
    QA, QB: out  std_logic_vector(8 downto 0));
1449 
  end component;
1450 
  component EC_RAMB8_S18_S18 is port (
1451 
    DataInA, DataInB: in  std_logic_vector(17 downto 0);
1452 
    AddressA, AddressB: in  std_logic_vector(8 downto 0);
1453 
    ClockA, ClockB: in  std_logic;
1454 
    ClockEnA, ClockEnB: in  std_logic;
1455 
    WrA, WrB: in  std_logic;
1456 
    QA, QB: out  std_logic_vector(17 downto 0));
1457 
  end component;
1458 
constant DMAX : integer := dbits+18;
1459 
constant AMAX : integer := 13;
1460 
signal gnd, vcc : std_ulogic;
1461 
signal do1, do2, di1, di2 : std_logic_vector(DMAX downto 0);
1462 
signal addr1, addr2 : std_logic_vector(AMAX downto 0);
1463 
begin
1464 
  gnd <= '0'; vcc <= '1';
1465 
  dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
1466 
  di1(dbits-1 downto 0) <= datain1; di1(DMAX downto dbits) <= (others => '0');
1467 
  di2(dbits-1 downto 0) <= datain2; di2(DMAX downto dbits) <= (others => '0');
1468 
  addr1(abits-1 downto 0) <= address1; addr1(AMAX downto abits) <= (others => '0');
1469 
  addr2(abits-1 downto 0) <= address2; addr2(AMAX downto abits) <= (others => '0');
1470 
 
1471 
  a9 : if abits <= 9 generate
1472 
    x : for i in 0 to ((dbits-1)/18) generate
1473 
      r0 : EC_RAMB8_S18_S18 port map (
1474 
        di1((i+1)*18-1 downto i*18), di2((i+1)*18-1 downto i*18),
1475 
        addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
1476 
        enable1, enable2, write1, write2,
1477 
        do1((i+1)*18-1 downto i*18), do2((i+1)*18-1 downto i*18));
1478 
    end generate;
1479 
  end generate;
1480 
  a10 : if abits = 10 generate
1481 
    x : for i in 0 to ((dbits-1)/9) generate
1482 
      r0 : EC_RAMB8_S9_S9 port map (
1483 
        di1((i+1)*9-1 downto i*9), di2((i+1)*9-1 downto i*9),
1484 
        addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
1485 
        enable1, enable2, write1, write2,
1486 
        do1((i+1)*9-1 downto i*9), do2((i+1)*9-1 downto i*9));
1487 
    end generate;
1488 
  end generate;
1489 
  a11 : if abits = 11 generate
1490 
    x : for i in 0 to ((dbits-1)/4) generate
1491 
      r0 : EC_RAMB8_S4_S4 port map (
1492 
        di1((i+1)*4-1 downto i*4), di2((i+1)*4-1 downto i*4),
1493 
        addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
1494 
        enable1, enable2, write1, write2,
1495 
        do1((i+1)*4-1 downto i*4), do2((i+1)*4-1 downto i*4));
1496 
    end generate;
1497 
  end generate;
1498 
  a12 : if abits = 12 generate
1499 
    x : for i in 0 to ((dbits-1)/2) generate
1500 
      r0 : EC_RAMB8_S2_S2 port map (
1501 
        di1((i+1)*2-1 downto i*2), di2((i+1)*2-1 downto i*2),
1502 
        addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
1503 
        enable1, enable2, write1, write2,
1504 
        do1((i+1)*2-1 downto i*2), do2((i+1)*2-1 downto i*2));
1505 
    end generate;
1506 
  end generate;
1507 
  a13 : if abits = 13 generate
1508 
    x : for i in 0 to ((dbits-1)/1) generate
1509 
      r0 : EC_RAMB8_S1_S1 port map (
1510 
        di1((i+1)*1-1 downto i*1), di2((i+1)*1-1 downto i*1),
1511 
        addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
1512 
        enable1, enable2, write1, write2,
1513 
        do1((i+1)*1-1 downto i*1), do2((i+1)*1-1 downto i*1));
1514 
    end generate;
1515 
  end generate;
1516 
 
1517 
  -- pragma translate_off
1518 
  unsup : if (abits > 13) generate
1519 
    x : process
1520 
    begin
1521 
      assert false
1522 
        report "Lattice EC syncram_dp: unsupported memory configuration!"
1523 
        severity failure;
1524 
      wait;
1525 
    end process;
1526 
  end generate;
1527 
  -- pragma translate_on
1528 
 
1529 
end;
1530 
 

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