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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [gencomp/] [clkgen.in] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali
    choice 'Clock generator                     ' \
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        "Inferred               CONFIG_CLK_INFERRED \
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        Actel-HCLKBUF           CONFIG_CLK_HCLKBUF \
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        Altera-ALTPLL           CONFIG_CLK_ALTDLL \
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        Lattice-EXPLL           CONFIG_CLK_LATDLL \
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        RH-LIB18T-PLL           CONFIG_CLK_LIB18T \
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        Xilinx-CLKDLL           CONFIG_CLK_CLKDLL \
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        Xilinx-DCM              CONFIG_CLK_DCM" Inferred
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    if [ "$CONFIG_CLK_DCM" = "y" -o "$CONFIG_CLK_ALTDLL" = "y" \
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                                 -o "$CONFIG_CLK_LATDLL" = "y" \
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        -o "$CONFIG_CLK_CLKDLL" = "y" -o "$CONFIG_CLK_LIB18T" = "y"]; then
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      int 'Clock multiplication factor (2 - 32)' CONFIG_CLK_MUL 2
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      int 'Clock division factor (2 - 32)' CONFIG_CLK_DIV 2
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    fi
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    if [ "$CONFIG_CLK_CLKDLL" = "y" -o "$CONFIG_CLK_DCM" = "y" ]; then
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      bool 'Enable Xilinx CLKDLL for PCI clock' CONFIG_PCI_CLKDLL
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    fi
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    if [ "$CONFIG_CLK_DCM" = "y" ]; then
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      bool 'Disable external feedback for SDRAM clock' CONFIG_CLK_NOFB
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    fi
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  if [ "$CONFIG_PCI_ENABLE" != "y" ]; then
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    bool 'Use PCI clock as system clock' CONFIG_PCI_SYSCLK
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  fi

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