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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: gencomp
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-- File: gencomp.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Declaration of portable memory modules
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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package gencomp is
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---------------------------------------------------------------------------
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-- BASIC DECLARATIONS
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---------------------------------------------------------------------------
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-- technologies and libraries
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constant NTECH : integer := 31;
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type tech_ability_type is array (0 to NTECH) of integer;
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constant inferred : integer := 0;
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constant virtex : integer := 1;
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constant virtex2 : integer := 2;
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constant memvirage : integer := 3;
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constant axcel : integer := 4;
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constant proasic : integer := 5;
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constant atc18s : integer := 6;
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constant altera : integer := 7;
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constant umc : integer := 8;
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constant rhumc : integer := 9;
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constant apa3 : integer := 10;
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constant spartan3 : integer := 11;
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constant ihp25 : integer := 12;
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constant rhlib18t : integer := 13;
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constant virtex4 : integer := 14;
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constant lattice : integer := 15;
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constant ut25 : integer := 16;
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constant spartan3e : integer := 17;
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constant peregrine : integer := 18;
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constant memartisan : integer := 19;
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constant virtex5 : integer := 20;
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constant custom1 : integer := 21;
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constant ihp25rh : integer := 22;
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constant stratix1 : integer := 23;
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constant stratix2 : integer := 24;
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constant eclipse : integer := 25;
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constant stratix3 : integer := 26;
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constant cyclone3 : integer := 27;
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constant memvirage90 : integer := 28;
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constant tsmc90 : integer := 29;
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constant easic90 : integer := 30;
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constant atc18rha : integer := 31;
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constant DEFMEMTECH : integer := inferred;
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constant DEFPADTECH : integer := inferred;
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constant DEFFABTECH : integer := inferred;
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constant is_fpga : tech_ability_type :=
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(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
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proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
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virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
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stratix1 => 1, stratix2 => 1, eclipse => 1,
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stratix3 => 1, cyclone3 => 1, others => 0);
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constant infer_mul : tech_ability_type := is_fpga;
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constant syncram_2p_write_through : tech_ability_type :=
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(inferred => 0, virtex => 0, virtex2 => 1, memvirage => 0,
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axcel => 0, proasic => 0, atc18s => 0, altera => 0,
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umc => 0, rhumc => 1, apa3 => 0, spartan3 => 1,
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ihp25 => 0, rhlib18t => 0, virtex4 => 1, lattice => 0,
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ut25 => 0, spartan3e => 1, virtex5 => 1, eclipse => 1,
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memvirage90 => 0, atc18rha => 0, others => 0);
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constant regfile_3p_write_through : tech_ability_type :=
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(inferred => 0, virtex => 0, virtex2 => 1, memvirage => 0,
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axcel => 0, proasic => 0, atc18s => 0, altera => 0,
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umc => 0, rhumc => 1, apa3 => 0, spartan3 => 1,
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ihp25 => 1, rhlib18t => 0, virtex4 => 1, lattice => 0,
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ut25 => 0, spartan3e => 1, virtex5 => 1, ihp25rh => 1,
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eclipse => 1, memvirage90 => 0, atc18rha => 0, others => 0);
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constant regfile_3p_infer : tech_ability_type :=
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(inferred => 1, rhumc => 1, ihp25 => 1, rhlib18t => 0,
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peregrine => 1, ihp25rh => 1, umc => 1, others => 0);
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constant syncram_2p_dest_rw_collision : tech_ability_type :=
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(memartisan => 1, others => 0);
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constant syncram_dp_dest_rw_collision : tech_ability_type :=
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(memartisan => 1, others => 0);
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constant has_sram : tech_ability_type :=
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(inferred => 1, virtex => 1, virtex2 => 1, memvirage => 1,
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axcel => 1, proasic => 1, atc18s => 0, altera => 1,
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umc => 1, rhumc => 1, apa3 => 1, spartan3 => 1,
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ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 1,
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ut25 => 1, spartan3e => 1, virtex5 => 1, eclipse => 1,
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memvirage90 => 1, atc18rha => 1, others => 1);
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constant has_2pram : tech_ability_type :=
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( atc18s => 0, umc => 0, rhumc => 0, ihp25 => 0, others => 1);
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constant has_dpram : tech_ability_type :=
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(virtex => 1, virtex2 => 1, memvirage => 1, axcel => 1,
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altera => 1, apa3 => 1, spartan3 => 1, virtex4 => 1,
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lattice => 1, spartan3e => 1, memartisan => 1, virtex5 => 1,
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custom1 => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
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cyclone3 => 1, memvirage90 => 1, atc18rha => 1, others => 0);
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constant has_sram64 : tech_ability_type :=
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(inferred => 0, virtex2 => 1, spartan3 => 1, virtex4 => 1,
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spartan3e => 1, memartisan => 1, virtex5 => 1,
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custom1 => 0, others => 0);
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constant padoen_polarity : tech_ability_type :=
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(inferred => 0, virtex => 0, virtex2 => 0, memvirage => 0,
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axcel => 1, proasic => 1, atc18s => 0, altera => 0,
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umc => 1, rhumc => 1, spartan3 => 0, apa3 => 1,
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ihp25 => 1, rhlib18t => 0, virtex4 => 0, lattice => 0,
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ut25 => 1, spartan3e => 0, peregrine => 1, easic90 => 1,
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others => 0);
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constant has_pads : tech_ability_type :=
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(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
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axcel => 1, proasic => 1, atc18s => 1, altera => 0,
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umc => 1, rhumc => 1, apa3 => 1, spartan3 => 1,
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ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 0,
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ut25 => 1, spartan3e => 1, peregrine => 1, virtex5 => 1,
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easic90 => 1, atc18rha => 1, others => 0);
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constant has_ds_pads : tech_ability_type :=
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(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
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axcel => 1, proasic => 0, atc18s => 0, altera => 0,
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umc => 0, rhumc => 0, apa3 => 0, spartan3 => 1,
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ihp25 => 0, rhlib18t => 1, virtex4 => 1, lattice => 0,
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ut25 => 1, spartan3e => 1, virtex5 => 1, others => 0);
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constant has_ds_combo : tech_ability_type :=
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( rhumc => 1, ut25 => 1, others => 0);
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constant has_clkand : tech_ability_type :=
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( virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
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virtex5 => 1, ut25 => 1, others => 0);
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constant has_clkmux : tech_ability_type :=
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( virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
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virtex5 => 1, others => 0);
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constant has_techbuf : tech_ability_type :=
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( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
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spartan3 => 1, spartan3e => 1, axcel => 1, ut25 => 1,
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apa3 => 1, others => 0);
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constant has_tapsel : tech_ability_type :=
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( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
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spartan3 => 1, spartan3e => 1, others => 0);
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constant need_extra_sync_reset : tech_ability_type :=
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(axcel => 1, atc18s => 1, ut25 => 1, rhumc => 1, tsmc90 => 1,
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rhlib18t => 1, atc18rha => 1, others => 0);
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-- pragma translate_off
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subtype tech_description is string(1 to 10);
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type tech_table_type is array (0 to NTECH) of tech_description;
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constant tech_table : tech_table_type := (
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inferred => "inferred ", virtex => "virtex ",
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virtex2 => "virtex2 ", memvirage => "virage ",
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axcel => "axcel ", proasic => "proasic ",
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atc18s => "atc18s ", altera => "altera ",
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umc => "umc18 ", rhumc => "rhumc ",
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apa3 => "proasic3 ", spartan3 => "spartan3 ",
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ihp25 => "ihp25 ", rhlib18t => "rhlib18t ",
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virtex4 => "virtex4 ", lattice => "lattice ",
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ut25 => "ut025crh ", spartan3e => "spartan3e ",
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peregrine => "peregrine ", memartisan => "artisan ",
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virtex5 => "virtex5 ", custom1 => "custom1 ",
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ihp25rh => "ihp25rh ", stratix1 => "stratix ",
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stratix2 => "stratixii ", eclipse => "eclipse ",
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stratix3 => "stratixiii", cyclone3 => "cycloneiii",
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memvirage90 => "virage90 ", tsmc90 => "tsmc90 ",
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easic90 => "nextreme ", atc18rha => "atc18rha "
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);
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-- pragma translate_on
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-- input/output voltage
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constant x18v : integer := 1;
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constant x25v : integer := 2;
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constant x33v : integer := 3;
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constant x50v : integer := 5;
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-- input/output levels
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constant ttl : integer := 0;
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constant cmos : integer := 1;
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constant pci33 : integer := 2;
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constant pci66 : integer := 3;
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constant lvds : integer := 4;
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constant sstl2_i : integer := 5;
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constant sstl2_ii : integer := 6;
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constant sstl3_i : integer := 7;
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constant sstl3_ii : integer := 8;
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constant sstl18_i : integer := 9;
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constant sstl18_ii: integer := 10;
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-- pad types
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constant normal : integer := 0;
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constant pullup : integer := 1;
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constant pulldown : integer := 2;
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constant opendrain: integer := 3;
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constant schmitt : integer := 4;
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constant dci : integer := 5;
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---------------------------------------------------------------------------
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-- MEMORY
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---------------------------------------------------------------------------
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-- synchronous single-port ram
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component syncram
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generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8);
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port (
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clk : in std_ulogic;
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address : in std_logic_vector((abits -1) downto 0);
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datain : in std_logic_vector((dbits -1) downto 0);
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dataout : out std_logic_vector((dbits -1) downto 0);
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enable : in std_ulogic;
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write : in std_ulogic;
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testin : in std_logic_vector(3 downto 0) := "0000");
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end component;
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-- synchronous two-port ram (1 read, 1 write port)
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component syncram_2p
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generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
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wrfst : integer := 0);
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port (
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rclk : in std_ulogic;
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renable : in std_ulogic;
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raddress : in std_logic_vector((abits -1) downto 0);
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dataout : out std_logic_vector((dbits -1) downto 0);
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wclk : in std_ulogic;
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write : in std_ulogic;
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waddress : in std_logic_vector((abits -1) downto 0);
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datain : in std_logic_vector((dbits -1) downto 0);
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testin : in std_logic_vector(3 downto 0) := "0000");
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end component;
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-- synchronous dual-port ram (2 read/write ports)
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component syncram_dp
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generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8);
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port (
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clk1 : in std_ulogic;
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address1 : in std_logic_vector((abits -1) downto 0);
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datain1 : in std_logic_vector((dbits -1) downto 0);
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dataout1 : out std_logic_vector((dbits -1) downto 0);
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enable1 : in std_ulogic;
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write1 : in std_ulogic;
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clk2 : in std_ulogic;
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address2 : in std_logic_vector((abits -1) downto 0);
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datain2 : in std_logic_vector((dbits -1) downto 0);
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dataout2 : out std_logic_vector((dbits -1) downto 0);
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enable2 : in std_ulogic;
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write2 : in std_ulogic;
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testin : in std_logic_vector(3 downto 0) := "0000");
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end component;
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-- synchronous 3-port regfile (2 read, 1 write port)
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component regfile_3p
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generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
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wrfst : integer := 0; numregs : integer := 64);
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port (
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wclk : in std_ulogic;
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| 298 |
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waddr : in std_logic_vector((abits -1) downto 0);
|
| 299 |
|
|
wdata : in std_logic_vector((dbits -1) downto 0);
|
| 300 |
|
|
we : in std_ulogic;
|
| 301 |
|
|
rclk : in std_ulogic;
|
| 302 |
|
|
raddr1 : in std_logic_vector((abits -1) downto 0);
|
| 303 |
|
|
re1 : in std_ulogic;
|
| 304 |
|
|
rdata1 : out std_logic_vector((dbits -1) downto 0);
|
| 305 |
|
|
raddr2 : in std_logic_vector((abits -1) downto 0);
|
| 306 |
|
|
re2 : in std_ulogic;
|
| 307 |
|
|
rdata2 : out std_logic_vector((dbits -1) downto 0);
|
| 308 |
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
| 309 |
|
|
end component;
|
| 310 |
|
|
|
| 311 |
|
|
-- 64-bit synchronous single-port ram with 32-bit write strobe
|
| 312 |
|
|
component syncram64
|
| 313 |
|
|
generic (tech : integer := 0; abits : integer := 6);
|
| 314 |
|
|
port (
|
| 315 |
|
|
clk : in std_ulogic;
|
| 316 |
|
|
address : in std_logic_vector (abits -1 downto 0);
|
| 317 |
|
|
datain : in std_logic_vector (63 downto 0);
|
| 318 |
|
|
dataout : out std_logic_vector (63 downto 0);
|
| 319 |
|
|
enable : in std_logic_vector (1 downto 0);
|
| 320 |
|
|
write : in std_logic_vector (1 downto 0);
|
| 321 |
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
| 322 |
|
|
end component;
|
| 323 |
|
|
|
| 324 |
|
|
component syncramft
|
| 325 |
|
|
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
|
| 326 |
|
|
ft : integer range 0 to 2 := 0 );
|
| 327 |
|
|
port (
|
| 328 |
|
|
clk : in std_ulogic;
|
| 329 |
|
|
address : in std_logic_vector((abits -1) downto 0);
|
| 330 |
|
|
datain : in std_logic_vector((dbits -1) downto 0);
|
| 331 |
|
|
dataout : out std_logic_vector((dbits -1) downto 0);
|
| 332 |
|
|
write : in std_ulogic;
|
| 333 |
|
|
enable : in std_ulogic;
|
| 334 |
|
|
error : out std_logic_vector((dbits + 7) / 8 downto 0);
|
| 335 |
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
| 336 |
|
|
end component;
|
| 337 |
|
|
|
| 338 |
|
|
component syncram_2pft
|
| 339 |
|
|
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
|
| 340 |
|
|
sepclk : integer := 0; wrfst : integer := 0; ft : integer := 0);
|
| 341 |
|
|
port (
|
| 342 |
|
|
rclk : in std_ulogic;
|
| 343 |
|
|
renable : in std_ulogic;
|
| 344 |
|
|
raddress : in std_logic_vector((abits -1) downto 0);
|
| 345 |
|
|
dataout : out std_logic_vector((dbits -1) downto 0);
|
| 346 |
|
|
wclk : in std_ulogic;
|
| 347 |
|
|
write : in std_ulogic;
|
| 348 |
|
|
waddress : in std_logic_vector((abits -1) downto 0);
|
| 349 |
|
|
datain : in std_logic_vector((dbits -1) downto 0);
|
| 350 |
|
|
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
|
| 351 |
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
| 352 |
|
|
end component;
|
| 353 |
|
|
|
| 354 |
|
|
component syncfifo
|
| 355 |
|
|
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
|
| 356 |
|
|
sepclk : integer := 0; wrfst : integer := 0);
|
| 357 |
|
|
port (
|
| 358 |
|
|
rst : in std_ulogic;
|
| 359 |
|
|
rclk : in std_ulogic;
|
| 360 |
|
|
renable : in std_ulogic;
|
| 361 |
|
|
dataout : out std_logic_vector((dbits -1) downto 0);
|
| 362 |
|
|
wclk : in std_ulogic;
|
| 363 |
|
|
write : in std_ulogic;
|
| 364 |
|
|
datain : in std_logic_vector((dbits -1) downto 0);
|
| 365 |
|
|
full : out std_ulogic;
|
| 366 |
|
|
empty : out std_ulogic
|
| 367 |
|
|
);
|
| 368 |
|
|
end component;
|
| 369 |
|
|
|
| 370 |
|
|
|
| 371 |
|
|
---------------------------------------------------------------------------
|
| 372 |
|
|
-- PADS
|
| 373 |
|
|
---------------------------------------------------------------------------
|
| 374 |
|
|
|
| 375 |
|
|
component inpad
|
| 376 |
|
|
generic (tech : integer := 0; level : integer := 0;
|
| 377 |
|
|
voltage : integer := x33v; filter : integer := 0;
|
| 378 |
|
|
strength : integer := 0);
|
| 379 |
|
|
port (pad : in std_ulogic; o : out std_ulogic);
|
| 380 |
|
|
end component;
|
| 381 |
|
|
|
| 382 |
|
|
component inpadv
|
| 383 |
|
|
generic (tech : integer := 0; level : integer := 0;
|
| 384 |
|
|
voltage : integer := x33v; width : integer := 1);
|
| 385 |
|
|
port (
|
| 386 |
|
|
pad : in std_logic_vector(width-1 downto 0);
|
| 387 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
| 388 |
|
|
end component;
|
| 389 |
|
|
|
| 390 |
|
|
component iopad
|
| 391 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 392 |
|
|
voltage : integer := x33v; strength : integer := 12;
|
| 393 |
|
|
oepol : integer := 0);
|
| 394 |
|
|
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
| 395 |
|
|
end component;
|
| 396 |
|
|
|
| 397 |
|
|
component iopadv
|
| 398 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 399 |
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
| 400 |
|
|
oepol : integer := 0);
|
| 401 |
|
|
port (
|
| 402 |
|
|
pad : inout std_logic_vector(width-1 downto 0);
|
| 403 |
|
|
i : in std_logic_vector(width-1 downto 0);
|
| 404 |
|
|
en : in std_ulogic;
|
| 405 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
| 406 |
|
|
end component;
|
| 407 |
|
|
|
| 408 |
|
|
component iopadvv is
|
| 409 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 410 |
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
| 411 |
|
|
oepol : integer := 0);
|
| 412 |
|
|
port (
|
| 413 |
|
|
pad : inout std_logic_vector(width-1 downto 0);
|
| 414 |
|
|
i : in std_logic_vector(width-1 downto 0);
|
| 415 |
|
|
en : in std_logic_vector(width-1 downto 0);
|
| 416 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
| 417 |
|
|
end component;
|
| 418 |
|
|
|
| 419 |
|
|
component iodpad
|
| 420 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 421 |
|
|
voltage : integer := x33v; strength : integer := 12;
|
| 422 |
|
|
oepol : integer := 0);
|
| 423 |
|
|
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
|
| 424 |
|
|
end component;
|
| 425 |
|
|
|
| 426 |
|
|
component iodpadv
|
| 427 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 428 |
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
| 429 |
|
|
oepol : integer := 0);
|
| 430 |
|
|
port (
|
| 431 |
|
|
pad : inout std_logic_vector(width-1 downto 0);
|
| 432 |
|
|
i : in std_logic_vector(width-1 downto 0);
|
| 433 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
| 434 |
|
|
end component;
|
| 435 |
|
|
|
| 436 |
|
|
component outpad
|
| 437 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 438 |
|
|
voltage : integer := x33v; strength : integer := 12);
|
| 439 |
|
|
port (pad : out std_ulogic; i : in std_ulogic);
|
| 440 |
|
|
end component;
|
| 441 |
|
|
|
| 442 |
|
|
component outpadv
|
| 443 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 444 |
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1);
|
| 445 |
|
|
port (
|
| 446 |
|
|
pad : out std_logic_vector(width-1 downto 0);
|
| 447 |
|
|
i : in std_logic_vector(width-1 downto 0));
|
| 448 |
|
|
end component;
|
| 449 |
|
|
|
| 450 |
|
|
component odpad
|
| 451 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 452 |
|
|
voltage : integer := x33v; strength : integer := 12;
|
| 453 |
|
|
oepol : integer := 0);
|
| 454 |
|
|
port (pad : out std_ulogic; i : in std_ulogic);
|
| 455 |
|
|
end component;
|
| 456 |
|
|
|
| 457 |
|
|
component odpadv
|
| 458 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 459 |
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
| 460 |
|
|
oepol : integer := 0);
|
| 461 |
|
|
port (
|
| 462 |
|
|
pad : out std_logic_vector(width-1 downto 0);
|
| 463 |
|
|
i : in std_logic_vector(width-1 downto 0));
|
| 464 |
|
|
end component;
|
| 465 |
|
|
|
| 466 |
|
|
component toutpad
|
| 467 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 468 |
|
|
voltage : integer := x33v; strength : integer := 12;
|
| 469 |
|
|
oepol : integer := 0);
|
| 470 |
|
|
port (pad : out std_ulogic; i, en : in std_ulogic);
|
| 471 |
|
|
end component;
|
| 472 |
|
|
|
| 473 |
|
|
component toutpadv
|
| 474 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 475 |
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
| 476 |
|
|
oepol : integer := 0);
|
| 477 |
|
|
port (
|
| 478 |
|
|
pad : out std_logic_vector(width-1 downto 0);
|
| 479 |
|
|
i : in std_logic_vector(width-1 downto 0);
|
| 480 |
|
|
en : in std_ulogic);
|
| 481 |
|
|
end component;
|
| 482 |
|
|
|
| 483 |
|
|
component toutpadvv is
|
| 484 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 485 |
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
| 486 |
|
|
oepol : integer := 0);
|
| 487 |
|
|
port (
|
| 488 |
|
|
pad : out std_logic_vector(width-1 downto 0);
|
| 489 |
|
|
i : in std_logic_vector(width-1 downto 0);
|
| 490 |
|
|
en : in std_logic_vector(width-1 downto 0));
|
| 491 |
|
|
end component;
|
| 492 |
|
|
|
| 493 |
|
|
component skew_outpad
|
| 494 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 495 |
|
|
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
|
| 496 |
|
|
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
|
| 497 |
|
|
o : out std_ulogic);
|
| 498 |
|
|
end component;
|
| 499 |
|
|
|
| 500 |
|
|
component clkpad
|
| 501 |
|
|
generic (tech : integer := 0; level : integer := 0;
|
| 502 |
|
|
voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
|
| 503 |
|
|
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
|
| 504 |
|
|
end component;
|
| 505 |
|
|
|
| 506 |
|
|
component inpad_ds
|
| 507 |
|
|
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
|
| 508 |
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic);
|
| 509 |
|
|
end component;
|
| 510 |
|
|
|
| 511 |
|
|
component clkpad_ds
|
| 512 |
|
|
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
|
| 513 |
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic);
|
| 514 |
|
|
end component;
|
| 515 |
|
|
|
| 516 |
|
|
component inpad_dsv
|
| 517 |
|
|
generic (tech : integer := 0; level : integer := lvds;
|
| 518 |
|
|
voltage : integer := x33v; width : integer := 1);
|
| 519 |
|
|
port (
|
| 520 |
|
|
padp : in std_logic_vector(width-1 downto 0);
|
| 521 |
|
|
padn : in std_logic_vector(width-1 downto 0);
|
| 522 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
| 523 |
|
|
end component;
|
| 524 |
|
|
|
| 525 |
|
|
component iopad_ds
|
| 526 |
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
| 527 |
|
|
voltage : integer := x33v; strength : integer := 12;
|
| 528 |
|
|
oepol : integer := 0);
|
| 529 |
|
|
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
| 530 |
|
|
end component;
|
| 531 |
|
|
|
| 532 |
|
|
component outpad_ds
|
| 533 |
|
|
generic (tech : integer := 0; level : integer := lvds;
|
| 534 |
|
|
voltage : integer := x33v; oepol : integer := 0);
|
| 535 |
|
|
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
|
| 536 |
|
|
end component;
|
| 537 |
|
|
|
| 538 |
|
|
component outpad_dsv
|
| 539 |
|
|
generic (tech : integer := 0; level : integer := lvds;
|
| 540 |
|
|
voltage : integer := x33v; width : integer := 1);
|
| 541 |
|
|
port (
|
| 542 |
|
|
padp : out std_logic_vector(width-1 downto 0);
|
| 543 |
|
|
padn : out std_logic_vector(width-1 downto 0);
|
| 544 |
|
|
i, en: in std_logic_vector(width-1 downto 0));
|
| 545 |
|
|
end component;
|
| 546 |
|
|
|
| 547 |
|
|
component lvds_combo is
|
| 548 |
|
|
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
|
| 549 |
|
|
oepol : integer := 0);
|
| 550 |
|
|
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
|
| 551 |
|
|
odval, osval, en : in std_logic_vector(0 to width-1);
|
| 552 |
|
|
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
|
| 553 |
|
|
idval, isval : out std_logic_vector(0 to width-1);
|
| 554 |
|
|
lvdsref : in std_logic := '1'
|
| 555 |
|
|
);
|
| 556 |
|
|
end component;
|
| 557 |
|
|
|
| 558 |
|
|
---------------------------------------------------------------------------
|
| 559 |
|
|
-- BUFFERS
|
| 560 |
|
|
---------------------------------------------------------------------------
|
| 561 |
|
|
|
| 562 |
|
|
component techbuf is
|
| 563 |
|
|
generic(
|
| 564 |
|
|
buftype : integer range 0 to 4 := 0;
|
| 565 |
|
|
tech : integer range 0 to NTECH := inferred);
|
| 566 |
|
|
port(
|
| 567 |
|
|
i : in std_ulogic;
|
| 568 |
|
|
o : out std_ulogic
|
| 569 |
|
|
);
|
| 570 |
|
|
end component;
|
| 571 |
|
|
|
| 572 |
|
|
---------------------------------------------------------------------------
|
| 573 |
|
|
-- CLOCK GENERATION
|
| 574 |
|
|
---------------------------------------------------------------------------
|
| 575 |
|
|
|
| 576 |
|
|
type clkgen_in_type is record
|
| 577 |
|
|
pllref : std_logic; -- optional reference for PLL
|
| 578 |
|
|
pllrst : std_logic; -- optional reset for PLL
|
| 579 |
|
|
pllctrl : std_logic_vector(1 downto 0); -- optional control for PLL
|
| 580 |
|
|
clksel : std_logic_vector(1 downto 0); -- optional clock select
|
| 581 |
|
|
end record;
|
| 582 |
|
|
|
| 583 |
|
|
type clkgen_out_type is record
|
| 584 |
|
|
clklock : std_logic;
|
| 585 |
|
|
pcilock : std_logic;
|
| 586 |
|
|
end record;
|
| 587 |
|
|
|
| 588 |
|
|
component clkgen
|
| 589 |
|
|
generic (
|
| 590 |
|
|
tech : integer := DEFFABTECH;
|
| 591 |
|
|
clk_mul : integer := 1;
|
| 592 |
|
|
clk_div : integer := 1;
|
| 593 |
|
|
sdramen : integer := 0;
|
| 594 |
|
|
noclkfb : integer := 1;
|
| 595 |
|
|
pcien : integer := 0;
|
| 596 |
|
|
pcidll : integer := 0;
|
| 597 |
|
|
pcisysclk: integer := 0;
|
| 598 |
|
|
freq : integer := 25000;
|
| 599 |
|
|
clk2xen : integer := 0;
|
| 600 |
|
|
clksel : integer := 0; -- enable clock select
|
| 601 |
|
|
clk_odiv : integer := 0); -- Proasic3 output divider
|
| 602 |
|
|
port (
|
| 603 |
|
|
clkin : in std_logic;
|
| 604 |
|
|
pciclkin: in std_logic;
|
| 605 |
|
|
clk : out std_logic; -- main clock
|
| 606 |
|
|
clkn : out std_logic; -- inverted main clock
|
| 607 |
|
|
clk2x : out std_logic; -- 2x clock
|
| 608 |
|
|
sdclk : out std_logic; -- SDRAM clock
|
| 609 |
|
|
pciclk : out std_logic; -- PCI clock
|
| 610 |
|
|
cgi : in clkgen_in_type;
|
| 611 |
|
|
cgo : out clkgen_out_type;
|
| 612 |
|
|
clk4x : out std_logic; -- 4x clock
|
| 613 |
|
|
clk1xu : out std_logic; -- unscaled 1X clock
|
| 614 |
|
|
clk2xu : out std_logic); -- unscaled 2X clock
|
| 615 |
|
|
end component;
|
| 616 |
|
|
|
| 617 |
|
|
component clkand
|
| 618 |
|
|
generic( tech : integer := 0;
|
| 619 |
|
|
ren : integer range 0 to 1 := 0); -- registered enable
|
| 620 |
|
|
port(
|
| 621 |
|
|
i : in std_ulogic;
|
| 622 |
|
|
en : in std_ulogic;
|
| 623 |
|
|
o : out std_ulogic
|
| 624 |
|
|
);
|
| 625 |
|
|
end component;
|
| 626 |
|
|
|
| 627 |
|
|
component clkmux
|
| 628 |
|
|
generic( tech : integer := 0;
|
| 629 |
|
|
rsel : integer range 0 to 1 := 0); -- registered sel
|
| 630 |
|
|
port(
|
| 631 |
|
|
i0, i1 : in std_ulogic;
|
| 632 |
|
|
sel : in std_ulogic;
|
| 633 |
|
|
o : out std_ulogic;
|
| 634 |
|
|
rst : in std_ulogic := '1'
|
| 635 |
|
|
);
|
| 636 |
|
|
end component;
|
| 637 |
|
|
|
| 638 |
|
|
|
| 639 |
|
|
|
| 640 |
|
|
|
| 641 |
|
|
---------------------------------------------------------------------------
|
| 642 |
|
|
-- TAP controller
|
| 643 |
|
|
---------------------------------------------------------------------------
|
| 644 |
|
|
|
| 645 |
|
|
component tap
|
| 646 |
|
|
generic (
|
| 647 |
|
|
tech : integer := 0;
|
| 648 |
|
|
irlen : integer range 2 to 8 := 4;
|
| 649 |
|
|
idcode : integer range 0 to 255 := 9;
|
| 650 |
|
|
manf : integer range 0 to 2047 := 804;
|
| 651 |
|
|
part : integer range 0 to 65535 := 0;
|
| 652 |
|
|
ver : integer range 0 to 15 := 0;
|
| 653 |
|
|
trsten : integer range 0 to 1 := 1;
|
| 654 |
|
|
scantest : integer := 0);
|
| 655 |
|
|
port (
|
| 656 |
|
|
trst : in std_ulogic;
|
| 657 |
|
|
tck : in std_ulogic;
|
| 658 |
|
|
tms : in std_ulogic;
|
| 659 |
|
|
tdi : in std_ulogic;
|
| 660 |
|
|
tdo : out std_ulogic;
|
| 661 |
|
|
tapo_tck : out std_ulogic;
|
| 662 |
|
|
tapo_tdi : out std_ulogic;
|
| 663 |
|
|
tapo_inst : out std_logic_vector(7 downto 0);
|
| 664 |
|
|
tapo_rst : out std_ulogic;
|
| 665 |
|
|
tapo_capt : out std_ulogic;
|
| 666 |
|
|
tapo_shft : out std_ulogic;
|
| 667 |
|
|
tapo_upd : out std_ulogic;
|
| 668 |
|
|
tapo_xsel1 : out std_ulogic;
|
| 669 |
|
|
tapo_xsel2 : out std_ulogic;
|
| 670 |
|
|
tapi_en1 : in std_ulogic;
|
| 671 |
|
|
tapi_tdo1 : in std_ulogic;
|
| 672 |
|
|
tapi_tdo2 : in std_ulogic;
|
| 673 |
|
|
testen : in std_ulogic := '0';
|
| 674 |
|
|
testrst : in std_ulogic := '1';
|
| 675 |
|
|
tdoen : out std_ulogic
|
| 676 |
|
|
);
|
| 677 |
|
|
end component;
|
| 678 |
|
|
|
| 679 |
|
|
---------------------------------------------------------------------------
|
| 680 |
|
|
-- DDR registers and PHY
|
| 681 |
|
|
---------------------------------------------------------------------------
|
| 682 |
|
|
|
| 683 |
|
|
component ddr_ireg is
|
| 684 |
|
|
generic ( tech : integer);
|
| 685 |
|
|
port ( Q1 : out std_ulogic;
|
| 686 |
|
|
Q2 : out std_ulogic;
|
| 687 |
|
|
C1 : in std_ulogic;
|
| 688 |
|
|
C2 : in std_ulogic;
|
| 689 |
|
|
CE : in std_ulogic;
|
| 690 |
|
|
D : in std_ulogic;
|
| 691 |
|
|
R : in std_ulogic;
|
| 692 |
|
|
S : in std_ulogic);
|
| 693 |
|
|
end component;
|
| 694 |
|
|
|
| 695 |
|
|
component ddr_oreg is generic ( tech : integer);
|
| 696 |
|
|
port
|
| 697 |
|
|
( Q : out std_ulogic;
|
| 698 |
|
|
C1 : in std_ulogic;
|
| 699 |
|
|
C2 : in std_ulogic;
|
| 700 |
|
|
CE : in std_ulogic;
|
| 701 |
|
|
D1 : in std_ulogic;
|
| 702 |
|
|
D2 : in std_ulogic;
|
| 703 |
|
|
R : in std_ulogic;
|
| 704 |
|
|
S : in std_ulogic);
|
| 705 |
|
|
end component;
|
| 706 |
|
|
|
| 707 |
|
|
component ddrphy
|
| 708 |
|
|
generic (tech : integer := virtex2; MHz : integer := 100;
|
| 709 |
|
|
rstdelay : integer := 200; dbits : integer := 16;
|
| 710 |
|
|
clk_mul : integer := 2 ; clk_div : integer := 2;
|
| 711 |
|
|
rskew : integer :=0; mobile : integer := 0);
|
| 712 |
|
|
port (
|
| 713 |
|
|
rst : in std_ulogic;
|
| 714 |
|
|
clk : in std_logic; -- input clock
|
| 715 |
|
|
clkout : out std_ulogic; -- system clock
|
| 716 |
|
|
clkread : out std_ulogic; -- read clock
|
| 717 |
|
|
lock : out std_ulogic; -- DCM locked
|
| 718 |
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
| 719 |
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
| 720 |
|
|
ddr_clk_fb_out : out std_logic;
|
| 721 |
|
|
ddr_clk_fb : in std_logic;
|
| 722 |
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
| 723 |
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
| 724 |
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
| 725 |
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
| 726 |
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
| 727 |
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
| 728 |
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
| 729 |
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
| 730 |
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
| 731 |
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
| 732 |
|
|
|
| 733 |
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
| 734 |
|
|
ba : in std_logic_vector ( 1 downto 0); -- data mask
|
| 735 |
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
| 736 |
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
| 737 |
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
| 738 |
|
|
oen : in std_ulogic;
|
| 739 |
|
|
dqs : in std_ulogic;
|
| 740 |
|
|
dqsoen : in std_ulogic;
|
| 741 |
|
|
rasn : in std_ulogic;
|
| 742 |
|
|
casn : in std_ulogic;
|
| 743 |
|
|
wen : in std_ulogic;
|
| 744 |
|
|
csn : in std_logic_vector(1 downto 0);
|
| 745 |
|
|
cke : in std_logic_vector(1 downto 0);
|
| 746 |
|
|
ck : in std_logic_vector(2 downto 0);
|
| 747 |
|
|
moben : in std_logic);
|
| 748 |
|
|
end component;
|
| 749 |
|
|
|
| 750 |
|
|
component ddr2phy
|
| 751 |
|
|
generic (tech : integer := virtex5; MHz : integer := 100;
|
| 752 |
|
|
rstdelay : integer := 200; dbits : integer := 16;
|
| 753 |
|
|
clk_mul : integer := 2; clk_div : integer := 2;
|
| 754 |
|
|
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
|
| 755 |
|
|
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
|
| 756 |
|
|
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
|
| 757 |
|
|
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0);
|
| 758 |
|
|
port (
|
| 759 |
|
|
rst : in std_ulogic;
|
| 760 |
|
|
clk : in std_logic; -- input clock
|
| 761 |
|
|
clkref200 : in std_logic; -- input 200MHz clock
|
| 762 |
|
|
clkout : out std_ulogic; -- system clock
|
| 763 |
|
|
lock : out std_ulogic; -- DCM locked
|
| 764 |
|
|
|
| 765 |
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
| 766 |
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
| 767 |
|
|
ddr_clk_fb_out : out std_logic;
|
| 768 |
|
|
ddr_clk_fb : in std_logic;
|
| 769 |
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
| 770 |
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
| 771 |
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
| 772 |
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
| 773 |
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
| 774 |
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
| 775 |
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
| 776 |
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
| 777 |
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
| 778 |
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
| 779 |
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
| 780 |
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
| 781 |
|
|
|
| 782 |
|
|
addr : in std_logic_vector (13 downto 0);
|
| 783 |
|
|
ba : in std_logic_vector ( 1 downto 0);
|
| 784 |
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
|
| 785 |
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
| 786 |
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
| 787 |
|
|
oen : in std_ulogic;
|
| 788 |
|
|
dqs : in std_ulogic;
|
| 789 |
|
|
dqsoen : in std_ulogic;
|
| 790 |
|
|
rasn : in std_ulogic;
|
| 791 |
|
|
casn : in std_ulogic;
|
| 792 |
|
|
wen : in std_ulogic;
|
| 793 |
|
|
csn : in std_logic_vector(1 downto 0);
|
| 794 |
|
|
cke : in std_logic_vector(1 downto 0);
|
| 795 |
|
|
cal_en : in std_logic_vector(dbits/8-1 downto 0);
|
| 796 |
|
|
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
|
| 797 |
|
|
cal_pll : in std_logic_vector(1 downto 0);
|
| 798 |
|
|
cal_rst : in std_logic;
|
| 799 |
|
|
odt : in std_logic_vector(1 downto 0)
|
| 800 |
|
|
);
|
| 801 |
|
|
end component;
|
| 802 |
|
|
|
| 803 |
|
|
---------------------------------------------------------------------------
|
| 804 |
|
|
-- 61x61 Multiplier
|
| 805 |
|
|
---------------------------------------------------------------------------
|
| 806 |
|
|
|
| 807 |
|
|
component mul_61x61
|
| 808 |
|
|
generic (multech : integer := 0);
|
| 809 |
|
|
port(A : in std_logic_vector(60 downto 0);
|
| 810 |
|
|
B : in std_logic_vector(60 downto 0);
|
| 811 |
|
|
EN : in std_logic;
|
| 812 |
|
|
CLK : in std_logic;
|
| 813 |
|
|
PRODUCT : out std_logic_vector(121 downto 0));
|
| 814 |
|
|
end component;
|
| 815 |
|
|
|
| 816 |
|
|
---------------------------------------------------------------------------
|
| 817 |
|
|
-- Ring oscillator
|
| 818 |
|
|
---------------------------------------------------------------------------
|
| 819 |
|
|
|
| 820 |
|
|
component ringosc
|
| 821 |
|
|
generic (tech : integer := 0);
|
| 822 |
|
|
port (
|
| 823 |
|
|
roen : in Std_ULogic;
|
| 824 |
|
|
roout : out Std_ULogic);
|
| 825 |
|
|
end component;
|
| 826 |
|
|
|
| 827 |
|
|
end;
|
