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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [allddr.vhd] - Blame information for rev 2

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1 2 dimamali 
------------------------------------------------------------------------------
2 
--  This file is a part of the GRLIB VHDL IP LIBRARY
3 
--  Copyright (C) 2003, Gaisler Research
4 
--
5 
--  This program is free software; you can redistribute it and/or modify
6 
--  it under the terms of the GNU General Public License as published by
7 
--  the Free Software Foundation; either version 2 of the License, or
8 
--  (at your option) any later version.
9 
--
10 
--  This program is distributed in the hope that it will be useful,
11 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
--  GNU General Public License for more details.
14 
--
15 
--  You should have received a copy of the GNU General Public License
16 
--  along with this program; if not, write to the Free Software
17 
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18 
-----------------------------------------------------------------------------
19 
-- Entity:      libddr
20 
-- File:        libddr.vhd
21 
-- Author:      David Lindh, Jiri Gaisler - Gaisler Research
22 
-- Description: DDR input/output registers
23 
------------------------------------------------------------------------------
24 
 
25 
library ieee;
26 
use ieee.std_logic_1164.all;
27 
library techmap;
28 
use techmap.gencomp.all;
29 
 
30 
package allddr is
31 
 
32 
component unisim_iddr_reg is
33 
  generic ( tech : integer := virtex4);
34 
  port(
35 
         Q1 : out std_ulogic;
36 
         Q2 : out std_ulogic;
37 
         C1 : in std_ulogic;
38 
         C2 : in std_ulogic;
39 
         CE : in std_ulogic;
40 
         D : in std_ulogic;
41 
         R : in std_ulogic;
42 
         S : in std_ulogic
43 
      );
44 
end component;
45 
 
46 
component gen_iddr_reg
47 
  port (
48 
    Q1 : out std_ulogic;
49 
    Q2 : out std_ulogic;
50 
    C1 : in std_ulogic;
51 
    C2 : in std_ulogic;
52 
    CE : in std_ulogic;
53 
    D  : in std_ulogic;
54 
    R  : in std_ulogic;
55 
    S  : in std_ulogic);
56 
end component;
57 
 
58 
component ec_oddr_reg
59 
  port (
60 
      Q : out std_ulogic;
61 
      C1 : in std_ulogic;
62 
      C2 : in std_ulogic;
63 
      CE : in std_ulogic;
64 
      D1 : in std_ulogic;
65 
      D2 : in std_ulogic;
66 
      R : in std_ulogic;
67 
      S : in std_ulogic);
68 
end component;
69 
 
70 
component unisim_oddr_reg
71 
  generic ( tech : integer := virtex4);
72 
  port (
73 
      Q : out std_ulogic;
74 
      C1 : in std_ulogic;
75 
      C2 : in std_ulogic;
76 
      CE : in std_ulogic;
77 
      D1 : in std_ulogic;
78 
      D2 : in std_ulogic;
79 
      R : in std_ulogic;
80 
      S : in std_ulogic);
81 
end component;
82 
 
83 
component gen_oddr_reg
84 
  port (
85 
      Q : out std_ulogic;
86 
      C1 : in std_ulogic;
87 
      C2 : in std_ulogic;
88 
      CE : in std_ulogic;
89 
      D1 : in std_ulogic;
90 
      D2 : in std_ulogic;
91 
      R : in std_ulogic;
92 
      S : in std_ulogic);
93 
end component;
94 
 
95 
component spartan3e_ddr_phy
96 
  generic (MHz : integer := 100; rstdelay : integer := 200;
97 
        dbits : integer := 16; clk_mul : integer := 2 ;
98 
        clk_div : integer := 2; rskew : integer := 0);
99 
 
100 
  port (
101 
    rst       : in  std_ulogic;
102 
    clk       : in  std_logic;                  -- input clock
103 
    clkout    : out std_ulogic;                 -- DDR state clock
104 
    clkread   : out std_ulogic;                 -- DDR read clock
105 
    lock      : out std_ulogic;                 -- DCM locked
106 
 
107 
    ddr_clk     : out std_logic_vector(2 downto 0);
108 
    ddr_clkb    : out std_logic_vector(2 downto 0);
109 
    ddr_clk_fb_out  : out std_logic;
110 
    ddr_clk_fb  : in std_logic;
111 
    ddr_cke     : out std_logic_vector(1 downto 0);
112 
    ddr_csb     : out std_logic_vector(1 downto 0);
113 
    ddr_web     : out std_ulogic;                       -- ddr write enable
114 
    ddr_rasb    : out std_ulogic;                       -- ddr ras
115 
    ddr_casb    : out std_ulogic;                       -- ddr cas
116 
    ddr_dm      : out std_logic_vector (dbits/8-1 downto 0);    -- ddr dm
117 
    ddr_dqs     : inout std_logic_vector (dbits/8-1 downto 0);    -- ddr dqs
118 
    ddr_ad      : out std_logic_vector (13 downto 0);   -- ddr address
119 
    ddr_ba      : out std_logic_vector (1 downto 0);    -- ddr bank address
120 
    ddr_dq      : inout  std_logic_vector (dbits-1 downto 0); -- ddr data
121 
 
122 
    addr        : in  std_logic_vector (13 downto 0); -- data mask
123 
    ba          : in  std_logic_vector ( 1 downto 0); -- data mask
124 
    dqin        : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
125 
    dqout       : in  std_logic_vector (dbits*2-1 downto 0); -- ddr input data
126 
    dm          : in  std_logic_vector (dbits/4-1 downto 0); -- data mask
127 
    oen         : in  std_ulogic;
128 
    dqs         : in  std_ulogic;
129 
    dqsoen      : in  std_ulogic;
130 
    rasn        : in  std_ulogic;
131 
    casn        : in  std_ulogic;
132 
    wen         : in  std_ulogic;
133 
    csn         : in  std_logic_vector(1 downto 0);
134 
    cke         : in  std_logic_vector(1 downto 0)
135 
  );
136 
 
137 
end component;
138 
 
139 
component virtex4_ddr_phy
140 
  generic (MHz : integer := 100; rstdelay : integer := 200;
141 
        dbits : integer := 16; clk_mul : integer := 2 ;
142 
        clk_div : integer := 2; rskew : integer := 0);
143 
 
144 
  port (
145 
    rst       : in  std_ulogic;
146 
    clk       : in  std_logic;                  -- input clock
147 
    clkout    : out std_ulogic;                 -- system clock
148 
    lock      : out std_ulogic;                 -- DCM locked
149 
 
150 
    ddr_clk     : out std_logic_vector(2 downto 0);
151 
    ddr_clkb    : out std_logic_vector(2 downto 0);
152 
    ddr_clk_fb_out  : out std_logic;
153 
    ddr_clk_fb  : in std_logic;
154 
    ddr_cke     : out std_logic_vector(1 downto 0);
155 
    ddr_csb     : out std_logic_vector(1 downto 0);
156 
    ddr_web     : out std_ulogic;                       -- ddr write enable
157 
    ddr_rasb    : out std_ulogic;                       -- ddr ras
158 
    ddr_casb    : out std_ulogic;                       -- ddr cas
159 
    ddr_dm      : out std_logic_vector (dbits/8-1 downto 0);    -- ddr dm
160 
    ddr_dqs     : inout std_logic_vector (dbits/8-1 downto 0);    -- ddr dqs
161 
    ddr_ad      : out std_logic_vector (13 downto 0);   -- ddr address
162 
    ddr_ba      : out std_logic_vector (1 downto 0);    -- ddr bank address
163 
    ddr_dq      : inout  std_logic_vector (dbits-1 downto 0); -- ddr data
164 
 
165 
    addr        : in  std_logic_vector (13 downto 0); -- data mask
166 
    ba          : in  std_logic_vector ( 1 downto 0); -- data mask
167 
    dqin        : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
168 
    dqout       : in  std_logic_vector (dbits*2-1 downto 0); -- ddr input data
169 
    dm          : in  std_logic_vector (dbits/4-1 downto 0); -- data mask
170 
    oen         : in  std_ulogic;
171 
    dqs         : in  std_ulogic;
172 
    dqsoen      : in  std_ulogic;
173 
    rasn        : in  std_ulogic;
174 
    casn        : in  std_ulogic;
175 
    wen         : in  std_ulogic;
176 
    csn         : in  std_logic_vector(1 downto 0);
177 
    cke         : in  std_logic_vector(1 downto 0);
178 
    ck          : in  std_logic_vector(2 downto 0)
179 
  );
180 
 
181 
end component;
182 
 
183 
component virtex2_ddr_phy
184 
  generic (MHz : integer := 100; rstdelay : integer := 200;
185 
        dbits : integer := 16; clk_mul : integer := 2 ;
186 
        clk_div : integer := 2; rskew : integer := 0);
187 
 
188 
  port (
189 
    rst       : in  std_ulogic;
190 
    clk       : in  std_logic;                  -- input clock
191 
    clkout    : out std_ulogic;                 -- system clock
192 
    lock      : out std_ulogic;                 -- DCM locked
193 
 
194 
    ddr_clk     : out std_logic_vector(2 downto 0);
195 
    ddr_clkb    : out std_logic_vector(2 downto 0);
196 
    ddr_clk_fb_out  : out std_logic;
197 
    ddr_clk_fb  : in std_logic;
198 
    ddr_cke     : out std_logic_vector(1 downto 0);
199 
    ddr_csb     : out std_logic_vector(1 downto 0);
200 
    ddr_web     : out std_ulogic;                       -- ddr write enable
201 
    ddr_rasb    : out std_ulogic;                       -- ddr ras
202 
    ddr_casb    : out std_ulogic;                       -- ddr cas
203 
    ddr_dm      : out std_logic_vector (dbits/8-1 downto 0);    -- ddr dm
204 
    ddr_dqs     : inout std_logic_vector (dbits/8-1 downto 0);    -- ddr dqs
205 
    ddr_ad      : out std_logic_vector (13 downto 0);   -- ddr address
206 
    ddr_ba      : out std_logic_vector (1 downto 0);    -- ddr bank address
207 
    ddr_dq      : inout  std_logic_vector (dbits-1 downto 0); -- ddr data
208 
 
209 
    addr        : in  std_logic_vector (13 downto 0); -- data mask
210 
    ba          : in  std_logic_vector ( 1 downto 0); -- data mask
211 
    dqin        : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
212 
    dqout       : in  std_logic_vector (dbits*2-1 downto 0); -- ddr input data
213 
    dm          : in  std_logic_vector (dbits/4-1 downto 0); -- data mask
214 
    oen         : in  std_ulogic;
215 
    dqs         : in  std_ulogic;
216 
    dqsoen      : in  std_ulogic;
217 
    rasn        : in  std_ulogic;
218 
    casn        : in  std_ulogic;
219 
    wen         : in  std_ulogic;
220 
    csn         : in  std_logic_vector(1 downto 0);
221 
    cke         : in  std_logic_vector(1 downto 0)
222 
  );
223 
 
224 
end component;
225 
 
226 
component stratixii_ddr_phy
227 
  generic (MHz : integer := 100; rstdelay : integer := 200;
228 
        dbits : integer := 16; clk_mul : integer := 2 ;
229 
        clk_div : integer := 2);
230 
 
231 
  port (
232 
    rst       : in  std_ulogic;
233 
    clk       : in  std_logic;                  -- input clock
234 
    clkout    : out std_ulogic;                 -- system clock
235 
    lock      : out std_ulogic;                 -- DCM locked
236 
 
237 
    ddr_clk     : out std_logic_vector(2 downto 0);
238 
    ddr_clkb    : out std_logic_vector(2 downto 0);
239 
    ddr_clk_fb_out  : out std_logic;
240 
    ddr_clk_fb  : in std_logic;
241 
    ddr_cke     : out std_logic_vector(1 downto 0);
242 
    ddr_csb     : out std_logic_vector(1 downto 0);
243 
    ddr_web     : out std_ulogic;                       -- ddr write enable
244 
    ddr_rasb    : out std_ulogic;                       -- ddr ras
245 
    ddr_casb    : out std_ulogic;                       -- ddr cas
246 
    ddr_dm      : out std_logic_vector (dbits/8-1 downto 0);    -- ddr dm
247 
    ddr_dqs     : inout std_logic_vector (dbits/8-1 downto 0);    -- ddr dqs
248 
    ddr_ad      : out std_logic_vector (13 downto 0);   -- ddr address
249 
    ddr_ba      : out std_logic_vector (1 downto 0);    -- ddr bank address
250 
    ddr_dq      : inout  std_logic_vector (dbits-1 downto 0); -- ddr data
251 
 
252 
    addr        : in  std_logic_vector (13 downto 0); -- data mask
253 
    ba          : in  std_logic_vector ( 1 downto 0); -- data mask
254 
    dqin        : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
255 
    dqout       : in  std_logic_vector (dbits*2-1 downto 0); -- ddr input data
256 
    dm          : in  std_logic_vector (dbits/4-1 downto 0); -- data mask
257 
    oen         : in  std_ulogic;
258 
    dqs         : in  std_ulogic;
259 
    dqsoen      : in  std_ulogic;
260 
    rasn        : in  std_ulogic;
261 
    casn        : in  std_ulogic;
262 
    wen         : in  std_ulogic;
263 
    csn         : in  std_logic_vector(1 downto 0);
264 
    cke         : in  std_logic_vector(1 downto 0)
265 
  );
266 
 
267 
end component;
268 
 
269 
component cycloneiii_ddr_phy
270 
  generic (MHz : integer := 100; rstdelay : integer := 200;
271 
        dbits : integer := 16; clk_mul : integer := 2 ;
272 
        clk_div : integer := 2; rskew : integer := 0);
273 
 
274 
  port (
275 
    rst       : in  std_ulogic;
276 
    clk       : in  std_logic;                  -- input clock
277 
    clkout    : out std_ulogic;                 -- system clock
278 
    lock      : out std_ulogic;                 -- DCM locked
279 
 
280 
    ddr_clk     : out std_logic_vector(2 downto 0);
281 
    ddr_clkb    : out std_logic_vector(2 downto 0);
282 
    ddr_clk_fb_out  : out std_logic;
283 
    ddr_clk_fb  : in std_logic;
284 
    ddr_cke     : out std_logic_vector(1 downto 0);
285 
    ddr_csb     : out std_logic_vector(1 downto 0);
286 
    ddr_web     : out std_ulogic;                       -- ddr write enable
287 
    ddr_rasb    : out std_ulogic;                       -- ddr ras
288 
    ddr_casb    : out std_ulogic;                       -- ddr cas
289 
    ddr_dm      : out std_logic_vector (dbits/8-1 downto 0);    -- ddr dm
290 
    ddr_dqs     : inout std_logic_vector (dbits/8-1 downto 0);    -- ddr dqs
291 
    ddr_ad      : out std_logic_vector (13 downto 0);   -- ddr address
292 
    ddr_ba      : out std_logic_vector (1 downto 0);    -- ddr bank address
293 
    ddr_dq      : inout  std_logic_vector (dbits-1 downto 0); -- ddr data
294 
 
295 
    addr        : in  std_logic_vector (13 downto 0); -- data mask
296 
    ba          : in  std_logic_vector ( 1 downto 0); -- data mask
297 
    dqin        : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
298 
    dqout       : in  std_logic_vector (dbits*2-1 downto 0); -- ddr input data
299 
    dm          : in  std_logic_vector (dbits/4-1 downto 0); -- data mask
300 
    oen         : in  std_ulogic;
301 
    dqs         : in  std_ulogic;
302 
    dqsoen      : in  std_ulogic;
303 
    rasn        : in  std_ulogic;
304 
    casn        : in  std_ulogic;
305 
    wen         : in  std_ulogic;
306 
    csn         : in  std_logic_vector(1 downto 0);
307 
    cke         : in  std_logic_vector(1 downto 0)
308 
  );
309 
 
310 
end component;
311 
 
312 
component generic_ddr_phy
313 
  generic (MHz : integer := 100; rstdelay : integer := 200;
314 
           dbits : integer := 16; clk_mul : integer := 2 ;
315 
           clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0);
316 
 
317 
  port (
318 
    rst         : in  std_ulogic;
319 
    clk         : in  std_logic;    -- input clock
320 
    clkout      : out std_ulogic;   -- system clock
321 
    lock        : out std_ulogic;   -- DCM locked
322 
 
323 
    ddr_clk     : out std_logic_vector(2 downto 0);
324 
    ddr_clkb    : out std_logic_vector(2 downto 0);
325 
    ddr_clk_fb_out : out std_logic;
326 
    ddr_clk_fb  : in std_logic;
327 
    ddr_cke     : out std_logic_vector(1 downto 0);
328 
    ddr_csb     : out std_logic_vector(1 downto 0);
329 
    ddr_web     : out std_ulogic;                             -- ddr write enable
330 
    ddr_rasb    : out std_ulogic;                             -- ddr ras
331 
    ddr_casb    : out std_ulogic;                             -- ddr cas
332 
    ddr_dm      : out std_logic_vector (dbits/8-1 downto 0);  -- ddr dm
333 
    ddr_dqs     : inout std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
334 
    ddr_ad      : out std_logic_vector (13 downto 0);         -- ddr address
335 
    ddr_ba      : out std_logic_vector (1 downto 0);          -- ddr bank address
336 
    ddr_dq      : inout  std_logic_vector (dbits-1 downto 0); -- ddr data
337 
 
338 
    addr        : in  std_logic_vector (13 downto 0);         -- data mask
339 
    ba          : in  std_logic_vector ( 1 downto 0);         -- data mask
340 
    dqin        : out std_logic_vector (dbits*2-1 downto 0);  -- ddr input data
341 
    dqout       : in  std_logic_vector (dbits*2-1 downto 0);  -- ddr input data
342 
    dm          : in  std_logic_vector (dbits/4-1 downto 0);  -- data mask
343 
    oen         : in  std_ulogic;
344 
    dqs         : in  std_ulogic;
345 
    dqsoen      : in  std_ulogic;
346 
    rasn        : in  std_ulogic;
347 
    casn        : in  std_ulogic;
348 
    wen         : in  std_ulogic;
349 
    csn         : in  std_logic_vector(1 downto 0);
350 
    cke         : in  std_logic_vector(1 downto 0);
351 
    ck          : in  std_logic_vector(2 downto 0);
352 
    moben       : in  std_logic
353 
  );
354 
 
355 
end component;
356 
 
357 
component tsmc90_tci_ddr_phy
358 
  generic (MHz : integer := 100; rstdelay : integer := 200;
359 
           dbits : integer := 16);
360 
 
361 
  port (
362 
    rst           : in  std_ulogic;
363 
    clk           : in  std_logic;    -- input clock
364 
    clk90_sigi_0  : in  std_logic;
365 
    rclk_sigi_1   : in  std_logic;
366 
    clkout        : out std_ulogic;   -- system clock
367 
    lock          : out std_ulogic;   -- DCM locked
368 
 
369 
    ddr_clk     : out std_logic_vector(2 downto 0);
370 
    ddr_clkb    : out std_logic_vector(2 downto 0);
371 
    --ddr_clk_fb_out : out std_logic;
372 
    --ddr_clk_fb  : in std_logic;
373 
    ddr_cke     : out std_logic_vector(1 downto 0);
374 
    ddr_csb     : out std_logic_vector(1 downto 0);
375 
    ddr_web     : out std_ulogic;                             -- ddr write enable
376 
    ddr_rasb    : out std_ulogic;                             -- ddr ras
377 
    ddr_casb    : out std_ulogic;                             -- ddr cas
378 
    ddr_dm      : out std_logic_vector (dbits/8-1 downto 0);  -- ddr dm
379 
    ddr_dqsin   : in std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
380 
    ddr_dqsout  : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
381 
    ddr_dqsoen  : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
382 
    ddr_ad      : out std_logic_vector (13 downto 0);         -- ddr address
383 
    ddr_ba      : out std_logic_vector (1 downto 0);          -- ddr bank address
384 
    ddr_dqin    : in  std_logic_vector (dbits-1 downto 0); -- ddr data
385 
    ddr_dqout   : out  std_logic_vector (dbits-1 downto 0); -- ddr data
386 
    ddr_dqoen   : out  std_logic_vector (dbits-1 downto 0); -- ddr data
387 
 
388 
    addr        : in  std_logic_vector (13 downto 0);         -- data mask
389 
    ba          : in  std_logic_vector ( 1 downto 0);         -- data mask
390 
    dqin        : out std_logic_vector (dbits*2-1 downto 0);  -- ddr input data
391 
    dqout       : in  std_logic_vector (dbits*2-1 downto 0);  -- ddr input data
392 
    dm          : in  std_logic_vector (dbits/4-1 downto 0);  -- data mask
393 
    oen         : in  std_ulogic;
394 
    dqs         : in  std_ulogic;
395 
    dqsoen      : in  std_ulogic;
396 
    rasn        : in  std_ulogic;
397 
    casn        : in  std_ulogic;
398 
    wen         : in  std_ulogic;
399 
    csn         : in  std_logic_vector(1 downto 0);
400 
    cke         : in  std_logic_vector(1 downto 0);
401 
    ck          : in  std_logic_vector(2 downto 0);
402 
    moben       : in  std_logic;
403 
    conf        : in  std_logic_vector(63 downto 0);
404 
    tstclkout   : out std_logic_vector(3 downto 0)
405 
  );
406 
 
407 
end component;
408 
 
409 
component virtex5_ddr2_phy
410 
  generic (MHz : integer := 100; rstdelay : integer := 200;
411 
        dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
412 
        ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
413 
        ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
414 
        ddelayb6 : integer := 0; ddelayb7 : integer := 0;
415 
   numidelctrl : integer := 4; norefclk : integer := 0;
416 
   tech : integer := virtex5);
417 
 
418 
  port (
419 
    rst       : in  std_ulogic;
420 
    clk       : in  std_logic;                  -- input clock
421 
    clkref200 : in  std_logic;                  -- input 200MHz clock
422 
    clkout    : out std_ulogic;                 -- system clock
423 
    lock      : out std_ulogic;                 -- DCM locked
424 
 
425 
    ddr_clk     : out std_logic_vector(2 downto 0);
426 
    ddr_clkb    : out std_logic_vector(2 downto 0);
427 
    ddr_cke     : out std_logic_vector(1 downto 0);
428 
    ddr_csb     : out std_logic_vector(1 downto 0);
429 
    ddr_web     : out std_ulogic;                       -- ddr write enable
430 
    ddr_rasb    : out std_ulogic;                       -- ddr ras
431 
    ddr_casb    : out std_ulogic;                       -- ddr cas
432 
    ddr_dm      : out std_logic_vector (dbits/8-1 downto 0);    -- ddr dm
433 
    ddr_dqs     : inout std_logic_vector (dbits/8-1 downto 0);    -- ddr dqs
434 
    ddr_dqsn    : inout std_logic_vector (dbits/8-1 downto 0);    -- ddr dqsn
435 
    ddr_ad      : out std_logic_vector (13 downto 0);   -- ddr address
436 
    ddr_ba      : out std_logic_vector (1 downto 0);    -- ddr bank address
437 
    ddr_dq      : inout  std_logic_vector (dbits-1 downto 0); -- ddr data
438 
    ddr_odt     : out std_logic_vector(1 downto 0);
439 
 
440 
    addr        : in  std_logic_vector (13 downto 0); -- data mask
441 
    ba          : in  std_logic_vector ( 1 downto 0); -- data mask
442 
    dqin        : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
443 
    dqout       : in  std_logic_vector (dbits*2-1 downto 0); -- ddr input data
444 
    dm          : in  std_logic_vector (dbits/4-1 downto 0); -- data mask
445 
    oen         : in  std_ulogic;
446 
    dqs         : in  std_ulogic;
447 
    dqsoen      : in  std_ulogic;
448 
    rasn        : in  std_ulogic;
449 
    casn        : in  std_ulogic;
450 
    wen         : in  std_ulogic;
451 
    csn         : in  std_logic_vector(1 downto 0);
452 
    cke         : in  std_logic_vector(1 downto 0);
453 
    cal_en      : in  std_logic_vector(dbits/8-1 downto 0);
454 
    cal_inc     : in  std_logic_vector(dbits/8-1 downto 0);
455 
    cal_rst     : in  std_logic;
456 
    odt     : in  std_logic_vector(1 downto 0)
457 
 );
458 
end component;
459 
 
460 
component stratixiii_ddr2_phy
461 
  generic (MHz : integer := 100; rstdelay : integer := 200;
462 
        dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
463 
        ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
464 
        ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
465 
        ddelayb6 : integer := 0; ddelayb7 : integer := 0;
466 
   numidelctrl : integer := 4; norefclk : integer := 0;
467 
   tech : integer := stratix3; rskew : integer := 0);
468 
 
469 
  port (
470 
    rst       : in  std_ulogic;
471 
    clk       : in  std_logic;                  -- input clock
472 
    clkref200 : in  std_logic;                  -- input 200MHz clock
473 
    clkout    : out std_ulogic;                 -- system clock
474 
    lock      : out std_ulogic;                 -- DCM locked
475 
 
476 
    ddr_clk     : out std_logic_vector(2 downto 0);
477 
    ddr_clkb    : out std_logic_vector(2 downto 0);
478 
    ddr_cke     : out std_logic_vector(1 downto 0);
479 
    ddr_csb     : out std_logic_vector(1 downto 0);
480 
    ddr_web     : out std_ulogic;                       -- ddr write enable
481 
    ddr_rasb    : out std_ulogic;                       -- ddr ras
482 
    ddr_casb    : out std_ulogic;                       -- ddr cas
483 
    ddr_dm      : out std_logic_vector (dbits/8-1 downto 0);    -- ddr dm
484 
    ddr_dqs     : inout std_logic_vector (dbits/8-1 downto 0);    -- ddr dqs
485 
    ddr_dqsn    : inout std_logic_vector (dbits/8-1 downto 0);    -- ddr dqsn
486 
    ddr_ad      : out std_logic_vector (13 downto 0);   -- ddr address
487 
    ddr_ba      : out std_logic_vector (1 downto 0);    -- ddr bank address
488 
    ddr_dq      : inout  std_logic_vector (dbits-1 downto 0); -- ddr data
489 
    ddr_odt     : out std_logic_vector(1 downto 0);
490 
 
491 
    addr        : in  std_logic_vector (13 downto 0); -- data mask
492 
    ba          : in  std_logic_vector ( 1 downto 0); -- data mask
493 
    dqin        : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
494 
    dqout       : in  std_logic_vector (dbits*2-1 downto 0); -- ddr input data
495 
    dm          : in  std_logic_vector (dbits/4-1 downto 0); -- data mask
496 
    oen         : in  std_ulogic;
497 
    dqs         : in  std_ulogic;
498 
    dqsoen      : in  std_ulogic;
499 
    rasn        : in  std_ulogic;
500 
    casn        : in  std_ulogic;
501 
    wen         : in  std_ulogic;
502 
    csn         : in  std_logic_vector(1 downto 0);
503 
    cke         : in  std_logic_vector(1 downto 0);
504 
    cal_en      : in  std_logic_vector(dbits/8-1 downto 0);
505 
    cal_inc     : in  std_logic_vector(dbits/8-1 downto 0);
506 
    cal_pll     : in  std_logic_vector(1 downto 0);
507 
    cal_rst     : in  std_logic;
508 
    odt     : in  std_logic_vector(1 downto 0)
509 
 );
510 
end component;
511 
 
512 
 
513 
component spartan3a_ddr2_phy
514 
  generic (MHz         : integer := 125; rstdelay : integer := 200;
515 
           dbits       : integer := 16;  clk_mul  : integer := 2;
516 
           clk_div     : integer := 2;   tech     : integer := spartan3;
517 
           rskew       : integer := 0);
518 
  port (
519 
    rst            : in    std_ulogic;
520 
    clk            : in    std_logic;   -- input clock
521 
    clkout         : out   std_ulogic;  -- system clock
522 
    lock           : out   std_ulogic;  -- DCM locked
523 
 
524 
    ddr_clk        : out   std_logic_vector(2 downto 0);
525 
    ddr_clkb       : out   std_logic_vector(2 downto 0);
526 
    ddr_clk_fb_out : out   std_logic;
527 
    ddr_clk_fb     : in    std_logic;
528 
    ddr_cke        : out   std_logic_vector(1 downto 0);
529 
    ddr_csb        : out   std_logic_vector(1 downto 0);
530 
    ddr_web        : out   std_ulogic;  -- ddr write enable
531 
    ddr_rasb       : out   std_ulogic;  -- ddr ras
532 
    ddr_casb       : out   std_ulogic;  -- ddr cas
533 
    ddr_dm         : out   std_logic_vector (dbits/8-1 downto 0);  -- ddr dm
534 
    ddr_dqs        : inout std_logic_vector (dbits/8-1 downto 0);  -- ddr dqs
535 
    ddr_dqsn       : inout std_logic_vector (dbits/8-1 downto 0);  -- ddr dqsn
536 
    ddr_ad         : out   std_logic_vector (13 downto 0);         -- ddr address
537 
    ddr_ba         : out   std_logic_vector (1 downto 0);          -- ddr bank address
538 
    ddr_dq         : inout std_logic_vector (dbits-1 downto 0);    -- ddr data
539 
    ddr_odt        : out   std_logic_vector(1 downto 0);
540 
 
541 
    addr           : in    std_logic_vector (13 downto 0);
542 
    ba             : in    std_logic_vector ( 1 downto 0);
543 
    dqin           : out   std_logic_vector (dbits*2-1 downto 0);  -- ddr data
544 
    dqout          : in    std_logic_vector (dbits*2-1 downto 0);  -- ddr data
545 
    dm             : in    std_logic_vector (dbits/4-1 downto 0);  -- data mask
546 
    oen            : in    std_ulogic;
547 
    dqs            : in    std_ulogic;
548 
    dqsoen         : in    std_ulogic;
549 
    rasn           : in    std_ulogic;
550 
    casn           : in    std_ulogic;
551 
    wen            : in    std_ulogic;
552 
    csn            : in    std_logic_vector(1 downto 0);
553 
    cke            : in    std_logic_vector(1 downto 0);
554 
    cal_pll        : in    std_logic_vector(1 downto 0);
555 
    odt            : in    std_logic_vector(1 downto 0)
556 
    );
557 
end component;
558 
end;

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