URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [allpads.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log


------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
----------------------------------------------------------------------------
-- Package:     allpads
-- File:        allpads.vhd
-- Author:      Jiri Gaisler - Gaisler Research
-- Description: All tech pads
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
 
package allpads is
 
component apa3_clkpad
  generic (level : integer := 0; voltage : integer := 0);
  port (pad : in std_ulogic; o : out std_ulogic);
end component;
 
component axcel_inpad
  generic (level : integer := 0; voltage : integer := 0);
  port (pad : in std_ulogic; o : out std_ulogic);
end component;
 
component axcel_iopad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
 
component axcel_outpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_ulogic; i : in std_ulogic);
end component;
 
component axcel_odpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_ulogic; i : in std_ulogic);
end component;
 
component axcel_toutpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
 
component axcel_clkpad
  generic (level : integer := 0; voltage : integer := 0);
  port (pad : in std_ulogic; o : out std_ulogic);
end component;
 
component axcel_inpad_ds
  generic (level : integer := lvds; voltage : integer := x33v);
  port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
 
component axcel_outpad_ds
  generic (level : integer := lvds; voltage : integer := x33v);
  port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
 
component atc18_inpad
  generic (level : integer := 0; voltage : integer := 0);
  port (pad : in std_logic; o : out std_logic);
end component;
 
component atc18_iopad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
 
component atc18_outpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i : in std_logic);
end component;
 
component atc18_odpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i : in std_logic);
end component;
 
component atc18_toutpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i, en : in std_logic);
end component;
 
component atc18_clkpad
  generic (level : integer := 0; voltage : integer := 0);
  port (pad : in std_logic; o : out std_logic);
end component;
 
  component ihp25_inpad
    generic(level : integer := 0; voltage : integer := 0);
    port (pad : in std_logic; o : out std_logic);
  end component;
 
  component ihp25rh_inpad
    generic(level : integer := 0; voltage : integer := 0);
    port (pad : in std_logic; o : out std_logic);
  end component;
 
  component ihp25_iopad
    generic (level : integer := 0; slew : integer := 0;
             voltage : integer := 0; strength : integer := 0);
    port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
  end component;
 
  component ihp25rh_iopad
    generic (level : integer := 0; slew : integer := 0;
             voltage : integer := 0; strength : integer := 0);
    port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
  end component;
 
  component ihp25_outpad
    generic (level : integer := 0; slew : integer := 0;
             voltage : integer := 0; strength : integer := 0);
    port (pad : out  std_logic; i : in  std_logic);
  end component;
 
  component ihp25rh_outpad
    generic (level : integer := 0; slew : integer := 0;
             voltage : integer := 0; strength : integer := 0);
    port (pad : out  std_logic; i : in  std_logic);
  end component;
 
  component ihp25_toutpad
    generic (level : integer := 0; slew : integer := 0;
             voltage : integer := 0; strength : integer := 0);
    port (pad : out std_ulogic; i, en : in std_logic);
  end component;
 
  component ihp25rh_toutpad
    generic (level : integer := 0; slew : integer := 0;
             voltage : integer := 0; strength : integer := 0);
    port (pad : out std_ulogic; i, en : in std_logic);
  end component;
 
  component ihp25_clkpad
    generic (level : integer := 0; voltage : integer := 0);
    port (pad : in std_ulogic; o : out std_ulogic);
  end component;
 
  component ihp25rh_clkpad
    generic (level : integer := 0; voltage : integer := 0);
    port (pad : in std_ulogic; o : out std_ulogic);
  end component;
 
component rhumc_inpad
  generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
  port (pad : in std_logic; o : out std_logic);
end component;
 
component rhumc_iopad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
 
component rhumc_outpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i : in std_logic);
end component;
 
component rhumc_toutpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i, en : in std_logic);
end component;
 
component umc_inpad
  generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
  port (pad : in std_logic; o : out std_logic);
end component;
 
component umc_iopad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
 
component umc_outpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i : in std_logic);
end component;
 
component umc_toutpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i, en : in std_logic);
end component;
 
component virtex_inpad
  generic (level : integer := 0; voltage : integer := x33v);
  port (pad : in std_ulogic; o : out std_ulogic);
end component;
 
component virtex_iopad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := x33v; strength : integer := 12);
  port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
 
component virtex_outpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := x33v; strength : integer := 12);
  port (pad : out std_ulogic; i : in std_ulogic);
end component;
 
component virtex_odpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := x33v; strength : integer := 12);
  port (pad : out std_ulogic; i : in std_ulogic);
end component;
 
component virtex_toutpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := x33v; strength : integer := 12);
  port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
 
component virtex_skew_outpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
  port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
        o : out std_ulogic);
end component;
 
component virtex_clkpad
  generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
  port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
end component;
 
component virtex_inpad_ds
  generic (level : integer := lvds; voltage : integer := x33v);
  port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
 
component virtex5_iopad_ds
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := x33v; strength : integer := 12);
  port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
 
component virtex4_inpad_ds
  generic (level : integer := lvds; voltage : integer := x33v);
  port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
 
component virtex_outpad_ds
  generic (level : integer := lvds; voltage : integer := x33v);
  port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
 
component virtex5_outpad_ds
  generic (level : integer := lvds; voltage : integer := x33v);
  port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
 
component virtex4_clkpad_ds is
  generic (level : integer := lvds; voltage : integer := x33v);
  port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
 
component virtex_clkpad_ds is
  generic (level : integer := lvds; voltage : integer := x33v);
  port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
 
component rh_lib18t_inpad
  generic ( voltage : integer := 0; filter : integer := 0);
  port (pad : in std_logic; o : out std_logic);
end component;
 
component rh_lib18t_iopad
  generic ( strength : integer := 0);
  port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
 
component rh_lib18t_inpad_ds is
  port (padp, padn : in std_ulogic; o : out std_ulogic; en : in std_ulogic);
end component;
 
component rh_lib18t_outpad_ds is
  port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
 
component ut025crh_inpad
  generic ( level : integer := 0; voltage : integer := 0; filter : integer := 0);
  port (pad : in std_logic; o : out std_logic);
end component;
 
component ut025crh_iopad  is
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
 
component ut025crh_outpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_ulogic; i : in std_ulogic);
end component;
 
component ut025crh_toutpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
 
component ut025crh_lvds_combo
  generic (voltage : integer := 0; width : integer := 1);
  port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
        odval, osval, en : in std_logic_vector(0 to width-1);
        idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
        idval, isval : out std_logic_vector(0 to width-1));
end component;
 
component rhumc_lvds_combo
  generic (voltage : integer := 0; width : integer := 1);
  port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
        odval, osval, en : in std_logic_vector(0 to width-1);
        idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
        idval, isval : out std_logic_vector(0 to width-1);
        lvdsref : in std_logic);
end component;
 
component umc_lvds_combo
  generic (voltage : integer := 0; width : integer := 1);
  port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
        odval, osval, en : in std_logic_vector(0 to width-1);
        idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
        idval, isval : out std_logic_vector(0 to width-1);
        lvdsref : in std_logic);
end component;
 
component peregrine_inpad is
  generic (level : integer := 0; voltage : integer := 0; filter : integer := 0;
                strength : integer := 0);
  port (pad : in std_ulogic; o : out std_ulogic);
end component;
 
component peregrine_iopad  is
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
 
component peregrine_toutpad  is
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
 
component nextreme_inpad
  generic (level : integer := 0; voltage : integer := 0);
  port (pad : in std_logic; o : out std_logic);
end component;
 
component nextreme_iopad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
 
component nextreme_toutpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i, en : in std_logic);
end component;
 
component atc18rha_inpad
  generic (level : integer := 0; voltage : integer := 0);
  port (pad : in std_logic; o : out std_logic);
end component;
 
component atc18rha_iopad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
 
component atc18rha_outpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i : in std_logic);
end component;
 
component atc18rha_odpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i : in std_logic);
end component;
 
component atc18rha_toutpad
  generic (level : integer := 0; slew : integer := 0;
           voltage : integer := 0; strength : integer := 0);
  port (pad : out std_logic; i, en : in std_logic);
end component;
 
component atc18rha_clkpad
  generic (level : integer := 0; voltage : integer := 0);
  port (pad : in std_logic; o : out std_logic);
end component;
 
end;

Browse

Tools

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [allpads.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`----------------------------------------------------------------------------`
19			`-- Package: allpads`
20			`-- File: allpads.vhd`
21			`-- Author: Jiri Gaisler - Gaisler Research`
22			`-- Description: All tech pads`
23			`------------------------------------------------------------------------------`
24
25			`library ieee;`
26			`use ieee.std_logic_1164.all;`
27			`library techmap;`
28			`use techmap.gencomp.all;`
29
30			`package allpads is`
31
32			`component apa3_clkpad`
33			`generic (level : integer := 0; voltage : integer := 0);`
34			`port (pad : in std_ulogic; o : out std_ulogic);`
35			`end component;`
36
37			`component axcel_inpad`
38			`generic (level : integer := 0; voltage : integer := 0);`
39			`port (pad : in std_ulogic; o : out std_ulogic);`
40			`end component;`
41
42			`component axcel_iopad`
43			`generic (level : integer := 0; slew : integer := 0;`
44			`voltage : integer := 0; strength : integer := 0);`
45			`port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);`
46			`end component;`
47
48			`component axcel_outpad`
49			`generic (level : integer := 0; slew : integer := 0;`
50			`voltage : integer := 0; strength : integer := 0);`
51			`port (pad : out std_ulogic; i : in std_ulogic);`
52			`end component;`
53
54			`component axcel_odpad`
55			`generic (level : integer := 0; slew : integer := 0;`
56			`voltage : integer := 0; strength : integer := 0);`
57			`port (pad : out std_ulogic; i : in std_ulogic);`
58			`end component;`
59
60			`component axcel_toutpad`
61			`generic (level : integer := 0; slew : integer := 0;`
62			`voltage : integer := 0; strength : integer := 0);`
63			`port (pad : out std_ulogic; i, en : in std_ulogic);`
64			`end component;`
65
66			`component axcel_clkpad`
67			`generic (level : integer := 0; voltage : integer := 0);`
68			`port (pad : in std_ulogic; o : out std_ulogic);`
69			`end component;`
70
71			`component axcel_inpad_ds`
72			`generic (level : integer := lvds; voltage : integer := x33v);`
73			`port (padp, padn : in std_ulogic; o : out std_ulogic);`
74			`end component;`
75
76			`component axcel_outpad_ds`
77			`generic (level : integer := lvds; voltage : integer := x33v);`
78			`port (padp, padn : out std_ulogic; i : in std_ulogic);`
79			`end component;`
80
81			`component atc18_inpad`
82			`generic (level : integer := 0; voltage : integer := 0);`
83			`port (pad : in std_logic; o : out std_logic);`
84			`end component;`
85
86			`component atc18_iopad`
87			`generic (level : integer := 0; slew : integer := 0;`
88			`voltage : integer := 0; strength : integer := 0);`
89			`port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);`
90			`end component;`
91
92			`component atc18_outpad`
93			`generic (level : integer := 0; slew : integer := 0;`
94			`voltage : integer := 0; strength : integer := 0);`
95			`port (pad : out std_logic; i : in std_logic);`
96			`end component;`
97
98			`component atc18_odpad`
99			`generic (level : integer := 0; slew : integer := 0;`
100			`voltage : integer := 0; strength : integer := 0);`
101			`port (pad : out std_logic; i : in std_logic);`
102			`end component;`
103
104			`component atc18_toutpad`
105			`generic (level : integer := 0; slew : integer := 0;`
106			`voltage : integer := 0; strength : integer := 0);`
107			`port (pad : out std_logic; i, en : in std_logic);`
108			`end component;`
109
110			`component atc18_clkpad`
111			`generic (level : integer := 0; voltage : integer := 0);`
112			`port (pad : in std_logic; o : out std_logic);`
113			`end component;`
114
115			`component ihp25_inpad`
116			`generic(level : integer := 0; voltage : integer := 0);`
117			`port (pad : in std_logic; o : out std_logic);`
118			`end component;`
119
120			`component ihp25rh_inpad`
121			`generic(level : integer := 0; voltage : integer := 0);`
122			`port (pad : in std_logic; o : out std_logic);`
123			`end component;`
124
125			`component ihp25_iopad`
126			`generic (level : integer := 0; slew : integer := 0;`
127			`voltage : integer := 0; strength : integer := 0);`
128			`port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);`
129			`end component;`
130
131			`component ihp25rh_iopad`
132			`generic (level : integer := 0; slew : integer := 0;`
133			`voltage : integer := 0; strength : integer := 0);`
134			`port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);`
135			`end component;`
136
137			`component ihp25_outpad`
138			`generic (level : integer := 0; slew : integer := 0;`
139			`voltage : integer := 0; strength : integer := 0);`
140			`port (pad : out std_logic; i : in std_logic);`
141			`end component;`
142
143			`component ihp25rh_outpad`
144			`generic (level : integer := 0; slew : integer := 0;`
145			`voltage : integer := 0; strength : integer := 0);`
146			`port (pad : out std_logic; i : in std_logic);`
147			`end component;`
148
149			`component ihp25_toutpad`
150			`generic (level : integer := 0; slew : integer := 0;`
151			`voltage : integer := 0; strength : integer := 0);`
152			`port (pad : out std_ulogic; i, en : in std_logic);`
153			`end component;`
154
155			`component ihp25rh_toutpad`
156			`generic (level : integer := 0; slew : integer := 0;`
157			`voltage : integer := 0; strength : integer := 0);`
158			`port (pad : out std_ulogic; i, en : in std_logic);`
159			`end component;`
160
161			`component ihp25_clkpad`
162			`generic (level : integer := 0; voltage : integer := 0);`
163			`port (pad : in std_ulogic; o : out std_ulogic);`
164			`end component;`
165
166			`component ihp25rh_clkpad`
167			`generic (level : integer := 0; voltage : integer := 0);`
168			`port (pad : in std_ulogic; o : out std_ulogic);`
169			`end component;`
170
171			`component rhumc_inpad`
172			`generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);`
173			`port (pad : in std_logic; o : out std_logic);`
174			`end component;`
175
176			`component rhumc_iopad`
177			`generic (level : integer := 0; slew : integer := 0;`
178			`voltage : integer := 0; strength : integer := 0);`
179			`port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);`
180			`end component;`
181
182			`component rhumc_outpad`
183			`generic (level : integer := 0; slew : integer := 0;`
184			`voltage : integer := 0; strength : integer := 0);`
185			`port (pad : out std_logic; i : in std_logic);`
186			`end component;`
187
188			`component rhumc_toutpad`
189			`generic (level : integer := 0; slew : integer := 0;`
190			`voltage : integer := 0; strength : integer := 0);`
191			`port (pad : out std_logic; i, en : in std_logic);`
192			`end component;`
193
194			`component umc_inpad`
195			`generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);`
196			`port (pad : in std_logic; o : out std_logic);`
197			`end component;`
198
199			`component umc_iopad`
200			`generic (level : integer := 0; slew : integer := 0;`
201			`voltage : integer := 0; strength : integer := 0);`
202			`port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);`
203			`end component;`
204
205			`component umc_outpad`
206			`generic (level : integer := 0; slew : integer := 0;`
207			`voltage : integer := 0; strength : integer := 0);`
208			`port (pad : out std_logic; i : in std_logic);`
209			`end component;`
210
211			`component umc_toutpad`
212			`generic (level : integer := 0; slew : integer := 0;`
213			`voltage : integer := 0; strength : integer := 0);`
214			`port (pad : out std_logic; i, en : in std_logic);`
215			`end component;`
216
217			`component virtex_inpad`
218			`generic (level : integer := 0; voltage : integer := x33v);`
219			`port (pad : in std_ulogic; o : out std_ulogic);`
220			`end component;`
221
222			`component virtex_iopad`
223			`generic (level : integer := 0; slew : integer := 0;`
224			`voltage : integer := x33v; strength : integer := 12);`
225			`port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);`
226			`end component;`
227
228			`component virtex_outpad`
229			`generic (level : integer := 0; slew : integer := 0;`
230			`voltage : integer := x33v; strength : integer := 12);`
231			`port (pad : out std_ulogic; i : in std_ulogic);`
232			`end component;`
233
234			`component virtex_odpad`
235			`generic (level : integer := 0; slew : integer := 0;`
236			`voltage : integer := x33v; strength : integer := 12);`
237			`port (pad : out std_ulogic; i : in std_ulogic);`
238			`end component;`
239
240			`component virtex_toutpad`
241			`generic (level : integer := 0; slew : integer := 0;`
242			`voltage : integer := x33v; strength : integer := 12);`
243			`port (pad : out std_ulogic; i, en : in std_ulogic);`
244			`end component;`
245
246			`component virtex_skew_outpad`
247			`generic (level : integer := 0; slew : integer := 0;`
248			`voltage : integer := x33v; strength : integer := 12; skew : integer := 0);`
249			`port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;`
250			`o : out std_ulogic);`
251			`end component;`
252
253			`component virtex_clkpad`
254			`generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0);`
255			`port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);`
256			`end component;`
257
258			`component virtex_inpad_ds`
259			`generic (level : integer := lvds; voltage : integer := x33v);`
260			`port (padp, padn : in std_ulogic; o : out std_ulogic);`
261			`end component;`
262
263			`component virtex5_iopad_ds`
264			`generic (level : integer := 0; slew : integer := 0;`
265			`voltage : integer := x33v; strength : integer := 12);`
266			`port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);`
267			`end component;`
268
269			`component virtex4_inpad_ds`
270			`generic (level : integer := lvds; voltage : integer := x33v);`
271			`port (padp, padn : in std_ulogic; o : out std_ulogic);`
272			`end component;`
273
274			`component virtex_outpad_ds`
275			`generic (level : integer := lvds; voltage : integer := x33v);`
276			`port (padp, padn : out std_ulogic; i : in std_ulogic);`
277			`end component;`
278
279			`component virtex5_outpad_ds`
280			`generic (level : integer := lvds; voltage : integer := x33v);`
281			`port (padp, padn : out std_ulogic; i : in std_ulogic);`
282			`end component;`
283
284			`component virtex4_clkpad_ds is`
285			`generic (level : integer := lvds; voltage : integer := x33v);`
286			`port (padp, padn : in std_ulogic; o : out std_ulogic);`
287			`end component;`
288
289			`component virtex_clkpad_ds is`
290			`generic (level : integer := lvds; voltage : integer := x33v);`
291			`port (padp, padn : in std_ulogic; o : out std_ulogic);`
292			`end component;`
293
294			`component rh_lib18t_inpad`
295			`generic ( voltage : integer := 0; filter : integer := 0);`
296			`port (pad : in std_logic; o : out std_logic);`
297			`end component;`
298
299			`component rh_lib18t_iopad`
300			`generic ( strength : integer := 0);`
301			`port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);`
302			`end component;`
303
304			`component rh_lib18t_inpad_ds is`
305			`port (padp, padn : in std_ulogic; o : out std_ulogic; en : in std_ulogic);`
306			`end component;`
307
308			`component rh_lib18t_outpad_ds is`
309			`port (padp, padn : out std_ulogic; i, en : in std_ulogic);`
310			`end component;`
311
312			`component ut025crh_inpad`
313			`generic ( level : integer := 0; voltage : integer := 0; filter : integer := 0);`
314			`port (pad : in std_logic; o : out std_logic);`
315			`end component;`
316
317			`component ut025crh_iopad is`
318			`generic (level : integer := 0; slew : integer := 0;`
319			`voltage : integer := 0; strength : integer := 0);`
320			`port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);`
321			`end component;`
322
323			`component ut025crh_outpad`
324			`generic (level : integer := 0; slew : integer := 0;`
325			`voltage : integer := 0; strength : integer := 0);`
326			`port (pad : out std_ulogic; i : in std_ulogic);`
327			`end component;`
328
329			`component ut025crh_toutpad`
330			`generic (level : integer := 0; slew : integer := 0;`
331			`voltage : integer := 0; strength : integer := 0);`
332			`port (pad : out std_ulogic; i, en : in std_ulogic);`
333			`end component;`
334
335			`component ut025crh_lvds_combo`
336			`generic (voltage : integer := 0; width : integer := 1);`
337			`port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);`
338			`odval, osval, en : in std_logic_vector(0 to width-1);`
339			`idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);`
340			`idval, isval : out std_logic_vector(0 to width-1));`
341			`end component;`
342
343			`component rhumc_lvds_combo`
344			`generic (voltage : integer := 0; width : integer := 1);`
345			`port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);`
346			`odval, osval, en : in std_logic_vector(0 to width-1);`
347			`idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);`
348			`idval, isval : out std_logic_vector(0 to width-1);`
349			`lvdsref : in std_logic);`
350			`end component;`
351
352			`component umc_lvds_combo`
353			`generic (voltage : integer := 0; width : integer := 1);`
354			`port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);`
355			`odval, osval, en : in std_logic_vector(0 to width-1);`
356			`idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);`
357			`idval, isval : out std_logic_vector(0 to width-1);`
358			`lvdsref : in std_logic);`
359			`end component;`
360
361			`component peregrine_inpad is`
362			`generic (level : integer := 0; voltage : integer := 0; filter : integer := 0;`
363			`strength : integer := 0);`
364			`port (pad : in std_ulogic; o : out std_ulogic);`
365			`end component;`
366
367			`component peregrine_iopad is`
368			`generic (level : integer := 0; slew : integer := 0;`
369			`voltage : integer := 0; strength : integer := 0);`
370			`port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);`
371			`end component;`
372
373			`component peregrine_toutpad is`
374			`generic (level : integer := 0; slew : integer := 0;`
375			`voltage : integer := 0; strength : integer := 0);`
376			`port (pad : out std_ulogic; i, en : in std_ulogic);`
377			`end component;`
378
379			`component nextreme_inpad`
380			`generic (level : integer := 0; voltage : integer := 0);`
381			`port (pad : in std_logic; o : out std_logic);`
382			`end component;`
383
384			`component nextreme_iopad`
385			`generic (level : integer := 0; slew : integer := 0;`
386			`voltage : integer := 0; strength : integer := 0);`
387			`port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);`
388			`end component;`
389
390			`component nextreme_toutpad`
391			`generic (level : integer := 0; slew : integer := 0;`
392			`voltage : integer := 0; strength : integer := 0);`
393			`port (pad : out std_logic; i, en : in std_logic);`
394			`end component;`
395
396			`component atc18rha_inpad`
397			`generic (level : integer := 0; voltage : integer := 0);`
398			`port (pad : in std_logic; o : out std_logic);`
399			`end component;`
400
401			`component atc18rha_iopad`
402			`generic (level : integer := 0; slew : integer := 0;`
403			`voltage : integer := 0; strength : integer := 0);`
404			`port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);`
405			`end component;`
406
407			`component atc18rha_outpad`
408			`generic (level : integer := 0; slew : integer := 0;`
409			`voltage : integer := 0; strength : integer := 0);`
410			`port (pad : out std_logic; i : in std_logic);`
411			`end component;`
412
413			`component atc18rha_odpad`
414			`generic (level : integer := 0; slew : integer := 0;`
415			`voltage : integer := 0; strength : integer := 0);`
416			`port (pad : out std_logic; i : in std_logic);`
417			`end component;`
418
419			`component atc18rha_toutpad`
420			`generic (level : integer := 0; slew : integer := 0;`
421			`voltage : integer := 0; strength : integer := 0);`
422			`port (pad : out std_logic; i, en : in std_logic);`
423			`end component;`
424
425			`component atc18rha_clkpad`
426			`generic (level : integer := 0; voltage : integer := 0);`
427			`port (pad : in std_logic; o : out std_logic);`
428			`end component;`
429
430			`end;`