1 |
2 |
dimamali |
------------------------------------------------------------------------------
|
2 |
|
|
-- This file is a part of the GRLIB VHDL IP LIBRARY
|
3 |
|
|
-- Copyright (C) 2003, Gaisler Research
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you can redistribute it and/or modify
|
6 |
|
|
-- it under the terms of the GNU General Public License as published by
|
7 |
|
|
-- the Free Software Foundation; either version 2 of the License, or
|
8 |
|
|
-- (at your option) any later version.
|
9 |
|
|
--
|
10 |
|
|
-- This program is distributed in the hope that it will be useful,
|
11 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
|
|
-- GNU General Public License for more details.
|
14 |
|
|
--
|
15 |
|
|
-- You should have received a copy of the GNU General Public License
|
16 |
|
|
-- along with this program; if not, write to the Free Software
|
17 |
|
|
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
18 |
|
|
-----------------------------------------------------------------------------
|
19 |
|
|
-- Entity: clkpad
|
20 |
|
|
-- File: clkpad.vhd
|
21 |
|
|
-- Author: Jiri Gaisler - Gaisler Research
|
22 |
|
|
-- Description: Clock pad with technology wrapper
|
23 |
|
|
------------------------------------------------------------------------------
|
24 |
|
|
|
25 |
|
|
library techmap;
|
26 |
|
|
library ieee;
|
27 |
|
|
use ieee.std_logic_1164.all;
|
28 |
|
|
use techmap.gencomp.all;
|
29 |
|
|
use techmap.allpads.all;
|
30 |
|
|
|
31 |
|
|
entity clkpad is
|
32 |
|
|
generic (tech : integer := 0; level : integer := 0;
|
33 |
|
|
voltage : integer := x33v; arch : integer := 0;
|
34 |
|
|
hf : integer := 0);
|
35 |
|
|
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1'; lock : out std_ulogic);
|
36 |
|
|
end;
|
37 |
|
|
|
38 |
|
|
architecture rtl of clkpad is
|
39 |
|
|
begin
|
40 |
|
|
gen0 : if has_pads(tech) = 0 generate
|
41 |
|
|
o <= to_X01(pad);
|
42 |
|
|
end generate;
|
43 |
|
|
xcv : if (tech = virtex) generate
|
44 |
|
|
u0 : virtex_clkpad generic map (level, voltage, 0, 0) port map (pad, o, rstn);
|
45 |
|
|
end generate;
|
46 |
|
|
xcv2 : if (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
|
47 |
|
|
u0 : virtex_clkpad generic map (level, voltage, arch, hf) port map (pad, o, rstn, lock);
|
48 |
|
|
end generate;
|
49 |
|
|
axc : if (tech = axcel) generate
|
50 |
|
|
u0 : axcel_clkpad generic map (level, voltage) port map (pad, o);
|
51 |
|
|
end generate;
|
52 |
|
|
pa3 : if (tech = proasic) or (tech = apa3) generate
|
53 |
|
|
u0 : apa3_clkpad generic map (level, voltage) port map (pad, o);
|
54 |
|
|
end generate;
|
55 |
|
|
atc : if (tech = atc18s) generate
|
56 |
|
|
u0 : atc18_clkpad generic map (level, voltage) port map (pad, o);
|
57 |
|
|
end generate;
|
58 |
|
|
atcrh : if (tech = atc18rha) generate
|
59 |
|
|
u0 : atc18rha_clkpad generic map (level, voltage) port map (pad, o);
|
60 |
|
|
end generate;
|
61 |
|
|
um : if (tech = umc) generate
|
62 |
|
|
u0 : umc_inpad generic map (level, voltage) port map (pad, o);
|
63 |
|
|
end generate;
|
64 |
|
|
rhu : if (tech = rhumc) generate
|
65 |
|
|
u0 : rhumc_inpad generic map (level, voltage) port map (pad, o);
|
66 |
|
|
end generate;
|
67 |
|
|
ihp : if (tech = ihp25) generate
|
68 |
|
|
u0 : ihp25_clkpad generic map (level, voltage) port map (pad, o);
|
69 |
|
|
end generate;
|
70 |
|
|
rh18t : if (tech = rhlib18t) generate
|
71 |
|
|
u0 : rh_lib18t_inpad port map (pad, o);
|
72 |
|
|
end generate;
|
73 |
|
|
ut025 : if (tech = ut25) generate
|
74 |
|
|
u0 : ut025crh_inpad port map (pad, o);
|
75 |
|
|
end generate;
|
76 |
|
|
pere : if (tech = peregrine) generate
|
77 |
|
|
u0 : peregrine_inpad port map (pad, o);
|
78 |
|
|
end generate;
|
79 |
|
|
end;
|