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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: inpad_ds
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-- File: inpad_ds.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: input pad with technology wrapper
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------------------------------------------------------------------------------
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library techmap;
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library ieee;
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use ieee.std_logic_1164.all;
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use techmap.gencomp.all;
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use techmap.allpads.all;
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entity inpad_ds is
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generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end;
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architecture rtl of inpad_ds is
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signal gnd : std_ulogic;
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begin
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gnd <= '0';
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gen0 : if has_ds_pads(tech) = 0 generate
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o <= to_X01(padp) after 1 ns;
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end generate;
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xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) generate
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u0 : virtex_inpad_ds generic map (level, voltage) port map (padp, padn, o);
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end generate;
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xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
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u0 : virtex4_inpad_ds generic map (level, voltage) port map (padp, padn, o);
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end generate;
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axc : if (tech = axcel) generate
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u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
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end generate;
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rht : if (tech = rhlib18t) generate
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u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
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end generate;
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end;
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library techmap;
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library ieee;
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use ieee.std_logic_1164.all;
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use techmap.gencomp.all;
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entity inpad_dsv is
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generic (tech : integer := 0; level : integer := lvds;
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voltage : integer := x33v; width : integer := 1);
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port (
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padp : in std_logic_vector(width-1 downto 0);
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padn : in std_logic_vector(width-1 downto 0);
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o : out std_logic_vector(width-1 downto 0));
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end;
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architecture rtl of inpad_dsv is
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begin
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v : for i in width-1 downto 0 generate
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u0 : inpad_ds generic map (tech, level, voltage) port map (padp(i), padn(i), o(i));
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end generate;
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end;
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