1 |
2 |
dimamali |
------------------------------------------------------------------------------
|
2 |
|
|
-- This file is a part of the GRLIB VHDL IP LIBRARY
|
3 |
|
|
-- Copyright (C) 2003, Gaisler Research
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you can redistribute it and/or modify
|
6 |
|
|
-- it under the terms of the GNU General Public License as published by
|
7 |
|
|
-- the Free Software Foundation; either version 2 of the License, or
|
8 |
|
|
-- (at your option) any later version.
|
9 |
|
|
--
|
10 |
|
|
-- This program is distributed in the hope that it will be useful,
|
11 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
|
|
-- GNU General Public License for more details.
|
14 |
|
|
--
|
15 |
|
|
-- You should have received a copy of the GNU General Public License
|
16 |
|
|
-- along with this program; if not, write to the Free Software
|
17 |
|
|
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
18 |
|
|
-----------------------------------------------------------------------------
|
19 |
|
|
-- Entity: regfile_3p
|
20 |
|
|
-- File: regfile_3p.vhd
|
21 |
|
|
-- Author: Jiri Gaisler Gaisler Research
|
22 |
|
|
-- Description: 3-port regfile implemented with two 2-port rams
|
23 |
|
|
------------------------------------------------------------------------------
|
24 |
|
|
|
25 |
|
|
library ieee;
|
26 |
|
|
library techmap;
|
27 |
|
|
use ieee.std_logic_1164.all;
|
28 |
|
|
use techmap.gencomp.all;
|
29 |
|
|
use techmap.allmem.all;
|
30 |
|
|
|
31 |
|
|
entity regfile_3p is
|
32 |
|
|
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
|
33 |
|
|
wrfst : integer := 0; numregs : integer := 64);
|
34 |
|
|
port (
|
35 |
|
|
wclk : in std_ulogic;
|
36 |
|
|
waddr : in std_logic_vector((abits -1) downto 0);
|
37 |
|
|
wdata : in std_logic_vector((dbits -1) downto 0);
|
38 |
|
|
we : in std_ulogic;
|
39 |
|
|
rclk : in std_ulogic;
|
40 |
|
|
raddr1 : in std_logic_vector((abits -1) downto 0);
|
41 |
|
|
re1 : in std_ulogic;
|
42 |
|
|
rdata1 : out std_logic_vector((dbits -1) downto 0);
|
43 |
|
|
raddr2 : in std_logic_vector((abits -1) downto 0);
|
44 |
|
|
re2 : in std_ulogic;
|
45 |
|
|
rdata2 : out std_logic_vector((dbits -1) downto 0);
|
46 |
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
47 |
|
|
end;
|
48 |
|
|
|
49 |
|
|
architecture rtl of regfile_3p is
|
50 |
|
|
constant rfinfer : boolean := (regfile_3p_infer(tech) = 1) or
|
51 |
|
|
(((tech = spartan3) or (tech = spartan3e) or (tech = virtex2) or (tech = virtex4) or (tech = virtex5)) and (abits <= 5));
|
52 |
|
|
begin
|
53 |
|
|
|
54 |
|
|
s0 : if rfinfer generate
|
55 |
|
|
rhu : generic_regfile_3p generic map (tech, abits, dbits, wrfst, numregs)
|
56 |
|
|
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2);
|
57 |
|
|
end generate;
|
58 |
|
|
|
59 |
|
|
s1 : if not rfinfer generate
|
60 |
|
|
pere : if tech = peregrine generate
|
61 |
|
|
rfhard : peregrine_regfile_3p generic map (abits, dbits)
|
62 |
|
|
port map ( wclk, waddr, wdata, we, raddr1, re1, rdata1, raddr2, re2, rdata2);
|
63 |
|
|
end generate;
|
64 |
|
|
dp : if tech /= peregrine generate
|
65 |
|
|
x0 : syncram_2p generic map (tech, abits, dbits, 0, wrfst)
|
66 |
|
|
port map (rclk, re1, raddr1, rdata1, wclk, we, waddr, wdata, testin);
|
67 |
|
|
x1 : syncram_2p generic map (tech, abits, dbits, 0, wrfst)
|
68 |
|
|
port map (rclk, re2, raddr2, rdata2, wclk, we, waddr, wdata, testin);
|
69 |
|
|
end generate;
|
70 |
|
|
end generate;
|
71 |
|
|
|
72 |
|
|
end;
|
73 |
|
|
|