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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [ssrctrl_net.vhd] - Blame information for rev 2

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------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Entity:        ssrctrl_net
-- file:          ssrctrl_net.vhd
-- Description:   Wrapper for SSRAM controller
------------------------------------------------------------------------------
library  ieee;
use      ieee.std_logic_1164.all;
 
library  techmap;
use      techmap.gencomp.all;
 
entity ssrctrl_net is
   generic (
      tech:                   Integer := 0;
      bus16:                  Integer := 1);
   port (
      rst:              in    Std_Logic;
      clk:              in    Std_Logic;
 
      n_ahbsi_hsel:     in    Std_Logic_Vector(0 to 15);
      n_ahbsi_haddr:    in    Std_Logic_Vector(31 downto 0);
      n_ahbsi_hwrite:   in    Std_Logic;
      n_ahbsi_htrans:   in    Std_Logic_Vector(1 downto 0);
      n_ahbsi_hsize:    in    Std_Logic_Vector(2 downto 0);
      n_ahbsi_hburst:   in    Std_Logic_Vector(2 downto 0);
      n_ahbsi_hwdata:   in    Std_Logic_Vector(31 downto 0);
      n_ahbsi_hprot:    in    Std_Logic_Vector(3 downto 0);
      n_ahbsi_hready:   in    Std_Logic;
      n_ahbsi_hmaster:  in    Std_Logic_Vector(3 downto 0);
      n_ahbsi_hmastlock:in    Std_Logic;
      n_ahbsi_hmbsel:   in    Std_Logic_Vector(0 to 3);
      n_ahbsi_hcache:   in    Std_Logic;
      n_ahbsi_hirq:     in    Std_Logic_Vector(31 downto 0);
 
      n_ahbso_hready:   out   Std_Logic;
      n_ahbso_hresp:    out   Std_Logic_Vector(1 downto 0);
      n_ahbso_hrdata:   out   Std_Logic_Vector(31 downto 0);
      n_ahbso_hsplit:   out   Std_Logic_Vector(15 downto 0);
      n_ahbso_hcache:   out   Std_Logic;
      n_ahbso_hirq:     out   Std_Logic_Vector(31 downto 0);
 
      n_apbi_psel:      in    Std_Logic_Vector(0 to 15);
      n_apbi_penable:   in    Std_Logic;
      n_apbi_paddr:     in    Std_Logic_Vector(31 downto 0);
      n_apbi_pwrite:    in    Std_Logic;
      n_apbi_pwdata:    in    Std_Logic_Vector(31 downto 0);
      n_apbi_pirq:      in    Std_Logic_Vector(31 downto 0);
 
      n_apbo_prdata:    out   Std_Logic_Vector(31 downto 0);
      n_apbo_pirq:      out   Std_Logic_Vector(31 downto 0);
 
      n_sri_data:       in    Std_Logic_Vector(31 downto 0);
      n_sri_brdyn:      in    Std_Logic;
      n_sri_bexcn:      in    Std_Logic;
      n_sri_writen:     in    Std_Logic;
      n_sri_wrn:        in    Std_Logic_Vector(3 downto 0);
      n_sri_bwidth:     in    Std_Logic_Vector(1 downto 0);
      n_sri_sd:         in    Std_Logic_Vector(63 downto 0);
      n_sri_cb:         in    Std_Logic_Vector(7 downto 0);
      n_sri_scb:        in    Std_Logic_Vector(7 downto 0);
      n_sri_edac:       in    Std_Logic;
 
      n_sro_address:    out   Std_Logic_Vector(31 downto 0);
      n_sro_data:       out   Std_Logic_Vector(31 downto 0);
      n_sro_sddata:     out   Std_Logic_Vector(63 downto 0);
      n_sro_ramsn:      out   Std_Logic_Vector(7 downto 0);
      n_sro_ramoen:     out   Std_Logic_Vector(7 downto 0);
      n_sro_ramn:       out   Std_Logic;
      n_sro_romn:       out   Std_Logic;
      n_sro_mben:       out   Std_Logic_Vector(3 downto 0);
      n_sro_iosn:       out   Std_Logic;
      n_sro_romsn:      out   Std_Logic_Vector(7 downto 0);
      n_sro_oen:        out   Std_Logic;
      n_sro_writen:     out   Std_Logic;
      n_sro_wrn:        out   Std_Logic_Vector(3 downto 0);
      n_sro_bdrive:     out   Std_Logic_Vector(3 downto 0);
      n_sro_vbdrive:    out   Std_Logic_Vector(31 downto 0);
      n_sro_svbdrive:   out   Std_Logic_Vector(63 downto 0);
      n_sro_read:       out   Std_Logic;
      n_sro_sa:         out   Std_Logic_Vector(14 downto 0);
      n_sro_cb:         out   Std_Logic_Vector(7 downto 0);
      n_sro_scb:        out   Std_Logic_Vector(7 downto 0);
      n_sro_vcdrive:    out   Std_Logic_Vector(7 downto 0);
      n_sro_svcdrive:   out   Std_Logic_Vector(7 downto 0);
      n_sro_ce:         out   Std_Logic);
end entity ssrctrl_net;
 
architecture rtl of ssrctrl_net is
   component ssrctrl_unisim
   port (
      rst:              in    Std_Logic;
      clk:              in    Std_Logic;
 
      n_ahbsi_hsel:     in    Std_Logic_Vector(0 to 15);
      n_ahbsi_haddr:    in    Std_Logic_Vector(31 downto 0);
      n_ahbsi_hwrite:   in    Std_Logic;
      n_ahbsi_htrans:   in    Std_Logic_Vector(1 downto 0);
      n_ahbsi_hsize:    in    Std_Logic_Vector(2 downto 0);
      n_ahbsi_hburst:   in    Std_Logic_Vector(2 downto 0);
      n_ahbsi_hwdata:   in    Std_Logic_Vector(31 downto 0);
      n_ahbsi_hprot:    in    Std_Logic_Vector(3 downto 0);
      n_ahbsi_hready:   in    Std_Logic;
      n_ahbsi_hmaster:  in    Std_Logic_Vector(3 downto 0);
      n_ahbsi_hmastlock:in    Std_Logic;
      n_ahbsi_hmbsel:   in    Std_Logic_Vector(0 to 3);
      n_ahbsi_hcache:   in    Std_Logic;
      n_ahbsi_hirq:     in    Std_Logic_Vector(31 downto 0);
 
      n_ahbso_hready:   out   Std_Logic;
      n_ahbso_hresp:    out   Std_Logic_Vector(1 downto 0);
      n_ahbso_hrdata:   out   Std_Logic_Vector(31 downto 0);
      n_ahbso_hsplit:   out   Std_Logic_Vector(15 downto 0);
      n_ahbso_hcache:   out   Std_Logic;
      n_ahbso_hirq:     out   Std_Logic_Vector(31 downto 0);
 
      n_apbi_psel:      in    Std_Logic_Vector(0 to 15);
      n_apbi_penable:   in    Std_Logic;
      n_apbi_paddr:     in    Std_Logic_Vector(31 downto 0);
      n_apbi_pwrite:    in    Std_Logic;
      n_apbi_pwdata:    in    Std_Logic_Vector(31 downto 0);
      n_apbi_pirq:      in    Std_Logic_Vector(31 downto 0);
 
      n_apbo_prdata:    out   Std_Logic_Vector(31 downto 0);
      n_apbo_pirq:      out   Std_Logic_Vector(31 downto 0);
 
      n_sri_data:       in    Std_Logic_Vector(31 downto 0);
      n_sri_brdyn:      in    Std_Logic;
      n_sri_bexcn:      in    Std_Logic;
      n_sri_writen:     in    Std_Logic;
      n_sri_wrn:        in    Std_Logic_Vector(3 downto 0);
      n_sri_bwidth:     in    Std_Logic_Vector(1 downto 0);
      n_sri_sd:         in    Std_Logic_Vector(63 downto 0);
      n_sri_cb:         in    Std_Logic_Vector(7 downto 0);
      n_sri_scb:        in    Std_Logic_Vector(7 downto 0);
      n_sri_edac:       in    Std_Logic;
 
      n_sro_address:    out   Std_Logic_Vector(31 downto 0);
      n_sro_data:       out   Std_Logic_Vector(31 downto 0);
      n_sro_sddata:     out   Std_Logic_Vector(63 downto 0);
      n_sro_ramsn:      out   Std_Logic_Vector(7 downto 0);
      n_sro_ramoen:     out   Std_Logic_Vector(7 downto 0);
      n_sro_ramn:       out   Std_Logic;
      n_sro_romn:       out   Std_Logic;
      n_sro_mben:       out   Std_Logic_Vector(3 downto 0);
      n_sro_iosn:       out   Std_Logic;
      n_sro_romsn:      out   Std_Logic_Vector(7 downto 0);
      n_sro_oen:        out   Std_Logic;
      n_sro_writen:     out   Std_Logic;
      n_sro_wrn:        out   Std_Logic_Vector(3 downto 0);
      n_sro_bdrive:     out   Std_Logic_Vector(3 downto 0);
      n_sro_vbdrive:    out   Std_Logic_Vector(31 downto 0);
      n_sro_svbdrive:   out   Std_Logic_Vector(63 downto 0);
      n_sro_read:       out   Std_Logic;
      n_sro_sa:         out   Std_Logic_Vector(14 downto 0);
      n_sro_cb:         out   Std_Logic_Vector(7 downto 0);
      n_sro_scb:        out   Std_Logic_Vector(7 downto 0);
      n_sro_vcdrive:    out   Std_Logic_Vector(7 downto 0);
      n_sro_svcdrive:   out   Std_Logic_Vector(7 downto 0);
      n_sro_ce:         out   Std_Logic);
   end component;
 
begin
   xil : if ((tech = virtex2)  or (tech = virtex4) or (tech = virtex5) or
             (tech = spartan3) or (tech = spartan3e)) and bus16=1 generate
      ssrctrlxil: ssrctrl_unisim
         port map(
            rst               => rst,
            clk               => clk,
            n_ahbsi_hsel      => n_ahbsi_hsel,
            n_ahbsi_haddr     => n_ahbsi_haddr,
            n_ahbsi_hwrite    => n_ahbsi_hwrite,
            n_ahbsi_htrans    => n_ahbsi_htrans,
            n_ahbsi_hsize     => n_ahbsi_hsize,
            n_ahbsi_hburst    => n_ahbsi_hburst,
            n_ahbsi_hwdata    => n_ahbsi_hwdata,
            n_ahbsi_hprot     => n_ahbsi_hprot,
            n_ahbsi_hready    => n_ahbsi_hready,
            n_ahbsi_hmaster   => n_ahbsi_hmaster,
            n_ahbsi_hmastlock => n_ahbsi_hmastlock,
            n_ahbsi_hmbsel    => n_ahbsi_hmbsel,
            n_ahbsi_hcache    => n_ahbsi_hcache,
            n_ahbsi_hirq      => n_ahbsi_hirq,
            n_ahbso_hready    => n_ahbso_hready,
            n_ahbso_hresp     => n_ahbso_hresp,
            n_ahbso_hrdata    => n_ahbso_hrdata,
            n_ahbso_hsplit    => n_ahbso_hsplit,
            n_ahbso_hcache    => n_ahbso_hcache,
            n_ahbso_hirq      => n_ahbso_hirq,
            n_apbi_psel       => n_apbi_psel,
            n_apbi_penable    => n_apbi_penable,
            n_apbi_paddr      => n_apbi_paddr,
            n_apbi_pwrite     => n_apbi_pwrite,
            n_apbi_pwdata     => n_apbi_pwdata,
            n_apbi_pirq       => n_apbi_pirq,
            n_apbo_prdata     => n_apbo_prdata,
            n_apbo_pirq       => n_apbo_pirq,
            n_sri_data        => n_sri_data,
            n_sri_brdyn       => n_sri_brdyn,
            n_sri_bexcn       => n_sri_bexcn,
            n_sri_writen      => n_sri_writen,
            n_sri_wrn         => n_sri_wrn,
            n_sri_bwidth      => n_sri_bwidth,
            n_sri_sd          => n_sri_sd,
            n_sri_cb          => n_sri_cb,
            n_sri_scb         => n_sri_scb,
            n_sri_edac        => n_sri_edac,
            n_sro_address     => n_sro_address,
            n_sro_data        => n_sro_data,
            n_sro_sddata      => n_sro_sddata,
            n_sro_ramsn       => n_sro_ramsn,
            n_sro_ramoen      => n_sro_ramoen,
            n_sro_ramn        => n_sro_ramn,
            n_sro_romn        => n_sro_romn,
            n_sro_mben        => n_sro_mben,
            n_sro_iosn        => n_sro_iosn,
            n_sro_romsn       => n_sro_romsn,
            n_sro_oen         => n_sro_oen,
            n_sro_writen      => n_sro_writen,
            n_sro_wrn         => n_sro_wrn,
            n_sro_bdrive      => n_sro_bdrive,
            n_sro_vbdrive     => n_sro_vbdrive,
            n_sro_svbdrive    => n_sro_svbdrive,
            n_sro_read        => n_sro_read,
            n_sro_sa          => n_sro_sa,
            n_sro_cb          => n_sro_cb,
            n_sro_scb         => n_sro_scb,
            n_sro_vcdrive     => n_sro_vcdrive,
            n_sro_svcdrive    => n_sro_svcdrive,
            n_sro_ce          => n_sro_ce);
   end generate;
 
-- pragma translate_off
   nonet : if not (((tech = virtex2)  or (tech = virtex4) or (tech = virtex5) or
                    (tech = spartan3) or (tech = spartan3e)))
      generate
         err : process
         begin
            assert False report "ERROR : No ssrctrl netlist available for this technology!"
            severity Failure;
            wait;
         end process;
      end generate;
   nobus16 : if not ( bus16=1 )
      generate
         err : process
         begin
            assert False report "ERROR : 16-bit PROM bus option not selected for ssrctrl netlist!"
            severity Failure;
            wait;
         end process;
      end generate;
-- pragma translate_on
 
end architecture;

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [ssrctrl_net.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Entity: ssrctrl_net`
20			`-- file: ssrctrl_net.vhd`
21			`-- Description: Wrapper for SSRAM controller`
22			`------------------------------------------------------------------------------`
23			`library ieee;`
24			`use ieee.std_logic_1164.all;`
25
26			`library techmap;`
27			`use techmap.gencomp.all;`
28
29			`entity ssrctrl_net is`
30			`generic (`
31			`tech: Integer := 0;`
32			`bus16: Integer := 1);`
33			`port (`
34			`rst: in Std_Logic;`
35			`clk: in Std_Logic;`
36
37			`n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);`
38			`n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);`
39			`n_ahbsi_hwrite: in Std_Logic;`
40			`n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);`
41			`n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);`
42			`n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);`
43			`n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);`
44			`n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);`
45			`n_ahbsi_hready: in Std_Logic;`
46			`n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);`
47			`n_ahbsi_hmastlock:in Std_Logic;`
48			`n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);`
49			`n_ahbsi_hcache: in Std_Logic;`
50			`n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);`
51
52			`n_ahbso_hready: out Std_Logic;`
53			`n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);`
54			`n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);`
55			`n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);`
56			`n_ahbso_hcache: out Std_Logic;`
57			`n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);`
58
59			`n_apbi_psel: in Std_Logic_Vector(0 to 15);`
60			`n_apbi_penable: in Std_Logic;`
61			`n_apbi_paddr: in Std_Logic_Vector(31 downto 0);`
62			`n_apbi_pwrite: in Std_Logic;`
63			`n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);`
64			`n_apbi_pirq: in Std_Logic_Vector(31 downto 0);`
65
66			`n_apbo_prdata: out Std_Logic_Vector(31 downto 0);`
67			`n_apbo_pirq: out Std_Logic_Vector(31 downto 0);`
68
69			`n_sri_data: in Std_Logic_Vector(31 downto 0);`
70			`n_sri_brdyn: in Std_Logic;`
71			`n_sri_bexcn: in Std_Logic;`
72			`n_sri_writen: in Std_Logic;`
73			`n_sri_wrn: in Std_Logic_Vector(3 downto 0);`
74			`n_sri_bwidth: in Std_Logic_Vector(1 downto 0);`
75			`n_sri_sd: in Std_Logic_Vector(63 downto 0);`
76			`n_sri_cb: in Std_Logic_Vector(7 downto 0);`
77			`n_sri_scb: in Std_Logic_Vector(7 downto 0);`
78			`n_sri_edac: in Std_Logic;`
79
80			`n_sro_address: out Std_Logic_Vector(31 downto 0);`
81			`n_sro_data: out Std_Logic_Vector(31 downto 0);`
82			`n_sro_sddata: out Std_Logic_Vector(63 downto 0);`
83			`n_sro_ramsn: out Std_Logic_Vector(7 downto 0);`
84			`n_sro_ramoen: out Std_Logic_Vector(7 downto 0);`
85			`n_sro_ramn: out Std_Logic;`
86			`n_sro_romn: out Std_Logic;`
87			`n_sro_mben: out Std_Logic_Vector(3 downto 0);`
88			`n_sro_iosn: out Std_Logic;`
89			`n_sro_romsn: out Std_Logic_Vector(7 downto 0);`
90			`n_sro_oen: out Std_Logic;`
91			`n_sro_writen: out Std_Logic;`
92			`n_sro_wrn: out Std_Logic_Vector(3 downto 0);`
93			`n_sro_bdrive: out Std_Logic_Vector(3 downto 0);`
94			`n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);`
95			`n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);`
96			`n_sro_read: out Std_Logic;`
97			`n_sro_sa: out Std_Logic_Vector(14 downto 0);`
98			`n_sro_cb: out Std_Logic_Vector(7 downto 0);`
99			`n_sro_scb: out Std_Logic_Vector(7 downto 0);`
100			`n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);`
101			`n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);`
102			`n_sro_ce: out Std_Logic);`
103			`end entity ssrctrl_net;`
104
105			`architecture rtl of ssrctrl_net is`
106			`component ssrctrl_unisim`
107			`port (`
108			`rst: in Std_Logic;`
109			`clk: in Std_Logic;`
110
111			`n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);`
112			`n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);`
113			`n_ahbsi_hwrite: in Std_Logic;`
114			`n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);`
115			`n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);`
116			`n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);`
117			`n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);`
118			`n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);`
119			`n_ahbsi_hready: in Std_Logic;`
120			`n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);`
121			`n_ahbsi_hmastlock:in Std_Logic;`
122			`n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);`
123			`n_ahbsi_hcache: in Std_Logic;`
124			`n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);`
125
126			`n_ahbso_hready: out Std_Logic;`
127			`n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);`
128			`n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);`
129			`n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);`
130			`n_ahbso_hcache: out Std_Logic;`
131			`n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);`
132
133			`n_apbi_psel: in Std_Logic_Vector(0 to 15);`
134			`n_apbi_penable: in Std_Logic;`
135			`n_apbi_paddr: in Std_Logic_Vector(31 downto 0);`
136			`n_apbi_pwrite: in Std_Logic;`
137			`n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);`
138			`n_apbi_pirq: in Std_Logic_Vector(31 downto 0);`
139
140			`n_apbo_prdata: out Std_Logic_Vector(31 downto 0);`
141			`n_apbo_pirq: out Std_Logic_Vector(31 downto 0);`
142
143			`n_sri_data: in Std_Logic_Vector(31 downto 0);`
144			`n_sri_brdyn: in Std_Logic;`
145			`n_sri_bexcn: in Std_Logic;`
146			`n_sri_writen: in Std_Logic;`
147			`n_sri_wrn: in Std_Logic_Vector(3 downto 0);`
148			`n_sri_bwidth: in Std_Logic_Vector(1 downto 0);`
149			`n_sri_sd: in Std_Logic_Vector(63 downto 0);`
150			`n_sri_cb: in Std_Logic_Vector(7 downto 0);`
151			`n_sri_scb: in Std_Logic_Vector(7 downto 0);`
152			`n_sri_edac: in Std_Logic;`
153
154			`n_sro_address: out Std_Logic_Vector(31 downto 0);`
155			`n_sro_data: out Std_Logic_Vector(31 downto 0);`
156			`n_sro_sddata: out Std_Logic_Vector(63 downto 0);`
157			`n_sro_ramsn: out Std_Logic_Vector(7 downto 0);`
158			`n_sro_ramoen: out Std_Logic_Vector(7 downto 0);`
159			`n_sro_ramn: out Std_Logic;`
160			`n_sro_romn: out Std_Logic;`
161			`n_sro_mben: out Std_Logic_Vector(3 downto 0);`
162			`n_sro_iosn: out Std_Logic;`
163			`n_sro_romsn: out Std_Logic_Vector(7 downto 0);`
164			`n_sro_oen: out Std_Logic;`
165			`n_sro_writen: out Std_Logic;`
166			`n_sro_wrn: out Std_Logic_Vector(3 downto 0);`
167			`n_sro_bdrive: out Std_Logic_Vector(3 downto 0);`
168			`n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);`
169			`n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);`
170			`n_sro_read: out Std_Logic;`
171			`n_sro_sa: out Std_Logic_Vector(14 downto 0);`
172			`n_sro_cb: out Std_Logic_Vector(7 downto 0);`
173			`n_sro_scb: out Std_Logic_Vector(7 downto 0);`
174			`n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);`
175			`n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);`
176			`n_sro_ce: out Std_Logic);`
177			`end component;`
178
179			`begin`
180			`xil : if ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or`
181			`(tech = spartan3) or (tech = spartan3e)) and bus16=1 generate`
182			`ssrctrlxil: ssrctrl_unisim`
183			`port map(`
184			`rst => rst,`
185			`clk => clk,`
186			`n_ahbsi_hsel => n_ahbsi_hsel,`
187			`n_ahbsi_haddr => n_ahbsi_haddr,`
188			`n_ahbsi_hwrite => n_ahbsi_hwrite,`
189			`n_ahbsi_htrans => n_ahbsi_htrans,`
190			`n_ahbsi_hsize => n_ahbsi_hsize,`
191			`n_ahbsi_hburst => n_ahbsi_hburst,`
192			`n_ahbsi_hwdata => n_ahbsi_hwdata,`
193			`n_ahbsi_hprot => n_ahbsi_hprot,`
194			`n_ahbsi_hready => n_ahbsi_hready,`
195			`n_ahbsi_hmaster => n_ahbsi_hmaster,`
196			`n_ahbsi_hmastlock => n_ahbsi_hmastlock,`
197			`n_ahbsi_hmbsel => n_ahbsi_hmbsel,`
198			`n_ahbsi_hcache => n_ahbsi_hcache,`
199			`n_ahbsi_hirq => n_ahbsi_hirq,`
200			`n_ahbso_hready => n_ahbso_hready,`
201			`n_ahbso_hresp => n_ahbso_hresp,`
202			`n_ahbso_hrdata => n_ahbso_hrdata,`
203			`n_ahbso_hsplit => n_ahbso_hsplit,`
204			`n_ahbso_hcache => n_ahbso_hcache,`
205			`n_ahbso_hirq => n_ahbso_hirq,`
206			`n_apbi_psel => n_apbi_psel,`
207			`n_apbi_penable => n_apbi_penable,`
208			`n_apbi_paddr => n_apbi_paddr,`
209			`n_apbi_pwrite => n_apbi_pwrite,`
210			`n_apbi_pwdata => n_apbi_pwdata,`
211			`n_apbi_pirq => n_apbi_pirq,`
212			`n_apbo_prdata => n_apbo_prdata,`
213			`n_apbo_pirq => n_apbo_pirq,`
214			`n_sri_data => n_sri_data,`
215			`n_sri_brdyn => n_sri_brdyn,`
216			`n_sri_bexcn => n_sri_bexcn,`
217			`n_sri_writen => n_sri_writen,`
218			`n_sri_wrn => n_sri_wrn,`
219			`n_sri_bwidth => n_sri_bwidth,`
220			`n_sri_sd => n_sri_sd,`
221			`n_sri_cb => n_sri_cb,`
222			`n_sri_scb => n_sri_scb,`
223			`n_sri_edac => n_sri_edac,`
224			`n_sro_address => n_sro_address,`
225			`n_sro_data => n_sro_data,`
226			`n_sro_sddata => n_sro_sddata,`
227			`n_sro_ramsn => n_sro_ramsn,`
228			`n_sro_ramoen => n_sro_ramoen,`
229			`n_sro_ramn => n_sro_ramn,`
230			`n_sro_romn => n_sro_romn,`
231			`n_sro_mben => n_sro_mben,`
232			`n_sro_iosn => n_sro_iosn,`
233			`n_sro_romsn => n_sro_romsn,`
234			`n_sro_oen => n_sro_oen,`
235			`n_sro_writen => n_sro_writen,`
236			`n_sro_wrn => n_sro_wrn,`
237			`n_sro_bdrive => n_sro_bdrive,`
238			`n_sro_vbdrive => n_sro_vbdrive,`
239			`n_sro_svbdrive => n_sro_svbdrive,`
240			`n_sro_read => n_sro_read,`
241			`n_sro_sa => n_sro_sa,`
242			`n_sro_cb => n_sro_cb,`
243			`n_sro_scb => n_sro_scb,`
244			`n_sro_vcdrive => n_sro_vcdrive,`
245			`n_sro_svcdrive => n_sro_svcdrive,`
246			`n_sro_ce => n_sro_ce);`
247			`end generate;`
248
249			`-- pragma translate_off`
250			`nonet : if not (((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or`
251			`(tech = spartan3) or (tech = spartan3e)))`
252			`generate`
253			`err : process`
254			`begin`
255			`assert False report "ERROR : No ssrctrl netlist available for this technology!"`
256			`severity Failure;`
257			`wait;`
258			`end process;`
259			`end generate;`
260			`nobus16 : if not ( bus16=1 )`
261			`generate`
262			`err : process`
263			`begin`
264			`assert False report "ERROR : 16-bit PROM bus option not selected for ssrctrl netlist!"`
265			`severity Failure;`
266			`wait;`
267			`end process;`
268			`end generate;`
269			`-- pragma translate_on`
270
271			`end architecture;`