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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: tap
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-- File: tap.vhd
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-- Author: Edvin Catovic - Gaisler Research
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-- Description: TAP controller technology wrapper
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.alltap.all;
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library grlib;
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use grlib.stdlib.all;
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entity tap is
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generic (
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tech : integer := 0;
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irlen : integer range 2 to 8 := 4;
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idcode : integer range 0 to 255 := 9;
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manf : integer range 0 to 2047 := 804;
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part : integer range 0 to 65535 := 0;
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ver : integer range 0 to 15 := 0;
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trsten : integer range 0 to 1 := 1;
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scantest : integer := 0);
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port (
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trst : in std_ulogic;
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tck : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_inst : out std_logic_vector(7 downto 0);
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic;
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tapi_en1 : in std_ulogic;
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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testen : in std_ulogic := '0';
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testrst : in std_ulogic := '1';
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tdoen : out std_ulogic
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);
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end;
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architecture rtl of tap is
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signal tckn, ltck, ltckn : std_ulogic;
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begin
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xcv : if tech = virtex generate
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u0 : virtex_tap port map (tapi_tdo1, tapi_tdo1, tapo_tck, tapo_tdi, tapo_rst,
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tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
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end generate;
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xc2v : if tech = virtex2 generate
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u0 : virtex2_tap port map (tapi_tdo1, tapi_tdo1, tapo_tck, tapo_tdi, tapo_rst,
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tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
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end generate;
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xc4v : if tech = virtex4 generate
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u0 : virtex4_tap port map (tapi_tdo1, tapi_tdo1, tapo_tck, tapo_tdi, tapo_rst,
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tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
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end generate;
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xc5v : if tech = virtex5 generate
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u0 : virtex5_tap port map (tapi_tdo1, tapi_tdo1, tapo_tck, tapo_tdi, tapo_rst,
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tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
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end generate;
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xc3s : if (tech = spartan3) or (tech = spartan3e) generate
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u0 : spartan3_tap port map (tapi_tdo1, tapi_tdo1, tapo_tck, tapo_tdi, tapo_rst,
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tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
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end generate;
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alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
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(tech = stratix3) or (tech = cyclone3) generate
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u0 : altera_tap port map (tapi_tdo1, tapi_tdo1, tapo_tck, tapo_tdi, tapo_inst, tapo_rst,
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tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
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end generate;
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actpa3 : if (tech = apa3) generate
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u0 : proasic3_tap port map (tck, tms, tdi, trst, tdo,
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tapi_tdo1, tapi_tdo2, tapi_en1, tapo_tck, tapo_tdi, tapo_rst,
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tapo_capt, tapo_shft, tapo_upd, tapo_inst);
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end generate;
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inf : if (tech /= virtex2) and (tech /= spartan3) and (tech /= spartan3e)
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and (tech /= virtex) and (tech /= virtex4) and (tech /= virtex5) and
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(tech /= altera) and (tech /= stratix1) and (tech /= stratix2) and
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(tech /= stratix3) and (tech /= cyclone3) and (tech /= apa3)
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generate
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asic : if is_fpga(tech) = 0 generate
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tckn <= tck when (scantest = 1) and (testen = '1') else not tck;
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pclk : techbuf generic map (tech => tech) port map (tck, ltck);
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nclk : techbuf generic map (tech => tech) port map (tckn, ltckn);
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end generate;
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fpga : if is_fpga(tech) = 1 generate
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ltck <= tck; ltckn <= not tck;
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end generate;
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u0 : tap_gen generic map (irlen => irlen, manf => manf, part => part, ver => ver,
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idcode => idcode, scantest => scantest)
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port map (trst, ltck, ltckn, tms, tdi, tdo, tapi_en1, tapi_tdo1, tapi_tdo2, tapo_tck,
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tapo_tdi, tapo_inst, tapo_rst, tapo_capt, tapo_shft, tapo_upd, tapo_xsel1,
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tapo_xsel2, testen, testrst, tdoen);
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end generate;
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end;
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