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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: genclkbuf
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-- File: genclkbuf.vhd
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-- Author: Jiri Gaisler, Marko Isomaki - Gaisler Research
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-- Description: Hard buffers with tech wrapper
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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entity techbuf is
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generic(
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buftype : integer range 0 to 4 := 0;
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tech : integer range 0 to NTECH := inferred);
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port( i : in std_ulogic; o : out std_ulogic);
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end entity;
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architecture rtl of techbuf is
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component clkbuf_apa3 is generic( buftype : integer range 0 to 3 := 0);
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port( i : in std_ulogic; o : out std_ulogic);
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end component;
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component clkbuf_actel is generic( buftype : integer range 0 to 3 := 0);
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port( i : in std_ulogic; o : out std_ulogic);
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end component;
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component clkbuf_xilinx is generic( buftype : integer range 0 to 3 := 0);
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port( i : in std_ulogic; o : out std_ulogic);
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end component;
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component clkbuf_ut025crh is generic( buftype : integer range 0 to 3 := 0);
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port( i : in std_ulogic; o : out std_ulogic);
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end component;
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begin
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gen : if has_techbuf(tech) = 0 generate
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o <= i;
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end generate;
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pa3 : if (tech = apa3) generate
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axc : clkbuf_apa3 generic map (buftype => buftype) port map(i => i, o => o);
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end generate;
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axc : if (tech = axcel) generate
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axc : clkbuf_actel generic map (buftype => buftype) port map(i => i, o => o);
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end generate;
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xil : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or
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(tech = spartan3e) or (tech = virtex5) generate
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xil : clkbuf_xilinx generic map (buftype => buftype) port map(i => i, o => o);
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end generate;
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ut : if (tech = ut25) generate
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axc : clkbuf_ut025crh generic map (buftype => buftype) port map(i => i, o => o);
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end generate;
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end architecture;
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