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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: various
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-- File: clkgen_xilinx.vhd
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-- Author: Jiri Gaisler, Gaisler Research
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-- Author: Richard Pender, Pender Electronic Design
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-- Description: Clock generators for Virtex and Virtex-2 fpgas
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-- pragma translate_off
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library grlib;
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use grlib.stdlib.all;
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library unisim;
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use unisim.BUFG;
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use unisim.DCM;
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use unisim.BUFGDLL;
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use unisim.BUFGMUX;
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-- pragma translate_on
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library techmap;
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use techmap.gencomp.all;
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------------------------------------------------------------------
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-- Virtex2 clock generator ---------------------------------------
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------------------------------------------------------------------
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entity clkgen_virtex2 is
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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noclkfb : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000; -- clock frequency in KHz
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clk2xen : integer := 0;
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clksel : integer := 0); -- enable clock select
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port (
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clkin : in std_ulogic;
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pciclkin: in std_ulogic;
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clk : out std_ulogic; -- main clock
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clkn : out std_ulogic; -- inverted main clock
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clk2x : out std_ulogic; -- double clock
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sdclk : out std_ulogic; -- SDRAM clock
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pciclk : out std_ulogic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type;
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clk1xu : out std_ulogic; -- unscaled clock
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clk2xu : out std_ulogic -- unscaled 2X clock
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);
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end;
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architecture struct of clkgen_virtex2 is
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component BUFG port (O : out std_logic; I : in std_logic); end component;
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component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
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I1 : in std_ulogic; S : in std_ulogic);
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end component;
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component DCM
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generic (
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CLKDV_DIVIDE : real := 2.0;
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CLKFX_DIVIDE : integer := 1;
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CLKFX_MULTIPLY : integer := 4;
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CLKIN_DIVIDE_BY_2 : boolean := false;
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CLKIN_PERIOD : real := 10.0;
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CLKOUT_PHASE_SHIFT : string := "NONE";
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CLK_FEEDBACK : string := "1X";
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DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
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DFS_FREQUENCY_MODE : string := "LOW";
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DLL_FREQUENCY_MODE : string := "LOW";
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DSS_MODE : string := "NONE";
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DUTY_CYCLE_CORRECTION : boolean := true;
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FACTORY_JF : bit_vector := X"C080";
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PHASE_SHIFT : integer := 0;
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STARTUP_WAIT : boolean := false
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);
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port (
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CLKFB : in std_logic;
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CLKIN : in std_logic;
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DSSEN : in std_logic;
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PSCLK : in std_logic;
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PSEN : in std_logic;
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PSINCDEC : in std_logic;
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RST : in std_logic;
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CLK0 : out std_logic;
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CLK90 : out std_logic;
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CLK180 : out std_logic;
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CLK270 : out std_logic;
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CLK2X : out std_logic;
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CLK2X180 : out std_logic;
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CLKDV : out std_logic;
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CLKFX : out std_logic;
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CLKFX180 : out std_logic;
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LOCKED : out std_logic;
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PSDONE : out std_logic;
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STATUS : out std_logic_vector (7 downto 0));
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end component;
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component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
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constant VERSION : integer := 1;
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constant CLKIN_PERIOD_ST : string := "20.0";
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attribute CLKIN_PERIOD : string;
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attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
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signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
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signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
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signal clk0B, clkint, pciclkint : std_logic;
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begin
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gnd <= '0';
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clk <= clk_i when (CLK2XEN = 0) else clk_p;
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clkn <= clk_m; clk2x <= clk_i2;
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c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
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clkint <= clkin;
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end generate;
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c2 : if PCIEN /= 0 generate
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pciclkint <= pciclkin;
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p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
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p0 : if PCIDLL = 1 generate
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x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
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end generate;
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p1 : if PCIDLL = 0 generate
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x1 : BUFG port map (I => pciclkint, O => pciclk);
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end generate;
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end generate;
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c3 : if PCIEN = 0 generate
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pciclk <= '0';
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end generate;
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clk1xu <= clk_k;
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clk2xu <= clk_x;
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bufg0 : BUFG port map (I => clk0B, O => clk_i);
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bufg1 : BUFG port map (I => clk_j, O => clk_k);
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bufg2 : BUFG port map (I => clk_l, O => clk_m);
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buf34gen : if (CLK2XEN /= 0) generate
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cs0 : if (clksel = 0) generate
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bufg3 : BUFG port map (I => clk_n, O => clk_i2);
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end generate;
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cs1 : if (clksel /= 0) generate
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bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
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end generate;
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bufg4 : BUFG port map (I => clk_o, O => clk_p);
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end generate;
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dll0rst <= not cgi.pllrst;
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dll0 : DCM
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generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
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port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
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PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
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CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
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clk2xgen : if (CLK2XEN /= 0) generate
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dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
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port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
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PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
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CLK2X => clk_n, LOCKED => dll2xlock);
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rstdel2x : process (clk_i, dll0lock)
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begin
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if dll0lock = '0' then dll2xrst <= (others => '1');
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elsif rising_edge(clk_i) then
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dll2xrst <= dll2xrst(1 to 3) & '0';
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end if;
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end process;
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end generate;
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clk_sd1 : if (CLK2XEN = 0) generate
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bufg3 : BUFG port map (I => clk_x, O => clk_i2);
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dll2xlock <= dll0lock;
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clk_sd <= clk_i;
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end generate;
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clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
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clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
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sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
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cgo.clklock <= dll1lock;
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dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
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port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
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PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
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LOCKED => dll1lock);
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rstdel : process (clk_sd, dll2xlock)
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begin
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if dll2xlock = '0' then dll1rst <= (others => '1');
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elsif rising_edge(clk_sd) then
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dll1rst <= dll1rst(1 to 3) & '0';
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end if;
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end process;
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end generate;
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sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
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sdclk <= clk_i;
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cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
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end generate;
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sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
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sdclk <= clk_i2;
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cgo.clklock <= dll2xlock;
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end generate;
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cgo.pcilock <= '1';
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-- pragma translate_off
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bootmsg : report_version
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generic map (
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"clkgen_virtex2" & ": virtex-2 sdram/pci clock generator, version " & tost(VERSION),
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"clkgen_virtex2" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
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-- pragma translate_on
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end;
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library ieee;
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use ieee.std_logic_1164.all;
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-- pragma translate_off
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library grlib;
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use grlib.stdlib.all;
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library unisim;
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use unisim.BUFG;
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use unisim.CLKDLL;
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use unisim.BUFGDLL;
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-- pragma translate_on
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library techmap;
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use techmap.gencomp.all;
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entity clkgen_virtex is
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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noclkfb : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0);
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port (
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clkin : in std_logic;
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pciclkin: in std_logic;
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clk : out std_logic; -- main clock
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clkn : out std_logic; -- inverted main clock
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clk2x : out std_logic; -- double clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type
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);
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end;
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architecture rtl of clkgen_virtex is
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component BUFG port (O : out std_logic; I : in std_logic); end component;
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component CLKDLL
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port (
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CLK0 : out std_ulogic;
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CLK180 : out std_ulogic;
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CLK270 : out std_ulogic;
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CLK2X : out std_ulogic;
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CLK90 : out std_ulogic;
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CLKDV : out std_ulogic;
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LOCKED : out std_ulogic;
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CLKFB : in std_ulogic;
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CLKIN : in std_ulogic;
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RST : in std_ulogic);
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end component;
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component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
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signal gnd, clk_i, clk_j, clk_k, dll0rst, dll0lock, dll1lock : std_logic;
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signal dll1rst : std_logic_vector(0 to 3);
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signal clk0B, clkint, CLK2XL, CLKDV, CLK180, pciclkint : std_logic;
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begin
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gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
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c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
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clkint <= clkin;
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end generate;
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c2 : if PCIEN /= 0 generate
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pciclkint <= pciclkin;
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p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
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p0 : if PCIDLL = 1 generate
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x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
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end generate;
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p1 : if PCIDLL = 0 generate
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x1 : BUFG port map (I => pciclkint, O => pciclk);
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end generate;
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end generate;
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c3 : if PCIEN = 0 generate
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pciclk <= '0';
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end generate;
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bufg0 : BUFG port map (I => clk0B, O => clk_i);
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bufg1 : BUFG port map (I => clk_j, O => clk_k);
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dll0rst <= not cgi.pllrst;
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dll0 : CLKDLL
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port map (CLKIN => clkint, CLKFB => clk_k, CLK0 => clk_j, CLK180 => CLK180,
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CLK2X => CLK2XL, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
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324 |
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clk0B <= CLK2XL when clk_mul/clk_div = 2
|
326 |
|
|
else CLKDV when clk_div/clk_mul = 2 else clk_j;
|
327 |
|
|
|
328 |
|
|
sd0 : if (SDRAMEN /= 0) and (NOCLKFB = 0) generate
|
329 |
|
|
cgo.clklock <= dll1lock;
|
330 |
|
|
dll1 : CLKDLL
|
331 |
|
|
port map (CLKIN => clk_i, CLKFB => cgi.pllref, RST => dll1rst(0), CLK0 => sdclk,
|
332 |
|
|
CLK2X => clk2x, LOCKED => dll1lock);
|
333 |
|
|
rstdel : process (clk_i)
|
334 |
|
|
begin
|
335 |
|
|
if dll0lock = '0' then dll1rst <= (others => '1');
|
336 |
|
|
elsif rising_edge(clk_i) then
|
337 |
|
|
dll1rst <= dll1rst(1 to 3) & '0';
|
338 |
|
|
end if;
|
339 |
|
|
end process;
|
340 |
|
|
end generate;
|
341 |
|
|
|
342 |
|
|
sd1 : if not ((SDRAMEN /= 0) and (NOCLKFB = 0)) generate
|
343 |
|
|
sdclk <= clk_i; cgo.clklock <= dll0lock;
|
344 |
|
|
end generate;
|
345 |
|
|
|
346 |
|
|
cgo.pcilock <= '1';
|
347 |
|
|
|
348 |
|
|
end;
|
349 |
|
|
|
350 |
|
|
library ieee;
|
351 |
|
|
use ieee.std_logic_1164.all;
|
352 |
|
|
-- pragma translate_off
|
353 |
|
|
library grlib;
|
354 |
|
|
use grlib.stdlib.all;
|
355 |
|
|
library unisim;
|
356 |
|
|
use unisim.BUFG;
|
357 |
|
|
use unisim.DCM;
|
358 |
|
|
-- pragma translate_on
|
359 |
|
|
library techmap;
|
360 |
|
|
use techmap.gencomp.all;
|
361 |
|
|
|
362 |
|
|
entity clkmul_virtex2 is
|
363 |
|
|
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
|
364 |
|
|
port (
|
365 |
|
|
resetin : in std_logic;
|
366 |
|
|
clkin : in std_logic;
|
367 |
|
|
clk : out std_logic;
|
368 |
|
|
resetout: out std_logic
|
369 |
|
|
);
|
370 |
|
|
end;
|
371 |
|
|
|
372 |
|
|
architecture struct of clkmul_virtex2 is
|
373 |
|
|
|
374 |
|
|
-- attribute CLKFX_MULTIPLY : string;
|
375 |
|
|
-- attribute CLKFX_DIVIDE : string;
|
376 |
|
|
attribute CLKIN_PERIOD : string;
|
377 |
|
|
--
|
378 |
|
|
-- attribute CLKFX_MULTIPLY of dll0: label is "5";
|
379 |
|
|
-- attribute CLKFX_DIVIDE of dll0: label is "4";
|
380 |
|
|
attribute CLKIN_PERIOD of dll0: label is "20";
|
381 |
|
|
--
|
382 |
|
|
-- attribute CLKFX_MULTIPLY of dll1: label is "4";
|
383 |
|
|
-- attribute CLKFX_DIVIDE of dll1: label is "4";
|
384 |
|
|
-- attribute CLKIN_PERIOD of dll1: label is "25";
|
385 |
|
|
--
|
386 |
|
|
|
387 |
|
|
component DCM
|
388 |
|
|
generic (
|
389 |
|
|
CLKDV_DIVIDE : real := 2.0;
|
390 |
|
|
CLKFX_DIVIDE : integer := 1;
|
391 |
|
|
CLKFX_MULTIPLY : integer := 4;
|
392 |
|
|
CLKIN_DIVIDE_BY_2 : boolean := false;
|
393 |
|
|
CLKIN_PERIOD : real := 10.0;
|
394 |
|
|
CLKOUT_PHASE_SHIFT : string := "NONE";
|
395 |
|
|
CLK_FEEDBACK : string := "1X";
|
396 |
|
|
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
|
397 |
|
|
DFS_FREQUENCY_MODE : string := "LOW";
|
398 |
|
|
DLL_FREQUENCY_MODE : string := "LOW";
|
399 |
|
|
DSS_MODE : string := "NONE";
|
400 |
|
|
DUTY_CYCLE_CORRECTION : boolean := true;
|
401 |
|
|
FACTORY_JF : bit_vector := X"C080";
|
402 |
|
|
PHASE_SHIFT : integer := 0;
|
403 |
|
|
STARTUP_WAIT : boolean := false
|
404 |
|
|
);
|
405 |
|
|
port (
|
406 |
|
|
CLKFB : in std_logic;
|
407 |
|
|
CLKIN : in std_logic;
|
408 |
|
|
DSSEN : in std_logic;
|
409 |
|
|
PSCLK : in std_logic;
|
410 |
|
|
PSEN : in std_logic;
|
411 |
|
|
PSINCDEC : in std_logic;
|
412 |
|
|
RST : in std_logic;
|
413 |
|
|
CLK0 : out std_logic;
|
414 |
|
|
CLK90 : out std_logic;
|
415 |
|
|
CLK180 : out std_logic;
|
416 |
|
|
CLK270 : out std_logic;
|
417 |
|
|
CLK2X : out std_logic;
|
418 |
|
|
CLK2X180 : out std_logic;
|
419 |
|
|
CLKDV : out std_logic;
|
420 |
|
|
CLKFX : out std_logic;
|
421 |
|
|
CLKFX180 : out std_logic;
|
422 |
|
|
LOCKED : out std_logic;
|
423 |
|
|
PSDONE : out std_logic;
|
424 |
|
|
STATUS : out std_logic_vector (7 downto 0));
|
425 |
|
|
end component;
|
426 |
|
|
|
427 |
|
|
component BUFG port ( O : out std_logic; I : in std_logic); end component;
|
428 |
|
|
|
429 |
|
|
signal gnd, clk_i, clk_j, clk_k, clk_l : std_logic;
|
430 |
|
|
signal clk0B, clk_FB, dll0rst, lock : std_logic;
|
431 |
|
|
|
432 |
|
|
begin
|
433 |
|
|
|
434 |
|
|
gnd <= '0'; clk <= clk_i;
|
435 |
|
|
dll0rst <= not resetin;
|
436 |
|
|
|
437 |
|
|
bufg0 : BUFG port map (I => clk0B, O => clk_i);
|
438 |
|
|
bufg1 : BUFG port map (I => clk_j, O => clk_k);
|
439 |
|
|
|
440 |
|
|
dll0 : DCM
|
441 |
|
|
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
|
442 |
|
|
port map ( CLKIN => clkin, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
|
443 |
|
|
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
|
444 |
|
|
LOCKED => resetout, CLKFX => clk0B );
|
445 |
|
|
|
446 |
|
|
end;
|
447 |
|
|
|
448 |
|
|
library ieee;
|
449 |
|
|
use ieee.std_logic_1164.all;
|
450 |
|
|
-- pragma translate_off
|
451 |
|
|
library grlib;
|
452 |
|
|
use grlib.stdlib.all;
|
453 |
|
|
library unisim;
|
454 |
|
|
use unisim.BUFG;
|
455 |
|
|
use unisim.DCM;
|
456 |
|
|
use unisim.BUFGDLL;
|
457 |
|
|
use unisim.BUFGMUX;
|
458 |
|
|
-- pragma translate_on
|
459 |
|
|
library techmap;
|
460 |
|
|
use techmap.gencomp.all;
|
461 |
|
|
|
462 |
|
|
entity clkgen_spartan3 is
|
463 |
|
|
generic (
|
464 |
|
|
clk_mul : integer := 1;
|
465 |
|
|
clk_div : integer := 1;
|
466 |
|
|
sdramen : integer := 0;
|
467 |
|
|
noclkfb : integer := 0;
|
468 |
|
|
pcien : integer := 0;
|
469 |
|
|
pcidll : integer := 0;
|
470 |
|
|
pcisysclk: integer := 0;
|
471 |
|
|
freq : integer := 50000; -- clock frequency in KHz
|
472 |
|
|
clk2xen : integer := 0;
|
473 |
|
|
clksel : integer := 0); -- enable clock select
|
474 |
|
|
port (
|
475 |
|
|
clkin : in std_ulogic;
|
476 |
|
|
pciclkin: in std_ulogic;
|
477 |
|
|
clk : out std_ulogic; -- main clock
|
478 |
|
|
clkn : out std_ulogic; -- inverted main clock
|
479 |
|
|
clk2x : out std_ulogic; -- double clock
|
480 |
|
|
sdclk : out std_ulogic; -- SDRAM clock
|
481 |
|
|
pciclk : out std_ulogic; -- PCI clock
|
482 |
|
|
cgi : in clkgen_in_type;
|
483 |
|
|
cgo : out clkgen_out_type;
|
484 |
|
|
clk1xu : out std_ulogic; -- unscaled clock
|
485 |
|
|
clk2xu : out std_ulogic -- unscaled 2X clock
|
486 |
|
|
);
|
487 |
|
|
end;
|
488 |
|
|
|
489 |
|
|
architecture struct of clkgen_spartan3 is
|
490 |
|
|
|
491 |
|
|
component BUFG port (O : out std_logic; I : in std_logic); end component;
|
492 |
|
|
|
493 |
|
|
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
|
494 |
|
|
I1 : in std_ulogic; S : in std_ulogic);
|
495 |
|
|
end component;
|
496 |
|
|
|
497 |
|
|
component DCM
|
498 |
|
|
generic (
|
499 |
|
|
CLKDV_DIVIDE : real := 2.0;
|
500 |
|
|
CLKFX_DIVIDE : integer := 1;
|
501 |
|
|
CLKFX_MULTIPLY : integer := 4;
|
502 |
|
|
CLKIN_DIVIDE_BY_2 : boolean := false;
|
503 |
|
|
CLKIN_PERIOD : real := 10.0;
|
504 |
|
|
CLKOUT_PHASE_SHIFT : string := "NONE";
|
505 |
|
|
CLK_FEEDBACK : string := "1X";
|
506 |
|
|
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
|
507 |
|
|
DFS_FREQUENCY_MODE : string := "LOW";
|
508 |
|
|
DLL_FREQUENCY_MODE : string := "LOW";
|
509 |
|
|
DSS_MODE : string := "NONE";
|
510 |
|
|
DUTY_CYCLE_CORRECTION : boolean := true;
|
511 |
|
|
FACTORY_JF : bit_vector := X"C080";
|
512 |
|
|
PHASE_SHIFT : integer := 0;
|
513 |
|
|
STARTUP_WAIT : boolean := false
|
514 |
|
|
);
|
515 |
|
|
port (
|
516 |
|
|
CLKFB : in std_logic;
|
517 |
|
|
CLKIN : in std_logic;
|
518 |
|
|
DSSEN : in std_logic;
|
519 |
|
|
PSCLK : in std_logic;
|
520 |
|
|
PSEN : in std_logic;
|
521 |
|
|
PSINCDEC : in std_logic;
|
522 |
|
|
RST : in std_logic;
|
523 |
|
|
CLK0 : out std_logic;
|
524 |
|
|
CLK90 : out std_logic;
|
525 |
|
|
CLK180 : out std_logic;
|
526 |
|
|
CLK270 : out std_logic;
|
527 |
|
|
CLK2X : out std_logic;
|
528 |
|
|
CLK2X180 : out std_logic;
|
529 |
|
|
CLKDV : out std_logic;
|
530 |
|
|
CLKFX : out std_logic;
|
531 |
|
|
CLKFX180 : out std_logic;
|
532 |
|
|
LOCKED : out std_logic;
|
533 |
|
|
PSDONE : out std_logic;
|
534 |
|
|
STATUS : out std_logic_vector (7 downto 0));
|
535 |
|
|
end component;
|
536 |
|
|
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
|
537 |
|
|
|
538 |
|
|
constant VERSION : integer := 1;
|
539 |
|
|
constant CLKIN_PERIOD_ST : string := "20.0";
|
540 |
|
|
attribute CLKIN_PERIOD : string;
|
541 |
|
|
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
|
542 |
|
|
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
|
543 |
|
|
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
|
544 |
|
|
signal clk0B, clkint, pciclkint : std_logic;
|
545 |
|
|
|
546 |
|
|
begin
|
547 |
|
|
|
548 |
|
|
gnd <= '0';
|
549 |
|
|
clk <= clk_i when (CLK2XEN = 0) else clk_p;
|
550 |
|
|
clkn <= not clk_i when (CLK2XEN = 0) else not clk_p;
|
551 |
|
|
clk2x <= clk_i2;
|
552 |
|
|
|
553 |
|
|
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
|
554 |
|
|
clkint <= clkin;
|
555 |
|
|
end generate;
|
556 |
|
|
|
557 |
|
|
c2 : if PCIEN /= 0 generate
|
558 |
|
|
pciclkint <= pciclkin;
|
559 |
|
|
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
|
560 |
|
|
p0 : if PCIDLL = 1 generate
|
561 |
|
|
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
|
562 |
|
|
end generate;
|
563 |
|
|
p1 : if PCIDLL = 0 generate
|
564 |
|
|
x1 : BUFG port map (I => pciclkint, O => pciclk);
|
565 |
|
|
end generate;
|
566 |
|
|
end generate;
|
567 |
|
|
|
568 |
|
|
c3 : if PCIEN = 0 generate
|
569 |
|
|
pciclk <= '0';
|
570 |
|
|
end generate;
|
571 |
|
|
|
572 |
|
|
clk1xu <= clk_j;
|
573 |
|
|
clk2xu <= clk_k;
|
574 |
|
|
bufg0 : BUFG port map (I => clk0B, O => clk_i);
|
575 |
|
|
bufg1 : BUFG port map (I => clk_x, O => clk_k);
|
576 |
|
|
buf34gen : if (CLK2XEN /= 0) generate
|
577 |
|
|
cs0 : if (clksel = 0) generate
|
578 |
|
|
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
|
579 |
|
|
end generate;
|
580 |
|
|
cs1 : if (clksel /= 0) generate
|
581 |
|
|
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
|
582 |
|
|
end generate;
|
583 |
|
|
bufg4 : BUFG port map (I => clk_o, O => clk_p);
|
584 |
|
|
end generate;
|
585 |
|
|
dll0rst <= not cgi.pllrst;
|
586 |
|
|
dll0 : DCM
|
587 |
|
|
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
|
588 |
|
|
CLK_FEEDBACK => "2X")
|
589 |
|
|
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
|
590 |
|
|
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
|
591 |
|
|
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
|
592 |
|
|
|
593 |
|
|
|
594 |
|
|
clk2xgen : if (CLK2XEN /= 0) generate
|
595 |
|
|
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
|
596 |
|
|
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
|
597 |
|
|
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
|
598 |
|
|
CLK2X => clk_n, LOCKED => dll2xlock);
|
599 |
|
|
rstdel2x : process (clk_i, dll0lock)
|
600 |
|
|
begin
|
601 |
|
|
if dll0lock = '0' then dll2xrst <= (others => '1');
|
602 |
|
|
elsif rising_edge(clk_i) then
|
603 |
|
|
dll2xrst <= dll2xrst(1 to 3) & '0';
|
604 |
|
|
end if;
|
605 |
|
|
end process;
|
606 |
|
|
end generate;
|
607 |
|
|
|
608 |
|
|
clk_sd1 : if (CLK2XEN = 0) generate
|
609 |
|
|
clk_i2 <= clk_k;
|
610 |
|
|
dll2xlock <= dll0lock;
|
611 |
|
|
clk_sd <= clk_i;
|
612 |
|
|
end generate;
|
613 |
|
|
|
614 |
|
|
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
|
615 |
|
|
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
|
616 |
|
|
|
617 |
|
|
|
618 |
|
|
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
|
619 |
|
|
cgo.clklock <= dll1lock;
|
620 |
|
|
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
|
621 |
|
|
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
|
622 |
|
|
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
|
623 |
|
|
LOCKED => dll1lock);
|
624 |
|
|
rstdel : process (clk_sd, dll2xlock)
|
625 |
|
|
begin
|
626 |
|
|
if dll2xlock = '0' then dll1rst <= (others => '1');
|
627 |
|
|
elsif rising_edge(clk_sd) then
|
628 |
|
|
dll1rst <= dll1rst(1 to 3) & '0';
|
629 |
|
|
end if;
|
630 |
|
|
end process;
|
631 |
|
|
end generate;
|
632 |
|
|
|
633 |
|
|
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
|
634 |
|
|
sdclk <= clk_i;
|
635 |
|
|
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
|
636 |
|
|
end generate;
|
637 |
|
|
|
638 |
|
|
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
|
639 |
|
|
sdclk <= clk_i2;
|
640 |
|
|
cgo.clklock <= dll2xlock;
|
641 |
|
|
end generate;
|
642 |
|
|
|
643 |
|
|
|
644 |
|
|
cgo.pcilock <= '1';
|
645 |
|
|
|
646 |
|
|
-- pragma translate_off
|
647 |
|
|
bootmsg : report_version
|
648 |
|
|
generic map (
|
649 |
|
|
"clkgen_spartan3e" & ": spartan3/e sdram/pci clock generator, version " & tost(VERSION),
|
650 |
|
|
"clkgen_spartan3e" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
|
651 |
|
|
-- pragma translate_on
|
652 |
|
|
|
653 |
|
|
|
654 |
|
|
end;
|
655 |
|
|
|
656 |
|
|
------------------------------------------------------------------
|
657 |
|
|
-- Virtex5 clock generator ---------------------------------------
|
658 |
|
|
------------------------------------------------------------------
|
659 |
|
|
|
660 |
|
|
library ieee;
|
661 |
|
|
use ieee.std_logic_1164.all;
|
662 |
|
|
-- pragma translate_off
|
663 |
|
|
library grlib;
|
664 |
|
|
use grlib.stdlib.all;
|
665 |
|
|
library unisim;
|
666 |
|
|
use unisim.BUFG;
|
667 |
|
|
use unisim.DCM;
|
668 |
|
|
use unisim.BUFGDLL;
|
669 |
|
|
use unisim.BUFGMUX;
|
670 |
|
|
-- pragma translate_on
|
671 |
|
|
library techmap;
|
672 |
|
|
use techmap.gencomp.all;
|
673 |
|
|
|
674 |
|
|
entity clkgen_virtex5 is
|
675 |
|
|
generic (
|
676 |
|
|
clk_mul : integer := 1;
|
677 |
|
|
clk_div : integer := 1;
|
678 |
|
|
sdramen : integer := 0;
|
679 |
|
|
noclkfb : integer := 0;
|
680 |
|
|
pcien : integer := 0;
|
681 |
|
|
pcidll : integer := 0;
|
682 |
|
|
pcisysclk: integer := 0;
|
683 |
|
|
freq : integer := 25000; -- clock frequency in KHz
|
684 |
|
|
clk2xen : integer := 0;
|
685 |
|
|
clksel : integer := 0); -- enable clock select
|
686 |
|
|
port (
|
687 |
|
|
clkin : in std_ulogic;
|
688 |
|
|
pciclkin: in std_ulogic;
|
689 |
|
|
clk : out std_ulogic; -- main clock
|
690 |
|
|
clkn : out std_ulogic; -- inverted main clock
|
691 |
|
|
clk2x : out std_ulogic; -- double clock
|
692 |
|
|
sdclk : out std_ulogic; -- SDRAM clock
|
693 |
|
|
pciclk : out std_ulogic; -- PCI clock
|
694 |
|
|
cgi : in clkgen_in_type;
|
695 |
|
|
cgo : out clkgen_out_type;
|
696 |
|
|
clk1xu : out std_ulogic; -- unscaled clock
|
697 |
|
|
clk2xu : out std_ulogic -- unscaled 2X clock
|
698 |
|
|
);
|
699 |
|
|
end;
|
700 |
|
|
|
701 |
|
|
architecture struct of clkgen_virtex5 is
|
702 |
|
|
|
703 |
|
|
component BUFG port (O : out std_logic; I : in std_logic); end component;
|
704 |
|
|
|
705 |
|
|
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
|
706 |
|
|
I1 : in std_ulogic; S : in std_ulogic);
|
707 |
|
|
end component;
|
708 |
|
|
|
709 |
|
|
component DCM
|
710 |
|
|
generic (
|
711 |
|
|
CLKDV_DIVIDE : real := 2.0;
|
712 |
|
|
CLKFX_DIVIDE : integer := 1;
|
713 |
|
|
CLKFX_MULTIPLY : integer := 4;
|
714 |
|
|
CLKIN_DIVIDE_BY_2 : boolean := false;
|
715 |
|
|
CLKIN_PERIOD : real := 10.0;
|
716 |
|
|
CLKOUT_PHASE_SHIFT : string := "NONE";
|
717 |
|
|
CLK_FEEDBACK : string := "1X";
|
718 |
|
|
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
|
719 |
|
|
DFS_FREQUENCY_MODE : string := "LOW";
|
720 |
|
|
DLL_FREQUENCY_MODE : string := "LOW";
|
721 |
|
|
DSS_MODE : string := "NONE";
|
722 |
|
|
DUTY_CYCLE_CORRECTION : boolean := true;
|
723 |
|
|
FACTORY_JF : bit_vector := X"C080";
|
724 |
|
|
PHASE_SHIFT : integer := 0;
|
725 |
|
|
STARTUP_WAIT : boolean := false
|
726 |
|
|
);
|
727 |
|
|
port (
|
728 |
|
|
CLKFB : in std_logic;
|
729 |
|
|
CLKIN : in std_logic;
|
730 |
|
|
DSSEN : in std_logic;
|
731 |
|
|
PSCLK : in std_logic;
|
732 |
|
|
PSEN : in std_logic;
|
733 |
|
|
PSINCDEC : in std_logic;
|
734 |
|
|
RST : in std_logic;
|
735 |
|
|
CLK0 : out std_logic;
|
736 |
|
|
CLK90 : out std_logic;
|
737 |
|
|
CLK180 : out std_logic;
|
738 |
|
|
CLK270 : out std_logic;
|
739 |
|
|
CLK2X : out std_logic;
|
740 |
|
|
CLK2X180 : out std_logic;
|
741 |
|
|
CLKDV : out std_logic;
|
742 |
|
|
CLKFX : out std_logic;
|
743 |
|
|
CLKFX180 : out std_logic;
|
744 |
|
|
LOCKED : out std_logic;
|
745 |
|
|
PSDONE : out std_logic;
|
746 |
|
|
STATUS : out std_logic_vector (7 downto 0));
|
747 |
|
|
end component;
|
748 |
|
|
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
|
749 |
|
|
|
750 |
|
|
constant VERSION : integer := 1;
|
751 |
|
|
constant CLKIN_PERIOD_ST : string := "20.0";
|
752 |
|
|
attribute CLKIN_PERIOD : string;
|
753 |
|
|
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
|
754 |
|
|
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, lsdclk : std_logic;
|
755 |
|
|
signal clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r: std_logic;
|
756 |
|
|
signal dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
|
757 |
|
|
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
|
758 |
|
|
signal clk0B, clkint, pciclkint : std_logic;
|
759 |
|
|
|
760 |
|
|
begin
|
761 |
|
|
|
762 |
|
|
gnd <= '0';
|
763 |
|
|
clk <= clk_i when (CLK2XEN = 0) else clk_p;
|
764 |
|
|
clkn <= clk_m; clk2x <= clk_i2;
|
765 |
|
|
|
766 |
|
|
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
|
767 |
|
|
clkint <= clkin;
|
768 |
|
|
end generate;
|
769 |
|
|
|
770 |
|
|
c2 : if PCIEN /= 0 generate
|
771 |
|
|
pciclkint <= pciclkin;
|
772 |
|
|
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
|
773 |
|
|
p0 : if PCIDLL = 1 generate
|
774 |
|
|
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
|
775 |
|
|
end generate;
|
776 |
|
|
p1 : if PCIDLL = 0 generate
|
777 |
|
|
x1 : BUFG port map (I => pciclkint, O => pciclk);
|
778 |
|
|
end generate;
|
779 |
|
|
end generate;
|
780 |
|
|
|
781 |
|
|
c3 : if PCIEN = 0 generate
|
782 |
|
|
pciclk <= '0';
|
783 |
|
|
end generate;
|
784 |
|
|
|
785 |
|
|
clk1xu <= clk_k;
|
786 |
|
|
clk2xu <= clk_x;
|
787 |
|
|
bufg0 : BUFG port map (I => clk0B, O => clk_i);
|
788 |
|
|
bufg1 : BUFG port map (I => clk_j, O => clk_k);
|
789 |
|
|
bufg2 : BUFG port map (I => clk_l, O => clk_m);
|
790 |
|
|
buf34gen : if (CLK2XEN /= 0) generate
|
791 |
|
|
cs0 : if (clksel = 0) generate
|
792 |
|
|
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
|
793 |
|
|
end generate;
|
794 |
|
|
cs1 : if (clksel /= 0) generate
|
795 |
|
|
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
|
796 |
|
|
end generate;
|
797 |
|
|
bufg4 : BUFG port map (I => clk_o, O => clk_p);
|
798 |
|
|
end generate;
|
799 |
|
|
dll0rst <= not cgi.pllrst;
|
800 |
|
|
dll0 : DCM
|
801 |
|
|
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
|
802 |
|
|
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
|
803 |
|
|
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
|
804 |
|
|
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
|
805 |
|
|
|
806 |
|
|
|
807 |
|
|
clk2xgen : if (CLK2XEN /= 0) generate
|
808 |
|
|
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
|
809 |
|
|
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
|
810 |
|
|
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
|
811 |
|
|
CLK2X => clk_n, LOCKED => dll2xlock);
|
812 |
|
|
rstdel2x : process (clk_i, dll0lock)
|
813 |
|
|
begin
|
814 |
|
|
if dll0lock = '0' then dll2xrst <= (others => '1');
|
815 |
|
|
elsif rising_edge(clk_i) then
|
816 |
|
|
dll2xrst <= dll2xrst(1 to 3) & '0';
|
817 |
|
|
end if;
|
818 |
|
|
end process;
|
819 |
|
|
end generate;
|
820 |
|
|
|
821 |
|
|
clk_sd1 : if (CLK2XEN = 0) generate
|
822 |
|
|
clk_i2 <= clk_x;
|
823 |
|
|
dll2xlock <= dll0lock;
|
824 |
|
|
clk_sd <= clk_i;
|
825 |
|
|
end generate;
|
826 |
|
|
|
827 |
|
|
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
|
828 |
|
|
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
|
829 |
|
|
|
830 |
|
|
|
831 |
|
|
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
|
832 |
|
|
cgo.clklock <= dll1lock;
|
833 |
|
|
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
|
834 |
|
|
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
|
835 |
|
|
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
|
836 |
|
|
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
|
837 |
|
|
LOCKED => dll1lock);
|
838 |
|
|
bufgx : BUFG port map (I => lsdclk, O => sdclk);
|
839 |
|
|
rstdel : process (clk_sd, dll2xlock)
|
840 |
|
|
begin
|
841 |
|
|
if dll2xlock = '0' then dll1rst <= (others => '1');
|
842 |
|
|
elsif rising_edge(clk_sd) then
|
843 |
|
|
dll1rst <= dll1rst(1 to 3) & '0';
|
844 |
|
|
end if;
|
845 |
|
|
end process;
|
846 |
|
|
end generate;
|
847 |
|
|
|
848 |
|
|
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
|
849 |
|
|
sdclk <= clk_i;
|
850 |
|
|
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
|
851 |
|
|
end generate;
|
852 |
|
|
|
853 |
|
|
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
|
854 |
|
|
sdclk <= clk_i2;
|
855 |
|
|
cgo.clklock <= dll2xlock;
|
856 |
|
|
end generate;
|
857 |
|
|
|
858 |
|
|
|
859 |
|
|
cgo.pcilock <= '1';
|
860 |
|
|
|
861 |
|
|
-- pragma translate_off
|
862 |
|
|
bootmsg : report_version
|
863 |
|
|
generic map (
|
864 |
|
|
"clkgen_virtex5" & ": virtex-5 sdram/pci clock generator, version " & tost(VERSION),
|
865 |
|
|
"clkgen_virtex5" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
|
866 |
|
|
-- pragma translate_on
|
867 |
|
|
|
868 |
|
|
|
869 |
|
|
end;
|
870 |
|
|
|
871 |
|
|
library ieee;
|
872 |
|
|
use ieee.std_logic_1164.all;
|
873 |
|
|
-- pragma translate_off
|
874 |
|
|
library unisim;
|
875 |
|
|
use unisim.BUFGMUX;
|
876 |
|
|
-- pragma translate_on
|
877 |
|
|
|
878 |
|
|
entity clkand_unisim is
|
879 |
|
|
port(
|
880 |
|
|
i : in std_ulogic;
|
881 |
|
|
en : in std_ulogic;
|
882 |
|
|
o : out std_ulogic
|
883 |
|
|
);
|
884 |
|
|
end entity;
|
885 |
|
|
|
886 |
|
|
architecture rtl of clkand_unisim is
|
887 |
|
|
|
888 |
|
|
component BUFGCE
|
889 |
|
|
port(
|
890 |
|
|
O : out STD_ULOGIC;
|
891 |
|
|
CE: in STD_ULOGIC;
|
892 |
|
|
I : in STD_ULOGIC
|
893 |
|
|
);
|
894 |
|
|
end component;
|
895 |
|
|
|
896 |
|
|
begin
|
897 |
|
|
buf : bufgce port map(I => i, CE => en, O => o);
|
898 |
|
|
end architecture;
|
899 |
|
|
|
900 |
|
|
|
901 |
|
|
library ieee;
|
902 |
|
|
use ieee.std_logic_1164.all;
|
903 |
|
|
-- pragma translate_off
|
904 |
|
|
library unisim;
|
905 |
|
|
use unisim.BUFGMUX;
|
906 |
|
|
-- pragma translate_on
|
907 |
|
|
|
908 |
|
|
entity clkmux_unisim is
|
909 |
|
|
port(
|
910 |
|
|
i0, i1 : in std_ulogic;
|
911 |
|
|
sel : in std_ulogic;
|
912 |
|
|
o : out std_ulogic
|
913 |
|
|
);
|
914 |
|
|
end entity;
|
915 |
|
|
|
916 |
|
|
architecture rtl of clkmux_unisim is
|
917 |
|
|
component bufgmux is
|
918 |
|
|
port(
|
919 |
|
|
i0, i1 : in std_ulogic;
|
920 |
|
|
s : in std_ulogic;
|
921 |
|
|
o : out std_ulogic);
|
922 |
|
|
end component;
|
923 |
|
|
signal sel0, sel1, cg0, cg1 : std_ulogic;
|
924 |
|
|
begin
|
925 |
|
|
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
|
926 |
|
|
end architecture;
|
927 |
|
|
|
928 |
|
|
|
929 |
|
|
|
930 |
|
|
|