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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [unisim/] [ddr_unisim.vhd] - Blame information for rev 2

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------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Entity:      unisim_iddr_reg
-- File:        unisim_iddr_reg.vhd
-- Author:      David Lindh, Jiri Gaisler - Gaisler Research
-- Description: Xilinx DDR input register
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.iddr;
--pragma translate_on
 
entity unisim_iddr_reg is
  generic (tech : integer := virtex4);
  port(
         Q1 : out std_ulogic;
         Q2 : out std_ulogic;
         C1 : in std_ulogic;
         C2 : in std_ulogic;
         CE : in std_ulogic;
         D : in std_ulogic;
         R : in std_ulogic;
         S : in std_ulogic
      );
end;
 
architecture rtl of unisim_iddr_reg is
    attribute BOX_TYPE : string;
--    attribute syn_useioff : boolean; 
--    attribute syn_useioff of rtl : architecture is false;
 
    component IDDR
      generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
          INIT_Q1 : bit := '0';
          INIT_Q2 : bit := '0';
          SRTYPE : string := "ASYNC");
      port
        ( Q1 : out std_ulogic;
          Q2 : out std_ulogic;
          C : in std_ulogic;
          CE : in std_ulogic;
          D : in std_ulogic;
          R : in std_ulogic;
          S : in std_ulogic);
    end component;
    attribute BOX_TYPE of IDDR : component is "PRIMITIVE";
  signal preQ2 : std_ulogic;
 
begin
 
 
-- SAME EDGE mode have when this is written an incorrect P&R
-- timing model, instead OPPOSITE_MODE with an extra register is used
--      V4 : if tech = virtex4 generate
--        U0 : IDDR
--          generic map(
--            DDR_CLK_EDGE => "SAME_EDGE",
--            INIT_Q1 =>  '0',
--            INIT_Q2 =>  '0',
--            SRTYPE =>  "ASYNC")
--          Port map(
--            Q1 => Q1,
--            Q2 => Q2,
--            C => C1,
--            CE => CE,                 
--            D => D,
--            R => R,    
--            S => S);
--     end generate;
 
       V4 : if (tech = virtex4) or (tech = virtex5) generate
       U0 : IDDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE"
--           ,INIT_Q1 =>  '0',
--           INIT_Q2 =>  '0',
--           SRTYPE =>  "ASYNC"
)
         Port map( Q1 => Q1, Q2 => preQ2, C => C1, CE => CE,
                   D => D, R => R,    S => S);
 
      q3reg : process (C1, preQ2, R)
        begin
          if R='1' then --asynchronous reset, active high
            Q2 <= '0';
          elsif C1'event and C1='1' then --Clock event - posedge
            Q2 <= preQ2;
          end if;
        end process;
     end generate;
 
    V2 : if tech = virtex2 or tech = spartan3 generate
 
      -- CE and S inputs inactive for virtex 2
 
      q1reg : process (C1, D, R)
      begin
        if R='1' then --asynchronous reset, active high
          Q1 <= '0';
        elsif C1'event and C1='1' then --Clock event - posedge
          Q1 <= D;
        end if;
      end process;
 
      q2reg : process (C1, D, R)
      begin
        if R='1' then --asynchronous reset, active high
         preQ2 <= '0';
        elsif C1'event and C1='0' then --Clock event - negedge
         preQ2 <= D;
        end if;
      end process;
 
      q3reg : process (C1, preQ2, R)
      begin
        if R='1' then --asynchronous reset, active high
          Q2 <= '0';
        elsif C1'event and C1='1' then --Clock event - posedge
          Q2 <= preQ2;
        end if;
      end process;
 
 -- NOTE: You must include the following constraints in the .ucf
 -- file when running back-end tools,
 -- in order to ensure that IOB DDR registers are used:
 -- -- INST "q2_reg" IOB=TRUE;
 -- INST "q1_reg" IOB=TRUE;
 -- -- Depending on the synthesis tools you use, it may be required to
 -- check the edif file for modifications to
 -- original net names...in this case, Synopsys changed the
 -- names: q1 and q2 to q1_reg and q2_reg
 
    end generate;
 
end;
 
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.oddr;
use unisim.FDDRRSE;
--pragma translate_on
 
entity unisim_oddr_reg is
  generic ( tech : integer := virtex4);
  port
    ( Q : out std_ulogic;
      C1 : in std_ulogic;
      C2 : in std_ulogic;
      CE : in std_ulogic;
      D1 : in std_ulogic;
      D2 : in std_ulogic;
      R : in std_ulogic;
      S : in std_ulogic);
end;
 
architecture rtl of unisim_oddr_reg is
  attribute BOX_TYPE : string;
 
 
  component ODDR
    generic
      ( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
--        INIT : bit := '0';
        SRTYPE : string := "SYNC");
    port
      (
        Q : out std_ulogic;
        C : in std_ulogic;
        CE : in std_ulogic;
        D1 : in std_ulogic;
        D2 : in std_ulogic;
        R : in std_ulogic;
        S : in std_ulogic
      );
  end component;
  attribute BOX_TYPE of
    ODDR : component is "PRIMITIVE";
 
  component FDDRRSE
--    generic ( INIT : bit := '0');
    port
      (
        Q : out std_ulogic;
        C0 : in std_ulogic;
        C1 : in std_ulogic;
        CE : in std_ulogic;
        D0 : in std_ulogic;
        D1 : in std_ulogic;
        R : in std_ulogic;
        S : in std_ulogic
      );
  end component;
  attribute BOX_TYPE of
    FDDRRSE : component is "PRIMITIVE";
 
  signal preD2 : std_ulogic;
 
begin
 
-- SAME EDGE mode have when this is written an incorrect P&R
-- timing model, instead OPPOSITE_MODE with an extra register is used
--    V4 : if tech = virtex4 generate
--      U0 : ODDR
--        generic map(
--          DDR_CLK_EDGE => "SAME_EDGE",
--          INIT => '0',
--          SRTYPE => "ASYNC")
--        port map(
--          Q => Q,
--          C => C1,
--          CE => CE,
--          D1 => D1,
--          D2 => D2,
--          R => R,
--          S => S);
--      end generate;
 
  V4 : if (tech = virtex4) or (tech = virtex5) generate
 
    d2reg : process (C1, D2, R)
       begin
         if R='1' then --asynchronous reset, active high
           preD2 <= '0';
         elsif C1'event and C1='1' then --Clock event - posedge
           preD2 <= D2;
         end if;
       end process;
 
     U0 : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE" -- ,INIT => '0'
         , SRTYPE => "ASYNC")
       port map(
         Q => Q,
         C => C1,
         CE => CE,
         D1 => D1,
         D2 => preD2,
         R => R,
         S => S);
  end generate;
 
  V2 : if tech = virtex2 or tech = spartan3 generate
 
      d2reg : process (C1, D2, R)
      begin
        if R='1' then --asynchronous reset, active high
          preD2 <= '0';
        elsif C1'event and C1='1' then --Clock event - posedge
          preD2 <= D2;
        end if;
      end process;
 
      c_dm : component FDDRRSE
--        generic map( INIT => '0')
        port map(
          Q =>  Q,
          D0 => D1,
          D1 => preD2,
          C0 => C1,
          C1 => C2,
          CE => CE,
          R => R,
          S => S);
  end generate;
 
 
end ;
 
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
use unisim.FDDRRSE;
--pragma translate_on
 
entity oddrv2 is
  generic ( tech : integer := virtex4);
  port
    ( Q : out std_ulogic;
      C1 : in std_ulogic;
      C2 : in std_ulogic;
      CE : in std_ulogic;
      D1 : in std_ulogic;
      D2 : in std_ulogic;
      R : in std_ulogic;
      S : in std_ulogic);
end;
 
architecture rtl of oddrv2 is
  component FD
        generic ( INIT : bit := '0');
        port (  Q : out std_ulogic;
                C : in std_ulogic;
                D : in std_ulogic);
  end component;
 
  component FDDRRSE
    port
      (
        Q : out std_ulogic;
        C0 : in std_ulogic;
        C1 : in std_ulogic;
        CE : in std_ulogic;
        D0 : in std_ulogic;
        D1 : in std_ulogic;
        R : in std_ulogic;
        S : in std_ulogic
      );
  end component;
 
  signal preD2 : std_ulogic;
 
begin
 
  rf : FD port map ( Q => preD2, C => C1, D => D2);
  rr : FDDRRSE  port map ( Q => Q, C0 => C1, C1 => C2,
        CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
 
 
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
use unisim.oddr2;
--pragma translate_on
 
entity oddrc3e is
  generic ( tech : integer := virtex4);
  port
    ( Q : out std_ulogic;
      C1 : in std_ulogic;
      C2 : in std_ulogic;
      CE : in std_ulogic;
      D1 : in std_ulogic;
      D2 : in std_ulogic;
      R : in std_ulogic;
      S : in std_ulogic);
end;
 
architecture rtl of oddrc3e is
  component FD
        generic ( INIT : bit := '0');
        port (  Q : out std_ulogic;
                C : in std_ulogic;
                D : in std_ulogic);
  end component;
 
  component ODDR2
        generic
        (
                DDR_ALIGNMENT : string := "NONE";
                INIT : bit := '0';
                SRTYPE : string := "SYNC"
        );
        port
        (
                Q : out std_ulogic;
                C0 : in std_ulogic;
                C1 : in std_ulogic;
                CE : in std_ulogic;
                D0 : in std_ulogic;
                D1 : in std_ulogic;
                R : in std_ulogic;
                S : in std_ulogic
        );
  end component;
 
  signal preD2 : std_ulogic;
 
begin
 
  rf : FD port map ( Q => preD2, C => C1, D => D2);
  rr : ODDR2  port map ( Q => Q, C0 => C1, C1 => C2,
        CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
 
 
 
 

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [unisim/] [ddr_unisim.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Entity: unisim_iddr_reg`
20			`-- File: unisim_iddr_reg.vhd`
21			`-- Author: David Lindh, Jiri Gaisler - Gaisler Research`
22			`-- Description: Xilinx DDR input register`
23			`------------------------------------------------------------------------------`
24
25			`library ieee;`
26			`use ieee.std_logic_1164.all;`
27			`library techmap;`
28			`use techmap.gencomp.all;`
29			`-- pragma translate_off`
30			`library unisim;`
31			`use unisim.iddr;`
32			`--pragma translate_on`
33
34			`entity unisim_iddr_reg is`
35			`generic (tech : integer := virtex4);`
36			`port(`
37			`Q1 : out std_ulogic;`
38			`Q2 : out std_ulogic;`
39			`C1 : in std_ulogic;`
40			`C2 : in std_ulogic;`
41			`CE : in std_ulogic;`
42			`D : in std_ulogic;`
43			`R : in std_ulogic;`
44			`S : in std_ulogic`
45			`);`
46			`end;`
47
48			`architecture rtl of unisim_iddr_reg is`
49			`attribute BOX_TYPE : string;`
50			`-- attribute syn_useioff : boolean;`
51			`-- attribute syn_useioff of rtl : architecture is false;`
52
53			`component IDDR`
54			`generic ( DDR_CLK_EDGE : string := "SAME_EDGE";`
55			`INIT_Q1 : bit := '0';`
56			`INIT_Q2 : bit := '0';`
57			`SRTYPE : string := "ASYNC");`
58			`port`
59			`( Q1 : out std_ulogic;`
60			`Q2 : out std_ulogic;`
61			`C : in std_ulogic;`
62			`CE : in std_ulogic;`
63			`D : in std_ulogic;`
64			`R : in std_ulogic;`
65			`S : in std_ulogic);`
66			`end component;`
67			`attribute BOX_TYPE of IDDR : component is "PRIMITIVE";`
68			`signal preQ2 : std_ulogic;`
69
70			`begin`
71
72
73			`-- SAME EDGE mode have when this is written an incorrect P&R`
74			`-- timing model, instead OPPOSITE_MODE with an extra register is used`
75			`-- V4 : if tech = virtex4 generate`
76			`-- U0 : IDDR`
77			`-- generic map(`
78			`-- DDR_CLK_EDGE => "SAME_EDGE",`
79			`-- INIT_Q1 => '0',`
80			`-- INIT_Q2 => '0',`
81			`-- SRTYPE => "ASYNC")`
82			`-- Port map(`
83			`-- Q1 => Q1,`
84			`-- Q2 => Q2,`
85			`-- C => C1,`
86			`-- CE => CE,`
87			`-- D => D,`
88			`-- R => R,`
89			`-- S => S);`
90			`-- end generate;`
91
92			`V4 : if (tech = virtex4) or (tech = virtex5) generate`
93			`U0 : IDDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE"`
94			`-- ,INIT_Q1 => '0',`
95			`-- INIT_Q2 => '0',`
96			`-- SRTYPE => "ASYNC"`
97			`)`
98			`Port map( Q1 => Q1, Q2 => preQ2, C => C1, CE => CE,`
99			`D => D, R => R, S => S);`
100
101			`q3reg : process (C1, preQ2, R)`
102			`begin`
103			`if R='1' then --asynchronous reset, active high`
104			`Q2 <= '0';`
105			`elsif C1'event and C1='1' then --Clock event - posedge`
106			`Q2 <= preQ2;`
107			`end if;`
108			`end process;`
109			`end generate;`
110
111			`V2 : if tech = virtex2 or tech = spartan3 generate`
112
113			`-- CE and S inputs inactive for virtex 2`
114
115			`q1reg : process (C1, D, R)`
116			`begin`
117			`if R='1' then --asynchronous reset, active high`
118			`Q1 <= '0';`
119			`elsif C1'event and C1='1' then --Clock event - posedge`
120			`Q1 <= D;`
121			`end if;`
122			`end process;`
123
124			`q2reg : process (C1, D, R)`
125			`begin`
126			`if R='1' then --asynchronous reset, active high`
127			`preQ2 <= '0';`
128			`elsif C1'event and C1='0' then --Clock event - negedge`
129			`preQ2 <= D;`
130			`end if;`
131			`end process;`
132
133			`q3reg : process (C1, preQ2, R)`
134			`begin`
135			`if R='1' then --asynchronous reset, active high`
136			`Q2 <= '0';`
137			`elsif C1'event and C1='1' then --Clock event - posedge`
138			`Q2 <= preQ2;`
139			`end if;`
140			`end process;`
141
142			`-- NOTE: You must include the following constraints in the .ucf`
143			`-- file when running back-end tools,`
144			`-- in order to ensure that IOB DDR registers are used:`
145			`-- -- INST "q2_reg" IOB=TRUE;`
146			`-- INST "q1_reg" IOB=TRUE;`
147			`-- -- Depending on the synthesis tools you use, it may be required to`
148			`-- check the edif file for modifications to`
149			`-- original net names...in this case, Synopsys changed the`
150			`-- names: q1 and q2 to q1_reg and q2_reg`
151
152			`end generate;`
153
154			`end;`
155
156			`library ieee;`
157			`use ieee.std_logic_1164.all;`
158			`library techmap;`
159			`use techmap.gencomp.all;`
160			`-- pragma translate_off`
161			`library unisim;`
162			`use unisim.oddr;`
163			`use unisim.FDDRRSE;`
164			`--pragma translate_on`
165
166			`entity unisim_oddr_reg is`
167			`generic ( tech : integer := virtex4);`
168			`port`
169			`( Q : out std_ulogic;`
170			`C1 : in std_ulogic;`
171			`C2 : in std_ulogic;`
172			`CE : in std_ulogic;`
173			`D1 : in std_ulogic;`
174			`D2 : in std_ulogic;`
175			`R : in std_ulogic;`
176			`S : in std_ulogic);`
177			`end;`
178
179			`architecture rtl of unisim_oddr_reg is`
180			`attribute BOX_TYPE : string;`
181
182
183			`component ODDR`
184			`generic`
185			`( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";`
186			`-- INIT : bit := '0';`
187			`SRTYPE : string := "SYNC");`
188			`port`
189			`(`
190			`Q : out std_ulogic;`
191			`C : in std_ulogic;`
192			`CE : in std_ulogic;`
193			`D1 : in std_ulogic;`
194			`D2 : in std_ulogic;`
195			`R : in std_ulogic;`
196			`S : in std_ulogic`
197			`);`
198			`end component;`
199			`attribute BOX_TYPE of`
200			`ODDR : component is "PRIMITIVE";`
201
202			`component FDDRRSE`
203			`-- generic ( INIT : bit := '0');`
204			`port`
205			`(`
206			`Q : out std_ulogic;`
207			`C0 : in std_ulogic;`
208			`C1 : in std_ulogic;`
209			`CE : in std_ulogic;`
210			`D0 : in std_ulogic;`
211			`D1 : in std_ulogic;`
212			`R : in std_ulogic;`
213			`S : in std_ulogic`
214			`);`
215			`end component;`
216			`attribute BOX_TYPE of`
217			`FDDRRSE : component is "PRIMITIVE";`
218
219			`signal preD2 : std_ulogic;`
220
221			`begin`
222
223			`-- SAME EDGE mode have when this is written an incorrect P&R`
224			`-- timing model, instead OPPOSITE_MODE with an extra register is used`
225			`-- V4 : if tech = virtex4 generate`
226			`-- U0 : ODDR`
227			`-- generic map(`
228			`-- DDR_CLK_EDGE => "SAME_EDGE",`
229			`-- INIT => '0',`
230			`-- SRTYPE => "ASYNC")`
231			`-- port map(`
232			`-- Q => Q,`
233			`-- C => C1,`
234			`-- CE => CE,`
235			`-- D1 => D1,`
236			`-- D2 => D2,`
237			`-- R => R,`
238			`-- S => S);`
239			`-- end generate;`
240
241			`V4 : if (tech = virtex4) or (tech = virtex5) generate`
242
243			`d2reg : process (C1, D2, R)`
244			`begin`
245			`if R='1' then --asynchronous reset, active high`
246			`preD2 <= '0';`
247			`elsif C1'event and C1='1' then --Clock event - posedge`
248			`preD2 <= D2;`
249			`end if;`
250			`end process;`
251
252			`U0 : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE" -- ,INIT => '0'`
253			`, SRTYPE => "ASYNC")`
254			`port map(`
255			`Q => Q,`
256			`C => C1,`
257			`CE => CE,`
258			`D1 => D1,`
259			`D2 => preD2,`
260			`R => R,`
261			`S => S);`
262			`end generate;`
263
264			`V2 : if tech = virtex2 or tech = spartan3 generate`
265
266			`d2reg : process (C1, D2, R)`
267			`begin`
268			`if R='1' then --asynchronous reset, active high`
269			`preD2 <= '0';`
270			`elsif C1'event and C1='1' then --Clock event - posedge`
271			`preD2 <= D2;`
272			`end if;`
273			`end process;`
274
275			`c_dm : component FDDRRSE`
276			`-- generic map( INIT => '0')`
277			`port map(`
278			`Q => Q,`
279			`D0 => D1,`
280			`D1 => preD2,`
281			`C0 => C1,`
282			`C1 => C2,`
283			`CE => CE,`
284			`R => R,`
285			`S => S);`
286			`end generate;`
287
288
289			`end ;`
290
291			`library ieee;`
292			`use ieee.std_logic_1164.all;`
293			`library techmap;`
294			`use techmap.gencomp.all;`
295			`-- pragma translate_off`
296			`library unisim;`
297			`use unisim.fd;`
298			`use unisim.FDDRRSE;`
299			`--pragma translate_on`
300
301			`entity oddrv2 is`
302			`generic ( tech : integer := virtex4);`
303			`port`
304			`( Q : out std_ulogic;`
305			`C1 : in std_ulogic;`
306			`C2 : in std_ulogic;`
307			`CE : in std_ulogic;`
308			`D1 : in std_ulogic;`
309			`D2 : in std_ulogic;`
310			`R : in std_ulogic;`
311			`S : in std_ulogic);`
312			`end;`
313
314			`architecture rtl of oddrv2 is`
315			`component FD`
316			`generic ( INIT : bit := '0');`
317			`port ( Q : out std_ulogic;`
318			`C : in std_ulogic;`
319			`D : in std_ulogic);`
320			`end component;`
321
322			`component FDDRRSE`
323			`port`
324			`(`
325			`Q : out std_ulogic;`
326			`C0 : in std_ulogic;`
327			`C1 : in std_ulogic;`
328			`CE : in std_ulogic;`
329			`D0 : in std_ulogic;`
330			`D1 : in std_ulogic;`
331			`R : in std_ulogic;`
332			`S : in std_ulogic`
333			`);`
334			`end component;`
335
336			`signal preD2 : std_ulogic;`
337
338			`begin`
339
340			`rf : FD port map ( Q => preD2, C => C1, D => D2);`
341			`rr : FDDRRSE port map ( Q => Q, C0 => C1, C1 => C2,`
342			`CE => CE, D0 => D1, D1 => preD2, R => R, S => R);`
343			`end;`
344
345
346			`library ieee;`
347			`use ieee.std_logic_1164.all;`
348			`library techmap;`
349			`use techmap.gencomp.all;`
350			`-- pragma translate_off`
351			`library unisim;`
352			`use unisim.fd;`
353			`use unisim.oddr2;`
354			`--pragma translate_on`
355
356			`entity oddrc3e is`
357			`generic ( tech : integer := virtex4);`
358			`port`
359			`( Q : out std_ulogic;`
360			`C1 : in std_ulogic;`
361			`C2 : in std_ulogic;`
362			`CE : in std_ulogic;`
363			`D1 : in std_ulogic;`
364			`D2 : in std_ulogic;`
365			`R : in std_ulogic;`
366			`S : in std_ulogic);`
367			`end;`
368
369			`architecture rtl of oddrc3e is`
370			`component FD`
371			`generic ( INIT : bit := '0');`
372			`port ( Q : out std_ulogic;`
373			`C : in std_ulogic;`
374			`D : in std_ulogic);`
375			`end component;`
376
377			`component ODDR2`
378			`generic`
379			`(`
380			`DDR_ALIGNMENT : string := "NONE";`
381			`INIT : bit := '0';`
382			`SRTYPE : string := "SYNC"`
383			`);`
384			`port`
385			`(`
386			`Q : out std_ulogic;`
387			`C0 : in std_ulogic;`
388			`C1 : in std_ulogic;`
389			`CE : in std_ulogic;`
390			`D0 : in std_ulogic;`
391			`D1 : in std_ulogic;`
392			`R : in std_ulogic;`
393			`S : in std_ulogic`
394			`);`
395			`end component;`
396
397			`signal preD2 : std_ulogic;`
398
399			`begin`
400
401			`rf : FD port map ( Q => preD2, C => C1, D => D2);`
402			`rr : ODDR2 port map ( Q => Q, C0 => C1, C1 => C2,`
403			`CE => CE, D0 => D1, D1 => preD2, R => R, S => R);`
404			`end;`
405
406
407
408