OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [unisim/] [grfpw_unisim.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali 
------------------------------------------------------------------------------
2 
--  This file is a part of the GRLIB VHDL IP LIBRARY
3 
--  Copyright (C) 2006, Gaisler Research AB - all rights reserved.
4 
--
5 
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
6 
-- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
7 
-- IN ADVANCE IN WRITING.
8 
-----------------------------------------------------------------------------
9 
-- Entity:      grfpw_unisim
10 
-- File:        grfpw_unisim.vhd
11 
-- Author:      Jan Andersson - Gaisler Research
12 
-- Description: tech wrapper for xilinx/unisim grfpw netlist
13 
------------------------------------------------------------------------------
14 
library ieee;
15 
use ieee.std_logic_1164.all;
16 
library unisim;
17 
use unisim.all;
18 
library techmap;
19 
use techmap.gencomp.all;
20 
 
21 
entity grfpw_unisim is
22 
  generic (tech : integer := 0);
23 
  port(
24 
    rst :  in std_logic;
25 
    clk :  in std_logic;
26 
    holdn :  in std_logic;
27 
    cpi_flush :  in std_logic;
28 
    cpi_exack :  in std_logic;
29 
    cpi_a_rs1 : in std_logic_vector(4 downto 0);
30 
    cpi_d_pc : in std_logic_vector(31 downto 0);
31 
    cpi_d_inst : in std_logic_vector(31 downto 0);
32 
    cpi_d_cnt : in std_logic_vector(1 downto 0);
33 
    cpi_d_trap :  in std_logic;
34 
    cpi_d_annul :  in std_logic;
35 
    cpi_d_pv :  in std_logic;
36 
    cpi_a_pc : in std_logic_vector(31 downto 0);
37 
    cpi_a_inst : in std_logic_vector(31 downto 0);
38 
    cpi_a_cnt : in std_logic_vector(1 downto 0);
39 
    cpi_a_trap :  in std_logic;
40 
    cpi_a_annul :  in std_logic;
41 
    cpi_a_pv :  in std_logic;
42 
    cpi_e_pc : in std_logic_vector(31 downto 0);
43 
    cpi_e_inst : in std_logic_vector(31 downto 0);
44 
    cpi_e_cnt : in std_logic_vector(1 downto 0);
45 
    cpi_e_trap :  in std_logic;
46 
    cpi_e_annul :  in std_logic;
47 
    cpi_e_pv :  in std_logic;
48 
    cpi_m_pc : in std_logic_vector(31 downto 0);
49 
    cpi_m_inst : in std_logic_vector(31 downto 0);
50 
    cpi_m_cnt : in std_logic_vector(1 downto 0);
51 
    cpi_m_trap :  in std_logic;
52 
    cpi_m_annul :  in std_logic;
53 
    cpi_m_pv :  in std_logic;
54 
    cpi_x_pc : in std_logic_vector(31 downto 0);
55 
    cpi_x_inst : in std_logic_vector(31 downto 0);
56 
    cpi_x_cnt : in std_logic_vector(1 downto 0);
57 
    cpi_x_trap :  in std_logic;
58 
    cpi_x_annul :  in std_logic;
59 
    cpi_x_pv :  in std_logic;
60 
    cpi_lddata : in std_logic_vector(31 downto 0);
61 
    cpi_dbg_enable :  in std_logic;
62 
    cpi_dbg_write :  in std_logic;
63 
    cpi_dbg_fsr :  in std_logic;
64 
    cpi_dbg_addr : in std_logic_vector(4 downto 0);
65 
    cpi_dbg_data : in std_logic_vector(31 downto 0);
66 
    cpo_data : out std_logic_vector(31 downto 0);
67 
    cpo_exc :  out std_logic;
68 
    cpo_cc : out std_logic_vector(1 downto 0);
69 
    cpo_ccv :  out std_logic;
70 
    cpo_ldlock :  out std_logic;
71 
    cpo_holdn :  out std_logic;
72 
    cpo_dbg_data : out std_logic_vector(31 downto 0);
73 
    rfi1_rd1addr : out std_logic_vector(3 downto 0);
74 
    rfi1_rd2addr : out std_logic_vector(3 downto 0);
75 
    rfi1_wraddr : out std_logic_vector(3 downto 0);
76 
    rfi1_wrdata : out std_logic_vector(31 downto 0);
77 
    rfi1_ren1 :  out std_logic;
78 
    rfi1_ren2 :  out std_logic;
79 
    rfi1_wren :  out std_logic;
80 
    rfi2_rd1addr : out std_logic_vector(3 downto 0);
81 
    rfi2_rd2addr : out std_logic_vector(3 downto 0);
82 
    rfi2_wraddr : out std_logic_vector(3 downto 0);
83 
    rfi2_wrdata : out std_logic_vector(31 downto 0);
84 
    rfi2_ren1 :  out std_logic;
85 
    rfi2_ren2 :  out std_logic;
86 
    rfi2_wren :  out std_logic;
87 
    rfo1_data1 : in std_logic_vector(31 downto 0);
88 
    rfo1_data2 : in std_logic_vector(31 downto 0);
89 
    rfo2_data1 : in std_logic_vector(31 downto 0);
90 
    rfo2_data2 : in std_logic_vector(31 downto 0);
91 
    disasen     :  in std_logic);
92 
end grfpw_unisim;
93 
 
94 
architecture rtl of grfpw_unisim is
95 
 
96 
component grfpw_0_unisim_v2
97 
  port(
98 
  rst :  in std_logic;
99 
  clk :  in std_logic;
100 
  holdn :  in std_logic;
101 
  cpi_flush :  in std_logic;
102 
  cpi_exack :  in std_logic;
103 
  cpi_a_rs1 : in std_logic_vector(4 downto 0);
104 
  cpi_d_pc : in std_logic_vector(31 downto 0);
105 
  cpi_d_inst : in std_logic_vector(31 downto 0);
106 
  cpi_d_cnt : in std_logic_vector(1 downto 0);
107 
  cpi_d_trap :  in std_logic;
108 
  cpi_d_annul :  in std_logic;
109 
  cpi_d_pv :  in std_logic;
110 
  cpi_a_pc : in std_logic_vector(31 downto 0);
111 
  cpi_a_inst : in std_logic_vector(31 downto 0);
112 
  cpi_a_cnt : in std_logic_vector(1 downto 0);
113 
  cpi_a_trap :  in std_logic;
114 
  cpi_a_annul :  in std_logic;
115 
  cpi_a_pv :  in std_logic;
116 
  cpi_e_pc : in std_logic_vector(31 downto 0);
117 
  cpi_e_inst : in std_logic_vector(31 downto 0);
118 
  cpi_e_cnt : in std_logic_vector(1 downto 0);
119 
  cpi_e_trap :  in std_logic;
120 
  cpi_e_annul :  in std_logic;
121 
  cpi_e_pv :  in std_logic;
122 
  cpi_m_pc : in std_logic_vector(31 downto 0);
123 
  cpi_m_inst : in std_logic_vector(31 downto 0);
124 
  cpi_m_cnt : in std_logic_vector(1 downto 0);
125 
  cpi_m_trap :  in std_logic;
126 
  cpi_m_annul :  in std_logic;
127 
  cpi_m_pv :  in std_logic;
128 
  cpi_x_pc : in std_logic_vector(31 downto 0);
129 
  cpi_x_inst : in std_logic_vector(31 downto 0);
130 
  cpi_x_cnt : in std_logic_vector(1 downto 0);
131 
  cpi_x_trap :  in std_logic;
132 
  cpi_x_annul :  in std_logic;
133 
  cpi_x_pv :  in std_logic;
134 
  cpi_lddata : in std_logic_vector(31 downto 0);
135 
  cpi_dbg_enable :  in std_logic;
136 
  cpi_dbg_write :  in std_logic;
137 
  cpi_dbg_fsr :  in std_logic;
138 
  cpi_dbg_addr : in std_logic_vector(4 downto 0);
139 
  cpi_dbg_data : in std_logic_vector(31 downto 0);
140 
  cpo_data : out std_logic_vector(31 downto 0);
141 
  cpo_exc :  out std_logic;
142 
  cpo_cc : out std_logic_vector(1 downto 0);
143 
  cpo_ccv :  out std_logic;
144 
  cpo_ldlock :  out std_logic;
145 
  cpo_holdn :  out std_logic;
146 
  cpo_dbg_data : out std_logic_vector(31 downto 0);
147 
  rfi1_rd1addr : out std_logic_vector(3 downto 0);
148 
  rfi1_rd2addr : out std_logic_vector(3 downto 0);
149 
  rfi1_wraddr : out std_logic_vector(3 downto 0);
150 
  rfi1_wrdata : out std_logic_vector(31 downto 0);
151 
  rfi1_ren1 :  out std_logic;
152 
  rfi1_ren2 :  out std_logic;
153 
  rfi1_wren :  out std_logic;
154 
  rfi2_rd1addr : out std_logic_vector(3 downto 0);
155 
  rfi2_rd2addr : out std_logic_vector(3 downto 0);
156 
  rfi2_wraddr : out std_logic_vector(3 downto 0);
157 
  rfi2_wrdata : out std_logic_vector(31 downto 0);
158 
  rfi2_ren1 :  out std_logic;
159 
  rfi2_ren2 :  out std_logic;
160 
  rfi2_wren :  out std_logic;
161 
  rfo1_data1 : in std_logic_vector(31 downto 0);
162 
  rfo1_data2 : in std_logic_vector(31 downto 0);
163 
  rfo2_data1 : in std_logic_vector(31 downto 0);
164 
  rfo2_data2 : in std_logic_vector(31 downto 0);
165 
  disasen     :  in std_logic);
166 
end component;
167 
 
168 
component grfpw_0_unisim_v4
169 
port(
170 
  rst :  in std_logic;
171 
  clk :  in std_logic;
172 
  holdn :  in std_logic;
173 
  cpi_flush :  in std_logic;
174 
  cpi_exack :  in std_logic;
175 
  cpi_a_rs1 : in std_logic_vector(4 downto 0);
176 
  cpi_d_pc : in std_logic_vector(31 downto 0);
177 
  cpi_d_inst : in std_logic_vector(31 downto 0);
178 
  cpi_d_cnt : in std_logic_vector(1 downto 0);
179 
  cpi_d_trap :  in std_logic;
180 
  cpi_d_annul :  in std_logic;
181 
  cpi_d_pv :  in std_logic;
182 
  cpi_a_pc : in std_logic_vector(31 downto 0);
183 
  cpi_a_inst : in std_logic_vector(31 downto 0);
184 
  cpi_a_cnt : in std_logic_vector(1 downto 0);
185 
  cpi_a_trap :  in std_logic;
186 
  cpi_a_annul :  in std_logic;
187 
  cpi_a_pv :  in std_logic;
188 
  cpi_e_pc : in std_logic_vector(31 downto 0);
189 
  cpi_e_inst : in std_logic_vector(31 downto 0);
190 
  cpi_e_cnt : in std_logic_vector(1 downto 0);
191 
  cpi_e_trap :  in std_logic;
192 
  cpi_e_annul :  in std_logic;
193 
  cpi_e_pv :  in std_logic;
194 
  cpi_m_pc : in std_logic_vector(31 downto 0);
195 
  cpi_m_inst : in std_logic_vector(31 downto 0);
196 
  cpi_m_cnt : in std_logic_vector(1 downto 0);
197 
  cpi_m_trap :  in std_logic;
198 
  cpi_m_annul :  in std_logic;
199 
  cpi_m_pv :  in std_logic;
200 
  cpi_x_pc : in std_logic_vector(31 downto 0);
201 
  cpi_x_inst : in std_logic_vector(31 downto 0);
202 
  cpi_x_cnt : in std_logic_vector(1 downto 0);
203 
  cpi_x_trap :  in std_logic;
204 
  cpi_x_annul :  in std_logic;
205 
  cpi_x_pv :  in std_logic;
206 
  cpi_lddata : in std_logic_vector(31 downto 0);
207 
  cpi_dbg_enable :  in std_logic;
208 
  cpi_dbg_write :  in std_logic;
209 
  cpi_dbg_fsr :  in std_logic;
210 
  cpi_dbg_addr : in std_logic_vector(4 downto 0);
211 
  cpi_dbg_data : in std_logic_vector(31 downto 0);
212 
  cpo_data : out std_logic_vector(31 downto 0);
213 
  cpo_exc :  out std_logic;
214 
  cpo_cc : out std_logic_vector(1 downto 0);
215 
  cpo_ccv :  out std_logic;
216 
  cpo_ldlock :  out std_logic;
217 
  cpo_holdn :  out std_logic;
218 
  cpo_dbg_data : out std_logic_vector(31 downto 0);
219 
  rfi1_rd1addr : out std_logic_vector(3 downto 0);
220 
  rfi1_rd2addr : out std_logic_vector(3 downto 0);
221 
  rfi1_wraddr : out std_logic_vector(3 downto 0);
222 
  rfi1_wrdata : out std_logic_vector(31 downto 0);
223 
  rfi1_ren1 :  out std_logic;
224 
  rfi1_ren2 :  out std_logic;
225 
  rfi1_wren :  out std_logic;
226 
  rfi2_rd1addr : out std_logic_vector(3 downto 0);
227 
  rfi2_rd2addr : out std_logic_vector(3 downto 0);
228 
  rfi2_wraddr : out std_logic_vector(3 downto 0);
229 
  rfi2_wrdata : out std_logic_vector(31 downto 0);
230 
  rfi2_ren1 :  out std_logic;
231 
  rfi2_ren2 :  out std_logic;
232 
  rfi2_wren :  out std_logic;
233 
  rfo1_data1 : in std_logic_vector(31 downto 0);
234 
  rfo1_data2 : in std_logic_vector(31 downto 0);
235 
  rfo2_data1 : in std_logic_vector(31 downto 0);
236 
  rfo2_data2 : in std_logic_vector(31 downto 0);
237 
  disasen     :  in std_logic);
238 
end component;
239 
 
240 
begin
241 
 
242 
  v2 : if (tech = virtex2) or (tech = spartan3) or  (tech = spartan3e)
243 
  generate
244 
    grfpw0 : grfpw_0_unisim_v2
245 
      port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
246 
        cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
247 
        cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
248 
        cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
249 
        cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
250 
        cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
251 
        cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
252 
        cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
253 
        rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
254 
        rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
255 
        rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
256 
        rfo1_data2, rfo2_data1, rfo2_data2, disasen);
257 
  end generate;
258 
 
259 
  v4 : if (tech = virtex4) or (tech = virtex5)
260 
  generate
261 
    grfpw0 : grfpw_0_unisim_v4
262 
      port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
263 
        cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
264 
        cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
265 
        cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
266 
        cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
267 
        cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
268 
        cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
269 
        cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
270 
        rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
271 
        rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
272 
        rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
273 
        rfo1_data2, rfo2_data1, rfo2_data2, disasen);
274 
  end generate;
275 
 
276 
-- pragma translate_off
277 
 
278 
  nomap : if not ((tech = virtex4) or (tech = virtex5) or (tech = virtex2) or
279 
                  (tech = spartan3) or  (tech = spartan3e)) generate
280 
    err : process
281 
    begin
282 
      assert false report "ERROR: No appropriate netlist available"
283 
        severity failure;
284 
      wait;
285 
    end process;
286 
 
287 
  end generate;
288 
 
289 
-- pragma translate_on
290 
 
291 
end;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.