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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: various
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-- File: mem_xilinx_gen.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Memory generators for Xilinx rams
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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--pragma translate_off
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library unisim;
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use unisim.RAMB4_S1;
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use unisim.RAMB4_S2;
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use unisim.RAMB4_S4;
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use unisim.RAMB4_S8;
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use unisim.RAMB4_S16;
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use unisim.RAMB4_S16_S16;
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--pragma translate_on
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library techmap;
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use techmap.gencomp.all;
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entity virtex_syncram is
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generic ( abits : integer := 6; dbits : integer := 8);
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port (
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clk : in std_ulogic;
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address : in std_logic_vector (abits -1 downto 0);
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datain : in std_logic_vector (dbits -1 downto 0);
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dataout : out std_logic_vector (dbits -1 downto 0);
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enable : in std_ulogic;
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write : in std_ulogic
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);
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end;
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architecture behav of virtex_syncram is
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component generic_syncram
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generic ( abits : integer := 10; dbits : integer := 8 );
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port (
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clk : in std_ulogic;
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address : in std_logic_vector((abits -1) downto 0);
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datain : in std_logic_vector((dbits -1) downto 0);
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dataout : out std_logic_vector((dbits -1) downto 0);
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write : in std_ulogic);
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end component;
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component ramb4_s16 port (
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do : out std_logic_vector (15 downto 0);
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addr : in std_logic_vector (7 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (15 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S8
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port (do : out std_logic_vector (7 downto 0);
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addr : in std_logic_vector (8 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (7 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S4
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port (do : out std_logic_vector (3 downto 0);
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addr : in std_logic_vector (9 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (3 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S2
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port (do : out std_logic_vector (1 downto 0);
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addr : in std_logic_vector (10 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (1 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S1
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port (do : out std_logic_vector (0 downto 0);
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addr : in std_logic_vector (11 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (0 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S16_S16
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port (
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doa : out std_logic_vector (15 downto 0);
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dob : out std_logic_vector (15 downto 0);
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addra : in std_logic_vector (7 downto 0);
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addrb : in std_logic_vector (7 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (15 downto 0);
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dib : in std_logic_vector (15 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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signal gnd : std_ulogic;
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signal do, di : std_logic_vector(dbits+32 downto 0);
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signal xa, ya : std_logic_vector(19 downto 0);
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begin
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gnd <= '0';
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dataout <= do(dbits-1 downto 0);
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di(dbits-1 downto 0) <= datain; di(dbits+32 downto dbits) <= (others => '0');
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xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
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ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
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a0 : if (abits <= 5) generate
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r0 : generic_syncram generic map (abits, dbits)
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port map (clk, address, datain, do(dbits-1 downto 0), write);
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do(dbits+32 downto dbits) <= (others => '0');
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end generate;
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a7 : if (abits > 5) and (abits <= 7) and (dbits <= 32) generate
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r0 : RAMB4_S16_S16 port map ( do(31 downto 16), do(15 downto 0),
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xa(7 downto 0), ya(7 downto 0), clk, clk, di(31 downto 16),
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di(15 downto 0), enable, enable, gnd, gnd, write, write);
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do(dbits+32 downto 32) <= (others => '0');
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end generate;
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a8 : if ((abits > 5) and (abits <= 7) and (dbits > 32)) or (abits = 8) generate
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x : for i in 0 to ((dbits-1)/16) generate
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r : RAMB4_S16 port map ( do (((i+1)*16)-1 downto i*16), xa(7 downto 0),
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clk, di (((i+1)*16)-1 downto i*16), enable, gnd, write );
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end generate;
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do(dbits+32 downto 16*(((dbits-1)/16)+1)) <= (others => '0');
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end generate;
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a9 : if abits = 9 generate
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x : for i in 0 to ((dbits-1)/8) generate
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r : RAMB4_S8 port map ( do (((i+1)*8)-1 downto i*8), xa(8 downto 0),
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clk, di (((i+1)*8)-1 downto i*8), enable, gnd, write );
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end generate;
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do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
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end generate;
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a10 : if abits = 10 generate
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x : for i in 0 to ((dbits-1)/4) generate
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r : RAMB4_S4 port map ( do (((i+1)*4)-1 downto i*4), xa(9 downto 0),
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clk, di (((i+1)*4)-1 downto i*4), enable, gnd, write );
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end generate;
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do(dbits+32 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
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end generate;
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a11 : if abits = 11 generate
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x : for i in 0 to ((dbits-1)/2) generate
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r : RAMB4_S2 port map ( do (((i+1)*2)-1 downto i*2), xa(10 downto 0),
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clk, di (((i+1)*2)-1 downto i*2), enable, gnd, write );
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end generate;
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do(dbits+32 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
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end generate;
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a12 : if abits = 12 generate
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x : for i in 0 to (dbits-1) generate
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r : RAMB4_S1 port map ( do (i downto i), xa(11 downto 0),
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clk, di(i downto i), enable, gnd, write );
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end generate;
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do(dbits+32 downto dbits) <= (others => '0');
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end generate;
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a13 : if abits > 12 generate
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x: generic_syncram generic map (abits, dbits)
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port map (clk, address, datain, do(dbits-1 downto 0), write);
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do(dbits+32 downto dbits) <= (others => '0');
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end generate;
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-- pragma translate_off
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-- a_to_high : if abits > 12 generate
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-- x : process
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-- begin
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-- assert false
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-- report "Address depth larger than 12 not supported for virtex_syncram"
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-- severity failure;
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-- wait;
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-- end process;
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-- end generate;
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-- pragma translate_on
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end;
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library ieee;
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use ieee.std_logic_1164.all;
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--pragma translate_off
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library unisim;
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use unisim.RAMB4_S1_S1;
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use unisim.RAMB4_S2_S2;
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use unisim.RAMB4_S4_S4;
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use unisim.RAMB4_S8_S8;
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use unisim.RAMB4_S16_S16;
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--pragma translate_on
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entity virtex_syncram_dp is
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generic (
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abits : integer := 6; dbits : integer := 8
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);
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port (
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clk1 : in std_ulogic;
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address1 : in std_logic_vector((abits -1) downto 0);
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datain1 : in std_logic_vector((dbits -1) downto 0);
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dataout1 : out std_logic_vector((dbits -1) downto 0);
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enable1 : in std_ulogic;
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write1 : in std_ulogic;
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clk2 : in std_ulogic;
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address2 : in std_logic_vector((abits -1) downto 0);
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datain2 : in std_logic_vector((dbits -1) downto 0);
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dataout2 : out std_logic_vector((dbits -1) downto 0);
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enable2 : in std_ulogic;
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write2 : in std_ulogic);
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end;
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architecture behav of virtex_syncram_dp is
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component RAMB4_S1_S1
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port (
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doa : out std_logic_vector (0 downto 0);
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dob : out std_logic_vector (0 downto 0);
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addra : in std_logic_vector (11 downto 0);
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addrb : in std_logic_vector (11 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (0 downto 0);
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dib : in std_logic_vector (0 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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component RAMB4_S2_S2
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port (
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doa : out std_logic_vector (1 downto 0);
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dob : out std_logic_vector (1 downto 0);
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addra : in std_logic_vector (10 downto 0);
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addrb : in std_logic_vector (10 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (1 downto 0);
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dib : in std_logic_vector (1 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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component RAMB4_S4_S4
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port (
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doa : out std_logic_vector (3 downto 0);
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dob : out std_logic_vector (3 downto 0);
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addra : in std_logic_vector (9 downto 0);
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addrb : in std_logic_vector (9 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (3 downto 0);
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dib : in std_logic_vector (3 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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component RAMB4_S8_S8
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port (
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doa : out std_logic_vector (7 downto 0);
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dob : out std_logic_vector (7 downto 0);
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addra : in std_logic_vector (8 downto 0);
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addrb : in std_logic_vector (8 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (7 downto 0);
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dib : in std_logic_vector (7 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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component RAMB4_S16_S16
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port (
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doa : out std_logic_vector (15 downto 0);
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dob : out std_logic_vector (15 downto 0);
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addra : in std_logic_vector (7 downto 0);
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addrb : in std_logic_vector (7 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (15 downto 0);
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dib : in std_logic_vector (15 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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signal gnd, vcc : std_ulogic;
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signal do1, do2, di1, di2 : std_logic_vector(dbits+16 downto 0);
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signal addr1, addr2 : std_logic_vector(19 downto 0);
|
316 |
|
|
begin
|
317 |
|
|
gnd <= '0'; vcc <= '1';
|
318 |
|
|
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
|
319 |
|
|
di1(dbits-1 downto 0) <= datain1; di1(dbits+16 downto dbits) <= (others => '0');
|
320 |
|
|
di2(dbits-1 downto 0) <= datain2; di2(dbits+16 downto dbits) <= (others => '0');
|
321 |
|
|
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
|
322 |
|
|
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
|
323 |
|
|
|
324 |
|
|
a8 : if abits <= 8 generate
|
325 |
|
|
x : for i in 0 to ((dbits-1)/16) generate
|
326 |
|
|
r0 : RAMB4_S16_S16 port map (
|
327 |
|
|
do1(((i+1)*16)-1 downto i*16), do2(((i+1)*16)-1 downto i*16),
|
328 |
|
|
addr1(7 downto 0), addr2(7 downto 0), clk1, clk2,
|
329 |
|
|
di1(((i+1)*16)-1 downto i*16), di2(((i+1)*16)-1 downto i*16),
|
330 |
|
|
enable1, enable2, gnd, gnd, write1, write2);
|
331 |
|
|
end generate;
|
332 |
|
|
end generate;
|
333 |
|
|
|
334 |
|
|
a9 : if abits = 9 generate
|
335 |
|
|
x : for i in 0 to ((dbits-1)/8) generate
|
336 |
|
|
r0 : RAMB4_S8_S8 port map (
|
337 |
|
|
do1(((i+1)*8)-1 downto i*8), do2(((i+1)*8)-1 downto i*8),
|
338 |
|
|
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
|
339 |
|
|
di1(((i+1)*8)-1 downto i*8), di2(((i+1)*8)-1 downto i*8),
|
340 |
|
|
enable1, enable2, gnd, gnd, write1, write2);
|
341 |
|
|
end generate;
|
342 |
|
|
end generate;
|
343 |
|
|
|
344 |
|
|
a10: if abits = 10 generate
|
345 |
|
|
x : for i in 0 to ((dbits-1)/4) generate
|
346 |
|
|
r0 : RAMB4_S4_S4 port map (
|
347 |
|
|
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
|
348 |
|
|
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
|
349 |
|
|
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
|
350 |
|
|
enable1, enable2, gnd, gnd, write1, write2);
|
351 |
|
|
end generate;
|
352 |
|
|
end generate;
|
353 |
|
|
|
354 |
|
|
a11: if abits = 11 generate
|
355 |
|
|
x : for i in 0 to ((dbits-1)/2) generate
|
356 |
|
|
r0 : RAMB4_S2_S2 port map (
|
357 |
|
|
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
|
358 |
|
|
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
|
359 |
|
|
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
|
360 |
|
|
enable1, enable2, gnd, gnd, write1, write2);
|
361 |
|
|
end generate;
|
362 |
|
|
end generate;
|
363 |
|
|
|
364 |
|
|
a12: if abits = 12 generate
|
365 |
|
|
x : for i in 0 to ((dbits-1)/1) generate
|
366 |
|
|
r0 : RAMB4_S1_S1 port map (
|
367 |
|
|
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
|
368 |
|
|
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
|
369 |
|
|
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
|
370 |
|
|
enable1, enable2, gnd, gnd, write1, write2);
|
371 |
|
|
end generate;
|
372 |
|
|
end generate;
|
373 |
|
|
|
374 |
|
|
-- pragma translate_off
|
375 |
|
|
a_to_high : if abits > 12 generate
|
376 |
|
|
x : process
|
377 |
|
|
begin
|
378 |
|
|
assert false
|
379 |
|
|
report "Address depth larger than 12 not supported for virtex_syncram_dp"
|
380 |
|
|
severity failure;
|
381 |
|
|
wait;
|
382 |
|
|
end process;
|
383 |
|
|
end generate;
|
384 |
|
|
-- pragma translate_on
|
385 |
|
|
|
386 |
|
|
end;
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
-- parametrisable sync ram generator using virtex2 select rams
|
390 |
|
|
|
391 |
|
|
library ieee;
|
392 |
|
|
use ieee.std_logic_1164.all;
|
393 |
|
|
--pragma translate_off
|
394 |
|
|
library unisim;
|
395 |
|
|
use unisim.RAMB16_S36_S36;
|
396 |
|
|
use unisim.RAMB16_S36;
|
397 |
|
|
use unisim.RAMB16_S18;
|
398 |
|
|
use unisim.RAMB16_S9;
|
399 |
|
|
use unisim.RAMB16_S4;
|
400 |
|
|
use unisim.RAMB16_S2;
|
401 |
|
|
use unisim.RAMB16_S1;
|
402 |
|
|
--pragma translate_on
|
403 |
|
|
|
404 |
|
|
entity virtex2_syncram is
|
405 |
|
|
generic ( abits : integer := 9; dbits : integer := 32);
|
406 |
|
|
port (
|
407 |
|
|
clk : in std_ulogic;
|
408 |
|
|
address : in std_logic_vector (abits -1 downto 0);
|
409 |
|
|
datain : in std_logic_vector (dbits -1 downto 0);
|
410 |
|
|
dataout : out std_logic_vector (dbits -1 downto 0);
|
411 |
|
|
enable : in std_ulogic;
|
412 |
|
|
write : in std_ulogic
|
413 |
|
|
);
|
414 |
|
|
end;
|
415 |
|
|
|
416 |
|
|
architecture behav of virtex2_syncram is
|
417 |
|
|
component RAMB16_S36_S36
|
418 |
|
|
port (
|
419 |
|
|
DOA : out std_logic_vector (31 downto 0);
|
420 |
|
|
DOB : out std_logic_vector (31 downto 0);
|
421 |
|
|
DOPA : out std_logic_vector (3 downto 0);
|
422 |
|
|
DOPB : out std_logic_vector (3 downto 0);
|
423 |
|
|
ADDRA : in std_logic_vector (8 downto 0);
|
424 |
|
|
ADDRB : in std_logic_vector (8 downto 0);
|
425 |
|
|
CLKA : in std_ulogic;
|
426 |
|
|
CLKB : in std_ulogic;
|
427 |
|
|
DIA : in std_logic_vector (31 downto 0);
|
428 |
|
|
DIB : in std_logic_vector (31 downto 0);
|
429 |
|
|
DIPA : in std_logic_vector (3 downto 0);
|
430 |
|
|
DIPB : in std_logic_vector (3 downto 0);
|
431 |
|
|
ENA : in std_ulogic;
|
432 |
|
|
ENB : in std_ulogic;
|
433 |
|
|
SSRA : in std_ulogic;
|
434 |
|
|
SSRB : in std_ulogic;
|
435 |
|
|
WEA : in std_ulogic;
|
436 |
|
|
WEB : in std_ulogic);
|
437 |
|
|
end component;
|
438 |
|
|
|
439 |
|
|
component RAMB16_S1
|
440 |
|
|
port (
|
441 |
|
|
DO : out std_logic_vector (0 downto 0);
|
442 |
|
|
ADDR : in std_logic_vector (13 downto 0);
|
443 |
|
|
CLK : in std_ulogic;
|
444 |
|
|
DI : in std_logic_vector (0 downto 0);
|
445 |
|
|
EN : in std_ulogic;
|
446 |
|
|
SSR : in std_ulogic;
|
447 |
|
|
WE : in std_ulogic
|
448 |
|
|
);
|
449 |
|
|
end component;
|
450 |
|
|
|
451 |
|
|
component RAMB16_S2
|
452 |
|
|
port (
|
453 |
|
|
DO : out std_logic_vector (1 downto 0);
|
454 |
|
|
ADDR : in std_logic_vector (12 downto 0);
|
455 |
|
|
CLK : in std_ulogic;
|
456 |
|
|
DI : in std_logic_vector (1 downto 0);
|
457 |
|
|
EN : in std_ulogic;
|
458 |
|
|
SSR : in std_ulogic;
|
459 |
|
|
WE : in std_ulogic
|
460 |
|
|
);
|
461 |
|
|
end component;
|
462 |
|
|
|
463 |
|
|
component RAMB16_S4
|
464 |
|
|
port (
|
465 |
|
|
DO : out std_logic_vector (3 downto 0);
|
466 |
|
|
ADDR : in std_logic_vector (11 downto 0);
|
467 |
|
|
CLK : in std_ulogic;
|
468 |
|
|
DI : in std_logic_vector (3 downto 0);
|
469 |
|
|
EN : in std_ulogic;
|
470 |
|
|
SSR : in std_ulogic;
|
471 |
|
|
WE : in std_ulogic
|
472 |
|
|
);
|
473 |
|
|
end component;
|
474 |
|
|
|
475 |
|
|
component RAMB16_S9
|
476 |
|
|
port (
|
477 |
|
|
DO : out std_logic_vector (7 downto 0);
|
478 |
|
|
DOP : out std_logic_vector (0 downto 0);
|
479 |
|
|
ADDR : in std_logic_vector (10 downto 0);
|
480 |
|
|
CLK : in std_ulogic;
|
481 |
|
|
DI : in std_logic_vector (7 downto 0);
|
482 |
|
|
DIP : in std_logic_vector (0 downto 0);
|
483 |
|
|
EN : in std_ulogic;
|
484 |
|
|
SSR : in std_ulogic;
|
485 |
|
|
WE : in std_ulogic
|
486 |
|
|
);
|
487 |
|
|
end component;
|
488 |
|
|
|
489 |
|
|
component RAMB16_S18
|
490 |
|
|
port (
|
491 |
|
|
DO : out std_logic_vector (15 downto 0);
|
492 |
|
|
DOP : out std_logic_vector (1 downto 0);
|
493 |
|
|
ADDR : in std_logic_vector (9 downto 0);
|
494 |
|
|
CLK : in std_ulogic;
|
495 |
|
|
DI : in std_logic_vector (15 downto 0);
|
496 |
|
|
DIP : in std_logic_vector (1 downto 0);
|
497 |
|
|
EN : in std_ulogic;
|
498 |
|
|
SSR : in std_ulogic;
|
499 |
|
|
WE : in std_ulogic
|
500 |
|
|
);
|
501 |
|
|
end component;
|
502 |
|
|
|
503 |
|
|
component RAMB16_S36
|
504 |
|
|
port (
|
505 |
|
|
DO : out std_logic_vector (31 downto 0);
|
506 |
|
|
DOP : out std_logic_vector (3 downto 0);
|
507 |
|
|
ADDR : in std_logic_vector (8 downto 0);
|
508 |
|
|
CLK : in std_ulogic;
|
509 |
|
|
DI : in std_logic_vector (31 downto 0);
|
510 |
|
|
DIP : in std_logic_vector (3 downto 0);
|
511 |
|
|
EN : in std_ulogic;
|
512 |
|
|
SSR : in std_ulogic;
|
513 |
|
|
WE : in std_ulogic
|
514 |
|
|
);
|
515 |
|
|
end component;
|
516 |
|
|
|
517 |
|
|
component generic_syncram
|
518 |
|
|
generic ( abits : integer := 10; dbits : integer := 8 );
|
519 |
|
|
port (
|
520 |
|
|
clk : in std_ulogic;
|
521 |
|
|
address : in std_logic_vector((abits -1) downto 0);
|
522 |
|
|
datain : in std_logic_vector((dbits -1) downto 0);
|
523 |
|
|
dataout : out std_logic_vector((dbits -1) downto 0);
|
524 |
|
|
write : in std_ulogic);
|
525 |
|
|
end component;
|
526 |
|
|
|
527 |
|
|
signal gnd : std_ulogic;
|
528 |
|
|
signal do, di : std_logic_vector(dbits+72 downto 0);
|
529 |
|
|
signal xa, ya : std_logic_vector(19 downto 0);
|
530 |
|
|
begin
|
531 |
|
|
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
|
532 |
|
|
di(dbits+72 downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
|
533 |
|
|
xa(19 downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
|
534 |
|
|
ya(19 downto abits) <= (others => '1');
|
535 |
|
|
|
536 |
|
|
a0 : if (abits <= 5) generate
|
537 |
|
|
r0 : generic_syncram generic map (abits, dbits)
|
538 |
|
|
port map (clk, address, datain, do(dbits-1 downto 0), write);
|
539 |
|
|
do(dbits+72 downto dbits) <= (others => '0');
|
540 |
|
|
end generate;
|
541 |
|
|
|
542 |
|
|
a8 : if (abits > 5) and (abits <= 8) generate
|
543 |
|
|
x : for i in 0 to ((dbits-1)/72) generate
|
544 |
|
|
r0 : RAMB16_S36_S36 port map (
|
545 |
|
|
do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72),
|
546 |
|
|
do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32),
|
547 |
|
|
xa(8 downto 0), ya(8 downto 0), clk, clk,
|
548 |
|
|
di(i*72+36+31 downto i*72+36), di(i*72+31 downto i*72),
|
549 |
|
|
di(i*72+36+32+3 downto i*72+36+32), di(i*72+32+3 downto i*72+32),
|
550 |
|
|
enable, enable, gnd, gnd, write, write);
|
551 |
|
|
end generate;
|
552 |
|
|
do(dbits+72 downto 72*(((dbits-1)/72)+1)) <= (others => '0');
|
553 |
|
|
end generate;
|
554 |
|
|
a9 : if (abits = 9) generate
|
555 |
|
|
x : for i in 0 to ((dbits-1)/36) generate
|
556 |
|
|
r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
|
557 |
|
|
do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0), clk,
|
558 |
|
|
di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
|
559 |
|
|
enable, gnd, write);
|
560 |
|
|
end generate;
|
561 |
|
|
do(dbits+72 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
|
562 |
|
|
end generate;
|
563 |
|
|
a10 : if (abits = 10) generate
|
564 |
|
|
x : for i in 0 to ((dbits-1)/18) generate
|
565 |
|
|
r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
|
566 |
|
|
do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0), clk,
|
567 |
|
|
di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
|
568 |
|
|
enable, gnd, write);
|
569 |
|
|
end generate;
|
570 |
|
|
do(dbits+72 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
|
571 |
|
|
end generate;
|
572 |
|
|
a11 : if abits = 11 generate
|
573 |
|
|
x : for i in 0 to ((dbits-1)/9) generate
|
574 |
|
|
r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
|
575 |
|
|
do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0), clk,
|
576 |
|
|
di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
|
577 |
|
|
enable, gnd, write);
|
578 |
|
|
end generate;
|
579 |
|
|
do(dbits+72 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
|
580 |
|
|
end generate;
|
581 |
|
|
a12 : if abits = 12 generate
|
582 |
|
|
x : for i in 0 to ((dbits-1)/4) generate
|
583 |
|
|
r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
|
584 |
|
|
clk, di(((i+1)*4)-1 downto i*4), enable, gnd, write);
|
585 |
|
|
end generate;
|
586 |
|
|
do(dbits+72 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
|
587 |
|
|
end generate;
|
588 |
|
|
a13 : if abits = 13 generate
|
589 |
|
|
x : for i in 0 to ((dbits-1)/2) generate
|
590 |
|
|
r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
|
591 |
|
|
clk, di(((i+1)*2)-1 downto i*2), enable, gnd, write);
|
592 |
|
|
end generate;
|
593 |
|
|
do(dbits+72 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
|
594 |
|
|
end generate;
|
595 |
|
|
a14 : if abits = 14 generate
|
596 |
|
|
x : for i in 0 to (dbits-1) generate
|
597 |
|
|
r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
|
598 |
|
|
clk, di((i+1)-1 downto i), enable, gnd, write);
|
599 |
|
|
end generate;
|
600 |
|
|
do(dbits+72 downto dbits) <= (others => '0');
|
601 |
|
|
end generate;
|
602 |
|
|
|
603 |
|
|
a15 : if abits > 14 generate
|
604 |
|
|
x: generic_syncram generic map (abits, dbits)
|
605 |
|
|
port map (clk, address, datain, do(dbits-1 downto 0), write);
|
606 |
|
|
do(dbits+72 downto dbits) <= (others => '0');
|
607 |
|
|
end generate;
|
608 |
|
|
|
609 |
|
|
-- pragma translate_off
|
610 |
|
|
-- a_to_high : if abits > 14 generate
|
611 |
|
|
-- x : process
|
612 |
|
|
-- begin
|
613 |
|
|
-- assert false
|
614 |
|
|
-- report "Address depth larger than 14 not supported for virtex2_syncram"
|
615 |
|
|
-- severity failure;
|
616 |
|
|
-- wait;
|
617 |
|
|
-- end process;
|
618 |
|
|
-- end generate;
|
619 |
|
|
-- pragma translate_on
|
620 |
|
|
|
621 |
|
|
end;
|
622 |
|
|
|
623 |
|
|
LIBRARY ieee;
|
624 |
|
|
use ieee.std_logic_1164.all;
|
625 |
|
|
--pragma translate_off
|
626 |
|
|
library unisim;
|
627 |
|
|
use unisim.RAMB16_S36_S36;
|
628 |
|
|
use unisim.RAMB16_S18_S18;
|
629 |
|
|
use unisim.RAMB16_S9_S9;
|
630 |
|
|
use unisim.RAMB16_S4_S4;
|
631 |
|
|
use unisim.RAMB16_S2_S2;
|
632 |
|
|
use unisim.RAMB16_S1_S1;
|
633 |
|
|
--pragma translate_on
|
634 |
|
|
|
635 |
|
|
entity virtex2_syncram_dp is
|
636 |
|
|
generic (
|
637 |
|
|
abits : integer := 4; dbits : integer := 32
|
638 |
|
|
);
|
639 |
|
|
port (
|
640 |
|
|
clk1 : in std_ulogic;
|
641 |
|
|
address1 : in std_logic_vector((abits -1) downto 0);
|
642 |
|
|
datain1 : in std_logic_vector((dbits -1) downto 0);
|
643 |
|
|
dataout1 : out std_logic_vector((dbits -1) downto 0);
|
644 |
|
|
enable1 : in std_ulogic;
|
645 |
|
|
write1 : in std_ulogic;
|
646 |
|
|
clk2 : in std_ulogic;
|
647 |
|
|
address2 : in std_logic_vector((abits -1) downto 0);
|
648 |
|
|
datain2 : in std_logic_vector((dbits -1) downto 0);
|
649 |
|
|
dataout2 : out std_logic_vector((dbits -1) downto 0);
|
650 |
|
|
enable2 : in std_ulogic;
|
651 |
|
|
write2 : in std_ulogic);
|
652 |
|
|
end;
|
653 |
|
|
|
654 |
|
|
architecture behav of virtex2_syncram_dp is
|
655 |
|
|
|
656 |
|
|
component RAMB16_S4_S4
|
657 |
|
|
port (
|
658 |
|
|
DOA : out std_logic_vector (3 downto 0);
|
659 |
|
|
DOB : out std_logic_vector (3 downto 0);
|
660 |
|
|
ADDRA : in std_logic_vector (11 downto 0);
|
661 |
|
|
ADDRB : in std_logic_vector (11 downto 0);
|
662 |
|
|
CLKA : in std_ulogic;
|
663 |
|
|
CLKB : in std_ulogic;
|
664 |
|
|
DIA : in std_logic_vector (3 downto 0);
|
665 |
|
|
DIB : in std_logic_vector (3 downto 0);
|
666 |
|
|
ENA : in std_ulogic;
|
667 |
|
|
ENB : in std_ulogic;
|
668 |
|
|
SSRA : in std_ulogic;
|
669 |
|
|
SSRB : in std_ulogic;
|
670 |
|
|
WEA : in std_ulogic;
|
671 |
|
|
WEB : in std_ulogic
|
672 |
|
|
);
|
673 |
|
|
end component;
|
674 |
|
|
|
675 |
|
|
component RAMB16_S1_S1
|
676 |
|
|
port (
|
677 |
|
|
DOA : out std_logic_vector (0 downto 0);
|
678 |
|
|
DOB : out std_logic_vector (0 downto 0);
|
679 |
|
|
ADDRA : in std_logic_vector (13 downto 0);
|
680 |
|
|
ADDRB : in std_logic_vector (13 downto 0);
|
681 |
|
|
CLKA : in std_ulogic;
|
682 |
|
|
CLKB : in std_ulogic;
|
683 |
|
|
DIA : in std_logic_vector (0 downto 0);
|
684 |
|
|
DIB : in std_logic_vector (0 downto 0);
|
685 |
|
|
ENA : in std_ulogic;
|
686 |
|
|
ENB : in std_ulogic;
|
687 |
|
|
SSRA : in std_ulogic;
|
688 |
|
|
SSRB : in std_ulogic;
|
689 |
|
|
WEA : in std_ulogic;
|
690 |
|
|
WEB : in std_ulogic
|
691 |
|
|
);
|
692 |
|
|
end component;
|
693 |
|
|
|
694 |
|
|
component RAMB16_S2_S2
|
695 |
|
|
port (
|
696 |
|
|
DOA : out std_logic_vector (1 downto 0);
|
697 |
|
|
DOB : out std_logic_vector (1 downto 0);
|
698 |
|
|
ADDRA : in std_logic_vector (12 downto 0);
|
699 |
|
|
ADDRB : in std_logic_vector (12 downto 0);
|
700 |
|
|
CLKA : in std_ulogic;
|
701 |
|
|
CLKB : in std_ulogic;
|
702 |
|
|
DIA : in std_logic_vector (1 downto 0);
|
703 |
|
|
DIB : in std_logic_vector (1 downto 0);
|
704 |
|
|
ENA : in std_ulogic;
|
705 |
|
|
ENB : in std_ulogic;
|
706 |
|
|
SSRA : in std_ulogic;
|
707 |
|
|
SSRB : in std_ulogic;
|
708 |
|
|
WEA : in std_ulogic;
|
709 |
|
|
WEB : in std_ulogic
|
710 |
|
|
);
|
711 |
|
|
end component;
|
712 |
|
|
|
713 |
|
|
component RAMB16_S9_S9
|
714 |
|
|
port (
|
715 |
|
|
DOA : out std_logic_vector (7 downto 0);
|
716 |
|
|
DOB : out std_logic_vector (7 downto 0);
|
717 |
|
|
DOPA : out std_logic_vector (0 downto 0);
|
718 |
|
|
DOPB : out std_logic_vector (0 downto 0);
|
719 |
|
|
ADDRA : in std_logic_vector (10 downto 0);
|
720 |
|
|
ADDRB : in std_logic_vector (10 downto 0);
|
721 |
|
|
CLKA : in std_ulogic;
|
722 |
|
|
CLKB : in std_ulogic;
|
723 |
|
|
DIA : in std_logic_vector (7 downto 0);
|
724 |
|
|
DIB : in std_logic_vector (7 downto 0);
|
725 |
|
|
DIPA : in std_logic_vector (0 downto 0);
|
726 |
|
|
DIPB : in std_logic_vector (0 downto 0);
|
727 |
|
|
ENA : in std_ulogic;
|
728 |
|
|
ENB : in std_ulogic;
|
729 |
|
|
SSRA : in std_ulogic;
|
730 |
|
|
SSRB : in std_ulogic;
|
731 |
|
|
WEA : in std_ulogic;
|
732 |
|
|
WEB : in std_ulogic
|
733 |
|
|
);
|
734 |
|
|
end component;
|
735 |
|
|
|
736 |
|
|
component RAMB16_S18_S18
|
737 |
|
|
port (
|
738 |
|
|
DOA : out std_logic_vector (15 downto 0);
|
739 |
|
|
DOB : out std_logic_vector (15 downto 0);
|
740 |
|
|
DOPA : out std_logic_vector (1 downto 0);
|
741 |
|
|
DOPB : out std_logic_vector (1 downto 0);
|
742 |
|
|
ADDRA : in std_logic_vector (9 downto 0);
|
743 |
|
|
ADDRB : in std_logic_vector (9 downto 0);
|
744 |
|
|
CLKA : in std_ulogic;
|
745 |
|
|
CLKB : in std_ulogic;
|
746 |
|
|
DIA : in std_logic_vector (15 downto 0);
|
747 |
|
|
DIB : in std_logic_vector (15 downto 0);
|
748 |
|
|
DIPA : in std_logic_vector (1 downto 0);
|
749 |
|
|
DIPB : in std_logic_vector (1 downto 0);
|
750 |
|
|
ENA : in std_ulogic;
|
751 |
|
|
ENB : in std_ulogic;
|
752 |
|
|
SSRA : in std_ulogic;
|
753 |
|
|
SSRB : in std_ulogic;
|
754 |
|
|
WEA : in std_ulogic;
|
755 |
|
|
WEB : in std_ulogic);
|
756 |
|
|
end component;
|
757 |
|
|
|
758 |
|
|
component RAMB16_S36_S36
|
759 |
|
|
port (
|
760 |
|
|
DOA : out std_logic_vector (31 downto 0);
|
761 |
|
|
DOB : out std_logic_vector (31 downto 0);
|
762 |
|
|
DOPA : out std_logic_vector (3 downto 0);
|
763 |
|
|
DOPB : out std_logic_vector (3 downto 0);
|
764 |
|
|
ADDRA : in std_logic_vector (8 downto 0);
|
765 |
|
|
ADDRB : in std_logic_vector (8 downto 0);
|
766 |
|
|
CLKA : in std_ulogic;
|
767 |
|
|
CLKB : in std_ulogic;
|
768 |
|
|
DIA : in std_logic_vector (31 downto 0);
|
769 |
|
|
DIB : in std_logic_vector (31 downto 0);
|
770 |
|
|
DIPA : in std_logic_vector (3 downto 0);
|
771 |
|
|
DIPB : in std_logic_vector (3 downto 0);
|
772 |
|
|
ENA : in std_ulogic;
|
773 |
|
|
ENB : in std_ulogic;
|
774 |
|
|
SSRA : in std_ulogic;
|
775 |
|
|
SSRB : in std_ulogic;
|
776 |
|
|
WEA : in std_ulogic;
|
777 |
|
|
WEB : in std_ulogic);
|
778 |
|
|
end component;
|
779 |
|
|
|
780 |
|
|
signal gnd, vcc : std_ulogic;
|
781 |
|
|
signal do1, do2, di1, di2 : std_logic_vector(dbits+36 downto 0);
|
782 |
|
|
signal addr1, addr2 : std_logic_vector(19 downto 0);
|
783 |
|
|
begin
|
784 |
|
|
gnd <= '0'; vcc <= '1';
|
785 |
|
|
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
|
786 |
|
|
di1(dbits-1 downto 0) <= datain1; di1(dbits+36 downto dbits) <= (others => '0');
|
787 |
|
|
di2(dbits-1 downto 0) <= datain2; di2(dbits+36 downto dbits) <= (others => '0');
|
788 |
|
|
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
|
789 |
|
|
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
|
790 |
|
|
|
791 |
|
|
a9 : if abits <= 9 generate
|
792 |
|
|
x : for i in 0 to ((dbits-1)/36) generate
|
793 |
|
|
r0 : RAMB16_S36_S36 port map (
|
794 |
|
|
do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36),
|
795 |
|
|
do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32),
|
796 |
|
|
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
|
797 |
|
|
di1(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-5 downto i*36),
|
798 |
|
|
di1(((i+1)*36)-1 downto i*36+32), di2(((i+1)*36)-1 downto i*36+32),
|
799 |
|
|
-- enable1, enable2, gnd, gnd, write1, write2);
|
800 |
|
|
vcc, vcc, gnd, gnd, write1, write2);
|
801 |
|
|
end generate;
|
802 |
|
|
do1(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
|
803 |
|
|
do2(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
|
804 |
|
|
end generate;
|
805 |
|
|
|
806 |
|
|
a10 : if abits = 10 generate
|
807 |
|
|
x : for i in 0 to ((dbits-1)/18) generate
|
808 |
|
|
r0 : RAMB16_S18_S18 port map (
|
809 |
|
|
do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18),
|
810 |
|
|
do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16),
|
811 |
|
|
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
|
812 |
|
|
di1(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-3 downto i*18),
|
813 |
|
|
di1(((i+1)*18)-1 downto i*18+16), di2(((i+1)*18)-1 downto i*18+16),
|
814 |
|
|
vcc, vcc, gnd, gnd, write1, write2);
|
815 |
|
|
-- enable1, enable2, gnd, gnd, write1, write2);
|
816 |
|
|
end generate;
|
817 |
|
|
do1(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
|
818 |
|
|
do2(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
|
819 |
|
|
end generate;
|
820 |
|
|
|
821 |
|
|
a11 : if abits = 11 generate
|
822 |
|
|
x : for i in 0 to ((dbits-1)/9) generate
|
823 |
|
|
r0 : RAMB16_S9_S9 port map (
|
824 |
|
|
do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9),
|
825 |
|
|
do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8),
|
826 |
|
|
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
|
827 |
|
|
di1(((i+1)*9)-2 downto i*9), di2(((i+1)*9)-2 downto i*9),
|
828 |
|
|
di1(((i+1)*9)-1 downto i*9+8), di2(((i+1)*9)-1 downto i*9+8),
|
829 |
|
|
vcc, vcc, gnd, gnd, write1, write2);
|
830 |
|
|
-- enable1, enable2, gnd, gnd, write1, write2);
|
831 |
|
|
end generate;
|
832 |
|
|
do1(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
|
833 |
|
|
do2(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
|
834 |
|
|
end generate;
|
835 |
|
|
|
836 |
|
|
a12 : if abits = 12 generate
|
837 |
|
|
x : for i in 0 to ((dbits-1)/4) generate
|
838 |
|
|
r0 : RAMB16_S4_S4 port map (
|
839 |
|
|
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
|
840 |
|
|
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
|
841 |
|
|
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
|
842 |
|
|
vcc, vcc, gnd, gnd, write1, write2);
|
843 |
|
|
-- enable1, enable2, gnd, gnd, write1, write2);
|
844 |
|
|
end generate;
|
845 |
|
|
do1(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
|
846 |
|
|
do2(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
|
847 |
|
|
end generate;
|
848 |
|
|
|
849 |
|
|
a13 : if abits = 13 generate
|
850 |
|
|
x : for i in 0 to ((dbits-1)/2) generate
|
851 |
|
|
r0 : RAMB16_S2_S2 port map (
|
852 |
|
|
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
|
853 |
|
|
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
|
854 |
|
|
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
|
855 |
|
|
vcc, vcc, gnd, gnd, write1, write2);
|
856 |
|
|
-- enable1, enable2, gnd, gnd, write1, write2);
|
857 |
|
|
end generate;
|
858 |
|
|
do1(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
|
859 |
|
|
do2(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
|
860 |
|
|
end generate;
|
861 |
|
|
|
862 |
|
|
a14 : if abits = 14 generate
|
863 |
|
|
x : for i in 0 to ((dbits-1)/1) generate
|
864 |
|
|
r0 : RAMB16_S1_S1 port map (
|
865 |
|
|
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
|
866 |
|
|
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
|
867 |
|
|
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
|
868 |
|
|
vcc, vcc, gnd, gnd, write1, write2);
|
869 |
|
|
-- enable1, enable2, gnd, gnd, write1, write2);
|
870 |
|
|
end generate;
|
871 |
|
|
do1(dbits+36 downto dbits) <= (others => '0');
|
872 |
|
|
do2(dbits+36 downto dbits) <= (others => '0');
|
873 |
|
|
end generate;
|
874 |
|
|
|
875 |
|
|
-- pragma translate_off
|
876 |
|
|
a_to_high : if abits > 14 generate
|
877 |
|
|
x : process
|
878 |
|
|
begin
|
879 |
|
|
assert false
|
880 |
|
|
report "Address depth larger than 14 not supported for virtex2_syncram_dp"
|
881 |
|
|
severity failure;
|
882 |
|
|
wait;
|
883 |
|
|
end process;
|
884 |
|
|
end generate;
|
885 |
|
|
-- pragma translate_on
|
886 |
|
|
|
887 |
|
|
end;
|
888 |
|
|
|
889 |
|
|
library ieee;
|
890 |
|
|
use ieee.std_logic_1164.all;
|
891 |
|
|
|
892 |
|
|
entity virtex2_syncram_2p is
|
893 |
|
|
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
|
894 |
|
|
wrfst : integer := 0);
|
895 |
|
|
port (
|
896 |
|
|
rclk : in std_ulogic;
|
897 |
|
|
renable : in std_ulogic;
|
898 |
|
|
raddress : in std_logic_vector((abits -1) downto 0);
|
899 |
|
|
dataout : out std_logic_vector((dbits -1) downto 0);
|
900 |
|
|
wclk : in std_ulogic;
|
901 |
|
|
write : in std_ulogic;
|
902 |
|
|
waddress : in std_logic_vector((abits -1) downto 0);
|
903 |
|
|
datain : in std_logic_vector((dbits -1) downto 0));
|
904 |
|
|
end;
|
905 |
|
|
|
906 |
|
|
architecture behav of virtex2_syncram_2p is
|
907 |
|
|
|
908 |
|
|
component virtex2_syncram_dp
|
909 |
|
|
generic ( abits : integer := 10; dbits : integer := 8 );
|
910 |
|
|
port (
|
911 |
|
|
clk1 : in std_ulogic;
|
912 |
|
|
address1 : in std_logic_vector((abits -1) downto 0);
|
913 |
|
|
datain1 : in std_logic_vector((dbits -1) downto 0);
|
914 |
|
|
dataout1 : out std_logic_vector((dbits -1) downto 0);
|
915 |
|
|
enable1 : in std_ulogic;
|
916 |
|
|
write1 : in std_ulogic;
|
917 |
|
|
clk2 : in std_ulogic;
|
918 |
|
|
address2 : in std_logic_vector((abits -1) downto 0);
|
919 |
|
|
datain2 : in std_logic_vector((dbits -1) downto 0);
|
920 |
|
|
dataout2 : out std_logic_vector((dbits -1) downto 0);
|
921 |
|
|
enable2 : in std_ulogic;
|
922 |
|
|
write2 : in std_ulogic
|
923 |
|
|
);
|
924 |
|
|
end component;
|
925 |
|
|
|
926 |
|
|
component generic_syncram_2p
|
927 |
|
|
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
|
928 |
|
|
port (
|
929 |
|
|
rclk : in std_ulogic;
|
930 |
|
|
wclk : in std_ulogic;
|
931 |
|
|
rdaddress: in std_logic_vector (abits -1 downto 0);
|
932 |
|
|
wraddress: in std_logic_vector (abits -1 downto 0);
|
933 |
|
|
data: in std_logic_vector (dbits -1 downto 0);
|
934 |
|
|
wren : in std_ulogic;
|
935 |
|
|
q: out std_logic_vector (dbits -1 downto 0)
|
936 |
|
|
);
|
937 |
|
|
end component;
|
938 |
|
|
|
939 |
|
|
signal write2, renable2 : std_ulogic;
|
940 |
|
|
signal datain2 : std_logic_vector((dbits-1) downto 0);
|
941 |
|
|
begin
|
942 |
|
|
|
943 |
|
|
nowf: if wrfst = 0 generate
|
944 |
|
|
write2 <= '0'; renable2 <= renable; datain2 <= (others => '0');
|
945 |
|
|
end generate;
|
946 |
|
|
|
947 |
|
|
wf : if wrfst = 1 generate
|
948 |
|
|
write2 <= '0' when (waddress /= raddress) else write;
|
949 |
|
|
renable2 <= renable or write2; datain2 <= datain;
|
950 |
|
|
end generate;
|
951 |
|
|
|
952 |
|
|
a0 : if abits <= 5 generate
|
953 |
|
|
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
|
954 |
|
|
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
|
955 |
|
|
end generate;
|
956 |
|
|
|
957 |
|
|
a6 : if abits > 5 generate
|
958 |
|
|
x0 : virtex2_syncram_dp generic map (abits, dbits)
|
959 |
|
|
port map (wclk, waddress, datain, open, write, write,
|
960 |
|
|
rclk, raddress, datain2, dataout, renable2, write2);
|
961 |
|
|
end generate;
|
962 |
|
|
end;
|
963 |
|
|
|
964 |
|
|
-- parametrisable sync ram generator using virtex2 block rams
|
965 |
|
|
|
966 |
|
|
library ieee;
|
967 |
|
|
use ieee.std_logic_1164.all;
|
968 |
|
|
--pragma translate_off
|
969 |
|
|
library unisim;
|
970 |
|
|
use unisim.RAMB16_S36_S36;
|
971 |
|
|
--pragma translate_on
|
972 |
|
|
|
973 |
|
|
entity virtex2_syncram64 is
|
974 |
|
|
generic ( abits : integer := 9);
|
975 |
|
|
port (
|
976 |
|
|
clk : in std_ulogic;
|
977 |
|
|
address : in std_logic_vector (abits -1 downto 0);
|
978 |
|
|
datain : in std_logic_vector (63 downto 0);
|
979 |
|
|
dataout : out std_logic_vector (63 downto 0);
|
980 |
|
|
enable : in std_logic_vector (1 downto 0);
|
981 |
|
|
write : in std_logic_vector (1 downto 0)
|
982 |
|
|
);
|
983 |
|
|
end;
|
984 |
|
|
|
985 |
|
|
architecture behav of virtex2_syncram64 is
|
986 |
|
|
component virtex2_syncram
|
987 |
|
|
generic ( abits : integer := 9; dbits : integer := 32);
|
988 |
|
|
port (
|
989 |
|
|
clk : in std_ulogic;
|
990 |
|
|
address : in std_logic_vector (abits -1 downto 0);
|
991 |
|
|
datain : in std_logic_vector (dbits -1 downto 0);
|
992 |
|
|
dataout : out std_logic_vector (dbits -1 downto 0);
|
993 |
|
|
enable : in std_ulogic;
|
994 |
|
|
write : in std_ulogic
|
995 |
|
|
);
|
996 |
|
|
end component;
|
997 |
|
|
component RAMB16_S36_S36
|
998 |
|
|
port (
|
999 |
|
|
DOA : out std_logic_vector (31 downto 0);
|
1000 |
|
|
DOB : out std_logic_vector (31 downto 0);
|
1001 |
|
|
DOPA : out std_logic_vector (3 downto 0);
|
1002 |
|
|
DOPB : out std_logic_vector (3 downto 0);
|
1003 |
|
|
ADDRA : in std_logic_vector (8 downto 0);
|
1004 |
|
|
ADDRB : in std_logic_vector (8 downto 0);
|
1005 |
|
|
CLKA : in std_ulogic;
|
1006 |
|
|
CLKB : in std_ulogic;
|
1007 |
|
|
DIA : in std_logic_vector (31 downto 0);
|
1008 |
|
|
DIB : in std_logic_vector (31 downto 0);
|
1009 |
|
|
DIPA : in std_logic_vector (3 downto 0);
|
1010 |
|
|
DIPB : in std_logic_vector (3 downto 0);
|
1011 |
|
|
ENA : in std_ulogic;
|
1012 |
|
|
ENB : in std_ulogic;
|
1013 |
|
|
SSRA : in std_ulogic;
|
1014 |
|
|
SSRB : in std_ulogic;
|
1015 |
|
|
WEA : in std_ulogic;
|
1016 |
|
|
WEB : in std_ulogic);
|
1017 |
|
|
end component;
|
1018 |
|
|
|
1019 |
|
|
signal gnd : std_logic_vector(3 downto 0);
|
1020 |
|
|
signal xa, ya : std_logic_vector(19 downto 0);
|
1021 |
|
|
begin
|
1022 |
|
|
|
1023 |
|
|
gnd <= "0000";
|
1024 |
|
|
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
|
1025 |
|
|
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
|
1026 |
|
|
|
1027 |
|
|
a8 : if abits <= 8 generate
|
1028 |
|
|
r0 : RAMB16_S36_S36 port map (
|
1029 |
|
|
dataout(63 downto 32), dataout(31 downto 0), open, open,
|
1030 |
|
|
xa(8 downto 0), ya(8 downto 0), clk, clk,
|
1031 |
|
|
datain(63 downto 32), datain(31 downto 0), gnd, gnd,
|
1032 |
|
|
enable(1), enable(0), gnd(0), gnd(0), write(1), write(0));
|
1033 |
|
|
end generate;
|
1034 |
|
|
a9 : if abits > 8 generate
|
1035 |
|
|
x1 : virtex2_syncram generic map ( abits, 32)
|
1036 |
|
|
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
|
1037 |
|
|
enable(1), write(1));
|
1038 |
|
|
x2 : virtex2_syncram generic map ( abits, 32)
|
1039 |
|
|
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
|
1040 |
|
|
enable(0), write(0));
|
1041 |
|
|
end generate;
|
1042 |
|
|
end;
|