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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [unisim/] [pads_unisim.vhd] - Blame information for rev 2

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1 2 dimamali 
------------------------------------------------------------------------------
2 
--  This file is a part of the GRLIB VHDL IP LIBRARY
3 
--  Copyright (C) 2003, Gaisler Research
4 
--
5 
--  This program is free software; you can redistribute it and/or modify
6 
--  it under the terms of the GNU General Public License as published by
7 
--  the Free Software Foundation; either version 2 of the License, or
8 
--  (at your option) any later version.
9 
--
10 
--  This program is distributed in the hope that it will be useful,
11 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
--  GNU General Public License for more details.
14 
--
15 
--  You should have received a copy of the GNU General Public License
16 
--  along with this program; if not, write to the Free Software
17 
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18 
-----------------------------------------------------------------------------
19 
-- Package:     pad_xilinx_gen
20 
-- File:        pad_xilinx_gen.vhd
21 
-- Author:      Jiri Gaisler - Gaisler Research
22 
-- Description: Xilinx pads wrappers
23 
------------------------------------------------------------------------------
24 
 
25 
library ieee;
26 
use ieee.std_logic_1164.all;
27 
library techmap;
28 
use techmap.gencomp.all;
29 
-- pragma translate_off
30 
library unisim;
31 
use unisim.IBUF;
32 
-- pragma translate_on
33 
 
34 
entity virtex_inpad is
35 
  generic (level : integer := 0; voltage : integer := x33v);
36 
  port (pad : in std_ulogic; o : out std_ulogic);
37 
end;
38 
architecture rtl of virtex_inpad is
39 
  component IBUF generic(
40 
      CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
41 
    port (O : out std_ulogic; I : in std_ulogic); end component;
42 
begin
43 
  pci0 : if level = pci33 generate
44 
    pci_5 : if voltage = x50v generate
45 
      ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
46 
    end generate;
47 
    pci_3 : if voltage /= x50v generate
48 
      ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
49 
    end generate;
50 
  end generate;
51 
  ttl0 : if level = ttl generate
52 
    ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
53 
  end generate;
54 
  cmos0 : if level = cmos generate
55 
    cmos_33 : if voltage = x33v generate
56 
      ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
57 
    end generate;
58 
    cmos_25 : if voltage /= x33v generate
59 
      ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
60 
    end generate;
61 
  end generate;
62 
  sstl2x : if level = sstl2_i generate
63 
    ip : IBUF generic map (IOSTANDARD => "SSTL2_I") port map (O => o, I => pad);
64 
  end generate;
65 
  sstl2y : if level = sstl2_ii generate
66 
    ip : IBUF generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
67 
  end generate;
68 
  gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos)
69 
        and (level /= sstl2_i)and (level /= sstl2_ii) generate
70 
    ip : IBUF port map (O => o, I => pad);
71 
  end generate;
72 
end;
73 
 
74 
library ieee;
75 
use ieee.std_logic_1164.all;
76 
library techmap;
77 
use techmap.gencomp.all;
78 
-- pragma translate_off
79 
library unisim;
80 
use unisim.IOBUF;
81 
-- pragma translate_on
82 
 
83 
entity virtex_iopad  is
84 
  generic (level : integer := 0; slew : integer := 0;
85 
           voltage : integer := x33v; strength : integer := 12);
86 
  port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
87 
end ;
88 
architecture rtl of virtex_iopad is
89 
  component IOBUF generic (
90 
      CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
91 
      IOSTANDARD  : string := "LVCMOS25"; SLEW : string := "SLOW");
92 
    port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
93 
begin
94 
  pci0 : if level = pci33 generate
95 
    pci_5 : if voltage = x50v generate
96 
      op : IOBUF generic map (IOSTANDARD => "PCI33_5")
97 
                 port map (O => o, IO => pad, I => i, T => en);
98 
    end generate;
99 
    pci_3 : if voltage /= x50v generate
100 
      op : IOBUF generic map (IOSTANDARD => "PCI33_3")
101 
                 port map (O => o, IO => pad, I => i, T => en);
102 
    end generate;
103 
  end generate;
104 
  ttl0 : if level = ttl generate
105 
    slow0 : if slew = 0 generate
106 
      op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
107 
                 port map (O => o, IO => pad, I => i, T => en);
108 
    end generate;
109 
    fast0 : if slew /= 0 generate
110 
      op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
111 
                 port map (O => o, IO => pad, I => i, T => en);
112 
    end generate;
113 
  end generate;
114 
  cmos0 : if level = cmos generate
115 
    slow0 : if slew = 0 generate
116 
      op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
117 
                 port map (O => o, IO => pad, I => i, T => en);
118 
    end generate;
119 
    fast0 : if slew /= 0 generate
120 
      op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
121 
                 port map (O => o, IO => pad, I => i, T => en);
122 
    end generate;
123 
  end generate;
124 
  sstl2x : if level = sstl2_i generate
125 
    op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
126 
                 port map (O => o, IO => pad, I => i, T => en);
127 
  end generate;
128 
  sstl2y : if level = sstl2_ii generate
129 
    op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
130 
                 port map (O => o, IO => pad, I => i, T => en);
131 
  end generate;
132 
  sstl18i : if level = sstl18_i generate
133 
    op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
134 
                 port map (O => o, IO => pad, I => i, T => en);
135 
  end generate;
136 
  sstl18ii : if level = sstl18_ii generate
137 
    op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
138 
                 port map (O => o, IO => pad, I => i, T => en);
139 
  end generate;
140 
  gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
141 
        (level /= sstl2_i) and (level /= sstl2_ii) and (level /= sstl18_i) and (level /= sstl18_ii) generate
142 
    op : IOBUF port map (O => o, IO => pad, I => i, T => en);
143 
  end generate;
144 
end;
145 
 
146 
library ieee;
147 
use ieee.std_logic_1164.all;
148 
library techmap;
149 
use techmap.gencomp.all;
150 
-- pragma translate_off
151 
library unisim;
152 
use unisim.OBUF;
153 
-- pragma translate_on
154 
 
155 
entity virtex_outpad  is
156 
  generic (level : integer := 0; slew : integer := 0;
157 
           voltage : integer := 0; strength : integer := 12);
158 
  port (pad : out std_ulogic; i : in std_ulogic);
159 
end ;
160 
architecture rtl of virtex_outpad is
161 
  component OBUF generic (
162 
      CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
163 
      IOSTANDARD  : string := "LVCMOS25"; SLEW : string := "SLOW");
164 
    port (O : out std_ulogic; I : in std_ulogic); end component;
165 
begin
166 
  pci0 : if level = pci33 generate
167 
    pci_5 : if voltage = x50v generate
168 
      op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
169 
                port map (O => pad, I => i);
170 
    end generate;
171 
    pci_3 : if voltage /= x50v generate
172 
      op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
173 
                port map (O => pad, I => i);
174 
    end generate;
175 
  end generate;
176 
  ttl0 : if level = ttl generate
177 
    slow0 : if slew = 0 generate
178 
      op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
179 
                port map (O => pad, I => i);
180 
    end generate;
181 
    fast0 : if slew /= 0 generate
182 
      op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
183 
                port map (O => pad, I => i);
184 
    end generate;
185 
  end generate;
186 
  cmos0 : if level = cmos generate
187 
    slow0 : if slew = 0 generate
188 
      op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
189 
                port map (O => pad, I => i);
190 
    end generate;
191 
    fast0 : if slew /= 0 generate
192 
      op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
193 
                port map (O => pad, I => i);
194 
    end generate;
195 
  end generate;
196 
  sstl2x : if level = sstl2_i generate
197 
      op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
198 
                port map (O => pad, I => i);
199 
  end generate;
200 
  sstl2y : if level = sstl2_ii generate
201 
      op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
202 
                port map (O => pad, I => i);
203 
  end generate;
204 
  sstl18i : if level = sstl18_i generate
205 
      op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
206 
                port map (O => pad, I => i);
207 
  end generate;
208 
  sstl18ii : if level = sstl18_ii generate
209 
      op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
210 
                port map (O => pad, I => i);
211 
  end generate;
212 
  gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
213 
        (level /= sstl2_i) and (level /= sstl2_ii) and
214 
   (level /= sstl18_i) and (level /= sstl18_ii) generate
215 
      op : OBUF port map (O => pad, I => i);
216 
  end generate;
217 
end;
218 
 
219 
library ieee;
220 
use ieee.std_logic_1164.all;
221 
library techmap;
222 
use techmap.gencomp.all;
223 
-- pragma translate_off
224 
library unisim;
225 
use unisim.OBUFT;
226 
-- pragma translate_on
227 
 
228 
entity virtex_toutpad  is
229 
  generic (level : integer := 0; slew : integer := 0;
230 
           voltage : integer := 0; strength : integer := 12);
231 
  port (pad : out std_ulogic; i, en : in std_ulogic);
232 
end ;
233 
architecture rtl of virtex_toutpad is
234 
  component OBUFT generic (
235 
      CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
236 
      IOSTANDARD  : string := "LVCMOS25"; SLEW : string := "SLOW");
237 
    port (O : out std_ulogic; I, T : in std_ulogic); end component;
238 
begin
239 
  pci0 : if level = pci33 generate
240 
    pci_5 : if voltage = x50v generate
241 
      op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_5")
242 
                 port map (O => pad, I => i, T => en);
243 
    end generate;
244 
    pci_3 : if voltage /= x50v generate
245 
      op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_3")
246 
                 port map (O => pad, I => i, T => en);
247 
    end generate;
248 
  end generate;
249 
  ttl0 : if level = ttl generate
250 
    slow0 : if slew = 0 generate
251 
      op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL")
252 
                 port map (O => pad, I => i, T => en);
253 
    end generate;
254 
    fast0 : if slew /= 0 generate
255 
      op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
256 
                 port map (O => pad, I => i, T => en);
257 
    end generate;
258 
  end generate;
259 
  cmos0 : if level = cmos generate
260 
    slow0 : if slew = 0 generate
261 
      op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33")
262 
                 port map (O => pad, I => i, T => en);
263 
    end generate;
264 
    fast0 : if slew /= 0 generate
265 
      op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
266 
                 port map (O => pad, I => i, T => en);
267 
    end generate;
268 
  end generate;
269 
  gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
270 
    op : OBUFT port map (O => pad, I => i, T => en);
271 
  end generate;
272 
end;
273 
 
274 
library ieee;
275 
use ieee.std_logic_1164.all;
276 
library techmap;
277 
use techmap.gencomp.all;
278 
-- pragma translate_off
279 
library unisim;
280 
use unisim.OBUF;
281 
use unisim.BUFG;
282 
use unisim.DCM;
283 
-- pragma translate_on
284 
 
285 
entity virtex_skew_outpad  is
286 
  generic (level : integer := 0; slew : integer := 0;
287 
           voltage : integer := 0; strength : integer := 12; skew : integer := 0);
288 
  port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
289 
        o : out std_ulogic);
290 
end ;
291 
architecture rtl of virtex_skew_outpad is
292 
  component OBUF generic (
293 
      CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
294 
      IOSTANDARD  : string := "LVCMOS25"; SLEW : string := "SLOW");
295 
    port (O : out std_ulogic; I : in std_ulogic); end component;
296 
  component DCM
297 
    generic (
298 
      CLKDV_DIVIDE : real := 2.0;
299 
      CLKFX_DIVIDE : integer := 1;
300 
      CLKFX_MULTIPLY : integer := 4;
301 
      CLKIN_DIVIDE_BY_2 : boolean := false;
302 
      CLKIN_PERIOD : real := 10.0;
303 
      CLKOUT_PHASE_SHIFT : string := "NONE";
304 
      CLK_FEEDBACK : string := "1X";
305 
      DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
306 
      DFS_FREQUENCY_MODE : string := "LOW";
307 
      DLL_FREQUENCY_MODE : string := "LOW";
308 
      DSS_MODE : string := "NONE";
309 
      DUTY_CYCLE_CORRECTION : boolean := true;
310 
      FACTORY_JF : bit_vector := X"C080";
311 
      PHASE_SHIFT : integer := 0;
312 
      STARTUP_WAIT : boolean := false
313 
    );
314 
    port (
315 
      CLKFB    : in  std_logic;
316 
      CLKIN    : in  std_logic;
317 
      DSSEN    : in  std_logic;
318 
      PSCLK    : in  std_logic;
319 
      PSEN     : in  std_logic;
320 
      PSINCDEC : in  std_logic;
321 
      RST      : in  std_logic;
322 
      CLK0     : out std_logic;
323 
      CLK90    : out std_logic;
324 
      CLK180   : out std_logic;
325 
      CLK270   : out std_logic;
326 
      CLK2X    : out std_logic;
327 
      CLK2X180 : out std_logic;
328 
      CLKDV    : out std_logic;
329 
      CLKFX    : out std_logic;
330 
      CLKFX180 : out std_logic;
331 
      LOCKED   : out std_logic;
332 
      PSDONE   : out std_logic;
333 
      STATUS   : out std_logic_vector (7 downto 0));
334 
  end component;
335 
  component BUFG port (O : out std_logic; I : in std_logic); end component;
336 
signal reset, clk0, clk0b, gnd, vcc : std_ulogic;
337 
begin
338 
  gnd <= '0'; vcc <= '1';
339 
  reset <= not rst;
340 
  dll0 : DCM
341 
    generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
342 
                 CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => skew)
343 
    port map ( CLKIN => i, CLKFB => clk0b, DSSEN => gnd, PSCLK => gnd,
344 
    PSEN => gnd, PSINCDEC => gnd, RST => reset, CLK0 => clk0);
345 
  bufg0 : BUFG port map (I => clk0, O => clk0b);
346 
 
347 
  o <= clk0b; -- output before pad
348 
 
349 
  --x0 : virtex_outpad generic map (level, slew, voltage, strength) port map (pad, clk0b);
350 
  pci0 : if level = pci33 generate
351 
    pci_5 : if voltage = x50v generate
352 
      op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
353 
                port map (O => pad, I => clk0b);
354 
    end generate;
355 
    pci_3 : if voltage /= x50v generate
356 
      op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
357 
                port map (O => pad, I => clk0b);
358 
    end generate;
359 
  end generate;
360 
  ttl0 : if level = ttl generate
361 
    slow0 : if slew = 0 generate
362 
      op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
363 
                port map (O => pad, I => clk0b);
364 
    end generate;
365 
    fast0 : if slew /= 0 generate
366 
      op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
367 
                port map (O => pad, I => clk0b);
368 
    end generate;
369 
  end generate;
370 
  cmos0 : if level = cmos generate
371 
    slow0 : if slew = 0 generate
372 
      op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
373 
                port map (O => pad, I => clk0b);
374 
    end generate;
375 
    fast0 : if slew /= 0 generate
376 
      op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
377 
                port map (O => pad, I => clk0b);
378 
    end generate;
379 
  end generate;
380 
  sstl2x : if level = sstl2_i generate
381 
      op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
382 
                port map (O => pad, I => clk0b);
383 
  end generate;
384 
  sstl2y : if level = sstl2_ii generate
385 
      op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
386 
                port map (O => pad, I => clk0b);
387 
  end generate;
388 
  sstl18i : if level = sstl18_i generate
389 
      op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
390 
                port map (O => pad, I => clk0b);
391 
  end generate;
392 
  sstl18ii : if level = sstl18_ii generate
393 
      op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
394 
                port map (O => pad, I => clk0b);
395 
  end generate;
396 
  gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
397 
        (level /= sstl2_i) and (level /= sstl2_ii) and
398 
   (level /= sstl18_i) and (level /= sstl18_ii) generate
399 
      op : OBUF port map (O => pad, I => clk0b);
400 
  end generate;
401 
end;
402 
 
403 
library ieee;
404 
use ieee.std_logic_1164.all;
405 
library techmap;
406 
use techmap.gencomp.all;
407 
-- pragma translate_off
408 
library unisim;
409 
use unisim.IBUFG;
410 
use unisim.IBUF;
411 
use unisim.BUFGMUX;
412 
use unisim.BUFG;
413 
-- pragma translate_on
414 
 
415 
entity virtex_clkpad is
416 
  generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
417 
  port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1'; lock : out std_ulogic);
418 
end;
419 
architecture rtl of virtex_clkpad is
420 
  component IBUFG  generic(
421 
      CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
422 
    port (O : out std_logic; I : in std_logic); end component;
423 
  component IBUF generic(
424 
      CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
425 
    port (O : out std_ulogic; I : in std_ulogic); end component;
426 
  component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
427 
  component BUFG port (O : out std_logic; I : in std_logic); end component;
428 
  component CLKDLL port ( CLK0    : out std_ulogic; CLK180  : out std_ulogic; CLK270  : out std_ulogic;
429 
      CLK2X   : out std_ulogic; CLK90   : out std_ulogic;  CLKDV   : out std_ulogic;
430 
      LOCKED  : out std_ulogic; CLKFB   : in  std_ulogic;   CLKIN   : in  std_ulogic;
431 
      RST     : in  std_ulogic);
432 
  end component;
433 
  component CLKDLLHF port ( CLK0   : out std_ulogic; CLK180 : out std_ulogic; CLKDV  : out std_ulogic;
434 
      LOCKED : out std_ulogic; CLKFB  : in std_ulogic; CLKIN  : in std_ulogic; RST   : in std_ulogic);
435 
  end component;
436 
  signal gnd, ol, ol2, ol3 : std_ulogic;
437 
  signal rst : std_ulogic;
438 
begin
439 
  gnd <= '0'; rst <= not rstn;
440 
  g0 : if arch = 0 generate
441 
    pci0 : if level = pci33 generate
442 
      pci_5 : if voltage = x50v generate
443 
        ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
444 
      end generate;
445 
      pci_3 : if voltage /= x50v generate
446 
        ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
447 
      end generate;
448 
    end generate;
449 
    ttl0 : if level = ttl generate
450 
      ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
451 
    end generate;
452 
    cmos0 : if level = cmos generate
453 
          cmos_33 : if voltage = x33v generate
454 
        ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
455 
      end generate;
456 
      cmos_25 : if voltage /= x33v generate
457 
        ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
458 
      end generate;
459 
    end generate;
460 
    sstl2 : if level = sstl2_ii generate
461 
      ip : IBUFG generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
462 
    end generate;
463 
    gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and (level /= sstl2_ii) generate
464 
      ip : IBUFG port map (O => o, I => pad);
465 
    end generate;
466 
    lock <= '1';
467 
  end generate;
468 
  g1 : if arch = 1 generate
469 
    pci0 : if level = pci33 generate
470 
      pci_5 : if voltage = x50v generate
471 
        ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
472 
        bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
473 
      end generate;
474 
      pci_3 : if voltage /= x50v generate
475 
        ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
476 
        bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
477 
      end generate;
478 
    end generate;
479 
    ttl0 : if level = ttl generate
480 
      ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
481 
      bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
482 
    end generate;
483 
    cmos0 : if level = cmos generate
484 
      ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
485 
      bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
486 
    end generate;
487 
    gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
488 
      ip : IBUF port map (O => ol, I => pad);
489 
      bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
490 
    end generate;
491 
    lock <= '1';
492 
  end generate;
493 
  g2 : if arch = 2 generate
494 
    pci0 : if level = pci33 generate
495 
      pci_5 : if voltage = x50v generate
496 
        ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
497 
        bf : BUFG port map (O => o, I => ol);
498 
      end generate;
499 
      pci_3 : if voltage /= x50v generate
500 
        ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
501 
        bf : BUFG port map (O => o, I => ol);
502 
      end generate;
503 
    end generate;
504 
    ttl0 : if level = ttl generate
505 
      ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
506 
      bf : BUFG port map (O => o, I => ol);
507 
    end generate;
508 
    cmos0 : if level = cmos generate
509 
      ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
510 
      bf : BUFG port map (O => o, I => ol);
511 
    end generate;
512 
    gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
513 
      ip : IBUFG port map (O => ol, I => pad);
514 
      bf : BUFG port map (O => o, I => ol);
515 
    end generate;
516 
    lock <= '1';
517 
  end generate;
518 
  g3 : if arch = 3 generate
519 
    ip : IBUFG port map (O => ol, I => pad);
520 
    hf0 : if hf = 0 generate
521 
      dll: CLKDLL port map(
522 
        CLK0 => ol2,
523 
        CLK180 => open,
524 
        CLK270 => open,
525 
        CLK2X  => open,
526 
        CLK90  => open,
527 
        CLKDV  => open,
528 
        LOCKED => lock,
529 
        CLKFB  => ol3,
530 
        CLKIN  => ol,
531 
        RST    => rst);
532 
    end generate;
533 
    hf1 : if hf = 1 generate
534 
      dll : CLKDLLHF
535 
        port map(
536 
          CLK0 => ol2,
537 
          CLK180 => open,
538 
          CLKDV => open,
539 
          LOCKED => lock,
540 
          CLKFB  => ol3,
541 
          CLKIN  => ol,
542 
          RST    => rst);
543 
    end generate;
544 
    bf : BUFG port map (O => ol3, I => ol2);
545 
    o <= ol3;
546 
  end generate g3;
547 
end;
548 
 
549 
library ieee;
550 
use ieee.std_logic_1164.all;
551 
library techmap;
552 
use techmap.gencomp.all;
553 
-- pragma translate_off
554 
library unisim;
555 
use unisim.OBUFDS_LVDS_25;
556 
use unisim.OBUFDS_LVDS_33;
557 
-- pragma translate_on
558 
 
559 
entity virtex_outpad_ds  is
560 
  generic (level : integer := lvds; voltage : integer := x33v);
561 
  port (padp, padn : out std_ulogic; i : in std_ulogic);
562 
end ;
563 
architecture rtl of virtex_outpad_ds is
564 
  component OBUFDS_LVDS_25
565 
     port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
566 
  end component;
567 
  component OBUFDS_LVDS_33
568 
     port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
569 
  end component;
570 
begin
571 
  xlvds : if level = lvds generate
572 
    lvds_33 : if voltage = x33v generate
573 
      op : OBUFDS_LVDS_33 port map (O => padp, OB => padn, I => i);
574 
    end generate;
575 
    lvds_25 : if voltage /= x33v generate
576 
      op : OBUFDS_LVDS_25 port map (O => padp, OB => padn, I => i);
577 
    end generate;
578 
  end generate;
579 
end;
580 
 
581 
library ieee;
582 
use ieee.std_logic_1164.all;
583 
library techmap;
584 
use techmap.gencomp.all;
585 
-- pragma translate_off
586 
library unisim;
587 
use unisim.IBUFDS_LVDS_25;
588 
use unisim.IBUFDS_LVDS_33;
589 
-- pragma translate_on
590 
 
591 
entity virtex_inpad_ds is
592 
  generic (level : integer := lvds; voltage : integer := x33v);
593 
  port (padp, padn : in std_ulogic; o : out std_ulogic);
594 
end;
595 
 
596 
architecture rtl of virtex_inpad_ds is
597 
  component IBUFDS_LVDS_25
598 
     port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
599 
  end component;
600 
  component IBUFDS_LVDS_33
601 
     port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
602 
  end component;
603 
begin
604 
  xlvds : if level = lvds generate
605 
    lvds_33 : if voltage = x33v generate
606 
      ip : IBUFDS_LVDS_33 port map (O => o, I => padp, IB => padn);
607 
    end generate;
608 
    lvds_25 : if voltage /= x33v generate
609 
      ip : IBUFDS_LVDS_25 port map (O => o, I => padp, IB => padn);
610 
    end generate;
611 
  end generate;
612 
  beh : if level /= lvds generate
613 
    o <= padp after 1 ns;
614 
  end generate;
615 
end;
616 
 
617 
library ieee;
618 
use ieee.std_logic_1164.all;
619 
library techmap;
620 
use techmap.gencomp.all;
621 
-- pragma translate_off
622 
library unisim;
623 
use unisim.IBUFGDS_LVDS_25;
624 
use unisim.IBUFGDS_LVDS_33;
625 
-- pragma translate_on
626 
 
627 
entity virtex_clkpad_ds is
628 
  generic (level : integer := lvds; voltage : integer := x33v);
629 
  port (padp, padn : in std_ulogic; o : out std_ulogic);
630 
end;
631 
 
632 
architecture rtl of virtex_clkpad_ds is
633 
  component IBUFGDS_LVDS_25
634 
     port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
635 
  end component;
636 
  component IBUFGDS_LVDS_33
637 
     port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
638 
  end component;
639 
begin
640 
  xlvds : if level = lvds generate
641 
    lvds_33 : if voltage = x33v generate
642 
      ip : IBUFGDS_LVDS_33 port map (O => o, I => padp, IB => padn);
643 
    end generate;
644 
    lvds_25 : if voltage /= x33v generate
645 
      ip : IBUFGDS_LVDS_25 port map (O => o, I => padp, IB => padn);
646 
    end generate;
647 
  end generate;
648 
  beh : if level /= lvds generate
649 
    o <= padp after 1 ns;
650 
  end generate;
651 
end;
652 
 
653 
library ieee;
654 
use ieee.std_logic_1164.all;
655 
library techmap;
656 
use techmap.gencomp.all;
657 
-- pragma translate_off
658 
library unisim;
659 
use unisim.IBUFDS;
660 
-- pragma translate_on
661 
 
662 
entity virtex4_inpad_ds is
663 
  generic (level : integer := lvds; voltage : integer := x33v);
664 
  port (padp, padn : in std_ulogic; o : out std_ulogic);
665 
end;
666 
 
667 
architecture rtl of virtex4_inpad_ds is
668 
  component IBUFDS
669 
  generic ( CAPACITANCE : string := "DONT_CARE";
670 
        DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
671 
        IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
672 
     port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
673 
  end component;
674 
begin
675 
  xlvds : if level = lvds generate
676 
    lvds_33 : if voltage = x33v generate
677 
      ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
678 
           port map (O => o, I => padp, IB => padn);
679 
    end generate;
680 
    lvds_25 : if voltage /= x33v generate
681 
      ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
682 
           port map (O => o, I => padp, IB => padn);
683 
    end generate;
684 
  end generate;
685 
  beh : if level /= lvds generate
686 
    o <= padp after 1 ns;
687 
  end generate;
688 
end;
689 
 
690 
library ieee;
691 
use ieee.std_logic_1164.all;
692 
library techmap;
693 
use techmap.gencomp.all;
694 
-- pragma translate_off
695 
library unisim;
696 
use unisim.IBUFGDS;
697 
-- pragma translate_on
698 
 
699 
entity virtex4_clkpad_ds is
700 
  generic (level : integer := lvds; voltage : integer := x33v);
701 
  port (padp, padn : in std_ulogic; o : out std_ulogic);
702 
end;
703 
 
704 
architecture rtl of virtex4_clkpad_ds is
705 
  component IBUFGDS
706 
  generic ( CAPACITANCE : string := "DONT_CARE";
707 
        DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
708 
        IOSTANDARD : string := "DEFAULT");
709 
     port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
710 
  end component;
711 
begin
712 
  xlvds : if level = lvds generate
713 
    lvds_33 : if voltage = x33v generate
714 
      ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
715 
           port map (O => o, I => padp, IB => padn);
716 
    end generate;
717 
    lvds_25 : if voltage /= x33v generate
718 
      ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
719 
           port map (O => o, I => padp, IB => padn);
720 
    end generate;
721 
  end generate;
722 
  beh : if level /= lvds generate
723 
    o <= padp after 1 ns;
724 
  end generate;
725 
end;
726 
 
727 
library ieee;
728 
use ieee.std_logic_1164.all;
729 
library techmap;
730 
use techmap.gencomp.all;
731 
-- pragma translate_off
732 
library unisim;
733 
use unisim.IOBUFDS;
734 
-- pragma translate_on
735 
 
736 
entity virtex5_iopad_ds  is
737 
  generic (level : integer := 0; slew : integer := 0;
738 
           voltage : integer := x33v; strength : integer := 12);
739 
  port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
740 
end ;
741 
architecture rtl of virtex5_iopad_ds is
742 
  component IOBUFDS generic (
743 
      CAPACITANCE : string := "DONT_CARE"; IBUF_DELAY_VALUE : string := "0";
744 
      IOSTANDARD  : string := "DEFAULT"; IFD_DELAY_VALUE : string := "AUTO");
745 
    port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic); end component;
746 
begin
747 
      iop : IOBUFDS generic map (IOSTANDARD => "DEFAULT")
748 
                 port map (O => o, IO => padp, IOB => padn, I => i, T => en);
749 
end;
750 
 
751 
library ieee;
752 
use ieee.std_logic_1164.all;
753 
library techmap;
754 
use techmap.gencomp.all;
755 
-- pragma translate_off
756 
library unisim;
757 
use unisim.OBUFDS;
758 
-- pragma translate_on
759 
 
760 
entity virtex5_outpad_ds  is
761 
  generic (level : integer := lvds; voltage : integer := x33v);
762 
  port (padp, padn : out std_ulogic; i : in std_ulogic);
763 
end ;
764 
architecture rtl of virtex5_outpad_ds is
765 
  component OBUFDS generic( IOSTANDARD  : string := "DEFAULT");
766 
     port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
767 
  end component;
768 
begin
769 
  xlvds : if level = lvds generate
770 
    lvds_33 : if voltage = x33v generate
771 
      op : OBUFDS generic map(IOSTANDARD  => "LVDS_33")
772 
         port map (O => padp, OB => padn, I => i);
773 
    end generate;
774 
    lvds_25 : if voltage /= x33v generate
775 
      op : OBUFDS generic map(IOSTANDARD  => "LVDS_25")
776 
         port map (O => padp, OB => padn, I => i);
777 
    end generate;
778 
  end generate;
779 
  xsstl18_i : if level = sstl18_i generate
780 
      op : OBUFDS generic map(IOSTANDARD  => "SSTL18_I")
781 
         port map (O => padp, OB => padn, I => i);
782 
  end generate;
783 
  xsstl18_ii : if level = sstl18_ii generate
784 
      op : OBUFDS generic map(IOSTANDARD  => "SSTL18_II")
785 
         port map (O => padp, OB => padn, I => i);
786 
  end generate;
787 
end;

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