URL
https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
2 |
dimamali |
------------------------------------------------------------------------------
|
2 |
|
|
-- This file is a part of the GRLIB VHDL IP LIBRARY
|
3 |
|
|
-- Copyright (C) 2003, Gaisler Research
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you can redistribute it and/or modify
|
6 |
|
|
-- it under the terms of the GNU General Public License as published by
|
7 |
|
|
-- the Free Software Foundation; either version 2 of the License, or
|
8 |
|
|
-- (at your option) any later version.
|
9 |
|
|
--
|
10 |
|
|
-- This program is distributed in the hope that it will be useful,
|
11 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
|
|
-- GNU General Public License for more details.
|
14 |
|
|
--
|
15 |
|
|
-- You should have received a copy of the GNU General Public License
|
16 |
|
|
-- along with this program; if not, write to the Free Software
|
17 |
|
|
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
18 |
|
|
-----------------------------------------------------------------------------
|
19 |
|
|
-- Entity: debug
|
20 |
|
|
-- File: debug.vhd
|
21 |
|
|
-- Author: Jiri Gaisler, Gaisler Research
|
22 |
|
|
-- Description: Various debug utilities
|
23 |
|
|
------------------------------------------------------------------------------
|
24 |
|
|
|
25 |
|
|
library ieee;
|
26 |
|
|
use ieee.std_logic_1164.all;
|
27 |
|
|
library grlib;
|
28 |
|
|
use grlib.amba.all;
|
29 |
|
|
|
30 |
|
|
package debug is
|
31 |
|
|
|
32 |
|
|
component grtestmod
|
33 |
|
|
generic (halt : integer := 0);
|
34 |
|
|
port (
|
35 |
|
|
resetn : in std_ulogic;
|
36 |
|
|
clk : in std_ulogic;
|
37 |
|
|
errorn : in std_ulogic;
|
38 |
|
|
address : in std_logic_vector(21 downto 2);
|
39 |
|
|
data : inout std_logic_vector(31 downto 0);
|
40 |
|
|
iosn : in std_ulogic;
|
41 |
|
|
oen : in std_ulogic;
|
42 |
|
|
writen : in std_ulogic;
|
43 |
|
|
brdyn : out std_ulogic
|
44 |
|
|
);
|
45 |
|
|
|
46 |
|
|
end component;
|
47 |
|
|
|
48 |
|
|
|
49 |
|
|
end;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.