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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [software/] [leon3/] [apbuart.c] - Blame information for rev 2

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#include <stdio.h>
 
#define DISABLE 0x0
#define ENABLE_RX 0x1
#define ENABLE_TX 0x2
#define RX_INT 0x4
#define TX_INT 0x8
#define EVEN_PARITY 0x20
#define ODD_PARITY 0x30
#define LOOP_BACK 0x80
#define FLOW_CONTROL 0x40
#define FIFO_TX_INT 0x200
#define FIFO_RX_INT 0x400
 
/*
 * uart[0] = data
 * uart[1] = status
 * uart[2] = control
 * uart[3] = scaler
 */
 
static inline int loadmem(int addr)
{
  int tmp;
  asm volatile (" lda [%1]1, %0 "
      : "=r"(tmp)
      : "r"(addr)
    );
  return tmp;
}
 
struct uart_regs
{
   volatile int data;
   volatile int status;
   volatile int control;
   volatile int scaler;
};
 
static char test[] = "40ti94a+0ygiyu05yhap5yi4h+a+iiyxhi4k59j0q905jkoyphoptjrhia4iy0+4";
static int testsize = sizeof test / sizeof test[0];
 
int apbuart_test(int addr)
{
        struct uart_regs *uart = (struct uart_regs *) addr;
        int temp;
        int i;
        int fifosize;
 
        if (report_device(0x0100C000)) return (0);
        /* set scaler to low value to speed up simulations */
        uart->scaler = 1;
        uart->status = 0;
        uart->data = 0;
 
        /* initialize receiver holding register to prevent X in gate level simulation */
 
        uart->control = 0;
        uart->control = ENABLE_TX;
        uart->data = 0;
        uart->data = 0;
        uart->control = ENABLE_TX | ENABLE_RX;// | LOOP_BACK;
        uart->control = ENABLE_TX | ENABLE_RX | LOOP_BACK;
        for (i = 0; i < 100; i++) {
          uart->data = 0;
        }
 
        for (i = 0; i < 100; i++) {
          temp = uart->data;
        }
 
 
        /* determine fifosize */
        uart->control = ENABLE_TX;
        while( ((loadmem((int)&uart->status) >> 2) & 0x1) != 1 ) {}
        uart->control = DISABLE;
 
        fifosize = 1;
        uart->data = 0;
        while ( ((loadmem((int)&uart->status) >> 20) & 0x3F) == fifosize ) {
          fifosize++;
          uart->data = 0;
        }
        if (fifosize > 1) {
          fifosize--;
        }
 
        uart->control = ENABLE_RX | ENABLE_TX;
 
        /*set counters to 0, and status bits to reset values*/
 
        temp = loadmem((int)&uart->status);
        while( (temp & 1) || !(temp & 4) || !(temp & 2) ) {
                temp = loadmem((int)&uart->data);
                temp = loadmem((int)&uart->status);
        }
 
        temp = 0;
        uart->control = DISABLE;
        uart->status = 0;
 
 
        /*
         *  TRANSMITTER TEST
         */
 
        if(fifosize > 1) {
                if(((loadmem((int)&uart->status) & 0x80) == 1) ) {
                        /*th bit incorrect*/
                        fail( 4);
                }
        }
 
 
        uart->data = (int) test[0];
 
        if( (loadmem((int)&uart->status) & 4) == 1) {
                /*te bit incorrect*/
                fail( 1);
        }
 
        if(loadmem((int)&uart->status) & 2 == 0) {
                /*ts bit incorrect*/
                fail( 2);
        }
 
        if (fifosize > 1) {
                for(i = 1; i < fifosize; i++) {
                        uart->data = (int) test[i % testsize];
                }
 
                if(((loadmem((int)&uart->status) & 0x80) == 1) ) {
                        /*th bit incorrect*/
                        fail( 5);
                }
 
                if( ((loadmem((int)&uart->status) >> 20) & 0x3F) != fifosize ) {
                        /*tcnt error*/
                        fail( 6);
                }
 
                if ( loadmem((int)&uart->status) & 0x200 == 0) {
                        /*tf bit incorrect*/
                        fail( 7);
                }
 
 
        }
 
        /*
         *  RECEIVER TEST (WITH LOOPBACK)
         */
 
        uart->scaler = 1;
 
        if(loadmem((int)&uart->status) & 1 != 0) {
                /*dr bit incorrect*/
                fail( 7);
        }
 
        uart->control = ENABLE_TX | ENABLE_RX | LOOP_BACK;
//        uart->control = ENABLE_TX | ENABLE_RX ;
 
        i = 0;
 
        if (fifosize == 1) {
                while((loadmem((int)&uart->status) & 1) == 0) {}
        } else {
                while((loadmem((int)&uart->status) & 0x400) == 0) {}
        }
 
        if( (loadmem((int)&uart->status) & 1) == 0 ) {
                /*dr bit incorrect*/
                fail( 8);
        }
 
        if( fifosize > 1 ) {
                if( ((loadmem((int)&uart->status) >> 26) & 0x3F) != fifosize) {
                        /*rcnt error*/
                        fail( 9);
                }
 
                if( (loadmem((int)&uart->status) & 0x100) == 0) {
                        /*rhalffull error */
                        fail( 10);
                }
 
                if( (loadmem((int)&uart->status) & 0x400) == 0) {
                        /*rfull error */
                        fail( 11);
                }
        }
 
        for(i = 0; i < fifosize; i++) {
                temp = loadmem((int)&uart->data);
                if(temp != test[i % testsize] ) {
                        /*data error*/
                        fail( 12);
                }
        }
 
        if(fifosize > 1) {
                if( (loadmem((int)&uart->status) & 0x100) != 0 ) {
                        /*rhalffull error*/
                        fail( 13);
                }
 
                if( ((loadmem((int)&uart->status) >> 26) & 0x3F) != 0) {
                        /*rcnt error*/
                        fail( 14);
                }
 
 
                if( (loadmem((int)&uart->status) & 0x400) != 0) {
                        /*rfull error */
                        fail( 11);
                }
        }
 
 
        if( loadmem((int)&uart->status) & 1 != 0 ) {
                /*dr bit error*/
                fail( 12);
        }
 
        uart->control = DISABLE;
        return 0;
 
}

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [software/] [leon3/] [apbuart.c] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`#include <stdio.h>`
2
3			`#define DISABLE 0x0`
4			`#define ENABLE_RX 0x1`
5			`#define ENABLE_TX 0x2`
6			`#define RX_INT 0x4`
7			`#define TX_INT 0x8`
8			`#define EVEN_PARITY 0x20`
9			`#define ODD_PARITY 0x30`
10			`#define LOOP_BACK 0x80`
11			`#define FLOW_CONTROL 0x40`
12			`#define FIFO_TX_INT 0x200`
13			`#define FIFO_RX_INT 0x400`
14
15			`/*`
16			`* uart[0] = data`
17			`* uart[1] = status`
18			`* uart[2] = control`
19			`* uart[3] = scaler`
20			`*/`
21
22			`static inline int loadmem(int addr)`
23			`{`
24			`int tmp;`
25			`asm volatile (" lda [%1]1, %0 "`
26			`: "=r"(tmp)`
27			`: "r"(addr)`
28			`);`
29			`return tmp;`
30			`}`
31
32			`struct uart_regs`
33			`{`
34			`volatile int data;`
35			`volatile int status;`
36			`volatile int control;`
37			`volatile int scaler;`
38			`};`
39
40			`static char test[] = "40ti94a+0ygiyu05yhap5yi4h+a+iiyxhi4k59j0q905jkoyphoptjrhia4iy0+4";`
41			`static int testsize = sizeof test / sizeof test[0];`
42
43			`int apbuart_test(int addr)`
44			`{`
45			`struct uart_regs uart = (struct uart_regs ) addr;`
46			`int temp;`
47			`int i;`
48			`int fifosize;`
49
50			`if (report_device(0x0100C000)) return (0);`
51			`/* set scaler to low value to speed up simulations */`
52			`uart->scaler = 1;`
53			`uart->status = 0;`
54			`uart->data = 0;`
55
56			`/* initialize receiver holding register to prevent X in gate level simulation */`
57
58			`uart->control = 0;`
59			`uart->control = ENABLE_TX;`
60			`uart->data = 0;`
61			`uart->data = 0;`
62			`uart->control = ENABLE_TX \| ENABLE_RX;// \| LOOP_BACK;`
63			`uart->control = ENABLE_TX \| ENABLE_RX \| LOOP_BACK;`
64			`for (i = 0; i < 100; i++) {`
65			`uart->data = 0;`
66			`}`
67
68			`for (i = 0; i < 100; i++) {`
69			`temp = uart->data;`
70			`}`
71
72
73			`/* determine fifosize */`
74			`uart->control = ENABLE_TX;`
75			`while( ((loadmem((int)&uart->status) >> 2) & 0x1) != 1 ) {}`
76			`uart->control = DISABLE;`
77
78			`fifosize = 1;`
79			`uart->data = 0;`
80			`while ( ((loadmem((int)&uart->status) >> 20) & 0x3F) == fifosize ) {`
81			`fifosize++;`
82			`uart->data = 0;`
83			`}`
84			`if (fifosize > 1) {`
85			`fifosize--;`
86			`}`
87
88			`uart->control = ENABLE_RX \| ENABLE_TX;`
89
90			`/set counters to 0, and status bits to reset values/`
91
92			`temp = loadmem((int)&uart->status);`
93			`while( (temp & 1) \|\| !(temp & 4) \|\| !(temp & 2) ) {`
94			`temp = loadmem((int)&uart->data);`
95			`temp = loadmem((int)&uart->status);`
96			`}`
97
98			`temp = 0;`
99			`uart->control = DISABLE;`
100			`uart->status = 0;`
101
102
103			`/*`
104			`* TRANSMITTER TEST`
105			`*/`
106
107			`if(fifosize > 1) {`
108			`if(((loadmem((int)&uart->status) & 0x80) == 1) ) {`
109			`/th bit incorrect/`
110			`fail( 4);`
111			`}`
112			`}`
113
114
115			`uart->data = (int) test[0];`
116
117			`if( (loadmem((int)&uart->status) & 4) == 1) {`
118			`/te bit incorrect/`
119			`fail( 1);`
120			`}`
121
122			`if(loadmem((int)&uart->status) & 2 == 0) {`
123			`/ts bit incorrect/`
124			`fail( 2);`
125			`}`
126
127			`if (fifosize > 1) {`
128			`for(i = 1; i < fifosize; i++) {`
129			`uart->data = (int) test[i % testsize];`
130			`}`
131
132			`if(((loadmem((int)&uart->status) & 0x80) == 1) ) {`
133			`/th bit incorrect/`
134			`fail( 5);`
135			`}`
136
137			`if( ((loadmem((int)&uart->status) >> 20) & 0x3F) != fifosize ) {`
138			`/tcnt error/`
139			`fail( 6);`
140			`}`
141
142			`if ( loadmem((int)&uart->status) & 0x200 == 0) {`
143			`/tf bit incorrect/`
144			`fail( 7);`
145			`}`
146
147
148			`}`
149
150			`/*`
151			`* RECEIVER TEST (WITH LOOPBACK)`
152			`*/`
153
154			`uart->scaler = 1;`
155
156			`if(loadmem((int)&uart->status) & 1 != 0) {`
157			`/dr bit incorrect/`
158			`fail( 7);`
159			`}`
160
161			`uart->control = ENABLE_TX \| ENABLE_RX \| LOOP_BACK;`
162			`// uart->control = ENABLE_TX \| ENABLE_RX ;`
163
164			`i = 0;`
165
166			`if (fifosize == 1) {`
167			`while((loadmem((int)&uart->status) & 1) == 0) {}`
168			`} else {`
169			`while((loadmem((int)&uart->status) & 0x400) == 0) {}`
170			`}`
171
172			`if( (loadmem((int)&uart->status) & 1) == 0 ) {`
173			`/dr bit incorrect/`
174			`fail( 8);`
175			`}`
176
177			`if( fifosize > 1 ) {`
178			`if( ((loadmem((int)&uart->status) >> 26) & 0x3F) != fifosize) {`
179			`/rcnt error/`
180			`fail( 9);`
181			`}`
182
183			`if( (loadmem((int)&uart->status) & 0x100) == 0) {`
184			`/rhalffull error /`
185			`fail( 10);`
186			`}`
187
188			`if( (loadmem((int)&uart->status) & 0x400) == 0) {`
189			`/rfull error /`
190			`fail( 11);`
191			`}`
192			`}`
193
194			`for(i = 0; i < fifosize; i++) {`
195			`temp = loadmem((int)&uart->data);`
196			`if(temp != test[i % testsize] ) {`
197			`/data error/`
198			`fail( 12);`
199			`}`
200			`}`
201
202			`if(fifosize > 1) {`
203			`if( (loadmem((int)&uart->status) & 0x100) != 0 ) {`
204			`/rhalffull error/`
205			`fail( 13);`
206			`}`
207
208			`if( ((loadmem((int)&uart->status) >> 26) & 0x3F) != 0) {`
209			`/rcnt error/`
210			`fail( 14);`
211			`}`
212
213
214			`if( (loadmem((int)&uart->status) & 0x400) != 0) {`
215			`/rfull error /`
216			`fail( 11);`
217			`}`
218			`}`
219
220
221			`if( loadmem((int)&uart->status) & 1 != 0 ) {`
222			`/dr bit error/`
223			`fail( 12);`
224			`}`
225
226			`uart->control = DISABLE;`
227			`return 0;`
228
229			`}`