| 1 |
2 |
dimamali |
/* -------------------------------------------------------------------------- */
|
| 2 |
|
|
/* Gaisler Research AB, 2007 */
|
| 3 |
|
|
/* -------------------------------------------------------------------------- */
|
| 4 |
|
|
/* Simple self reception test for OpenCore CAN_OC Controller, with DMA */
|
| 5 |
|
|
/* -------------------------------------------------------------------------- */
|
| 6 |
|
|
|
| 7 |
|
|
//struct can_oc_basic {
|
| 8 |
|
|
// volatile unsigned char control_register; /* 0000 */
|
| 9 |
|
|
// volatile unsigned char command_register; /* 0001 */
|
| 10 |
|
|
// volatile unsigned char status_register; /* 0002 */
|
| 11 |
|
|
// volatile unsigned char interrupt_register; /* 0003 */
|
| 12 |
|
|
// volatile unsigned char acceptance_code_register; /* 0004 */
|
| 13 |
|
|
// volatile unsigned char acceptance_mask_register; /* 0005 */
|
| 14 |
|
|
// volatile unsigned char bus_timing_0_register; /* 0006 */
|
| 15 |
|
|
// volatile unsigned char bus_timing_1_register; /* 0007 */
|
| 16 |
|
|
// volatile unsigned char output_control_register; /* 0008 */
|
| 17 |
|
|
// volatile unsigned char test_register; /* 0009 */
|
| 18 |
|
|
// volatile unsigned char tb_identifier_byte_0; /* 000A */
|
| 19 |
|
|
// volatile unsigned char tb_identifier_byte_1; /* 000B */
|
| 20 |
|
|
// volatile unsigned char tb_data_byte_1; /* 000C */
|
| 21 |
|
|
// volatile unsigned char tb_data_byte_2; /* 000D */
|
| 22 |
|
|
// volatile unsigned char tb_data_byte_3; /* 000E */
|
| 23 |
|
|
// volatile unsigned char tb_data_byte_4; /* 000F */
|
| 24 |
|
|
// volatile unsigned char tb_data_byte_5; /* 0010 */
|
| 25 |
|
|
// volatile unsigned char tb_data_byte_6; /* 0011 */
|
| 26 |
|
|
// volatile unsigned char tb_data_byte_7; /* 0012 */
|
| 27 |
|
|
// volatile unsigned char tb_data_byte_8; /* 0013 */
|
| 28 |
|
|
// volatile unsigned char rb_identifier_byte_0; /* 0014 */
|
| 29 |
|
|
// volatile unsigned char rb_identifier_byte_1; /* 0015 */
|
| 30 |
|
|
// volatile unsigned char rb_data_byte_1; /* 0016 */
|
| 31 |
|
|
// volatile unsigned char rb_data_byte_2; /* 0017 */
|
| 32 |
|
|
// volatile unsigned char rb_data_byte_3; /* 0018 */
|
| 33 |
|
|
// volatile unsigned char rb_data_byte_4; /* 0019 */
|
| 34 |
|
|
// volatile unsigned char rb_data_byte_5; /* 001A */
|
| 35 |
|
|
// volatile unsigned char rb_data_byte_6; /* 001B */
|
| 36 |
|
|
// volatile unsigned char rb_data_byte_7; /* 001C */
|
| 37 |
|
|
// volatile unsigned char rb_data_byte_8; /* 001D */
|
| 38 |
|
|
// volatile unsigned char extra_register; /* 001E */
|
| 39 |
|
|
// volatile unsigned char clock_divider_register; /* 001F */
|
| 40 |
|
|
//};
|
| 41 |
|
|
|
| 42 |
|
|
struct can_oc_extended {
|
| 43 |
|
|
volatile unsigned char control_register; /* 0000 */
|
| 44 |
|
|
volatile unsigned char command_register; /* 0001 */
|
| 45 |
|
|
volatile unsigned char status_register; /* 0002 */
|
| 46 |
|
|
volatile unsigned char interrupt_register; /* 0003 */
|
| 47 |
|
|
volatile unsigned char interrupt_enable_register; /* 0004 */
|
| 48 |
|
|
volatile unsigned char reserved_register; /* 0005 */
|
| 49 |
|
|
volatile unsigned char bus_timing_0_register; /* 0006 */
|
| 50 |
|
|
volatile unsigned char bus_timing_1_register; /* 0007 */
|
| 51 |
|
|
volatile unsigned char output_control_register; /* 0008 */
|
| 52 |
|
|
volatile unsigned char test_register; /* 0009 */
|
| 53 |
|
|
volatile unsigned char reserved_1_register; /* 000A */
|
| 54 |
|
|
volatile unsigned char arbitration_lost_capture; /* 000B */
|
| 55 |
|
|
volatile unsigned char error_code_capture; /* 000C */
|
| 56 |
|
|
volatile unsigned char error_warning_limit; /* 000D */
|
| 57 |
|
|
volatile unsigned char rx_error_counter; /* 000E */
|
| 58 |
|
|
volatile unsigned char tx_error_counter; /* 000F */
|
| 59 |
|
|
volatile unsigned char acceptance_code_0; /* 0010 */
|
| 60 |
|
|
volatile unsigned char acceptance_code_1; /* 0011 */
|
| 61 |
|
|
volatile unsigned char acceptance_code_2; /* 0012 */
|
| 62 |
|
|
volatile unsigned char acceptance_code_3; /* 0013 */
|
| 63 |
|
|
volatile unsigned char acceptance_mask_0; /* 0014 */
|
| 64 |
|
|
volatile unsigned char acceptance_mask_1; /* 0015 */
|
| 65 |
|
|
volatile unsigned char acceptance_mask_2; /* 0016 */
|
| 66 |
|
|
volatile unsigned char acceptance_mask_3; /* 0017 */
|
| 67 |
|
|
volatile unsigned char dummy0; /* 0018 */
|
| 68 |
|
|
volatile unsigned char dummy1; /* 0019 */
|
| 69 |
|
|
volatile unsigned char dummy2; /* 001A */
|
| 70 |
|
|
volatile unsigned char dummy3; /* 001B */
|
| 71 |
|
|
volatile unsigned char dummy4; /* 001C */
|
| 72 |
|
|
volatile unsigned char rx_message_counter; /* 001D */
|
| 73 |
|
|
volatile unsigned char rx_buffer_start_address; /* 001E */
|
| 74 |
|
|
volatile unsigned char clock_divider_register; /* 001F */
|
| 75 |
|
|
};
|
| 76 |
|
|
|
| 77 |
|
|
//struct can_oc_extended_rx_sff {
|
| 78 |
|
|
// volatile unsigned char rx_frame_information_sff; /* 0010 */
|
| 79 |
|
|
// volatile unsigned char rx_identifier_1_sff; /* 0011 */
|
| 80 |
|
|
// volatile unsigned char rx_identifier_2_sff; /* 0012 */
|
| 81 |
|
|
// volatile unsigned char rx_data_1_sff; /* 0013 */
|
| 82 |
|
|
// volatile unsigned char rx_data_2_sff; /* 0014 */
|
| 83 |
|
|
// volatile unsigned char rx_data_3_sff; /* 0015 */
|
| 84 |
|
|
// volatile unsigned char rx_data_4_sff; /* 0016 */
|
| 85 |
|
|
// volatile unsigned char rx_data_5_sff; /* 0017 */
|
| 86 |
|
|
// volatile unsigned char rx_data_6_sff; /* 0018 */
|
| 87 |
|
|
// volatile unsigned char rx_data_7_sff; /* 0019 */
|
| 88 |
|
|
// volatile unsigned char rx_data_8_sff; /* 001A */
|
| 89 |
|
|
//};
|
| 90 |
|
|
//
|
| 91 |
|
|
//struct can_oc_extended_rx_eff {
|
| 92 |
|
|
// volatile unsigned char rx_frame_information_eff; /* 0010 */
|
| 93 |
|
|
// volatile unsigned char rx_identifier_1_eff; /* 0011 */
|
| 94 |
|
|
// volatile unsigned char rx_identifier_2_eff; /* 0012 */
|
| 95 |
|
|
// volatile unsigned char rx_identifier_3_eff; /* 0013 */
|
| 96 |
|
|
// volatile unsigned char rx_identifier_4_eff; /* 0014 */
|
| 97 |
|
|
// volatile unsigned char rx_data_1_eff; /* 0015 */
|
| 98 |
|
|
// volatile unsigned char rx_data_2_eff; /* 0016 */
|
| 99 |
|
|
// volatile unsigned char rx_data_3_eff; /* 0017 */
|
| 100 |
|
|
// volatile unsigned char rx_data_4_eff; /* 0018 */
|
| 101 |
|
|
// volatile unsigned char rx_data_5_eff; /* 0019 */
|
| 102 |
|
|
// volatile unsigned char rx_data_6_eff; /* 001A */
|
| 103 |
|
|
// volatile unsigned char rx_data_7_eff; /* 001B */
|
| 104 |
|
|
// volatile unsigned char rx_data_8_eff; /* 001C */
|
| 105 |
|
|
//};
|
| 106 |
|
|
|
| 107 |
|
|
//struct can_oc_extended_tx_sff {
|
| 108 |
|
|
// volatile unsigned char tx_frame_information_sff; /* 0010 */
|
| 109 |
|
|
// volatile unsigned char tx_identifier_1_sff; /* 0011 */
|
| 110 |
|
|
// volatile unsigned char tx_identifier_2_sff; /* 0012 */
|
| 111 |
|
|
// volatile unsigned char tx_data_1_sff; /* 0013 */
|
| 112 |
|
|
// volatile unsigned char tx_data_2_sff; /* 0014 */
|
| 113 |
|
|
// volatile unsigned char tx_data_3_sff; /* 0015 */
|
| 114 |
|
|
// volatile unsigned char tx_data_4_sff; /* 0016 */
|
| 115 |
|
|
// volatile unsigned char tx_data_5_sff; /* 0017 */
|
| 116 |
|
|
// volatile unsigned char tx_data_6_sff; /* 0018 */
|
| 117 |
|
|
// volatile unsigned char tx_data_7_sff; /* 0019 */
|
| 118 |
|
|
// volatile unsigned char tx_data_8_sff; /* 001A */
|
| 119 |
|
|
//};
|
| 120 |
|
|
//
|
| 121 |
|
|
//struct can_oc_extended_tx_eff {
|
| 122 |
|
|
// volatile unsigned char tx_frame_information_eff; /* 0010 */
|
| 123 |
|
|
// volatile unsigned char tx_identifier_1_eff; /* 0011 */
|
| 124 |
|
|
// volatile unsigned char tx_identifier_2_eff; /* 0012 */
|
| 125 |
|
|
// volatile unsigned char tx_identifier_3_eff; /* 0013 */
|
| 126 |
|
|
// volatile unsigned char tx_identifier_4_eff; /* 0014 */
|
| 127 |
|
|
// volatile unsigned char tx_data_1_eff; /* 0015 */
|
| 128 |
|
|
// volatile unsigned char tx_data_2_eff; /* 0016 */
|
| 129 |
|
|
// volatile unsigned char tx_data_3_eff; /* 0017 */
|
| 130 |
|
|
// volatile unsigned char tx_data_4_eff; /* 0018 */
|
| 131 |
|
|
// volatile unsigned char tx_data_5_eff; /* 0019 */
|
| 132 |
|
|
// volatile unsigned char tx_data_6_eff; /* 001A */
|
| 133 |
|
|
// volatile unsigned char tx_data_7_eff; /* 001B */
|
| 134 |
|
|
// volatile unsigned char tx_data_8_eff; /* 001C */
|
| 135 |
|
|
//};
|
| 136 |
|
|
|
| 137 |
|
|
#define reset_mode_on 0x01
|
| 138 |
|
|
#define reset_mode_off 0xFE
|
| 139 |
|
|
//#define enable_all_int 0x1E
|
| 140 |
|
|
//#define tx_request 0x01
|
| 141 |
|
|
//#define basic_mode 0x7F
|
| 142 |
|
|
#define extended_mode 0x80
|
| 143 |
|
|
#define release_buffer 0x04
|
| 144 |
|
|
|
| 145 |
|
|
#define self_test_mode 0x04
|
| 146 |
|
|
#define self_reception 0x10
|
| 147 |
|
|
//#define enable_all_int_eff 0xFF
|
| 148 |
|
|
|
| 149 |
|
|
int can_oc_test(int addr)
|
| 150 |
|
|
{
|
| 151 |
|
|
struct can_oc_extended *ce = (struct can_oc_extended *) addr;
|
| 152 |
|
|
|
| 153 |
|
|
volatile unsigned char *buf = (volatile unsigned char *) (addr + 0x0010);
|
| 154 |
|
|
|
| 155 |
|
|
int tmp, i;
|
| 156 |
|
|
|
| 157 |
|
|
report_device(0x01019000);
|
| 158 |
|
|
|
| 159 |
|
|
// switch on reset mode
|
| 160 |
|
|
ce->control_register = reset_mode_on;
|
| 161 |
|
|
|
| 162 |
|
|
// switch to extended mode
|
| 163 |
|
|
ce->clock_divider_register = extended_mode;
|
| 164 |
|
|
ce->interrupt_enable_register = 0;
|
| 165 |
|
|
|
| 166 |
|
|
// set bus timing
|
| 167 |
|
|
ce->bus_timing_0_register = 0x80;
|
| 168 |
|
|
ce->bus_timing_1_register = 0x00;
|
| 169 |
|
|
|
| 170 |
|
|
// set acceptance and mask register
|
| 171 |
|
|
buf[0] = 0x05;
|
| 172 |
|
|
buf[1] = 0x06;
|
| 173 |
|
|
buf[2] = 0x07;
|
| 174 |
|
|
buf[3] = 0x08;
|
| 175 |
|
|
buf[4] = 0x70;
|
| 176 |
|
|
buf[5] = 0xe0;
|
| 177 |
|
|
buf[6] = 0xf0;
|
| 178 |
|
|
buf[7] = 0xc0;
|
| 179 |
|
|
|
| 180 |
|
|
// Setting the self test mode
|
| 181 |
|
|
ce->control_register = reset_mode_on | self_test_mode;
|
| 182 |
|
|
|
| 183 |
|
|
// Switch-off reset mode
|
| 184 |
|
|
ce->control_register = self_test_mode;
|
| 185 |
|
|
|
| 186 |
|
|
// ---------- transmit and check frame data ----------
|
| 187 |
|
|
|
| 188 |
|
|
// send first frame
|
| 189 |
|
|
// report_subtest(0);
|
| 190 |
|
|
buf[0] = 0x88;
|
| 191 |
|
|
for (tmp=1; tmp < 13; tmp++)
|
| 192 |
|
|
buf[tmp] = (unsigned char) ((tmp+4 + 16*tmp*0) & 0xFF);
|
| 193 |
|
|
ce->command_register = self_reception;
|
| 194 |
|
|
|
| 195 |
|
|
while (!ce->rx_message_counter);
|
| 196 |
|
|
|
| 197 |
|
|
for (i=1; i < 5; i++) {
|
| 198 |
|
|
// send frame
|
| 199 |
|
|
// report_subtest(i);
|
| 200 |
|
|
buf[0] = 0x88;
|
| 201 |
|
|
for (tmp=1; tmp < 13; tmp++)
|
| 202 |
|
|
buf[tmp] = (unsigned char) ((tmp+4 + 16*tmp*i) & 0xFF);
|
| 203 |
|
|
ce->command_register = self_reception;
|
| 204 |
|
|
|
| 205 |
|
|
// check frame
|
| 206 |
|
|
// report_subtest(10+i-1);
|
| 207 |
|
|
if (buf[0] != 0x88) fail(0);
|
| 208 |
|
|
for (tmp=1; tmp < 13; tmp++)
|
| 209 |
|
|
if (buf[tmp] != (unsigned char) ((tmp+4 + 16*tmp*(i-1)) & 0xFF)) fail (tmp);
|
| 210 |
|
|
ce->command_register = release_buffer;
|
| 211 |
|
|
|
| 212 |
|
|
while (!ce->rx_message_counter);
|
| 213 |
|
|
}
|
| 214 |
|
|
|
| 215 |
|
|
// check last frame
|
| 216 |
|
|
// report_subtest(10+4);
|
| 217 |
|
|
if (buf[0] != 0x88) fail(0);
|
| 218 |
|
|
for (tmp=1; tmp < 13; tmp++)
|
| 219 |
|
|
if (buf[tmp] != (unsigned char) ((tmp+4 + 16*tmp*(4)) & 0xFF)) fail (tmp);
|
| 220 |
|
|
ce->command_register = release_buffer;
|
| 221 |
|
|
|
| 222 |
|
|
ce->control_register = reset_mode_on;
|
| 223 |
|
|
}
|
