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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [software/] [leon3/] [grcan.c] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
 
2 
grcan_test(int paddr)
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   {
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   // start of test
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   report_device(0x0103D000);
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   // can register structures
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   struct grcan_ctrl {
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      volatile unsigned long conf;           /* 0x000 */
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      volatile unsigned long stat;           /* 0x004 */
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      volatile unsigned long ctrl;           /* 0x008 */
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      volatile unsigned long dummy0c;        /* 0x00C */
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      volatile unsigned long dummy10;        /* 0x010 */
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      volatile unsigned long dummy14;        /* 0x014 */
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      volatile unsigned long smask;          /* 0x018 */
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      volatile unsigned long scode;          /* 0x01C */
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   };
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   struct grcan_irq {
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      volatile unsigned long pimsr;          /* 0x100 */
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      volatile unsigned long pimr;           /* 0x104 */
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      volatile unsigned long pisr;           /* 0x108 */
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      volatile unsigned long pir;            /* 0x10C */
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      volatile unsigned long imr;            /* 0x110 */
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      volatile unsigned long picr;           /* 0x114 */
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   };
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   struct grcan_tx {
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      volatile unsigned long ctrl;           /* 0x200 */
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      volatile unsigned long addr;           /* 0x204 */
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      volatile unsigned long size;           /* 0x208 */
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      volatile unsigned long wr;             /* 0x20C */
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      volatile unsigned long rd;             /* 0x210 */
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      volatile unsigned long irq;            /* 0x214 */
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   };
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//   struct grcan_rx {
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//      volatile unsigned long ctrl;           /* 0x300 */
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//      volatile unsigned long addr;           /* 0x304 */
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//      volatile unsigned long size;           /* 0x308 */
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//      volatile unsigned long wr;             /* 0x30C */
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//      volatile unsigned long rd;             /* 0x310 */
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//      volatile unsigned long irq;            /* 0x314 */
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//      volatile unsigned long mask;           /* 0x318 */
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//      volatile unsigned long code;           /* 0x31C */
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//   };
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   // local registers
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   struct grcan_ctrl *lctrl = (struct grcan_ctrl *) (paddr);
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   struct grcan_irq  *lirq =  (struct grcan_irq *)  (paddr+0x100);
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   struct grcan_tx   *ltx0 =  (struct grcan_tx *)   (paddr+0x200);
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//   struct grcan_rx   *lrx0 =  (struct grcan_rx *)   (paddr+0x300);
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   // transmit and receive memory, allocate 2k memory
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   volatile long int memory[512];
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   // search for start of allocated memory
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   long int memorytxbase;
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   memorytxbase = (long int)&memory[0];
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   // search for 1k boundary within allocated memory, store as base
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   memorytxbase = memorytxbase & 0xFFFFFC00;
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   memorytxbase = memorytxbase + 0x400;
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   // baud rate configuration
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   int SCALER = 0;
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   int PS1 = 2;
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   int PS2 = 2;
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   int RSJ = 1;
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   int BPR = 0;
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   int SELECTION = 0;
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   int ENABLE = 0x1;
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   // setup transmit memory
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//   report_subtest(0x1);
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   // set temporary pointer to base memory start
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   volatile int *memorytx;
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   memorytx = (int*)memorytxbase;
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   *memorytx = 0x913579BD;
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   memorytx++;
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   *memorytx = 0x80000000;
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   memorytx++;
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   *memorytx = 0x01020304;
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   memorytx++;
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   *memorytx = 0x05060708;
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   memorytx++;
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   // reset controller, setup baud rate, clear int erupts, enable codec
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//   report_subtest(0x2);
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   lctrl->ctrl = 0x00000002;
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   lctrl->conf = (SCALER<<24) | (PS1<<20) | (PS2<<16) | (RSJ<<12) | (BPR<<8) | (SELECTION<<3) | (ENABLE<<1);
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   lirq->picr  = 0xFFFFFFFF;
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//   lirq->imr   = 0x00000540;
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   lctrl->ctrl = 0x00000001;
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   // transmit messages test
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//   report_subtest(0x3);
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   ltx0->addr   = memorytxbase;
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   ltx0->size   = 0x00000080;
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//   ltx0->wr     = 0x00000000;
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//   ltx0->rd     = 0x00000000;
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   ltx0->irq    = 0x00000010; // number of packets
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   ltx0->ctrl   = 0x00000001;
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   // send message
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   ltx0->wr     = 0x00000010; // number of packets
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   // wait for four messages being sent
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   while ((ltx0->rd & 0xFFFF) != 0x0010) ;
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   // check status
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//   report_subtest(0x4);
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   if (lctrl->stat != 0x00000000) fail(1);
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   if (lirq->pir != 0x00000540) fail(2);
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   // clear interrupt
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   lirq->picr  = 0xFFFFFFFF;
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   // reset controller, setup baud rate, clear int erupts, enable codec
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   SELECTION = 1;
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   ENABLE = 2;
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   lctrl->ctrl = 0x00000002;
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   lctrl->conf = (SCALER<<24) | (PS1<<20) | (PS2<<16) | (RSJ<<12) | (BPR<<8) | (SELECTION<<3) | (ENABLE<<1);
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   lirq->picr  = 0xFFFFFFFF;
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//   lirq->imr   = 0x00000540;
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   lctrl->ctrl = 0x00000001;
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   // transmit messages test
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//   report_subtest(0x5);
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   ltx0->addr   = memorytxbase;
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   ltx0->size   = 0x00000080;
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//   ltx0->wr     = 0x00000000;
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//   ltx0->rd     = 0x00000000;
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   ltx0->irq    = 0x00000010; // number of packets
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   ltx0->ctrl   = 0x00000001;
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   // send message
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   ltx0->wr     = 0x00000010; // number of packets
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   // wait for four messages being sent
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   while ((ltx0->rd & 0xFFFF) != 0x0010) ;
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   // check status
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//   report_subtest(0x6);
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   if (lctrl->stat != 0x00000000) fail(3);
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   if (lirq->pir != 0x00000540) fail(4);
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   // clear interrupt
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   lirq->picr  = 0xFFFFFFFF;
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   // reset core
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   lctrl->ctrl = 0x00000002;
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}

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