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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [software/] [leon3/] [grfpu_test.c] - Blame information for rev 2

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1 2 dimamali 
/**********************************************************************/
2 
/*  This file is a part of the GRFPU IP core testbench                */
3 
/*  Copyright (C) 2004-2008  Gaisler Research AB                      */
4 
/*  ALL RIGHTS RESERVED                                               */
5 
/*                                                                    */
6 
/**********************************************************************/
7 
 
8 
 
9 
#include "testmod.h"
10 
 
11 
#define FTT_CEXC 0x1c01f
12 
#define FTT 0x1c000
13 
#define IEEE754EXC (1 << 14)
14 
#define UNFINEXC   (1 << 15)
15 
#define NX 1
16 
#define DZ 2
17 
#define UF 4
18 
#define OF 8
19 
#define NV 16
20 
#define EQ 0
21 
#define LT 1
22 
#define GT 2
23 
#define UN 3
24 
 
25 
typedef unsigned long long uint64;
26 
 
27 
extern void grfpu_fdivd(uint64 *a, uint64 *b, uint64 *c);
28 
extern void grfpu_ttrap();
29 
extern void divident(uint64 *a);
30 
extern void divromtst(uint64 *a, uint64 *b);
31 
extern volatile unsigned int fsr1, fq1, tfsr, grfpufq;
32 
extern unsigned int grfpu_fitos(int a);
33 
extern uint64 grfpu_fitod(int a);
34 
extern unsigned int grfpu_fdtoi(uint64 a);
35 
extern unsigned int grfpu_fstoi(unsigned int a);
36 
extern unsigned int grfpu_fdtos(uint64 a);
37 
extern uint64 grfpu_fstod(unsigned int a);
38 
extern int grfpu_fcmpd(uint64 a, uint64 b);
39 
extern int grfpu_fcmped(uint64 a, uint64 b);
40 
extern uint64 grfpu_fsubd(uint64 a, uint64 b);
41 
extern void grfpc_dpdep_tst(uint64 *a);
42 
extern void grfpc_spdep_tst(unsigned int *a);
43 
extern void grfpc_spdpdep_tst(uint64 *a);
44 
extern void initfpreg();
45 
extern int grfpc_edac_test();
46 
 
47 
struct dp3_type {
48 
  uint64 op1;
49 
  uint64 op2;
50 
  uint64 res;
51 
};
52 
 
53 
 
54 
struct sp3_type {
55 
  float op1;
56 
  float op2;
57 
  float res;
58 
};
59 
 
60 
uint64 denorm = 0x0000000000010000LL;
61 
/*
62 
uint64 zero = 0x0;
63 
uint64 pzero = 0x0;
64 
*/
65 
uint64 nzero = 0x8000000000000000LL;
66 
uint64 inf =  0xfff0000000000000LL;
67 
uint64 ninf = 0xfff0000000000000LL;
68 
uint64 pinf = 0x7ff0000000000000LL;
69 
uint64 qnan = 0x7ff8000000000000LL;
70 
unsigned int qnan_sp = 0x7fc00000;
71 
uint64 snan = 0x7ff4000000000000LL;
72 
uint64 qsnan = 0x7fffe00000000000LL;
73 
unsigned long int qsnan_sp = 0x7fff0000;
74 
 
75 
unsigned int divisor[256];
76 
unsigned int divres[512];
77 
unsigned int sqrtres[256];
78 
struct dp3_type faddd_tv[16];
79 
struct dp3_type fmuld_tv[11];
80 
unsigned int fsr;
81 
 
82 
uint64 z;
83 
unsigned int fl;
84 
 
85 
double dbl;
86 
 
87 
uint64 dpres = 0xbff8000000000000LL;
88 
uint64 spdpres = 0x3fefdff00ffc484aLL;
89 
 
90 
extern unsigned int fptrap;
91 
 
92 
 
93 
int grfpu_test()
94 
{
95 
  int i;
96 
  uint64 x, y;
97 
 
98 
  uint64 a, b, c;
99 
  uint64 zero, pzero;
100 
 
101 
  unsigned int *unfaddr, unfinst, tmp;
102 
  unsigned int *t_add;
103 
 
104 
  if (((get_asr17() >> 10) & 003) != 1) return(0);  // check if GRFPU is present
105 
 
106 
  report_subtest(GRFPU_TEST);
107 
 
108 
  x = 0x3100a4068f346c9bLL;
109 
  y = 0; zero = 0; pzero = 0;
110 
 
111 
  /* install FP trap handler */
112 
  t_add = (unsigned int *) ((get_tbr() & ~0x0fff) | 0x80);
113 
  *t_add = 0xA010000F;  /* or %o7,%g0,%l0 */
114 
  t_add++;
115 
  *t_add = (0x40000000 | (((unsigned int) (&fptrap-t_add)) ));  /* call fptrap */
116 
  t_add++;
117 
  *t_add = 0x9E100010;  /* or %l0,%g0,%o7 */
118 
 
119 
 
120 
  initfpreg();
121 
 
122 
  /* FITOS, FITOD */
123 
  set_fsr(0x0f800000); tfsr = 0;
124 
  if ((grfpu_fitod(0) != 0x0) || (tfsr != 0))  fail(11);
125 
  if ((grfpu_fitod(-6) != 0xc018000000000000LL) || (tfsr != 0)) fail(11);
126 
  if ((grfpu_fitod(20) != 0x4034000000000000LL) || (tfsr != 0)) fail(11);
127 
  if ((grfpu_fitod(98) != 0x4058800000000000LL) || (tfsr != 0)) fail(11);
128 
  if ((grfpu_fitos(5) != 0x40a00000) || (tfsr != 0)) fail(11);
129 
 
130 
  /* FSTOI, FDTOI */
131 
  set_fsr(0x0f000000);
132 
  if ((grfpu_fdtoi(0x7000000000000000LL) != 0x7fffffff) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(12);
133 
  if ((grfpu_fdtoi(0xf000000000000000LL) != 0x80000000) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(12);
134 
  tfsr = 0;
135 
  if ((grfpu_fdtoi(0x0000000000000000LL) != 0) || (tfsr != 0)) fail(12);
136 
  if ((grfpu_fdtoi(0x05100302a1000001LL) != 0) || (tfsr != 0)) fail(12);
137 
  if ((grfpu_fstoi(0x47ffffff) != 0x0001ffff) || (tfsr != 0)) fail(12);
138 
  if ((grfpu_fdtoi(qnan) != 0x7fffffff) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(12);
139 
  tfsr = 0;
140 
  if ((grfpu_fdtoi(ninf) != 0x80000000) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(12);
141 
  tfsr = 0;
142 
  if ((grfpu_fdtoi(snan) != 0x7fffffff) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(12);
143 
  tfsr = 0;
144 
  grfpu_fdtoi(denorm); if (((tfsr >> 14) & 3) != 2) fail(12);
145 
 
146 
  /* FSTOD, FDTOS */
147 
  set_fsr(0x0f000000); tfsr = 0;
148 
  if ((grfpu_fstod(0x45601234) != 0x40ac024680000000LL) || (tfsr != 0)) fail(13);
149 
  if ((grfpu_fstod(0xf00abcd1) != 0xc601579a20000000LL) || (tfsr != 0)) fail(13);
150 
  if ((grfpu_fdtos(0x47f0000000000000LL) != 0x7f800000) || ((tfsr & FTT_CEXC) != (IEEE754EXC | OF))) fail(13);
151 
  tfsr = 0;
152 
  if ((grfpu_fdtos(0x81f0043000040000LL) != 0x80000000) || ((tfsr & FTT_CEXC) != (IEEE754EXC | UF))) fail(13);
153 
  tfsr = 0;
154 
  if ((grfpu_fdtos(0x0) != 0) || (tfsr != 0)) fail(13);
155 
  if ((grfpu_fdtos(qnan) != qnan_sp) || (tfsr != 0)) fail(13);
156 
  if ((grfpu_fdtos(pinf) != 0x7f800000) || (tfsr != 0)) fail(13);
157 
  if ((grfpu_fdtos(snan) != qsnan_sp) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(13);
158 
  tfsr = 0;
159 
  grfpu_fdtos(denorm); if (((tfsr >> 14) & 3) != 2) fail(13);
160 
 
161 
  /* FMOVS, FABSS, FNEGS */
162 
  set_fsr(0x0f800000); tfsr = 0;
163 
  if ((grfpu_fmovs(0x231abcde) != 0x231abcde) || (tfsr != 0)) fail(14);
164 
  if ((grfpu_fabss(0x231abcde) != 0x231abcde) || (tfsr != 0)) fail(14);
165 
  if ((grfpu_fabss(0xa31abcde) != 0x231abcde) || (tfsr != 0)) fail(14);
166 
  if ((grfpu_fnegs(0x231abcde) != 0xa31abcde) || (tfsr != 0)) fail(14);
167 
  if ((grfpu_fnegs(0xa31abcde) != 0x231abcde) || (tfsr != 0)) fail(14);
168 
 
169 
  /* FCMPxx */
170 
  set_fsr(0x0f800000);
171 
  if ((grfpu_fcmpd(0x546f010343208541LL, 0xd46f010343208541LL) != GT) || (tfsr != 0)) fail(15);
172 
  if ((grfpu_fcmpd(0xd46f010343208541LL, 0x546f010343208541LL) != LT) || (tfsr != 0)) fail(15);
173 
  if ((grfpu_fcmpd(0x0, 0x8000000000000000LL) != EQ) || (tfsr != 0)) fail(15);
174 
  if ((grfpu_fcmpd(pinf, ninf) != GT) || (tfsr != 0)) fail(15);
175 
  if ((grfpu_fcmpd(0x546f010343208541LL, 0x546fa10343208541LL) != LT) || (tfsr != 0)) fail(15);
176 
  if ((grfpu_fcmpd(0x546fa10343208541LL, 0x546f010343208541LL) != GT) || (tfsr != 0)) fail(15);
177 
  if ((grfpu_fcmpd(0x546fa10343208541LL, qnan) != UN) || (tfsr != 0)) fail(15);
178 
  if ((grfpu_fcmpd(0x546fa10343208541LL, snan) != UN) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(15);
179 
  tfsr = 0;
180 
  if ((grfpu_fcmpd(0x546fa10343208541LL, denorm) != GT) || (tfsr != 0)) fail(15);
181 
  if ((grfpu_fcmpd(denorm, 0x546fa10343208541LL) != LT) || (tfsr != 0)) fail(15);
182 
  if ((grfpu_fcmpd(qnan, 0x546fa10343208541LL) != UN) || (tfsr != 0)) fail(15);
183 
  if ((grfpu_fcmpd(snan, 0x546fa10343208541LL) != UN) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(15);
184 
 
185 
  tfsr = 0;
186 
  if ((grfpu_fcmped(0x546f010343208541LL, 0xd46f010343208541LL) != GT) || (tfsr != 0)) fail(15);
187 
  if ((grfpu_fcmped(0xd46f010343208541LL, 0x546f010343208541LL) != LT) || (tfsr != 0)) fail(15);
188 
  if ((grfpu_fcmped(0x0, 0x8000000000000000LL) != EQ) || (tfsr != 0)) fail(15);
189 
  if ((grfpu_fcmped(pinf, ninf) != GT) || (tfsr != 0)) fail(15);
190 
  if ((grfpu_fcmped(0x546f010343208541LL, 0x546fa10343208541LL) != LT) || (tfsr != 0)) fail(15);
191 
  if ((grfpu_fcmped(0x546fa10343208541LL, 0x546f010343208541LL) != GT) || (tfsr != 0)) fail(15);
192 
  if ((grfpu_fcmped(0x546fa10343208541LL, qnan) != UN) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(15);
193 
  if ((grfpu_fcmped(0x546fa10343208541LL, snan) != UN) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(15);
194 
  tfsr = 0;
195 
  if ((grfpu_fcmped(0x546fa10343208541LL, denorm) != GT) || (tfsr != 0)) fail(15);
196 
  if ((grfpu_fcmped(denorm, 0x546fa10343208541LL) != LT) || (tfsr != 0)) fail(15);
197 
  if ((grfpu_fcmped(qnan, 0x546fa10343208541LL) != UN) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(15);
198 
  if ((grfpu_fcmped(snan, 0x546fa10343208541LL) != UN) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(15);
199 
  tfsr = 0;
200 
  if ((grfpu_fcmps(0x0123abcd, 0x12345678) != LT) || (tfsr != 0)) fail(15);
201 
  if ((grfpu_fcmpes(0x0123abcd, 0x12345678) != LT) || (tfsr != 0)) fail(15);
202 
 
203 
 
204 
 
205 
  /* FADDx, FSUBx check */
206 
  tfsr = 0;
207 
  set_fsr(0x0f000000);
208 
  grfpu_faddd(&x, &zero, &z); if ((x != z) || (tfsr != 0)) fail(16);
209 
  grfpu_faddd(&x, &inf, &z);  if ((z != inf) || (tfsr != 0)) fail(16);
210 
  grfpu_faddd(&x, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(16);
211 
  grfpu_faddd(&x, &snan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(16);
212 
  tfsr = 0;  set_fsr(0x0);
213 
  grfpu_faddd(&x, &snan, &z); if (z != qsnan) fail(16);
214 
  set_fsr(0x0f000000);
215 
  grfpu_faddd(&x, &denorm, &z); if (((tfsr >> 14) & 3) != 2) fail(16);
216 
  tfsr = 0;
217 
  grfpu_faddd(&zero, &x, &z); if ((z != x) || (tfsr != 0)) fail(16);
218 
  grfpu_faddd(&zero, &inf, &z); if ((z != inf) || (tfsr != 0)) fail(16);
219 
  grfpu_faddd(&zero, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(16);
220 
  grfpu_faddd(&zero, &snan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(16);
221 
  set_fsr(0x0);
222 
  grfpu_faddd(&zero, &snan, &z); if (z != qsnan) fail(16);
223 
  set_fsr(0x0f000000);
224 
  grfpu_faddd(&zero, &denorm, &z); if (((tfsr >> 14) & 3) != 2) fail(16);
225 
  tfsr = 0;
226 
  grfpu_faddd(&inf, &x, &z); if ((z != inf) || (tfsr != 0)) fail(16);
227 
  grfpu_faddd(&inf, &zero, &z); if ((z != inf) || (tfsr != 0)) fail(16);
228 
  grfpu_faddd(&pinf, &pinf, &z); if ((z != pinf) || (tfsr != 0)) fail(16);
229 
  grfpu_faddd(&ninf, &ninf, &z); if ((z != ninf) || (tfsr != 0)) fail(16);
230 
  grfpu_faddd(&ninf, &pinf, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(16);
231 
  set_fsr(0x0);
232 
  grfpu_faddd(&ninf, &pinf, &z); if (z != qsnan) fail(16);
233 
  set_fsr(0x0f000000); tfsr = 0;
234 
  grfpu_faddd(&pinf, &ninf, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(16);
235 
  grfpu_faddd(&inf, &denorm, &z); if (((tfsr >> 14) & 3) != 2) fail(16);
236 
  tfsr = 0;
237 
  grfpu_faddd(&qnan, &x, &z); if ((z != qnan) || (tfsr != 0)) fail(16);
238 
  grfpu_faddd(&qnan, &zero, &z); if ((z != qnan) || (tfsr != 0)) fail(16);
239 
  grfpu_faddd(&qnan, &inf, &z); if ((z != qnan) || (tfsr != 0)) fail(16);
240 
  grfpu_faddd(&qnan, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(16);
241 
  grfpu_faddd(&qnan, &snan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(16);
242 
  tfsr = 0;
243 
  grfpu_faddd(&snan, &x, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(16);
244 
  tfsr = 0;
245 
  grfpu_faddd(&snan, &zero, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(16);
246 
  tfsr = 0;
247 
  grfpu_faddd(&snan, &inf, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(16);
248 
  tfsr = 0;
249 
  grfpu_faddd(&snan, &qnan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(16);
250 
  tfsr = 0;
251 
  grfpu_faddd(&snan, &snan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(16);
252 
  tfsr = 0;
253 
  grfpu_faddd(&snan, &denorm, &z); if (((tfsr >> 14) & 3) != 2) fail(16);
254 
 
255 
  set_fsr(0x0f000000); tfsr = 0;
256 
  for (i = 0; i < 13; i++)
257 
  {
258 
    grfpu_faddd(&faddd_tv[i].op1, &faddd_tv[i].op2, &z);
259 
    if (z != *((uint64 *) &faddd_tv[i].res))  fail(16);
260 
  }
261 
  if (tfsr != 0) fail(16);
262 
  grfpu_faddd(&faddd_tv[13].op1, &faddd_tv[13].op2, &z);
263 
  if ((z != faddd_tv[13].res) || ((tfsr & FTT_CEXC) != (IEEE754EXC | OF))) fail(16);
264 
  grfpu_faddd(&faddd_tv[14].op1, &faddd_tv[14].op2, &z);
265 
  if ((z != faddd_tv[14].res) || ((tfsr & FTT_CEXC) != (IEEE754EXC | UF))) fail(16);
266 
  grfpu_faddd(&faddd_tv[15].op1, &faddd_tv[15].op2, &z);
267 
  if ((z != faddd_tv[15].res) || ((tfsr & FTT_CEXC) != (IEEE754EXC | UF))) fail(16);
268 
  tfsr = 0;
269 
  if ((grfpu_fsubd(0x4000000000000000LL, 0x3ff0000000000000LL) != 0x3ff0000000000000LL) || (tfsr != 0)) fail(16);
270 
  if ((grfpu_fsubd(0x4000000000000000LL, 0xbff0000000000000LL) != 0x4008000000000000LL) || (tfsr != 0)) fail(16);
271 
  if ((grfpu_fsubd(0xc000000000000000LL, 0x3ff0000000000000LL) != 0xc008000000000000LL) || (tfsr != 0)) fail(16);
272 
  if ((grfpu_fsubd(0xc000000000000000LL, 0xbff0000000000000LL) != 0xbff0000000000000LL) || (tfsr != 0)) fail(16);
273 
 
274 
  if ((grfpu_fadds(0x40000000, 0x3f800000) != 0x40400000) || (tfsr != 0)) fail(16);
275 
  if ((grfpu_fsubs(0x40000000, 0x3f800000) != 0x3f800000) || (tfsr != 0)) fail(16);
276 
 
277 
 
278 
  /* FDIVD check */
279 
  tfsr = 0;
280 
  grfpu_fdivd(&x, &nzero, &z); if ((z != ninf) || ((tfsr & FTT_CEXC) != (IEEE754EXC | DZ))) fail(17);
281 
  tfsr = 0;
282 
  grfpu_fdivd(&x, &pinf, &z); if ((z != pzero) || (tfsr != 0)) fail(17);
283 
  grfpu_fdivd(&x, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(17);
284 
  grfpu_fdivd(&x, &snan, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(17);
285 
  grfpu_fdivd(&x, &denorm, &z); if ((tfsr & FTT) != UNFINEXC) fail(17);
286 
  tfsr = 0;
287 
  grfpu_fdivd(&zero, &x, &z); if ((z != zero) || (tfsr != 0)) fail(17);
288 
  grfpu_fdivd(&nzero, &pzero, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(17);
289 
  tfsr = 0;
290 
  grfpu_fdivd(&nzero, &pinf, &z); if ((z != nzero) || (tfsr != 0)) fail(17);
291 
  grfpu_fdivd(&zero, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail (7);
292 
  grfpu_fdivd(&zero, &snan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(17);
293 
  tfsr = 0;
294 
  grfpu_fdivd(&zero, &denorm, &z); if ((tfsr & FTT) != UNFINEXC) fail(17);
295 
  tfsr = 0;
296 
  grfpu_fdivd(&ninf, &x, &z); if ((z != ninf) || (tfsr != 0)) fail(17);
297 
  grfpu_fdivd(&ninf, &nzero, &z); if ((z != pinf) || (tfsr != 0)) fail(17);
298 
  grfpu_fdivd(&inf, &inf, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(17);
299 
  tfsr = 0;
300 
  grfpu_fdivd(&inf, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(17);
301 
  grfpu_fdivd(&inf, &snan, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(17);
302 
  tfsr = 0;
303 
  grfpu_fdivd(&inf, &denorm, &z); if ((tfsr & FTT) != UNFINEXC) fail(17);
304 
  tfsr = 0;
305 
  grfpu_fdivd(&qnan, &x, &z); if ((z != qnan) || (tfsr != 0)) fail(17);
306 
  grfpu_fdivd(&qnan, &zero, &z); if ((z != qnan) || (tfsr != 0)) fail(17);
307 
  grfpu_fdivd(&qnan, &inf, &z); if ((z != qnan) || (tfsr != 0)) fail(17);
308 
  grfpu_fdivd(&qnan, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(17);
309 
  grfpu_fdivd(&qnan, &snan, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(17);
310 
  grfpu_fdivd(&qnan, &denorm, &z); if ((tfsr & FTT) != UNFINEXC) fail(17);
311 
  grfpu_fdivd(&snan, &x, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(17);
312 
  tfsr = 0;
313 
  grfpu_fdivd(&snan, &zero, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(17);
314 
  tfsr = 0;
315 
  grfpu_fdivd(&snan, &inf, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(17);
316 
  tfsr = 0;
317 
  grfpu_fdivd(&snan, &qnan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(17);
318 
  tfsr = 0;
319 
  grfpu_fdivd(&snan, &snan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(17);
320 
  tfsr = 0;
321 
  grfpu_fdivd(&snan, &denorm, &z); if ((tfsr & FTT) != UNFINEXC) fail(17);
322 
 
323 
  tfsr = 0; a = 0x7f000102030000b0LL; b = 0x80fa0fff008723a1LL;  /* OF */
324 
  grfpu_fdivd(&a, &b, &c); if ((c != 0xfff0000000000000LL) || ((tfsr & FTT_CEXC) != (IEEE754EXC | OF))) fail(17);
325 
  tfsr = 0; a = 0x01000102030000b0LL; b = 0x421a0fff008723a1LL;  /* UF */
326 
  grfpu_fdivd(&a, &b, &c); if ((c != 0x0) || ((tfsr & FTT_CEXC) != (IEEE754EXC | UF))) fail(17);
327 
  tfsr = 0; a = 0x001abc0000000010LL; b = 0x3ff000400a07610cLL; /* emin */
328 
  grfpu_fdivd(&a, &b, &c); if ((c != 0x001abb9500ea6b0fLL) || (tfsr != 0)) fail(17);
329 
  tfsr = 0; a = 0x001abc0000000010LL; b = 0x3fffff400a07610cLL; /* emin - 1 */
330 
  grfpu_fdivd(&a, &b, &c); if ((c != 0x0) || ((tfsr & FTT_CEXC) != (IEEE754EXC | UF))) fail(17);
331 
 
332 
 
333 
  /* FDIVS */
334 
  tfsr = 0;
335 
  if ((grfpu_fdivs(0x42200000, 0x40040000) != 0x419b26ca) || (tfsr != 0)) fail(17);
336 
  if ((grfpu_fdivs(0x46effbff, 0x31c10000) != 0x549f291e) || (tfsr != 0)) fail(17);
337 
  if ((grfpu_fdivs(0x7981f800, 0x431ffffc) != 0x75cff338) || (tfsr != 0)) fail(17);
338 
  if ((grfpu_fdivs(0x00800000, 0x3f800001) != 0x0) || ((tfsr & FTT_CEXC) != (IEEE754EXC | UF))) fail(17);
339 
 
340 
 
341 
  /* FMULD */
342 
  tfsr = 0;
343 
  grfpu_fmuld(&x, &nzero, &z); if ((z != nzero) || (tfsr != 0)) fail(18);
344 
  grfpu_fmuld(&x, &pinf, &z); if ((z != pinf) || (tfsr != 0)) fail(18);
345 
  grfpu_fmuld(&x, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(18);
346 
  grfpu_fmuld(&x, &snan, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(18);
347 
  grfpu_fmuld(&x, &denorm, &z); if ((tfsr & FTT) != UNFINEXC) fail(18);
348 
  tfsr = 0;
349 
  grfpu_fmuld(&zero, &x, &z); if ((z != zero) || (tfsr != 0)) fail(18);
350 
  grfpu_fmuld(&nzero, &ninf, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(18);
351 
  tfsr = 0;
352 
  grfpu_fmuld(&zero, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(1177);
353 
  grfpu_fmuld(&zero, &snan, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(18);
354 
  grfpu_fmuld(&zero, &denorm, &z); if ((tfsr & FTT) != UNFINEXC) fail(18);
355 
  tfsr = 0;
356 
  grfpu_fmuld(&inf, &x, &z); if ((z != inf) || (tfsr != 0)) fail(18);
357 
  grfpu_fmuld(&inf, &zero, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(18);
358 
  tfsr = 0;
359 
  grfpu_fmuld(&inf, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(18);
360 
  grfpu_fmuld(&inf, &snan, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(18);
361 
  grfpu_fmuld(&inf, &denorm, &z); if ((tfsr & FTT) != UNFINEXC) fail(18);
362 
  tfsr = 0;
363 
  grfpu_fmuld(&qnan, &x, &z); if ((z != qnan) || (tfsr != 0)) fail(18);
364 
  grfpu_fmuld(&qnan, &zero, &z); if ((z != qnan) || (tfsr != 0)) fail(18);
365 
  grfpu_fmuld(&qnan, &inf, &z); if ((z != qnan) || (tfsr != 0)) fail(18);
366 
  grfpu_fmuld(&qnan, &qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(18);
367 
  grfpu_fmuld(&qnan, &snan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(18);
368 
  tfsr = 0;
369 
  grfpu_fmuld(&snan, &x, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(18);
370 
  tfsr = 0;
371 
  grfpu_fmuld(&snan, &zero, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(18);
372 
  tfsr = 0;
373 
  grfpu_fmuld(&snan, &inf, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(18);
374 
  tfsr = 0;
375 
  grfpu_fmuld(&snan, &qnan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(18);
376 
  tfsr = 0;
377 
  grfpu_fmuld(&snan, &snan, &z); if ((tfsr & FTT_CEXC) != (IEEE754EXC | NV)) fail(18);
378 
  tfsr = 0;
379 
  grfpu_fmuld(&snan, &denorm, &z); if (((tfsr >> 14) & 3) != 2) fail(18);
380 
 
381 
 
382 
  set_fsr(0x0f000000); tfsr = 0;
383 
  for (i = 0; i < 6; i++)
384 
  {
385 
    grfpu_fmuld(&fmuld_tv[i].op1, &fmuld_tv[i].op2, &z);
386 
    if ((z != fmuld_tv[i].res) || (tfsr != 0)) fail(18);
387 
  }
388 
  grfpu_fmuld(&fmuld_tv[6].op1, &fmuld_tv[6].op2, &z); if ((z != fmuld_tv[6].res) || ((tfsr & FTT_CEXC) != (IEEE754EXC | UF))) fail(18); tfsr = 0;
389 
  grfpu_fmuld(&fmuld_tv[7].op1, &fmuld_tv[7].op2, &z); if ((z != fmuld_tv[7].res) || ((tfsr & FTT_CEXC) != (IEEE754EXC | OF))) fail(18); tfsr = 0;
390 
  grfpu_fmuld(&fmuld_tv[8].op1, &fmuld_tv[8].op2, &z); if ((z != fmuld_tv[8].res) || ((tfsr & FTT_CEXC) != (IEEE754EXC | OF))) fail(18); tfsr = 0;
391 
  grfpu_fmuld(&fmuld_tv[9].op1, &fmuld_tv[9].op2, &z); if ((z != fmuld_tv[9].res) || ((tfsr & FTT_CEXC) != (IEEE754EXC | UF))) fail(18); tfsr = 0;
392 
  grfpu_fmuld(&fmuld_tv[10].op1, &fmuld_tv[10].op2, &z); if ((z != fmuld_tv[10].res) || ((tfsr & FTT_CEXC) != (IEEE754EXC | OF))) fail(18); tfsr = 0;
393 
  if ((grfpu_fmuls(0x40400000, 0x40000000) != 0x40c00000) || (tfsr != 0)) fail(18);
394 
 
395 
 
396 
 
397 
  /* FSQRTD */
398 
  set_fsr(0x0f000000); tfsr = 0;
399 
  grfpu_sqrtd(&pzero, &z); if ((z != pzero) || (tfsr != 0)) fail(19);
400 
  grfpu_sqrtd(&nzero, &z); if ((z != nzero) || (tfsr != 0)) fail(19);
401 
  grfpu_sqrtd(&pinf, &z); if ((z != pinf) || (tfsr != 0)) fail(19);
402 
  grfpu_sqrtd(&ninf, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(19);
403 
  tfsr = 0;
404 
  grfpu_sqrtd(&snan, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(19);
405 
  tfsr = 0;
406 
  grfpu_sqrtd(&qnan, &z); if ((z != qnan) || (tfsr != 0)) fail(19);
407 
  x = 0x4030000000000000LL; y = 0xc03de00030002001LL;
408 
  grfpu_sqrtd(&x, &z); if ((z != 0x4010000000000000LL) || (tfsr != 0)) fail(19);
409 
  grfpu_sqrtd(&y, &z); if ((z != qsnan) || ((tfsr & FTT_CEXC) != (IEEE754EXC | NV))) fail(19);
410 
  grfpu_sqrtd(&denorm, &z); if (((tfsr >> 14) & 3) != 2) fail(19);
411 
 
412 
 
413 
  /* FSQRTS */
414 
  tfsr = 0;
415 
  if ((grfpu_fsqrts(0x47c80000) != 0x43a00000) || (tfsr != 0)) fail(19);
416 
 
417 
 
418 
  /* check non-IEEE mode */
419 
  set_fsr(0x00400000);
420 
  grfpu_faddd(&x, &denorm, &z); if ((z != 0x4030000000000000LL) || (tfsr != 0)) fail(20);
421 
  grfpu_fmuld(&denorm, &y, &z); if ((z != 0x8000000000000000LL) || (tfsr != 0)) fail(20);
422 
 
423 
  /* check RZ, RP, RM rounding modes */
424 
  set_fsr(0x40000000); x = 0x3ff0000000000000LL; y = 0x3ca00000100200f0LL;
425 
  grfpu_faddd(&x, &y, &z); if (z != 0x3ff0000000000000LL) fail(21);
426 
  set_fsr(0x80000000); x = 0x3ff0000000000000LL; y = 0x0050000000010001LL;
427 
  grfpu_faddd(&x, &y, &z); if (z != 0x3ff0000000000001LL) fail(21);
428 
  set_fsr(0xc0000000); x = 0xbff0000000000000LL; y = 0x8050000000010001LL;
429 
  grfpu_faddd(&x, &y, &z); if (z != 0xbff0000000000001LL) fail(21);
430 
 
431 
  set_fsr(0x40000000); x = 0x3ff0000000000000LL;
432 
  grfpu_faddd(&x, &inf, &z); if (z != inf) fail(21);
433 
  set_fsr(0x80000000); x = 0x3ff0000000000000LL; y = 0x0050000000010001LL;
434 
  grfpu_faddd(&x, &inf, &z); if (z != inf) fail(21);
435 
  set_fsr(0xc0000000); x = 0xbff0000000000000LL; y = 0x8050000000010001LL;
436 
  grfpu_faddd(&x, &inf, &z); if (z != inf) fail(21);
437 
 
438 
  set_fsr(0x40000000); x = 0x3ff0000000000001LL; y = 0x4000000000000001LL;
439 
  grfpu_fmuld(&x, &y, &z); if (z != 0x4000000000000002LL) fail(21);
440 
  set_fsr(0x80000000);
441 
  grfpu_fmuld(&x, &y, &z); if (z != 0x4000000000000003LL) fail(21);
442 
  set_fsr(0xc0000000); x = 0xbff0000000000001LL;
443 
  grfpu_fmuld(&x, &y, &z); if (z != 0xc000000000000003LL) fail(21);
444 
 
445 
  set_fsr(0x40000000); x = 0x3ffab954734ba011LL; y = 0x3ff01012bc985631LL;
446 
  grfpu_fdivd(&x, &y, &z); if (z != 0x3ffa9e96b06cd02fLL) fail(21);
447 
  set_fsr(0x80000000);
448 
  grfpu_fdivd(&x, &y, &z); if (z != 0x3ffa9e96b06cd030LL) fail(21);
449 
  set_fsr(0xc0000000); y = 0xbff01012bc985631LL;
450 
  grfpu_fdivd(&x, &y, &z); if (z != 0xbffa9e96b06cd030LL) fail(21);
451 
 
452 
  set_fsr(0x40000000); x = 0x40e0000000000000LL; y = 0x4040000000000000LL;
453 
  grfpu_fdivd(&x, &y, &z); if (z != 0x4090000000000000LL) fail(21);
454 
  set_fsr(0x80000000);
455 
  grfpu_fdivd(&x, &y, &z); if (z != 0x4090000000000000LL) fail(21);
456 
  set_fsr(0xc0000000);
457 
  grfpu_fdivd(&x, &y, &z); if (z != 0x4090000000000000LL) fail(21);
458 
 
459 
  set_fsr(0x40000000);
460 
  if ((grfpu_fdivs(0x00800000, 0x3f800001) != 0x0)) fail(21);
461 
  set_fsr(0x80000000);
462 
  if ((grfpu_fdivs(0x00800000, 0x3f800001) != 0x0)) fail(21);
463 
  set_fsr(0xc0000000);
464 
  if ((grfpu_fdivs(0x00800000, 0x3f800001) != 0x0)) fail(21);
465 
 
466 
  set_fsr(0x40000000); x = 0x3ff0000000000000LL;
467 
  grfpu_sqrtd(&x, &z); if ((z != x) || (tfsr != 0)) fail(21);
468 
  set_fsr(0x80000000);
469 
  grfpu_sqrtd(&x, &z); if ((z != x) || (tfsr != 0)) fail(21);
470 
  set_fsr(0xc0000000);
471 
  grfpu_sqrtd(&x, &z); if ((z != x) || (tfsr != 0)) fail(21);
472 
 
473 
  set_fsr(0x40000000);
474 
  if ((grfpu_fsqrts(0x3f7fffff) != 0x3f7fffff)) fail(21);
475 
  set_fsr(0x80000000);
476 
  if ((grfpu_fsqrts(0x3f7fffff) != 0x3f800000)) fail(21);
477 
  set_fsr(0xc0000000);
478 
  if ((grfpu_fsqrts(0x3f7fffff) != 0x3f7fffff)) fail(21);
479 
 
480 
 
481 
  /* check GRFPC lock logic */
482 
  set_fsr(0);
483 
  grfpc_dpdep_tst(&z); if (z != 0xbff8000000000000LL) fail(22);
484 
  grfpc_spdep_tst(&fl); if (fl != 0xbfc00000) fail(22);
485 
  grfpc_spdpdep_tst(&z); if (z != 0x3fefdff00ffc484aLL) fail(22);
486 
 
487 
  /* check unfinished FP trap */
488 
  grfpu_fdivd(&x, &denorm, &z);
489 
  if (((tfsr & ((1 << 17) - 1)) >> 14) != 2) fail(23);
490 
  /* check FP instruction in FQ */
491 
  //unfaddr = ((unsigned int *) &grfpu_fdivd) + 2; unfinst = *unfaddr;
492 
  unfaddr = ((unsigned int *) grfpu_fdivd) + 2; unfinst = *unfaddr;
493 
  if (((unsigned int) unfaddr) != grfpufq) fail(24);
494 
  if (unfinst != *(&grfpufq+1)) fail(24);
495 
  if (*(&grfpufq+2) != 0) fail(24);
496 
  if (*(&grfpufq+3) != 0) fail(24);
497 
 
498 
 
499 
 
500 
  /* look-up table test */
501 
  x = 0x3100a4068f346c9bLL; y = 0;
502 
  divident(&x);
503 
  for (i = 0 ; i < 256; i++)
504 
  {
505 
    *((unsigned int *) &y) = divisor[i];
506 
    divromtst(&y, &z);
507 
    if (z != *((uint64 *) &divres[2*i]))  fail(25);
508 
  }
509 
 
510 
  for (i = 0; i < 256; i = i + 2)
511 
  {
512 
    *((unsigned int *) &y) = divisor[i];
513 
    grfpu_sqrtd(&y, &z);
514 
    if (z != *((uint64 *) &sqrtres[i])) fail(26);
515 
  }
516 
 
517 
//  report_end();
518 
}
519 
 
520 
struct dp3_type fmuld_tv[11] = {
521 
  {0x7e71000000000000LL, 0x4160100000000000LL, 0x7fe1110000000000LL}, /* max exp, no shift */
522 
  {0x0178100000000000LL, 0x3e880000fff00000LL, 0x00120c00c073f800LL}, /* min exp - 1, shift */
523 
  {0xc1efffffc0002000LL, 0x3fb3c75d224f280fLL, 0xc1b3c75cfac08192LL}, /* inc, shift */
524 
  {0xa12fff8000001fffLL, 0x3ee0000000ff0000LL, 0xa01fff8001fe1807LL}, /* trunc */
525 
  {0x41cffffe00000020LL, 0x40303ffffffffffdLL, 0x42103ffefc00000dLL}, /* shift */
526 
  {0x3fd000003fefffffLL, 0xbfd0000010000000LL, 0xbfb000004ff0003fLL},  /* inc */
527 
  {0x0170100000000000LL, 0x3e8000011a000000LL, 0x0LL},                /* min exp - 1, no shift */
528 
  {0x7e7c000000000000LL, 0x416a100001000010LL, 0x7ff0000000000000LL}, /* max exp, shift */
529 
  {0x75012034056ac000LL, 0xfa1009091000104fLL, 0xfff0000000000000LL}, /* of */
530 
  {0x0100203040030200LL, 0x003020340000a00bLL, 0x0LL},                /* uf */
531 
  {0x7fe0001010200001LL, 0x400000000010200aLL, 0x7ff0000000000000LL} /* of (emax + 1) */
532 
};
533 
 
534 
struct dp3_type faddd_tv[16] = {
535 
  {0x4200000000000000LL, 0x400fffffffffffffLL, 0x4200000000200000LL}, /* shift, round up */
536 
  {0x420fffffffffffffLL, 0x4000000000000000LL, 0x4210000000080000LL},
537 
  {0x4200000000000001LL, 0x3eb0000000000001LL, 0x4200000000000002LL}, /* guard, sticky */
538 
  {0x420f484c0137d208LL, 0xc20e780f256007abLL, 0x41ba079b7af94ba0LL}, /* close, pos */
539 
  {0x4201484c0137d208LL, 0x420e780f256007abLL, 0x4217e02d934becdaLL}, /* close, neg */
540 
  {0x420f484c0137d208LL, 0xc21e780f256007abLL, 0xc20da7d249883d4eLL}, /* close, pos */
541 
  {0x421f484c0137d208LL, 0xc20e780f256007abLL, 0x42100c446e87ce32LL},   /* close, neg */
542 
  {0xc03340ab37120891LL, 0x0000000000000000LL, 0xc03340ab37120891LL}, /* zero */
543 
  {0x0000000000000000LL, 0xc29e7a0f236007a6LL, 0xc29e7a0f236007a6LL}, /* zero */
544 
  {0x6f3f484c0137d208LL, 0x6e2e780f256007abLL, 0x6f3f485b3d3f64b8LL},
545 
  {0x6f3f484c0137d208LL, 0xee2e780f256007abLL, 0x6f3f483cc5303f58LL},
546 
  {0x7fe2f780ab123809LL, 0x7fd0000000000000LL, 0x7feaf780ab123809LL}, /* emax, no shift */
547 
  {0x0020000000000000LL, 0x8028000000000000LL, 0x8010000000000000LL}, /* emin, no uf */
548 
  {0x7feff780ab123809LL, 0x7feff2010203a111LL, 0x7ff0000000000000LL}, /* emax, shift, of */
549 
  {0x0010000000001000LL, 0x801ffffff203a111LL, 0x8000000000000000LL}, /* emin, uf */
550 
  {0x001abcd000023809LL, 0x801abcd000000111LL, 0x0}, /* emin, uf, lz */
551 
};
552 
 
553 
 
554 
unsigned int divisor[256] = {
555 
0x65300000,
556 
0x65301000,
557 
0x65302000,
558 
0x65303000,
559 
0x65304000,
560 
0x65305000,
561 
0x65306000,
562 
0x65307000,
563 
0x65308000,
564 
0x65309000,
565 
0x6530A000,
566 
0x6530B000,
567 
0x6530C000,
568 
0x6530D000,
569 
0x6530E000,
570 
0x6530F000,
571 
0x65310000,
572 
0x65311000,
573 
0x65312000,
574 
0x65313000,
575 
0x65314000,
576 
0x65315000,
577 
0x65316000,
578 
0x65317000,
579 
0x65318000,
580 
0x65319000,
581 
0x6531A000,
582 
0x6531B000,
583 
0x6531C000,
584 
0x6531D000,
585 
0x6531E000,
586 
0x6531F000,
587 
0x65320000,
588 
0x65321000,
589 
0x65322000,
590 
0x65323000,
591 
0x65324000,
592 
0x65325000,
593 
0x65326000,
594 
0x65327000,
595 
0x65328000,
596 
0x65329000,
597 
0x6532A000,
598 
0x6532B000,
599 
0x6532C000,
600 
0x6532D000,
601 
0x6532E000,
602 
0x6532F000,
603 
0x65330000,
604 
0x65331000,
605 
0x65332000,
606 
0x65333000,
607 
0x65334000,
608 
0x65335000,
609 
0x65336000,
610 
0x65337000,
611 
0x65338000,
612 
0x65339000,
613 
0x6533A000,
614 
0x6533B000,
615 
0x6533C000,
616 
0x6533D000,
617 
0x6533E000,
618 
0x6533F000,
619 
0x65340000,
620 
0x65341000,
621 
0x65342000,
622 
0x65343000,
623 
0x65344000,
624 
0x65345000,
625 
0x65346000,
626 
0x65347000,
627 
0x65348000,
628 
0x65349000,
629 
0x6534A000,
630 
0x6534B000,
631 
0x6534C000,
632 
0x6534D000,
633 
0x6534E000,
634 
0x6534F000,
635 
0x65350000,
636 
0x65351000,
637 
0x65352000,
638 
0x65353000,
639 
0x65354000,
640 
0x65355000,
641 
0x65356000,
642 
0x65357000,
643 
0x65358000,
644 
0x65359000,
645 
0x6535A000,
646 
0x6535B000,
647 
0x6535C000,
648 
0x6535D000,
649 
0x6535E000,
650 
0x6535F000,
651 
0x65360000,
652 
0x65361000,
653 
0x65362000,
654 
0x65363000,
655 
0x65364000,
656 
0x65365000,
657 
0x65366000,
658 
0x65367000,
659 
0x65368000,
660 
0x65369000,
661 
0x6536A000,
662 
0x6536B000,
663 
0x6536C000,
664 
0x6536D000,
665 
0x6536E000,
666 
0x6536F000,
667 
0x65370000,
668 
0x65371000,
669 
0x65372000,
670 
0x65373000,
671 
0x65374000,
672 
0x65375000,
673 
0x65376000,
674 
0x65377000,
675 
0x65378000,
676 
0x65379000,
677 
0x6537A000,
678 
0x6537B000,
679 
0x6537C000,
680 
0x6537D000,
681 
0x6537E000,
682 
0x6537F000,
683 
0x65380000,
684 
0x65381000,
685 
0x65382000,
686 
0x65383000,
687 
0x65384000,
688 
0x65385000,
689 
0x65386000,
690 
0x65387000,
691 
0x65388000,
692 
0x65389000,
693 
0x6538A000,
694 
0x6538B000,
695 
0x6538C000,
696 
0x6538D000,
697 
0x6538E000,
698 
0x6538F000,
699 
0x65390000,
700 
0x65391000,
701 
0x65392000,
702 
0x65393000,
703 
0x65394000,
704 
0x65395000,
705 
0x65396000,
706 
0x65397000,
707 
0x65398000,
708 
0x65399000,
709 
0x6539A000,
710 
0x6539B000,
711 
0x6539C000,
712 
0x6539D000,
713 
0x6539E000,
714 
0x6539F000,
715 
0x653A0000,
716 
0x653A1000,
717 
0x653A2000,
718 
0x653A3000,
719 
0x653A4000,
720 
0x653A5000,
721 
0x653A6000,
722 
0x653A7000,
723 
0x653A8000,
724 
0x653A9000,
725 
0x653AA000,
726 
0x653AB000,
727 
0x653AC000,
728 
0x653AD000,
729 
0x653AE000,
730 
0x653AF000,
731 
0x653B0000,
732 
0x653B1000,
733 
0x653B2000,
734 
0x653B3000,
735 
0x653B4000,
736 
0x653B5000,
737 
0x653B6000,
738 
0x653B7000,
739 
0x653B8000,
740 
0x653B9000,
741 
0x653BA000,
742 
0x653BB000,
743 
0x653BC000,
744 
0x653BD000,
745 
0x653BE000,
746 
0x653BF000,
747 
0x653C0000,
748 
0x653C1000,
749 
0x653C2000,
750 
0x653C3000,
751 
0x653C4000,
752 
0x653C5000,
753 
0x653C6000,
754 
0x653C7000,
755 
0x653C8000,
756 
0x653C9000,
757 
0x653CA000,
758 
0x653CB000,
759 
0x653CC000,
760 
0x653CD000,
761 
0x653CE000,
762 
0x653CF000,
763 
0x653D0000,
764 
0x653D1000,
765 
0x653D2000,
766 
0x653D3000,
767 
0x653D4000,
768 
0x653D5000,
769 
0x653D6000,
770 
0x653D7000,
771 
0x653D8000,
772 
0x653D9000,
773 
0x653DA000,
774 
0x653DB000,
775 
0x653DC000,
776 
0x653DD000,
777 
0x653DE000,
778 
0x653DF000,
779 
0x653E0000,
780 
0x653E1000,
781 
0x653E2000,
782 
0x653E3000,
783 
0x653E4000,
784 
0x653E5000,
785 
0x653E6000,
786 
0x653E7000,
787 
0x653E8000,
788 
0x653E9000,
789 
0x653EA000,
790 
0x653EB000,
791 
0x653EC000,
792 
0x653ED000,
793 
0x653EE000,
794 
0x653EF000,
795 
0x653F0000,
796 
0x653F1000,
797 
0x653F2000,
798 
0x653F3000,
799 
0x653F4000,
800 
0x653F5000,
801 
0x653F6000,
802 
0x653F7000,
803 
0x653F8000,
804 
0x653F9000,
805 
0x653FA000,
806 
0x653FB000,
807 
0x653FC000,
808 
0x653FD000,
809 
0x653FE000,
810 
0x653FF000};
811 
 
812 
unsigned int divres[512] = {
813 
0x0bc0a406,
814 
0x8f346c9b,
815 
0x0bc09373,
816 
0x1c185447,
817 
0x0bc08300,
818 
0x8e183c23,
819 
0x0bc072ae,
820 
0x83a9704a,
821 
0x0bc0627c,
822 
0x9cc166ff,
823 
0x0bc0526a,
824 
0x7ace64a4,
825 
0x0bc04277,
826 
0xc0b04ada,
827 
0x0bc032a4,
828 
0x12b191a0,
829 
0x0bc022ef,
830 
0x16806950,
831 
0x0bc01358,
832 
0x73280473,
833 
0x0bc003df,
834 
0xd10a0848,
835 
0x0bbfe909,
836 
0xb3b04632,
837 
0x0bbfca8e,
838 
0x711b8e88,
839 
0x0bbfac4d,
840 
0x32d41430,
841 
0x0bbf8e45,
842 
0x53d34b1b,
843 
0x0bbf7076,
844 
0x318237ef,
845 
0x0bbf52df,
846 
0x2badf99c,
847 
0x0bbf357f,
848 
0xa47c936c,
849 
0x0bbf1857,
850 
0x0061f5eb,
851 
0x0bbefb64,
852 
0xa6154515,
853 
0x0bbedea7,
854 
0xfe865a2b,
855 
0x0bbec220,
856 
0x74d37fbc,
857 
0x0bbea5cd,
858 
0x763f6669,
859 
0x0bbe89ae,
860 
0x722750f0,
861 
0x0bbe6dc2,
862 
0xd9f97623,
863 
0x0bbe520a,
864 
0x212b976c,
865 
0x0bbe3683,
866 
0xbd31caa2,
867 
0x0bbe1b2f,
868 
0x257575ca,
869 
0x0bbe000b,
870 
0xd34c7baf,
871 
0x0bbde519,
872 
0x41f097fe,
873 
0x0bbdca56,
874 
0xee76e9d0,
875 
0x0bbdafc4,
876 
0x57c7ab73,
877 
0x0bbd9560,
878 
0xfe961669,
879 
0x0bbd7b2c,
880 
0x65587275,
881 
0x0bbd6126,
882 
0x10404ec0,
883 
0x0bbd474d,
884 
0x8532e409,
885 
0x0bbd2da2,
886 
0x4bc19edf,
887 
0x0bbd1423,
888 
0xed22d101,
889 
0x0bbcfad1,
890 
0xf42a88e4,
891 
0x0bbce1ab,
892 
0xed438e80,
893 
0x0bbcc8b1,
894 
0x66688482,
895 
0x0bbcafe1,
896 
0xef1d2d01,
897 
0x0bbc973d,
898 
0x1867d0ef,
899 
0x0bbc7ec2,
900 
0x74cac962,
901 
0x0bbc6671,
902 
0x983e29fe,
903 
0x0bbc4e4a,
904 
0x18298ba9,
905 
0x0bbc364b,
906 
0x8b5df6db,
907 
0x0bbc1e75,
908 
0x8a0fecbf,
909 
0x0bbc06c7,
910 
0xadd18e7e,
911 
0x0bbbef41,
912 
0x918ce1f6,
913 
0x0bbbd7e2,
914 
0xd17e3336,
915 
0x0bbbc0ab,
916 
0x0b2e921b,
917 
0x0bbba999,
918 
0xdd6e6b65,
919 
0x0bbb92ae,
920 
0xe8503ca7,
921 
0x0bbb7be9,
922 
0xcd236272,
923 
0x0bbb654a,
924 
0x2e6f002c,
925 
0x0bbb4ecf,
926 
0xafed00fe,
927 
0x0bbb3879,
928 
0xf685313f,
929 
0x0bbb2248,
930 
0xa8486fde,
931 
0x0bbb0c3b,
932 
0x6c6bf73b,
933 
0x0bbaf651,
934 
0xeb44bcee,
935 
0x0bbae08b,
936 
0xce42e7f1,
937 
0x0bbacae8,
938 
0xbfed5cc0,
939 
0x0bbab568,
940 
0x6bdd5edd,
941 
0x0bbaa00a,
942 
0x7eba475e,
943 
0x0bba8ace,
944 
0xa6354feb,
945 
0x0bba75b4,
946 
0x910571db,
947 
0x0bba60bb,
948 
0xeee358ef,
949 
0x0bba4be4,
950 
0x70856941,
951 
0x0bba372d,
952 
0xc79bd7fe,
953 
0x0bba2297,
954 
0xa6ccd68c,
955 
0x0bba0e21,
956 
0xc1b0cfa0,
957 
0x0bb9f9cb,
958 
0xccceb605,
959 
0x0bb9e595,
960 
0x7d98648b,
961 
0x0bb9d17e,
962 
0x8a670ee7,
963 
0x0bb9bd86,
964 
0xaa77c310,
965 
0x0bb9a9ad,
966 
0x95e7fac4,
967 
0x0bb995f3,
968 
0x05b23ce5,
969 
0x0bb98256,
970 
0xb3aace57,
971 
0x0bb96ed8,
972 
0x5a7c7206,
973 
0x0bb95b77,
974 
0xb5a537c8,
975 
0x0bb94834,
976 
0x817359cc,
977 
0x0bb9350e,
978 
0x7b02284d,
979 
0x0bb92205,
980 
0x6037032e,
981 
0x0bb90f18,
982 
0xefbe614a,
983 
0x0bb8fc48,
984 
0xe908e522,
985 
0x0bb8e995,
986 
0x0c487ea9,
987 
0x0bb8d6fd,
988 
0x1a6d99e8,
989 
0x0bb8c480,
990 
0xd5245a34,
991 
0x0bb8b21f,
992 
0xfed1e1bc,
993 
0x0bb89fda,
994 
0x5a91a526,
995 
0x0bb88daf,
996 
0xac32cb0a,
997 
0x0bb87b9f,
998 
0xb83596f6,
999 
0x0bb869aa,
1000 
0x43c8dfe1,
1001 
0x0bb857cf,
1002 
0x14c791b5,
1003 
0x0bb8460d,
1004 
0xf1b639c6,
1005 
0x0bb83466,
1006 
0xa1c09df9,
1007 
0x0bb822d8,
1008 
0xecb75e6e,
1009 
0x0bb81164,
1010 
0x9b0da16b,
1011 
0x0bb80009,
1012 
0x75d6c959,
1013 
0x0bb7eec7,
1014 
0x46c434a5,
1015 
0x0bb7dd9d,
1016 
0xd8230752,
1017 
0x0bb7cc8c,
1018 
0xf4d9fe01,
1019 
0x0bb7bb94,
1020 
0x68674a50,
1021 
0x0bb7aab3,
1022 
0xfede7854,
1023 
0x0bb799eb,
1024 
0x84e65d0c,
1025 
0x0bb7893a,
1026 
0xc7b70d96,
1027 
0x0bb778a1,
1028 
0x9517df01,
1029 
0x0bb7681f,
1030 
0xbb5d6e91,
1031 
0x0bb757b5,
1032 
0x0967b24c,
1033 
0x0bb74761,
1034 
0x4ea011a2,
1035 
0x0bb73724,
1036 
0x5af78614,
1037 
0x0bb726fd,
1038 
0xfee4c3a0,
1039 
0x0bb716ee,
1040 
0x0b6268e8,
1041 
0x0bb706f4,
1042 
0x51ed36ce,
1043 
0x0bb6f710,
1044 
0xa4824f80,
1045 
0x0bb6e742,
1046 
0xd59d7cb4,
1047 
0x0bb6d78a,
1048 
0xb8377d0e,
1049 
0x0bb6c7e8,
1050 
0x1fc45872,
1051 
0x0bb6b85a,
1052 
0xe031bb32,
1053 
0x0bb6a8e2,
1054 
0xcde557f9,
1055 
0x0bb6997f,
1056 
0xbdbb5045,
1057 
0x0bb68a31,
1058 
0x8504a35c,
1059 
0x0bb67af7,
1060 
0xf985a39b,
1061 
0x0bb66bd2,
1062 
0xf17471ff,
1063 
0x0bb65cc2,
1064 
0x43777fce,
1065 
0x0bb64dc5,
1066 
0xc6a41642,
1067 
0x0bb63edd,
1068 
0x527ce411,
1069 
0x0bb63008,
1070 
0xbef090cf,
1071 
0x0bb62147,
1072 
0xe45855eb,
1073 
0x0bb6129a,
1074 
0x9b769d52,
1075 
0x0bb60400,
1076 
0xbd75a584,
1077 
0x0bb5f57a,
1078 
0x23e62b07,
1079 
0x0bb5e706,
1080 
0xa8be172c,
1081 
0x0bb5d8a6,
1082 
0x265733ff,
1083 
0x0bb5ca58,
1084 
0x776de54b,
1085 
0x0bb5bc1d,
1086 
0x771fe6ab,
1087 
0x0bb5adf5,
1088 
0x00eb0e78,
1089 
0x0bb59fde,
1090 
0xf0ac1594,
1091 
0x0bb591db,
1092 
0x229d63f2,
1093 
0x0bb583e9,
1094 
0x7355e1c1,
1095 
0x0bb57609,
1096 
0xbfc7cd32,
1097 
0x0bb5683b,
1098 
0xe53f94b8,
1099 
0x0bb55a7f,
1100 
0xc162b5b6,
1101 
0x0bb54cd5,
1102 
0x322e9f7f,
1103 
0x0bb53f3c,
1104 
0x15f79aa1,
1105 
0x0bb531b4,
1106 
0x4b67b45a,
1107 
0x0bb5243d,
1108 
0xb17dae30,
1109 
0x0bb516d8,
1110 
0x278bf18f,
1111 
0x0bb50983,
1112 
0x8d378767,
1113 
0x0bb4fc3f,
1114 
0xc27713ae,
1115 
0x0bb4ef0c,
1116 
0xa791d4bb,
1117 
0x0bb4e1ea,
1118 
0x1d1ea668,
1119 
0x0bb4d4d8,
1120 
0x040308e5,
1121 
0x0bb4c7d6,
1122 
0x3d722b37,
1123 
0x0bb4bae4,
1124 
0xaaebf948,
1125 
0x0bb4ae03,
1126 
0x2e3c2d7e,
1127 
0x0bb4a131,
1128 
0xa97965c9,
1129 
0x0bb4946f,
1130 
0xff043c1c,
1131 
0x0bb487be,
1132 
0x11866236,
1133 
0x0bb47b1b,
1134 
0xc3f1c0bf,
1135 
0x0bb46e88,
1136 
0xf97f999b,
1137 
0x0bb46205,
1138 
0x95afad73,
1139 
0x0bb45591,
1140 
0x7c476454,
1141 
0x0bb4492c,
1142 
0x9150f96c,
1143 
0x0bb43cd6,
1144 
0xb91aa9c8,
1145 
0x0bb4308f,
1146 
0xd835e60b,
1147 
0x0bb42457,
1148 
0xd3768716,
1149 
0x0bb4182e,
1150 
0x8ff20590,
1151 
0x0bb40c13,
1152 
0xf2feb43b,
1153 
0x0bb40007,
1154 
0xe232fd1f,
1155 
0x0bb3f40a,
1156 
0x4364a167,
1157 
0x0bb3e81a,
1158 
0xfca7fbf0,
1159 
0x0bb3dc39,
1160 
0xf44f468a,
1161 
0x0bb3d067,
1162 
0x10e9e1c3,
1163 
0x0bb3c4a2,
1164 
0x39439f4f,
1165 
0x0bb3b8eb,
1166 
0x54640ef1,
1167 
0x0bb3ad42,
1168 
0x498dcddf,
1169 
0x0bb3a1a7,
1170 
0x003dd89b,
1171 
0x0bb39619,
1172 
0x602adf2b,
1173 
0x0bb38a99,
1174 
0x51449bb8,
1175 
0x0bb37f26,
1176 
0xbbb32b79,
1177 
0x0bb373c1,
1178 
0x87d669ea,
1179 
0x0bb36869,
1180 
0x9e454e44,
1181 
0x0bb35d1e,
1182 
0xe7cd4b2d,
1183 
0x0bb351e1,
1184 
0x4d71b098,
1185 
0x0bb346b0,
1186 
0xb86b0fc3,
1187 
0x0bb33b8d,
1188 
0x1226a15a,
1189 
0x0bb33076,
1190 
0x4445adac,
1191 
0x0bb3256c,
1192 
0x389cf6eb,
1193 
0x0bb31a6e,
1194 
0xd934256e,
1195 
0x0bb30f7e,
1196 
0x104535f5,
1197 
0x0bb30499,
1198 
0xc83be9d6,
1199 
0x0bb2f9c1,
1200 
0xebb53923,
1201 
0x0bb2eef6,
1202 
0x657ec6aa,
1203 
0x0bb2e437,
1204 
0x209655d5,
1205 
0x0bb2d984,
1206 
0x08294263,
1207 
0x0bb2cedd,
1208 
0x0793f9e7,
1209 
0x0bb2c442,
1210 
0x0a617719,
1211 
0x0bb2b9b2,
1212 
0xfc4abeda,
1213 
0x0bb2af2f,
1214 
0xc9365eff,
1215 
0x0bb2a4b8,
1216 
0x5d37eec1,
1217 
0x0bb29a4c,
1218 
0xa48f90e3,
1219 
0x0bb28fec,
1220 
0x8ba97779,
1221 
0x0bb28597,
1222 
0xff1d694d,
1223 
0x0bb27b4e,
1224 
0xebae48dd,
1225 
0x0bb27111,
1226 
0x3e499cee,
1227 
0x0bb266de,
1228 
0xe4071aa8,
1229 
0x0bb25cb7,
1230 
0xca283138,
1231 
0x0bb2529b,
1232 
0xde1796f7,
1233 
0x0bb2488b,
1234 
0x0d68d803,
1235 
0x0bb23e85,
1236 
0x45d7e65a,
1237 
0x0bb2348a,
1238 
0x7548ab54,
1239 
0x0bb22a9a,
1240 
0x89c69a97,
1241 
0x0bb220b5,
1242 
0x71844661,
1243 
0x0bb216db,
1244 
0x1adaf53f,
1245 
0x0bb20d0b,
1246 
0x744a3910,
1247 
0x0bb20346,
1248 
0x6c77876c,
1249 
0x0bb1f98b,
1250 
0xf22dd349,
1251 
0x0bb1efdb,
1252 
0xf45d27ff,
1253 
0x0bb1e636,
1254 
0x621a457e,
1255 
0x0bb1dc9b,
1256 
0x2a9e3dd5,
1257 
0x0bb1d30a,
1258 
0x3d4613ee,
1259 
0x0bb1c983,
1260 
0x89925b81,
1261 
0x0bb1c006,
1262 
0xff26da3f,
1263 
0x0bb1b694,
1264 
0x8dca2a28,
1265 
0x0bb1ad2c,
1266 
0x25655d0f,
1267 
0x0bb1a3cd,
1268 
0xb603a13d,
1269 
0x0bb19a79,
1270 
0x2fd1e741,
1271 
0x0bb1912e,
1272 
0x831e88d2,
1273 
0x0bb187ed,
1274 
0xa058f0d6,
1275 
0x0bb17eb6,
1276 
0x78114473,
1277 
0x0bb17588,
1278 
0xfaf80d3a,
1279 
0x0bb16c65,
1280 
0x19dde45d,
1281 
0x0bb1634a,
1282 
0xc5b31eef,
1283 
0x0bb15a39,
1284 
0xef877b28,
1285 
0x0bb15132,
1286 
0x8889ceae,
1287 
0x0bb14834,
1288 
0x8207b5db,
1289 
0x0bb13f3f,
1290 
0xcd6d43ff,
1291 
0x0bb13654,
1292 
0x5c44b49a,
1293 
0x0bb12d72,
1294 
0x20361d87,
1295 
0x0bb12499,
1296 
0x0b07221b,
1297 
0x0bb11bc9,
1298 
0x0e9aa72d,
1299 
0x0bb11302,
1300 
0x1cf0880f,
1301 
0x0bb10a44,
1302 
0x28254c65,
1303 
0x0bb1018f,
1304 
0x2271dee5,
1305 
0x0bb0f8e2,
1306 
0xfe2b44f4,
1307 
0x0bb0f03f,
1308 
0xadc25723,
1309 
0x0bb0e7a5,
1310 
0x23c37a85,
1311 
0x0bb0df13,
1312 
0x52d65ad9,
1313 
0x0bb0d68a,
1314 
0x2dbda58c,
1315 
0x0bb0ce09,
1316 
0xa756c589,
1317 
0x0bb0c591,
1318 
0xb2999fdb,
1319 
0x0bb0bd22,
1320 
0x42985115,
1321 
0x0bb0b4bb,
1322 
0x4a7eeb87,
1323 
0x0bb0ac5c,
1324 
0xbd933636};
1325 
 
1326 
 
1327 
unsigned int sqrtres[256] = {
1328 
0x52900000,
1329 
0x00000000,
1330 
0x52900ff8,
1331 
0x07f60deb,
1332 
0x52901fe0,
1333 
0x3f61bad0,
1334 
0x52902fb8,
1335 
0xd4e30f48,
1336 
0x52903f81,
1337 
0xf636b80c,
1338 
0x52904f3b,
1339 
0xd03c0a64,
1340 
0x52905ee6,
1341 
0x8efad48b,
1342 
0x52906e82,
1343 
0x5da8fc2b,
1344 
0x52907e0f,
1345 
0x66afed07,
1346 
0x52908d8d,
1347 
0xd3b1d9aa,
1348 
0x52909cfd,
1349 
0xcd8ed009,
1350 
0x5290ac5f,
1351 
0x7c69a3c8,
1352 
0x5290bbb3,
1353 
0x07acafdb,
1354 
0x5290caf8,
1355 
0x960e710d,
1356 
0x5290da30,
1357 
0x4d95fb06,
1358 
0x5290e95a,
1359 
0x539f492c,
1360 
0x5290f876,
1361 
0xccdf6cd9,
1362 
0x52910785,
1363 
0xdd689a29,
1364 
0x52911687,
1365 
0xa8ae14a3,
1366 
0x5291257c,
1367 
0x5187fd09,
1368 
0x52913463,
1369 
0xfa37014e,
1370 
0x5291433e,
1371 
0xc467effb,
1372 
0x5291520c,
1373 
0xd1372feb,
1374 
0x529160ce,
1375 
0x41341d74,
1376 
0x52916f83,
1377 
0x34644df9,
1378 
0x52917e2b,
1379 
0xca46bab9,
1380 
0x52918cc8,
1381 
0x21d6d3e3,
1382 
0x52919b58,
1383 
0x598f7c9f,
1384 
0x5291a9dc,
1385 
0x8f6df104,
1386 
0x5291b854,
1387 
0xe0f496a0,
1388 
0x5291c6c1,
1389 
0x6b2db870,
1390 
0x5291d522,
1391 
0x4aae2ee1,
1392 
0x5291e377,
1393 
0x9b97f4a8,
1394 
0x5291f1c1,
1395 
0x799ca8ff,
1396 
0x52920000,
1397 
0x00000000,
1398 
0x52920e33,
1399 
0x499a21a9,
1400 
0x52921c5b,
1401 
0x70d9f824,
1402 
0x52922a78,
1403 
0x8fc76de5,
1404 
0x5292388a,
1405 
0xc0059c28,
1406 
0x52924692,
1407 
0x1ad4ea49,
1408 
0x5292548e,
1409 
0xb9151e85,
1410 
0x52926280,
1411 
0xb3476096,
1412 
0x52927068,
1413 
0x21902e9a,
1414 
0x52927e45,
1415 
0x1bb944c3,
1416 
0x52928c17,
1417 
0xb9337834,
1418 
0x529299e0,
1419 
0x11188575,
1420 
0x5292a79e,
1421 
0x3a2cd2e6,
1422 
0x5292b552,
1423 
0x4ae1278e,
1424 
0x5292c2fc,
1425 
0x595456a7,
1426 
0x5292d09c,
1427 
0x7b54e03e,
1428 
0x5292de32,
1429 
0xc6628741,
1430 
0x5292ebbf,
1431 
0x4fafdd4b,
1432 
0x5292f942,
1433 
0x2c23c47e,
1434 
0x529306bb,
1435 
0x705ae7c3,
1436 
0x5293142b,
1437 
0x30a929ab,
1438 
0x52932191,
1439 
0x811b0a41,
1440 
0x52932eee,
1441 
0x75770416,
1442 
0x52933c42,
1443 
0x213ee0c9,
1444 
0x5293498c,
1445 
0x97b10540,
1446 
0x529356cd,
1447 
0xebc9b5e2,
1448 
0x52936406,
1449 
0x30445306,
1450 
0x52937135,
1451 
0x779c8dcb,
1452 
0x52937e5b,
1453 
0xd40f95a1,
1454 
0x52938b79,
1455 
0x579d3eab,
1456 
0x5293988e,
1457 
0x1409212e,
1458 
0x5293a59a,
1459 
0x1adbb257,
1460 
0x5293b29d,
1461 
0x7d635662,
1462 
0x5293bf98,
1463 
0x4cb56c77,
1464 
0x5293cc8a,
1465 
0x99af5453,
1466 
0x5293d974,
1467 
0x74f76df2,
1468 
0x5293e655,
1469 
0xeefe1367,
1470 
0x5293f32f,
1471 
0x17fe8d04,
1472 
0x52940000,
1473 
0x00000000,
1474 
0x52940cc8,
1475 
0xb6d657c2,
1476 
0x52941989,
1477 
0x4c2329f0,
1478 
0x52942641,
1479 
0xcf569572,
1480 
0x529432f2,
1481 
0x4fb01c7a,
1482 
0x52943f9a,
1483 
0xdc3f79ce,
1484 
0x52944c3b,
1485 
0x83e57153,
1486 
0x529458d4,
1487 
0x55549c1a,
1488 
0x52946565,
1489 
0x5f122ff6,
1490 
0x529471ee,
1491 
0xaf76c2c6,
1492 
0x52947e70,
1493 
0x54af0989,
1494 
0x52948aea,
1495 
0x5cbc935f,
1496 
0x5294975c,
1497 
0xd5768088,
1498 
0x5294a3c7,
1499 
0xcc8a358a,
1500 
0x5294b02b,
1501 
0x4f7c0a88,
1502 
0x5294bc87,
1503 
0x6ba7f6ec,
1504 
0x5294c8dc,
1505 
0x2e423980,
1506 
0x5294d529,
1507 
0xa457fcfc,
1508 
0x5294e16f,
1509 
0xdacff937,
1510 
0x5294edae,
1511 
0xde6b10fe,
1512 
0x5294f9e6,
1513 
0xbbc4ecb3,
1514 
0x52950617,
1515 
0x7f5491bb,
1516 
0x52951241,
1517 
0x356cf6e0,
1518 
0x52951e63,
1519 
0xea3d95b0,
1520 
0x52952a7f,
1521 
0xa9d2f8ea,
1522 
0x52953694,
1523 
0x80174810,
1524 
0x529542a2,
1525 
0x78d2d036,
1526 
0x52954ea9,
1527 
0x9fac8a0f,
1528 
0x52955aaa,
1529 
0x002a9d5a,
1530 
0x529566a3,
1531 
0xa5b2e1b1,
1532 
0x52957296,
1533 
0x9b8b5cd8,
1534 
0x52957e82,
1535 
0xecdabe8d,
1536 
0x52958a68,
1537 
0xa4a8d9f3,
1538 
0x52959647,
1539 
0xcddf1ca5,
1540 
0x5295a220,
1541 
0x73490377,
1542 
0x5295adf2,
1543 
0x9f948cfb,
1544 
0x5295b9be,
1545 
0x5d52a9da,
1546 
0x5295c583,
1547 
0xb6f7ab03,
1548 
0x5295d142,
1549 
0xb6dbadc5,
1550 
0x5295dcfb,
1551 
0x673b05df,
1552 
0x5295e8ad,
1553 
0xd236a58f,
1554 
0x5295f45a,
1555 
0x01d483b4,
1556 
0x52960000,
1557 
0x00000000,
1558 
0x52960b9f,
1559 
0xd68a4554,
1560 
0x52961739,
1561 
0x8f2aaa48,
1562 
0x529622cd,
1563 
0x337f0fe8,
1564 
0x52962e5a,
1565 
0xcd0c3ebe,
1566 
0x529639e2,
1567 
0x653e421b,
1568 
0x52964564,
1569 
0x0568c1c3,
1570 
0x529650df,
1571 
0xb6c759f4,
1572 
0x52965c55,
1573 
0x827df1d2,
1574 
0x529667c5,
1575 
0x7199104b,
1576 
0x5296732f,
1577 
0x8d0e2f77,
1578 
0x52967e93,
1579 
0xddbc0e73,
1580 
0x529689f2,
1581 
0x6c6b01d0,
1582 
0x5296954b,
1583 
0x41cd4293};

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