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dimamali |
#include "testmod.h"
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#include "irqmp.h"
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struct irqmp *irqmp_base;
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static volatile int irqtbl[18];
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irqhandler(int irq)
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{
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irqtbl[irqtbl[0]] = irq + 0x10;
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irqtbl[0]++;
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}
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init_irqmp(struct irqmp *lr)
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{
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lr->irqlevel = 0; /* clear level reg */
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lr->irqmask = 0x0; /* mask all interrupts */
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lr->irqclear = -1; /* clear all pending interrupts */
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irqtbl[0] = 1; /* init irqtable */
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}
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irqtest(int addr)
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{
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int i, a, psr;
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volatile int marr[4];
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volatile int larr[4];
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struct irqmp *lr = (struct irqmp *) addr;
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irqmp_base = lr;
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report_device(0x0100d000);
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init_irqmp(lr);
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for (i=1; i<16; i++) catch_interrupt(irqhandler, i);
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/* test that interrupts are properly prioritised */
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lr->irqforce = 0x0fffe; /* force all interrupts */
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if (lr->irqforce != 0x0fffe) fail(1); /* check force reg */
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lr->irqmask = 0x0fffe; /* unmask all interrupts */
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if (lr->irqmask != 0x0fffe) fail(2); /* check mask reg */
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while (lr->irqforce) {}; /* wait until all iterrupts are taken */
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/* check that all interrupts were take in right order */
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if (irqtbl[0] != 16) fail(3);
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for (i=1;i<16;i++) { if (irqtbl[i] != (0x20 - i)) fail(4);}
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/* test priority of the two interrupt levels */
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irqtbl[0] = 1; /* init irqtable */
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lr->irqlevel = 0xaaaa; /* set level reg to odd irq -> level 1 */
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lr->irqmask = 0xfffe;
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if (lr->irqlevel != 0xaaaa) fail(5); /* check level reg */
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if (lr->irqmask != 0xfffe) fail(5); /* check mask reg */
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lr->irqforce = 0x0fffe; /* force all interrupts */
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while (lr->irqforce) {}; /* wait until all iterrupts are taken */
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/* check that all interrupts were take in right order */
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if (irqtbl[0] != 16) fail(6);
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for (i=1;i<8;i++) { if (irqtbl[i] != (0x20 - (i*2-1)))
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fail(7);}
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for (i=2;i<8;i++) { if (irqtbl[i+8] != (0x20 - (i*2)))
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fail(8);}
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/* check interrupts of multi-cycle instructions */
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marr[0] = 1; marr[1] = marr[0]+1; marr[2] = marr[1]+1;
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a = marr[2]+1; marr[3] = a; larr[0] = 6;
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lr->irqlevel = 0; /* clear level reg */
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lr->irqmask = 0x0; /* mask all interrupts */
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irqtbl[0] = 1; /* init irqtable */
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lr->irqmask = 0x00002; /* unmask interrupt */
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lr->irqforce = 0x00002; /* force interrupt */
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asm(
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" mov %asr17, %g1\n\t"
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" andcc %g1, 0x100, %g0\n\t"
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" be 1f\n\t"
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" nop \n\t"
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" umul %g0, %g1, %g0\n\t"
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" umul %g0, %g1, %g0\n\t"
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" umul %g0, %g1, %g0\n\t"
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" 1:\n\t"
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" ");
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lr->irqforce = 0x00002; /* force interrupt */
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asm("nop;");
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larr[1] = larr[0];
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if (larr[0] != 6) fail(10);
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lr->irqforce = 0x00002; /* force interrupt */
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asm("nop;");
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larr[1] = 0;
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if (larr[1] != 0) fail(11);
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while (lr->irqforce) {}; /* wait until all iterrupts are taken */
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/* check number of interrupts */
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if (irqtbl[0] != 4) fail(13);
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lr->irqmask = 0x0; /* mask all interrupts */
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/* check that PSR.PIL work properly */
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lr->irqforce = 0x0fffe; /* force all interrupts */
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irqtbl[0] = 1; /* init irqtable */
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psr = xgetpsr() | (15 << 8);
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setpsr(psr); /* PIL = 15 */
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lr->irqmask = -1; /* enable all interrupts */
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while (!lr->irqmask); /* avoid compiler optimisation */
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if (irqtbl[0] != 2) fail(14);
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if (irqtbl[1] != 0x1f) fail(15);
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setpsr(xgetpsr() - (1 << 8));
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for (i=2;i<16;i++) {
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setpsr(xgetpsr() - (1 << 8));
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if (irqtbl[0] != i+1) fail(16);
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if (irqtbl[i] != (0x20 - i)) fail(17);
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}
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/* test optional secondary interrupt controller */
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/*
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lr->irqmask = 0x0;
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lr->imask2 = 0x0;
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lr->ipend2 = 0x0;
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lr->ipend2 = 0x1;
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if (!lr->ipend2) return(0);
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lr->ipend2 = -1;
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lr->imask2 = -1;
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for (i=lr->istat2 & 0x1f; i >=0; i--) {
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if ((lr->istat2 & 0x1f) != i) fail (17+i);
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lr->istat2 = (1 << i);
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lr->irqclear = -1;
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}
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if (lr->istat2 & 0x20) fail (33);
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if (lr->irqpend) fail (34);
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*/
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lr->irqmask = 0x0; /* mask all interrupts */
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lr->irqclear = -1; /* clear all pending interrupts */
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return(0);
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}
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