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[/] [mips_fault_tolerant/] [trunk/] [source/] [Ir.vhd] - Blame information for rev 74

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Line No. Rev Author Line
1 40 jimi39 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:      Lazaridis Dimitris
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--
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-- Create Date:    22:19:43 06/05/2012
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-- Design Name:
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-- Module Name:    Ir - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Ir is
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port
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     (
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            clk         : in std_logic;
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                 rst : in  STD_LOGIC;
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                 imem_to_ir  : in std_logic_vector(31 downto 0);
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                 IRWrite    : in std_logic;
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                 Opcode      : out std_logic_vector(5 downto 0);
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                 rs          : out std_logic_vector(4 downto 0);
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            rt          : out std_logic_vector(4 downto 0);
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                 rd          : out std_logic_vector(4 downto 0);
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                 immed_addr  : out std_logic_vector(15 downto 0);
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            Ext_sz_c  : out std_logic;
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                 From_i_op : out std_logic_vector(1 downto 0);
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                 From_i_mux : out std_logic_vector(1 downto 0);
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                 lui : out  STD_LOGIC
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          );
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end Ir;
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architecture Behavioral of Ir is
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begin
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     process(clk,rst,imem_to_ir,IRWrite)
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          variable pre_out : std_logic_vector(31 downto 0);
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          begin
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                         if rst = '0' then
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                                     Opcode <= (others => '0');
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                                                         rs     <= (others => '0');
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                                                         rt     <= (others => '0');
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                                                         rd     <= (others => '0');
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                                                         immed_addr  <= (others => '0');
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               elsif(RISING_EDGE(clk))then
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                   if(IRWrite = '1') then
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                                     pre_out := imem_to_ir;
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                                     Opcode <= pre_out(31 downto 26);
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                 rs     <= pre_out(25 downto 21);
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                 rt     <= pre_out(20 downto 16);
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                                          rd     <= pre_out(15 downto 11);
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                 immed_addr <= pre_out(15 downto 0);
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                                  end if;
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                         end if;
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         end process;
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    process(clk,rst,imem_to_ir)  --Sign_ext control
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    begin
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         if rst = '0' then
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            Ext_sz_c <=  '0';
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         elsif RISING_EDGE(clk) then
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           if (imem_to_ir(31 downto 26) = "001100") or (imem_to_ir(31 downto 26) ="001101") or
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                   (imem_to_ir(31 downto 26) = "001110") then
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                   Ext_sz_c <=  '1';
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                else
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                   Ext_sz_c <=  '0';
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         end if;
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         end if;
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         end process;
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    process(clk,rst,imem_to_ir)   -- I type opcode control for less stages
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    begin
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    if rst = '0' then
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                From_i_op <= "00";
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                From_i_mux <= "00";
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         elsif RISING_EDGE(clk) then
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            case imem_to_ir(31 downto 26) is
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                      when "001000" =>               --addi
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                                      From_i_op <= "00";
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                                 From_i_mux <= "10";
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                                when "001001" =>
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                                      From_i_op <= "01";      --addiu
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                                 From_i_mux <= "10";
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                                when "001100" =>
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                                      From_i_op <= "00";      --andi
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                                 From_i_mux <= "11";
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                                when "001101" =>
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                                      From_i_op <= "01";      --ori
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                                 From_i_mux <= "11";
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                                when "001110" =>
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                                      From_i_op <= "10";      --xori
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                                 From_i_mux <= "11";
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                                when "001111" =>
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                                      From_i_op <= "00";      --lui
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                                 From_i_mux <= "00";
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                                when "001010" =>
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                                      From_i_op <= "10";      --slti
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                                 From_i_mux <= "01";
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                                when "001011" =>
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                                      From_i_op <= "11";      --sltiu
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                                 From_i_mux <= "01";
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                                when others =>
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                                      From_i_op <= "00";      --others
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                                 From_i_mux <= "00";
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                 end case;
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        end if;
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        end process;
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        process(clk,rst,imem_to_ir)  --for lui control
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        begin
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         if rst = '0' then
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            lui <= '0';
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         elsif RISING_EDGE(clk) then
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         if (imem_to_ir(31 downto 26) = "001111") then
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                   lui <= '1';
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      else
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         lui <= '0';
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    end if;
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    end if;
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        end process;
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        --with imem_to_ir(31 downto 26) select
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   --Ext_sz_c <= '1' when  ("001100" or "001101" or "001110"),
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   --             '0' when others;
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end Behavioral;
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