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[/] [mips_fault_tolerant/] [trunk/] [source/] [Logic.vhd] - Blame information for rev 46

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Line No. Rev Author Line
1 38 jimi39
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer:   Lazaridis Dimitris
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-- 
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-- Create Date:    23:38:50 04/05/2012 
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-- Design Name: 
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-- Module Name:    Logic - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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--USE ieee.std_logic_unsigned.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Logic is
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Generic
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(
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         busw : integer := 31
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);
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    Port
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(
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                A : in  STD_LOGIC_VECTOR (busw downto 0);
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           B : in  STD_LOGIC_VECTOR (busw downto 0);
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           ALUop : in  STD_LOGIC_VECTOR (1 downto 0);
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           S : out  STD_LOGIC_VECTOR  (busw downto 0)
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);
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end Logic;
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architecture Behavioral of Logic is
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begin
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log:process(ALUop,A,B)
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         begin
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         CASE ALUop IS
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              When  "00"  =>  S <= A and B;
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                        When  "01"  =>  S <= A or  B;
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         When  "10"  =>  S <= A xor B;
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         When  "11"  =>  S <= not(A or B);
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                        When others =>
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                                        S <= (others =>'0');
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         end Case;
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end process log;
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end Behavioral;
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