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[/] [mips_fault_tolerant/] [trunk/] [source/] [RF_mux.vhd] - Blame information for rev 22

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1 22 jimi39
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    19:02:24 06/24/2012 
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-- Design Name: 
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-- Module Name:    RF_mux - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity RF_mux is
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port (
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      clk   : in std_logic;
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                RFmux : in std_logic_vector(2 downto 0);
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      Hi_in : in std_logic_vector(31 downto 0);
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      Lo_in : in std_logic_vector(31 downto 0);
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      Alu_in: in std_logic_vector(31 downto 0);
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      From_N : in std_logic_vector(31 downto 0);
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      Mdr_fr_out : in std_logic_vector(31 downto 0);
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      RF_out: out std_logic_vector(31 downto 0)
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      );
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end RF_mux;
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architecture Behavioral of RF_mux is
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begin
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      process(clk,RFmux)
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                begin
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                if (FALLING_EDGE(clk))then
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                case RFmux is
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                           when "000" => RF_out <= Hi_in;
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                                          when "010" => RF_out <= Lo_in;
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                                          when "100" => RF_out <= Alu_in;
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                                          when "110" => RF_out <= Mdr_fr_out;
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                                          when "001" => RF_out <= From_N;
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                           when others => RF_out <= (others => '0');
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                end case;
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                end if;
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      end process;
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end Behavioral;
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