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[/] [mips_fault_tolerant/] [trunk/] [source/] [Shift.vhd] - Blame information for rev 27

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Line No. Rev Author Line
1 17 jimi39
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer:       Lazaridis Dimitris
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-- 
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-- Create Date:    00:18:51 04/23/2012 
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-- Design Name: 
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-- Module Name:    Shift - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--use IEEE.Std_logic_arith.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Shift is
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Port
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(
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           rst : in  STD_LOGIC;
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                          B : in  STD_LOGIC_VECTOR (31 downto 0);
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           ALUop : in  STD_LOGIC_VECTOR (1 downto 0);
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           Shamt_in : in  STD_LOGIC_VECTOR (4 downto 0);
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           S : out  STD_LOGIC_VECTOR (31 downto 0)
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);
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end Shift;
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architecture Behavioral of Shift is
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begin
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sht:process(rst,ALUop,B,Shamt_in)
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variable to_int: integer;
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variable shift_temp : STD_LOGIC_VECTOR (31 downto 0);
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begin
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          if rst = '0' then
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             S <= x"00000000";
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          else
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     to_int := CONV_INTEGER(Shamt_in);
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          case ALUop is
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                                    when "00" => shift_temp := std_logic_vector(unsigned(B) sll to_int); --shift_B sll 
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                                         when "01" => shift_temp := B;
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                                         when "10" => shift_temp := std_logic_vector(unsigned(B) srl to_int); --srl to_int; 
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                                         when "11" => shift_temp := to_stdlogicvector(to_bitvector(B) sra to_int);--sra to_int;  
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                                         when others => S <=(others=>'0');
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          end case;
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          end if;
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 S <= shift_temp;
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end process sht;
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end Behavioral;
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