OpenCores
URL https://opencores.org/ocsvn/mipsr2000/mipsr2000/trunk

Subversion Repositories mipsr2000

[/] [mipsr2000/] [trunk/] [ALU.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 jimi39 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Create Date:    17:28:35 04/21/2012
6 
-- Design Name:
7 
-- Module Name:    ALU - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision:
16 
-- Revision 0.01 - File Created
17 
-- Additional Comments:
18 
--
19 
----------------------------------------------------------------------------------
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
 
23 
-- Uncomment the following library declaration if using
24 
-- arithmetic functions with Signed or Unsigned values
25 
--use IEEE.NUMERIC_STD.ALL;
26 
 
27 
-- Uncomment the following library declaration if instantiating
28 
-- any Xilinx primitives in this code.
29 
--library UNISIM;
30 
--use UNISIM.VComponents.all;
31 
 
32 
entity ALU is
33 
    Port
34 
         (
35 
                  clk : in  std_logic;
36 
                rst,Mult_en : in  STD_LOGIC;
37 
           A_in : in  std_logic_vector(31 downto 0);
38 
           B_in : in  std_logic_vector(31 downto 0);
39 
                          I : in  std_logic_vector(31 downto 0);
40 
                          immed_addr : std_logic_vector(15 downto 0);
41 
           ALUOp : in  std_logic_vector(2 downto 0);
42 
                          ALUmux : in  std_logic_vector(1 downto 0);
43 
                          From_i_op : IN std_logic_vector(1 downto 0);
44 
                          From_i_mux : IN std_logic_vector(1 downto 0);
45 
                          lui : in  STD_LOGIC;
46 
                          ALUSrcA : in std_logic;
47 
                          ALUSrcB : in  STD_LOGIC_VECTOR(1 downto 0);
48 
                          N  : in std_logic_vector(31 downto 0);
49 
                          M : out std_logic_vector(31 downto 0);
50 
                          Alu_out_exit : out  std_logic_vector(31 downto 0);
51 
                          Hi_out : out std_logic_vector(31 downto 0);
52 
                          Lo_out : out std_logic_vector(31 downto 0);
53 
                          Zero : out std_logic
54 
);
55 
end ALU;
56 
 
57 
architecture Behavioral of ALU is
58 
 
59 
component Logic is
60 
Port
61 
(
62 
                A : in  STD_LOGIC_VECTOR (31 downto 0);
63 
           B : in  STD_LOGIC_VECTOR (31 downto 0);
64 
           ALUop : in  STD_LOGIC_VECTOR (1 downto 0);
65 
           S : out  STD_LOGIC_VECTOR  (31 downto 0)
66 
);
67 
end component;
68 
component adder is
69 
Port
70 
(
71 
           A : in  STD_LOGIC_VECTOR (31 downto 0);
72 
           B : in  STD_LOGIC_VECTOR (31 downto 0);
73 
           ALUop : in  STD_LOGIC_VECTOR (1 downto 0);
74 
                          --ov : out std_logic;
75 
                          S : out  STD_LOGIC_VECTOR (31 downto 0)
76 
);
77 
end component;
78 
component Mux_4_1 is
79 
Port
80 
(
81 
           Logic_out : in  std_logic_vector(31 downto 0);
82 
           Adder_out : in  std_logic_vector(31 downto 0);
83 
                          Shift_out : in  std_logic_vector(31 downto 0);
84 
                          Slt_out : in  std_logic_vector(31 downto 0);
85 
           ALUmux : in  std_logic_vector(1 downto 0);
86 
           Mux_out : out std_logic_vector(31 downto 0)
87 
);
88 
end component;
89 
Component Shift_mux is
90 
Port
91 
(
92 
                A : in  STD_LOGIC_VECTOR (4 downto 0);
93 
           Shamt : in  STD_LOGIC_VECTOR (4 downto 0);
94 
           sv : in  STD_LOGIC;
95 
                          lui : in  STD_LOGIC;
96 
           Shamt_out : out  STD_LOGIC_VECTOR (4 downto 0)
97 
);
98 
end Component;
99 
component Shift is
100 
Port
101 
(
102 
           rst : in  STD_LOGIC;
103 
                          B : in  STD_LOGIC_VECTOR (31 downto 0);
104 
           ALUop : in  STD_LOGIC_VECTOR (1 downto 0);
105 
           Shamt_in : in  STD_LOGIC_VECTOR (4 downto 0);
106 
           S : out  STD_LOGIC_VECTOR (31 downto 0)
107 
);
108 
end component;
109 
component SLT is
110 
Port
111 
(
112 
           Adder_out : in  STD_LOGIC_VECTOR (0 downto 0);
113 
           Slt_out : out  STD_LOGIC_VECTOR (31 downto 0)
114 
);
115 
end component;
116 
component Or_tree is
117 
Port (     Mux_out : in  STD_LOGIC_VECTOR (31 downto 0);
118 
           Zero : out  STD_LOGIC
119 
                );
120 
 
121 
end component;
122 
component Mult is
123 
Port (
124 
           A : in  STD_LOGIC_VECTOR (31 downto 0);
125 
           B : in  STD_LOGIC_VECTOR (31 downto 0);
126 
                          Hi_to_out : out STD_LOGIC_VECTOR (31 downto 0);
127 
                          Lo_to_out : out STD_LOGIC_VECTOR (31 downto 0)
128 
);
129 
end component;
130 
component In_mux is
131 
Generic (
132 
         busw : integer := 31
133 
);
134 
Port (
135 
                A_in : in  STD_LOGIC_VECTOR (busw downto 0);
136 
                          B_in : in  STD_LOGIC_VECTOR (busw downto 0);
137 
           I : in  STD_LOGIC_VECTOR (busw downto 0);
138 
                          ALUSrcA : in  STD_LOGIC;
139 
           ALUSrcB : in  STD_LOGIC_VECTOR(1 downto 0);
140 
           A : out  STD_LOGIC_VECTOR (busw downto 0);
141 
                          B : out  STD_LOGIC_VECTOR (busw downto 0)
142 
                          );
143 
end component;
144 
component Alu_out is
145 
port (
146 
      clk : in  STD_LOGIC;
147 
           rst : in  STD_LOGIC;
148 
                I  : in std_logic_vector(31 downto 0);
149 
                N  : in std_logic_vector(31 downto 0);
150 
                Alu_all_in : in std_logic_vector(31 downto 0);
151 
                M : out std_logic_vector(31 downto 0);
152 
                Alu_out : out std_logic_vector(31 downto 0)
153 
 
154 
);
155 
end component;
156 
component ALu_control is
157 
PORT
158 
(
159 
          instr_15_0 : IN std_logic_vector(15 downto 0);
160 
          ALUOp : IN std_logic_vector(2 downto 0);
161 
                         ALUmux : IN std_logic_vector(1 downto 0);
162 
                         From_i_op : IN std_logic_vector(1 downto 0);
163 
                         From_i_mux : IN std_logic_vector(1 downto 0);
164 
                         sv : out  STD_LOGIC;
165 
                         Mul_out_c : out  STD_LOGIC_VECTOR(1 downto 0);
166 
                         ALUmux_c : OUT std_logic_vector(1 downto 0);
167 
          ALUopcode : OUT std_logic_vector(1 downto 0)
168 
);
169 
end component;
170 
component Mult_out is
171 
port (
172 
                clk : in std_logic;
173 
                          rst,Mult_en : in  STD_LOGIC;
174 
                          Mul_out_c : in STD_LOGIC_VECTOR (1 downto 0);
175 
                          A_in : in STD_LOGIC_VECTOR (31 downto 0);
176 
                Hi_to_out : in STD_LOGIC_VECTOR (31 downto 0);
177 
                          Lo_to_out : in STD_LOGIC_VECTOR (31 downto 0);
178 
                          Hi_out : out STD_LOGIC_VECTOR (31 downto 0);
179 
                          Lo_out : out STD_LOGIC_VECTOR (31 downto 0)
180 
 
181 
        );
182 
end component;
183 
 
184 
signal Logic_out,Adder_out,Shift_out,Slt_out,Mux_out,A,B,Hi_to_out,Lo_to_out : std_logic_vector(31 downto 0);
185 
signal Shamt_m_out: std_logic_vector(4 downto 0);
186 
signal ALUopcode,ALUmux_c,Mul_out_c : std_logic_vector(1 downto 0);
187 
signal sv : std_logic;
188 
 
189 
begin
190 
Logic_a:Logic port map(A=>A,B=>B,ALUop=>ALUopcode,S=>Logic_out);
191 
Adder_a:adder port map(A=>A,B=>B,ALUop=>ALUopcode,S=>Adder_out);
192 
Shift_a:Shift port map(rst=>rst,B=>B,ALUop=>ALUopcode,Shamt_in=>Shamt_m_out,S=>Shift_out);
193 
Shift_mux_a:Shift_mux port map(A=>A(4 downto 0),Shamt=>immed_addr(10 downto 6),sv=>sv,lui=>lui,
194 
                               Shamt_out=>Shamt_m_out);
195 
SLT_a:SLT port map(Adder_out=>Adder_out(31 downto 31),Slt_out=>Slt_out);
196 
Mux_4_1_a:Mux_4_1 port map(Logic_out=>Logic_out,Adder_out=>Adder_out,
197 
                           Shift_out=>Shift_out,Slt_out=>Slt_out,ALUmux=>ALUmux_c,Mux_out=>Mux_out);
198 
Or_tree_a:Or_tree port map(Mux_out=>Mux_out,Zero=>Zero);
199 
Mult_a:Mult port map(A=>A,B=>B,Hi_to_out=>Hi_to_out,Lo_to_out=>Lo_to_out);
200 
In_mux_a:In_mux port map(A_in=>A_in,B_in=>B_in,I=>I,ALUSrcA=>ALUSrcA,ALUSrcB=>ALUSrcB,A=>A,B=>B);
201 
Alu_out_a:Alu_out port map(clk=>clk,rst=>rst,I=>I,N=>N,M=>M,Alu_all_in=>Mux_out,Alu_out=>Alu_out_exit);
202 
ALu_control_a:ALu_control port map(instr_15_0=>immed_addr,ALUOp=>ALUOp,ALUmux=>ALUmux,From_i_op=>From_i_op,
203 
                                   From_i_mux=>From_i_mux,sv=>sv,
204 
                                   ALUmux_c=>ALUmux_c,Mul_out_c=>Mul_out_c,ALUopcode=>ALUopcode);
205 
Mult_out_a:Mult_out port map(clk=>clk,rst=>rst,Mult_en=>Mult_en,Mul_out_c=>Mul_out_c,A_in=>A_in,
206 
                             Hi_to_out=>Hi_to_out,Lo_to_out=>Lo_to_out,
207 
                             Hi_out=>Hi_out,Lo_out=>Lo_out);
208 
 
209 
end Behavioral;
210 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.