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[/] [mipsr2000/] [trunk/] [ALU.vhd] - Blame information for rev 13

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1 3 jimi39 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    17:28:35 04/21/2012
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-- Design Name:
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-- Module Name:    ALU - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ALU is
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    Port
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         (
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                  clk : in  std_logic;
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                rst,Mult_en : in  STD_LOGIC;
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           A_in : in  std_logic_vector(31 downto 0);
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           B_in : in  std_logic_vector(31 downto 0);
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                          I : in  std_logic_vector(31 downto 0);
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                          immed_addr : std_logic_vector(15 downto 0);
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           ALUOp : in  std_logic_vector(2 downto 0);
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                          ALUmux : in  std_logic_vector(1 downto 0);
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                          From_i_op : IN std_logic_vector(1 downto 0);
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                          From_i_mux : IN std_logic_vector(1 downto 0);
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                          lui : in  STD_LOGIC;
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                          ALUSrcA : in std_logic;
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                          ALUSrcB : in  STD_LOGIC_VECTOR(1 downto 0);
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                          N  : in std_logic_vector(31 downto 0);
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                          M : out std_logic_vector(31 downto 0);
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                          Alu_out_exit : out  std_logic_vector(31 downto 0);
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                          Hi_out : out std_logic_vector(31 downto 0);
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                          Lo_out : out std_logic_vector(31 downto 0);
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                          Zero : out std_logic
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);
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end ALU;
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architecture Behavioral of ALU is
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component Logic is
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Port
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(
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                A : in  STD_LOGIC_VECTOR (31 downto 0);
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           B : in  STD_LOGIC_VECTOR (31 downto 0);
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           ALUop : in  STD_LOGIC_VECTOR (1 downto 0);
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           S : out  STD_LOGIC_VECTOR  (31 downto 0)
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);
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end component;
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component adder is
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Port
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(
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           A : in  STD_LOGIC_VECTOR (31 downto 0);
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           B : in  STD_LOGIC_VECTOR (31 downto 0);
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           ALUop : in  STD_LOGIC_VECTOR (1 downto 0);
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                          --ov : out std_logic;
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                          S : out  STD_LOGIC_VECTOR (31 downto 0)
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);
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end component;
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component Mux_4_1 is
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Port
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(
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           Logic_out : in  std_logic_vector(31 downto 0);
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           Adder_out : in  std_logic_vector(31 downto 0);
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                          Shift_out : in  std_logic_vector(31 downto 0);
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                          Slt_out : in  std_logic_vector(31 downto 0);
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           ALUmux : in  std_logic_vector(1 downto 0);
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           Mux_out : out std_logic_vector(31 downto 0)
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);
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end component;
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Component Shift_mux is
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Port
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(
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                A : in  STD_LOGIC_VECTOR (4 downto 0);
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           Shamt : in  STD_LOGIC_VECTOR (4 downto 0);
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           sv : in  STD_LOGIC;
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                          lui : in  STD_LOGIC;
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           Shamt_out : out  STD_LOGIC_VECTOR (4 downto 0)
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);
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end Component;
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component Shift is
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Port
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(
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           rst : in  STD_LOGIC;
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                          B : in  STD_LOGIC_VECTOR (31 downto 0);
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           ALUop : in  STD_LOGIC_VECTOR (1 downto 0);
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           Shamt_in : in  STD_LOGIC_VECTOR (4 downto 0);
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           S : out  STD_LOGIC_VECTOR (31 downto 0)
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);
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end component;
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component SLT is
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Port
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(
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           Adder_out : in  STD_LOGIC_VECTOR (0 downto 0);
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           Slt_out : out  STD_LOGIC_VECTOR (31 downto 0)
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);
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end component;
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component Or_tree is
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Port (     Mux_out : in  STD_LOGIC_VECTOR (31 downto 0);
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           Zero : out  STD_LOGIC
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                );
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end component;
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component Mult is
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Port (
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           A : in  STD_LOGIC_VECTOR (31 downto 0);
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           B : in  STD_LOGIC_VECTOR (31 downto 0);
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                          Hi_to_out : out STD_LOGIC_VECTOR (31 downto 0);
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                          Lo_to_out : out STD_LOGIC_VECTOR (31 downto 0)
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);
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end component;
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component In_mux is
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Generic (
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         busw : integer := 31
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);
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Port (
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                A_in : in  STD_LOGIC_VECTOR (busw downto 0);
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                          B_in : in  STD_LOGIC_VECTOR (busw downto 0);
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           I : in  STD_LOGIC_VECTOR (busw downto 0);
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                          ALUSrcA : in  STD_LOGIC;
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           ALUSrcB : in  STD_LOGIC_VECTOR(1 downto 0);
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           A : out  STD_LOGIC_VECTOR (busw downto 0);
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                          B : out  STD_LOGIC_VECTOR (busw downto 0)
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                          );
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end component;
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component Alu_out is
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port (
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      clk : in  STD_LOGIC;
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           rst : in  STD_LOGIC;
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                I  : in std_logic_vector(31 downto 0);
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                N  : in std_logic_vector(31 downto 0);
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                Alu_all_in : in std_logic_vector(31 downto 0);
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                M : out std_logic_vector(31 downto 0);
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                Alu_out : out std_logic_vector(31 downto 0)
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);
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end component;
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component ALu_control is
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PORT
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(
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          instr_15_0 : IN std_logic_vector(15 downto 0);
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          ALUOp : IN std_logic_vector(2 downto 0);
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                         ALUmux : IN std_logic_vector(1 downto 0);
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                         From_i_op : IN std_logic_vector(1 downto 0);
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                         From_i_mux : IN std_logic_vector(1 downto 0);
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                         sv : out  STD_LOGIC;
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                         Mul_out_c : out  STD_LOGIC_VECTOR(1 downto 0);
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                         ALUmux_c : OUT std_logic_vector(1 downto 0);
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          ALUopcode : OUT std_logic_vector(1 downto 0)
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);
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end component;
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component Mult_out is
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port (
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                clk : in std_logic;
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                          rst,Mult_en : in  STD_LOGIC;
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                          Mul_out_c : in STD_LOGIC_VECTOR (1 downto 0);
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                          A_in : in STD_LOGIC_VECTOR (31 downto 0);
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                Hi_to_out : in STD_LOGIC_VECTOR (31 downto 0);
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                          Lo_to_out : in STD_LOGIC_VECTOR (31 downto 0);
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                          Hi_out : out STD_LOGIC_VECTOR (31 downto 0);
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                          Lo_out : out STD_LOGIC_VECTOR (31 downto 0)
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        );
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end component;
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signal Logic_out,Adder_out,Shift_out,Slt_out,Mux_out,A,B,Hi_to_out,Lo_to_out : std_logic_vector(31 downto 0);
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signal Shamt_m_out: std_logic_vector(4 downto 0);
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signal ALUopcode,ALUmux_c,Mul_out_c : std_logic_vector(1 downto 0);
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signal sv : std_logic;
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begin
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Logic_a:Logic port map(A=>A,B=>B,ALUop=>ALUopcode,S=>Logic_out);
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Adder_a:adder port map(A=>A,B=>B,ALUop=>ALUopcode,S=>Adder_out);
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Shift_a:Shift port map(rst=>rst,B=>B,ALUop=>ALUopcode,Shamt_in=>Shamt_m_out,S=>Shift_out);
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Shift_mux_a:Shift_mux port map(A=>A(4 downto 0),Shamt=>immed_addr(10 downto 6),sv=>sv,lui=>lui,
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                               Shamt_out=>Shamt_m_out);
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SLT_a:SLT port map(Adder_out=>Adder_out(31 downto 31),Slt_out=>Slt_out);
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Mux_4_1_a:Mux_4_1 port map(Logic_out=>Logic_out,Adder_out=>Adder_out,
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                           Shift_out=>Shift_out,Slt_out=>Slt_out,ALUmux=>ALUmux_c,Mux_out=>Mux_out);
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Or_tree_a:Or_tree port map(Mux_out=>Mux_out,Zero=>Zero);
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Mult_a:Mult port map(A=>A,B=>B,Hi_to_out=>Hi_to_out,Lo_to_out=>Lo_to_out);
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In_mux_a:In_mux port map(A_in=>A_in,B_in=>B_in,I=>I,ALUSrcA=>ALUSrcA,ALUSrcB=>ALUSrcB,A=>A,B=>B);
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Alu_out_a:Alu_out port map(clk=>clk,rst=>rst,I=>I,N=>N,M=>M,Alu_all_in=>Mux_out,Alu_out=>Alu_out_exit);
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ALu_control_a:ALu_control port map(instr_15_0=>immed_addr,ALUOp=>ALUOp,ALUmux=>ALUmux,From_i_op=>From_i_op,
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                                   From_i_mux=>From_i_mux,sv=>sv,
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                                   ALUmux_c=>ALUmux_c,Mul_out_c=>Mul_out_c,ALUopcode=>ALUopcode);
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Mult_out_a:Mult_out port map(clk=>clk,rst=>rst,Mult_en=>Mult_en,Mul_out_c=>Mul_out_c,A_in=>A_in,
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                             Hi_to_out=>Hi_to_out,Lo_to_out=>Lo_to_out,
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                             Hi_out=>Hi_out,Lo_out=>Lo_out);
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end Behavioral;
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