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[/] [mipsr2000/] [trunk/] [ALu_control.vhd] - Blame information for rev 48

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1 5 jimi39 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:        Lazaridis Dimitris
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--
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-- Create Date:    03:17:24 07/23/2012
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-- Design Name:
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-- Module Name:    ALu_control - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ALu_control is
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PORT
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(         --clk : IN std_logic;
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          instr_15_0 : IN std_logic_vector(15 downto 0);
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          ALUOp : IN std_logic_vector(2 downto 0);
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                         ALUmux : IN std_logic_vector(1 downto 0);
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                         From_i_op : IN std_logic_vector(1 downto 0);
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                         From_i_mux : IN std_logic_vector(1 downto 0);
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                         sv : out  STD_LOGIC := '0';
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                         Mul_out_c : out  STD_LOGIC_VECTOR(1 downto 0);
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                         ALUmux_c : OUT std_logic_vector(1 downto 0);
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          ALUopcode : OUT std_logic_vector(1 downto 0)
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);
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end ALu_control;
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architecture Behavioral of ALu_control is
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begin
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Alu_Control : PROCESS(instr_15_0, ALUOp,ALUmux,From_i_op,From_i_mux)
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CONSTANT ADDr : std_logic_vector(5 downto 0) := "100000";
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CONSTANT ADDr_u : std_logic_vector(5 downto 0) := "100001";
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CONSTANT SUBr : std_logic_vector(5 downto 0) := "100010";
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CONSTANT SUBr_u : std_logic_vector(5 downto 0) := "100011";
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CONSTANT ANDr : std_logic_vector(5 downto 0) := "100100";
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CONSTANT ORr : std_logic_vector(5 downto 0) := "100101";
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CONSTANT XORr : std_logic_vector(5 downto 0) := "100110";
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CONSTANT NORr : std_logic_vector(5 downto 0) := "100111";
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CONSTANT SLTr : std_logic_vector(5 downto 0) := "101010";
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CONSTANT SLTUr : std_logic_vector(5 downto 0) := "101011";
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CONSTANT MULTr : std_logic_vector(5 downto 0) := "011000";
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CONSTANT Mtlor : std_logic_vector(5 downto 0) := "010011";
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CONSTANT Mthir : std_logic_vector(5 downto 0) := "010001";
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CONSTANT Mflor : std_logic_vector(5 downto 0) := "010010";
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CONSTANT Mfhir : std_logic_vector(5 downto 0) := "010000";
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CONSTANT Sllr : std_logic_vector(5 downto 0)  := "000000";
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CONSTANT SLLVr : std_logic_vector(5 downto 0) := "000100";
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CONSTANT SRLr : std_logic_vector(5 downto 0)  := "000010";
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CONSTANT SRÁr : std_logic_vector(5 downto 0)  := "000011";
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CONSTANT SRLVr : std_logic_vector(5 downto 0) := "000110";
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CONSTANT SRAVr : std_logic_vector(5 downto 0) := "000111";
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CONSTANT JRr  : std_logic_vector(5 downto 0)  := "001000";
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BEGIN
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  --if FALLING_EDGE(clk) then
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  case ALUOp is
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      when "000" =>
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                              ALUopcode <= "00";  -- add  I types
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                                                  ALUmux_c <= ALUmux;
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      when "001" => ALUopcode <= "01";  -- add unsigned
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                              ALUmux_c <= ALUmux;
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                when "010" => ALUopcode <= "01";  -- subtract signed
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                              ALUmux_c <= ALUmux;
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                when "011" => ALUopcode <= "11";  -- subtract unsigned
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                              ALUmux_c <= ALUmux;
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      when "110" => -- operation depends on function field  r types
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                case instr_15_0(5 downto 0) is   -- r types
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                when ADDr => ALUopcode <= "00"; -- add signed
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                                                      ALUmux_c <= "10";
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                                         when ADDr_u => ALUopcode <= "01";  -- add unsigned
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                                                      ALUmux_c <= "10";
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                when SUBr => ALUopcode <= "10"; -- subtract
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                                                       ALUmux_c <= "10";
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                                         when SUBr_u => ALUopcode <= "11"; --subtract unsigned
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                                                        ALUmux_c <= "10";
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                when ANDr => ALUopcode <= "00"; -- AND
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                                                        ALUmux_c <= "11";
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                when ORr => ALUopcode <= "01"; -- OR
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                                                        ALUmux_c <= "11";
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                                         when XORr => ALUopcode <= "10"; -- XOR
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                                                        ALUmux_c <= "11";
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                when NORr => ALUopcode <=  "11"; -- NOR
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                                ALUmux_c <= "11";
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                when SLTr => ALUopcode  <=  "10";   -- SLT
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                                ALUmux_c <= "01";
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                when SLTUr      => ALUopcode  <=  "11";   -- SLTU
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                                ALUmux_c <= "01";
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                when MULTr => ALUopcode <=  "00"; -- MULT
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                                ALUmux_c <= "00";
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                                  Mul_out_c <= "00";
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                when Mtlor      => ALUopcode <=  "00"; -- Mtlo
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                                ALUmux_c <= "00";
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                                Mul_out_c <= "01";
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                when Mthir      => ALUopcode <=  "00"; -- Mthi
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                                ALUmux_c <= "00";
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                                Mul_out_c <= "10";
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                when Mflor      => ALUopcode <=  "00"; -- Mflo
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                                ALUmux_c <= "00";
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                            --  Mul_out_c <= "00";
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                when Mfhir => ALUopcode <=  "00"; -- Mfhi
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                                ALUmux_c <= "00";
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                            --  Mul_out_c <= "00";
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                when Sllr =>   ALUopcode <= "00";  --sll
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                                 ALUmux_c <= "00";
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                               sv <= '0';
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                when    SRLr =>   ALUopcode <= "10";  --srl
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                                 ALUmux_c <= "00";
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                                                                                 sv <= '0';
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                                         when SRÁr =>   ALUopcode <= "11";  --sra
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                                 ALUmux_c <= "00";
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                                                                                 sv <= '0';
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                                         when   SLLVr =>  ALUopcode <= "00";  -- sllv
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                                                        ALUmux_c <= "00";
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                                                                                 sv <= '1';
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                                         when   SRLVr =>  ALUopcode <= "10";  --srlv
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                                 ALUmux_c <= "00";
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                                                                                 sv <= '1';
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                                         when SRAVr =>  ALUopcode <= "11";      --srav
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                                 ALUmux_c <= "00";
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                                                                                 sv <= '1';
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                when others => ALUopcode <= "00";
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                                                        ALUmux_c <= "00";
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                                                                                 Mul_out_c <= "00";
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                                                                            sv <= '0';
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                end case;
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         when "111" =>   -- I types Aluop from ir
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                        ALUopcode <= From_i_op;
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                  ALUmux_c       <= From_i_mux;
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     when others => ALUopcode <= "00";
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  end case;
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 -- end if;
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END PROCESS;
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end Behavioral;
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