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[/] [mipsr2000/] [trunk/] [Imem.vhd] - Blame information for rev 12

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:13:49 05/31/2012 
-- Design Name: 
-- Module Name:    Imem - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Imem is
port (
        clk : in std_logic;
                  en : in std_logic;
                  address : in std_logic_vector(12 downto 0);
                  imem_to_ir : out std_logic_vector(31 downto 0)
 
                );
end Imem;
 
architecture Behavioral of Imem is
Component Rom16_S36 is
port  (
       clk : in std_logic;
       we : in std_logic;
       en : in std_logic;
       ssr : in std_logic;
       addr : in std_logic_vector(10 downto 2);
       di : in std_logic_vector (31 downto 0);
       do : out std_logic_vector(31 downto 0)
     );
end component;
Component Rom16_S36_1 is
port  (
       clk : in std_logic;
       we : in std_logic;
       en : in std_logic;
       ssr : in std_logic;
       addr : in std_logic_vector(10 downto 2);
       di : in std_logic_vector (31 downto 0);
       do : out std_logic_vector(31 downto 0)
     );
end component;
 
Component Rom16_S36_2 is
port  (
       clk : in std_logic;
       we : in std_logic;
       en : in std_logic;
       ssr : in std_logic;
       addr : in std_logic_vector(10 downto 2);
       di : in std_logic_vector (31 downto 0);
       do : out std_logic_vector(31 downto 0)
     );
end component;
Component Rom16_S36_3 is
port  (
       clk : in std_logic;
       we : in std_logic;
       en : in std_logic;
       ssr : in std_logic;
       addr : in std_logic_vector(10 downto 2);
       di : in std_logic_vector (31 downto 0);
       do : out std_logic_vector(31 downto 0)
     );
end component;
Component Addr_dec is
port  (
              addr : in std_logic_vector(1 downto 0);
                             dec_out: out std_logic_vector(3 downto 0)
                            );
end component;
Component imem_or_out is
port  (
 
                 do_internal_0 :in std_logic_vector(31 downto 0);
                 do_internal_1 :in std_logic_vector(31 downto 0);
                 do_internal_2 :in std_logic_vector(31 downto 0);
                 do_internal_3 :in std_logic_vector(31 downto 0);
       imem_or_out   :out std_logic_vector(31 downto 0)
 
);
end component;
signal sl: std_logic_vector(3 downto 0);
signal do_internal_0,do_internal_1,do_internal_2,do_internal_3: std_logic_vector(31 downto 0);
 
begin
 
RI_0 : Rom16_S36
           port map
                (
                        clk => clk,
                        we => '0',
                        en => en,
                        ssr => sl(0),
                        addr => address (10 downto 2),
                        di => "00000000000000000000000000000000",
                        do => do_internal_0    --(0)
                );
 
RI_1 : Rom16_S36_1
           port map
                (
                        clk => clk,
                        we => '0',
                        en => en,
                        ssr => sl(1),
                        addr => address (10 downto 2),
                        di => "00000000000000000000000000000000",
                        do => do_internal_1    --(1)
                );
RI_2 : Rom16_S36_2
           port map
                (
                        clk => clk,
                        we => '0',
                        en => en,
                        ssr => sl(2),
                        addr => address (10 downto 2),
                        di => "00000000000000000000000000000000",
                        do => do_internal_2     --(2)
                );
 
RI_3 : Rom16_S36_3
           port map
                (
                        clk => clk,
                        we => '0',
                        en => en,
                        ssr => sl(3),
                        addr => address (10 downto 2),
                        di => "00000000000000000000000000000000",
                        do => do_internal_3     --(3)
                );
 
Addr_dec_i:Addr_dec port map(addr=>address(12 downto 11),dec_out=>sl);
 
 
imem_to_ir <=   do_internal_0 or        do_internal_1 or        do_internal_2 or        do_internal_3;
 
 
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	12	jimi39	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 01:13:49 05/31/2012`
6			`-- Design Name:`
7			`-- Module Name: Imem - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22
23			`-- Uncomment the following library declaration if using`
24			`-- arithmetic functions with Signed or Unsigned values`
25			`--use IEEE.NUMERIC_STD.ALL;`
26
27			`-- Uncomment the following library declaration if instantiating`
28			`-- any Xilinx primitives in this code.`
29			`--library UNISIM;`
30			`--use UNISIM.VComponents.all;`
31
32			`entity Imem is`
33			`port (`
34			`clk : in std_logic;`
35			`en : in std_logic;`
36			`address : in std_logic_vector(12 downto 0);`
37			`imem_to_ir : out std_logic_vector(31 downto 0)`
38
39			`);`
40			`end Imem;`
41
42			`architecture Behavioral of Imem is`
43			`Component Rom16_S36 is`
44			`port (`
45			`clk : in std_logic;`
46			`we : in std_logic;`
47			`en : in std_logic;`
48			`ssr : in std_logic;`
49			`addr : in std_logic_vector(10 downto 2);`
50			`di : in std_logic_vector (31 downto 0);`
51			`do : out std_logic_vector(31 downto 0)`
52			`);`
53			`end component;`
54			`Component Rom16_S36_1 is`
55			`port (`
56			`clk : in std_logic;`
57			`we : in std_logic;`
58			`en : in std_logic;`
59			`ssr : in std_logic;`
60			`addr : in std_logic_vector(10 downto 2);`
61			`di : in std_logic_vector (31 downto 0);`
62			`do : out std_logic_vector(31 downto 0)`
63			`);`
64			`end component;`
65
66			`Component Rom16_S36_2 is`
67			`port (`
68			`clk : in std_logic;`
69			`we : in std_logic;`
70			`en : in std_logic;`
71			`ssr : in std_logic;`
72			`addr : in std_logic_vector(10 downto 2);`
73			`di : in std_logic_vector (31 downto 0);`
74			`do : out std_logic_vector(31 downto 0)`
75			`);`
76			`end component;`
77			`Component Rom16_S36_3 is`
78			`port (`
79			`clk : in std_logic;`
80			`we : in std_logic;`
81			`en : in std_logic;`
82			`ssr : in std_logic;`
83			`addr : in std_logic_vector(10 downto 2);`
84			`di : in std_logic_vector (31 downto 0);`
85			`do : out std_logic_vector(31 downto 0)`
86			`);`
87			`end component;`
88			`Component Addr_dec is`
89			`port (`
90			`addr : in std_logic_vector(1 downto 0);`
91			`dec_out: out std_logic_vector(3 downto 0)`
92			`);`
93			`end component;`
94			`Component imem_or_out is`
95			`port (`
96
97			`do_internal_0 :in std_logic_vector(31 downto 0);`
98			`do_internal_1 :in std_logic_vector(31 downto 0);`
99			`do_internal_2 :in std_logic_vector(31 downto 0);`
100			`do_internal_3 :in std_logic_vector(31 downto 0);`
101			`imem_or_out :out std_logic_vector(31 downto 0)`
102
103			`);`
104			`end component;`
105			`signal sl: std_logic_vector(3 downto 0);`
106			`signal do_internal_0,do_internal_1,do_internal_2,do_internal_3: std_logic_vector(31 downto 0);`
107
108			`begin`
109
110			`RI_0 : Rom16_S36`
111			`port map`
112			`(`
113			`clk => clk,`
114			`we => '0',`
115			`en => en,`
116			`ssr => sl(0),`
117			`addr => address (10 downto 2),`
118			`di => "00000000000000000000000000000000",`
119			`do => do_internal_0 --(0)`
120			`);`
121
122			`RI_1 : Rom16_S36_1`
123			`port map`
124			`(`
125			`clk => clk,`
126			`we => '0',`
127			`en => en,`
128			`ssr => sl(1),`
129			`addr => address (10 downto 2),`
130			`di => "00000000000000000000000000000000",`
131			`do => do_internal_1 --(1)`
132			`);`
133			`RI_2 : Rom16_S36_2`
134			`port map`
135			`(`
136			`clk => clk,`
137			`we => '0',`
138			`en => en,`
139			`ssr => sl(2),`
140			`addr => address (10 downto 2),`
141			`di => "00000000000000000000000000000000",`
142			`do => do_internal_2 --(2)`
143			`);`
144
145			`RI_3 : Rom16_S36_3`
146			`port map`
147			`(`
148			`clk => clk,`
149			`we => '0',`
150			`en => en,`
151			`ssr => sl(3),`
152			`addr => address (10 downto 2),`
153			`di => "00000000000000000000000000000000",`
154			`do => do_internal_3 --(3)`
155			`);`
156
157			`Addr_dec_i:Addr_dec port map(addr=>address(12 downto 11),dec_out=>sl);`
158
159
160			`imem_to_ir <= do_internal_0 or do_internal_1 or do_internal_2 or do_internal_3;`
161
162
163
164			`end Behavioral;`
165

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[/] [mipsr2000/] [trunk/] [Imem.vhd] - Blame information for rev 12