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[/] [mipsr2000/] [trunk/] [Imem.vhd] - Blame information for rev 58

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Line No. Rev Author Line
1 12 jimi39 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    01:13:49 05/31/2012
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-- Design Name:
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-- Module Name:    Imem - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Imem is
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port (
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        clk : in std_logic;
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                  en : in std_logic;
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                  address : in std_logic_vector(12 downto 0);
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                  imem_to_ir : out std_logic_vector(31 downto 0)
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                );
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end Imem;
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architecture Behavioral of Imem is
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Component Rom16_S36 is
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port  (
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       clk : in std_logic;
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       we : in std_logic;
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       en : in std_logic;
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       ssr : in std_logic;
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       addr : in std_logic_vector(10 downto 2);
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       di : in std_logic_vector (31 downto 0);
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       do : out std_logic_vector(31 downto 0)
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     );
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end component;
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Component Rom16_S36_1 is
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port  (
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       clk : in std_logic;
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       we : in std_logic;
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       en : in std_logic;
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       ssr : in std_logic;
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       addr : in std_logic_vector(10 downto 2);
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       di : in std_logic_vector (31 downto 0);
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       do : out std_logic_vector(31 downto 0)
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     );
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end component;
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Component Rom16_S36_2 is
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port  (
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       clk : in std_logic;
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       we : in std_logic;
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       en : in std_logic;
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       ssr : in std_logic;
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       addr : in std_logic_vector(10 downto 2);
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       di : in std_logic_vector (31 downto 0);
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       do : out std_logic_vector(31 downto 0)
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     );
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end component;
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Component Rom16_S36_3 is
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port  (
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       clk : in std_logic;
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       we : in std_logic;
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       en : in std_logic;
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       ssr : in std_logic;
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       addr : in std_logic_vector(10 downto 2);
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       di : in std_logic_vector (31 downto 0);
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       do : out std_logic_vector(31 downto 0)
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     );
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end component;
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Component Addr_dec is
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port  (
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              addr : in std_logic_vector(1 downto 0);
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                             dec_out: out std_logic_vector(3 downto 0)
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                            );
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end component;
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Component imem_or_out is
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port  (
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                 do_internal_0 :in std_logic_vector(31 downto 0);
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                 do_internal_1 :in std_logic_vector(31 downto 0);
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                 do_internal_2 :in std_logic_vector(31 downto 0);
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                 do_internal_3 :in std_logic_vector(31 downto 0);
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       imem_or_out   :out std_logic_vector(31 downto 0)
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);
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end component;
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signal sl: std_logic_vector(3 downto 0);
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signal do_internal_0,do_internal_1,do_internal_2,do_internal_3: std_logic_vector(31 downto 0);
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begin
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RI_0 : Rom16_S36
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           port map
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                (
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                        clk => clk,
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                        we => '0',
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                        en => en,
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                        ssr => sl(0),
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                        addr => address (10 downto 2),
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                        di => "00000000000000000000000000000000",
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                        do => do_internal_0    --(0)
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                );
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RI_1 : Rom16_S36_1
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           port map
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                (
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                        clk => clk,
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                        we => '0',
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                        en => en,
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                        ssr => sl(1),
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                        addr => address (10 downto 2),
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                        di => "00000000000000000000000000000000",
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                        do => do_internal_1    --(1)
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                );
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RI_2 : Rom16_S36_2
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           port map
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                (
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                        clk => clk,
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                        we => '0',
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                        en => en,
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                        ssr => sl(2),
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                        addr => address (10 downto 2),
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                        di => "00000000000000000000000000000000",
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                        do => do_internal_2     --(2)
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                );
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RI_3 : Rom16_S36_3
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           port map
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                (
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                        clk => clk,
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                        we => '0',
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                        en => en,
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                        ssr => sl(3),
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                        addr => address (10 downto 2),
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                        di => "00000000000000000000000000000000",
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                        do => do_internal_3     --(3)
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                );
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Addr_dec_i:Addr_dec port map(addr=>address(12 downto 11),dec_out=>sl);
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imem_to_ir <=   do_internal_0 or        do_internal_1 or        do_internal_2 or        do_internal_3;
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end Behavioral;
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