OpenCores
URL https://opencores.org/ocsvn/mipsr2000/mipsr2000/trunk

Subversion Repositories mipsr2000

[/] [mipsr2000/] [trunk/] [Rom16_S36.vhd] - Blame information for rev 51

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 jimi39 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Create Date:    01:15:09 05/31/2012
6 
-- Design Name:
7 
-- Module Name:    Rom16_S36 - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision:
16 
-- Revision 0.01 - File Created
17 
-- Additional Comments:
18 
--
19 
----------------------------------------------------------------------------------
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
Library UNISIM;
23 
use UNISIM.vcomponents.all;
24 
-- Uncomment the following library declaration if using
25 
-- arithmetic functions with Signed or Unsigned values
26 
--use IEEE.NUMERIC_STD.ALL;
27 
 
28 
-- Uncomment the following library declaration if instantiating
29 
-- any Xilinx primitives in this code.
30 
--library UNISIM;
31 
--use UNISIM.VComponents.all;
32 
 
33 
entity Rom16_S36 is
34 
port (
35 
       clk : in std_logic;
36 
       we : in std_logic;
37 
       en : in std_logic;
38 
       ssr : in std_logic;
39 
       addr : in std_logic_vector(10 downto 2);
40 
       di : in std_logic_vector (31 downto 0);
41 
       do : out std_logic_vector(31 downto 0)
42 
                );
43 
end Rom16_S36;
44 
 
45 
 
46 
architecture Behavioral of Rom16_S36 is
47 
signal clk_inv : std_logic;
48 
begin
49 
     process(clk)
50 
          variable invert : std_logic;
51 
          begin
52 
          invert := not clk;
53 
          clk_inv <= invert;
54 
          end process;
55 
   -- RAMB16_S36: 512 x 32 + 4 Parity bits Single-Port RAM
56 
   --             Spartan-3
57 
   -- Xilinx HDL Language Template, version 13.1
58 
   RAMB16_S36_inst : RAMB16_S36
59 
   generic map (
60 
      INIT => X"000000000",  --  Value of output RAM registers at startup
61 
      SRVAL => X"000000000", --  Ouput value upon SSR assertion
62 
      WRITE_MODE => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
63 
      -- The following INIT_xx declarations specify the initial contents of the RAM
64 
      -- Address 0 to 127
65 
      INIT_00 => X"025388250253882402538823025388220253882102538820AF8900648F890064",
66 
      INIT_01 => X"001288C001200013012000110000881000008812025300180253882702538826",
67 
      INIT_02 => X"222900641672000112720001027288070272880602728804001288C3001288C2",
68 
      INIT_03 => X"2D2800642A2800640232802A0232802A3C0900643A2900643629006426290064",
69 
      INIT_04 => X"240e0001379c80003c1c100037bdeba03c1d7fff0100F809010000082408008C",
70 
      INIT_05 => X"210bfff824080008ac2e0090002f08213c010000ac2e00903c010000240f0004",
71 
      INIT_06 => X"012a68208d4a0090014c50213c0a00008d290090012b48213c090000210cfffc",
72 
      INIT_07 => X"03e00008000000001420fff1290100a021080004ac2d0090002808213c010000",
73 
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
74 
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
75 
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
76 
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
77 
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
78 
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
79 
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
80 
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
81 
      -- Address 128 to 255
82 
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
83 
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
84 
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
85 
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
86 
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
87 
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
88 
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
89 
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
90 
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
91 
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
92 
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
93 
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
94 
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
95 
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
96 
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
97 
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
98 
      -- Address 256 to 383
99 
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
100 
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
101 
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
102 
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
103 
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
104 
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
105 
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
106 
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
107 
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
108 
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
109 
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
110 
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
111 
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
112 
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
113 
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
114 
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
115 
      -- Address 384 to 511
116 
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
117 
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
118 
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
119 
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
120 
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
121 
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
122 
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
123 
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
124 
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
125 
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
126 
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
127 
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
128 
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
129 
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
130 
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
131 
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
132 
      -- The next set of INITP_xx are for the parity bits
133 
      -- Address 0 to 127
134 
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
135 
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
136 
      -- Address 128 to 255
137 
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
138 
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
139 
      -- Address 256 to 383
140 
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
141 
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
142 
      -- Address 384 to 511
143 
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
144 
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
145 
                port map (
146 
      DO => do,      -- 32-bit Data Output
147 
      DOP => open,    --unused  --dop,    -- 4-bit parity Output
148 
      ADDR => addr,  -- 9-bit Address Input
149 
      CLK => clk_inv,    -- Clock
150 
      DI => di,      -- 32-bit Data Input
151 
      DIP => "1111", --unused di(7 downto 4),    -- 4-bit parity Input
152 
      EN => en,      -- RAM Enable Input
153 
      SSR => ssr,    -- Synchronous Set/Reset Input
154 
      WE => we       -- Write Enable Input
155 
   );
156 
 
157 
   -- End of RAMB16_S36_inst instantiation
158 
 
159 
 
160 
end Behavioral;
161 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.