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[/] [mipsr2000/] [trunk/] [dmem.vhd] - Blame information for rev 58

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1 10 jimi39
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer:   Lazaridis Dimitris
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-- 
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-- Create Date:    22:01:13 06/13/2012 
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-- Design Name: 
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-- Module Name:    dmem - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity dmem is
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         port (
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               clk : in std_logic;
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                                        rst : in std_logic;
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                                        IorD : in std_logic;
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                                        we : in std_logic_vector(3 downto 0);
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               en : in std_logic_vector(3 downto 0);
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               ssr : in std_logic_vector(3 downto 0);
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               address : in std_logic_vector(10 downto 0);
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               data_in : in std_logic_vector(31 downto 0);
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               data_out : out std_logic_vector(31 downto 0)
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                                        );
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end dmem;
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architecture Behavioral of dmem is
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component RAMB16_S9_0 is
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port (
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       clk : in std_logic;
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                 we : in std_logic;
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       en : in std_logic;
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       ssr : in std_logic;
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       addr : in std_logic_vector(10 downto 0);
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       di : in std_logic_vector (7 downto 0);
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       do : out std_logic_vector(7 downto 0)
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        );
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end component;
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signal  data_out_buff,data_out_l,data_in_buff : std_logic_vector(31 downto 0);
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signal address_buff : std_logic_vector(10 downto 0);
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begin
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       -- This module uses 4 2Kx8 block RAMs
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       -- This module uses 4 2Kx8 block RAMs
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R1 : for I in 0 to 3 generate
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Ram : RAMB16_S9_0 port map (
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                         clk => clk,
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                         we => we(I),
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                         en => en(I),
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                         ssr => ssr(I),
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                         addr => address_buff,
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                         di => data_in_buff(((8*I)+7) downto (8*I)),
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                         do => data_out_buff(((8*I)+7) downto (8*I))
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);
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end generate R1;
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process(we,en,ssr,data_in,data_out_buff)
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variable we_check,en_check : std_logic;
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begin
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     we_check := we(0) or we(1) or we(2) or we(3);
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          en_check := en(0) or en(1) or en(2) or en(3);
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     if we_check = '1' and en_check = '1' then
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             data_in_buff  <= data_in;
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                  elsif en_check = '1' then
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                  data_out_l <= data_out_buff;
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        else
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        data_out_l <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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     end if;
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end process;
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process(clk,rst,IorD,address)
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variable adr_e : integer;
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variable adr_tmp : std_logic_vector(10 downto 0);
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variable E : std_logic;
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begin
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   if rst = '0' then
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            address_buff <= (others => '0');
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    else --if FALLING_EDGE(clk) then  --for more accurate timing + we,en
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            if IorD = '1' then
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                 address_buff <= address;
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                 adr_tmp := address;
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       adr_e := CONV_INTEGER(adr_tmp);
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       if (adr_e mod "100") = 0 then
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                 E := '0';
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                 else
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                 E := '1';
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                 end if;
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                 end if;
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         end if;
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end process;
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process(clk,rst,IorD,data_out_l)
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begin
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     if rst = '0' then
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            data_out <= (others => '0');
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    elsif RISING_EDGE(clk) then
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            if IorD = '1' then
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                    data_out <= data_out_l;
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                 end if;
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           end if;
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end process;
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end Behavioral;
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