Subversion Repositories mjpeg-decoder

# BEGIN Project Options

SET flowvendor = Other

SET vhdlsim = True

SET verilogsim = False

SET workingdirectory = /home/smanz/coregen/coregen/tmp

SET speedgrade = -7

SET simulationfiles = Behavioral

SET asysymbol = False

SET addpads = False

SET device = xc2vp30

SET implementationfiletype = ngc

SET busformat = BusFormatAngleBracketNotRipped

SET foundationsym = False

SET package = ff896

SET createndf = False

SET designentry = VHDL

SET devicefamily = virtex2p

SET formalverification = False

SET removerpms = False

# END Project Options

# BEGIN Select

SELECT Block_Memory_Generator family Xilinx,_Inc. 1.1

# END Select

# BEGIN Parameters

CSET write_depth_a=2048

CSET operating_mode_a=WRITE_FIRST

CSET operating_mode_b=WRITE_FIRST

CSET write_width_a=9

CSET write_width_b=9

CSET use_regcea_pin=false

CSET primitive=8kx2

CSET memory_type=Simple_Dual_Port_RAM

CSET byte_size=9

CSET disable_out_of_range_warnings=false

CSET use_regceb_pin=false

CSET remaining_memory_locations=0

CSET use_byte_write_enable=false

CSET enable_a=Always_Enabled

CSET enable_b=Always_Enabled

CSET component_name=jpeg_upsampling_buffer

CSET assume_synchronous_clk=false

CSET disable_collision_warnings=false

CSET algorithm=Minimum_Area

CSET fill_remaining_memory_locations=false

CSET register_output_of_memory_primitives=false

CSET use_ssra_pin=false

CSET read_width_a=9

CSET read_width_b=9

CSET register_output_of_memory_core=false

CSET output_reset_value_a=0

CSET output_reset_value_b=0

CSET load_init_file=false

CSET coe_file=no_coe_file_loaded

CSET use_ssrb_pin=false

CSET collision_warnings=ALL

# END Parameters

GENERATE