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smanz |
############################################################################
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## This system.ucf file is generated by Base System Builder based on the
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## settings in the selected Xilinx Board Definition file. Please add other
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## user constraints to this file based on customer design specifications.
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############################################################################
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Net sys_clk_pin LOC=AJ15;
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Net sys_clk_pin IOSTANDARD = LVCMOS25;
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Net sys_rst_pin LOC=AH5;
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Net sys_rst_pin IOSTANDARD = LVTTL;
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## System level constraints
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Net sys_clk_pin TNM_NET = sys_clk_pin;
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TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
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Net sys_rst_pin TIG;
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NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";
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NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";
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NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";
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TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;
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Net fpga_0_DDR_CLK_FB LOC=C16;
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Net fpga_0_DDR_CLK_FB IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_CLK_FB_OUT LOC=G23;
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Net fpga_0_DDR_CLK_FB_OUT IOSTANDARD = SSTL2_II;
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## IO Devices constraints
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#### Module RS232_Uart_1 constraints
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Net fpga_0_RS232_Uart_1_RX_pin LOC=AJ8;
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Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD = LVCMOS25;
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Net fpga_0_RS232_Uart_1_TX_pin LOC=AE7;
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Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD = LVCMOS25;
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Net fpga_0_RS232_Uart_1_TX_pin SLEW = SLOW;
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Net fpga_0_RS232_Uart_1_TX_pin DRIVE = 12;
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#### Module DDR_512MB_64Mx64_rank2_row13_col10_cl2_5 constraints
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<0> LOC=M25;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<0> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<1> LOC=N25;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<1> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<2> LOC=L26;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<2> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<3> LOC=M29;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<3> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<4> LOC=K30;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<4> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<5> LOC=G25;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<5> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<6> LOC=G26;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<6> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<7> LOC=D26;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<7> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<8> LOC=J24;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<8> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<9> LOC=K24;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<9> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<10> LOC=F28;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<10> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<11> LOC=F30;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<11> IOSTANDARD = SSTL2_II;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<12> LOC=M24;
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#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<12> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<12> LOC=M25;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<12> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<11> LOC=N25;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<11> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<10> LOC=L26;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<10> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<9> LOC=M29;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<9> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<8> LOC=K30;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<8> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<7> LOC=G25;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<7> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<6> LOC=G26;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<6> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<5> LOC=D26;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<5> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<4> LOC=J24;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<4> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<3> LOC=K24;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<3> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<2> LOC=F28;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<2> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<1> LOC=F30;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<1> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<0> LOC=M24;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<0> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin<1> LOC=M26;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin<0> LOC=K26;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin LOC=L27;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<1> LOC=R26;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<1> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<0> LOC=R25;
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| 98 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<0> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<1> LOC=R24;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<1> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<0> LOC=R23;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<0> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin LOC=N29;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin LOC=N26;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin IOSTANDARD = SSTL2_II;
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| 107 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<7> LOC=U26;
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| 108 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<7> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<6> LOC=V29;
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| 110 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<6> IOSTANDARD = SSTL2_II;
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<5> LOC=W29;
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| 112 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<5> IOSTANDARD = SSTL2_II;
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| 113 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<4> LOC=T22;
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| 114 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<4> IOSTANDARD = SSTL2_II;
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| 115 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<3> LOC=W28;
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| 116 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
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| 117 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<2> LOC=W27;
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| 118 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
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| 119 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<1> LOC=W26;
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| 120 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
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| 121 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<0> LOC=W25;
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| 122 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
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| 123 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<7> LOC=E30;
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| 124 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<7> IOSTANDARD = SSTL2_II;
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| 125 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<6> LOC=J29;
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| 126 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<6> IOSTANDARD = SSTL2_II;
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| 127 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<5> LOC=M30;
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| 128 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<5> IOSTANDARD = SSTL2_II;
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| 129 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<4> LOC=P29;
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| 130 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<4> IOSTANDARD = SSTL2_II;
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| 131 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<3> LOC=V23;
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| 132 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II;
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| 133 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<2> LOC=AA25;
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| 134 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II;
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| 135 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<1> LOC=AC25;
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| 136 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II;
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| 137 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<0> LOC=AH26;
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| 138 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II;
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| 139 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<63> LOC=C27;
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| 140 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<63> IOSTANDARD = SSTL2_II;
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| 141 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<62> LOC=D28;
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| 142 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<62> IOSTANDARD = SSTL2_II;
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| 143 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<61> LOC=D29;
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| 144 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<61> IOSTANDARD = SSTL2_II;
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| 145 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<60> LOC=D30;
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| 146 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<60> IOSTANDARD = SSTL2_II;
|
| 147 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<59> LOC=H25;
|
| 148 |
|
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<59> IOSTANDARD = SSTL2_II;
|
| 149 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<58> LOC=H26;
|
| 150 |
|
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<58> IOSTANDARD = SSTL2_II;
|
| 151 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<57> LOC=E27;
|
| 152 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<57> IOSTANDARD = SSTL2_II;
|
| 153 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<56> LOC=E28;
|
| 154 |
|
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<56> IOSTANDARD = SSTL2_II;
|
| 155 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<55> LOC=J26;
|
| 156 |
|
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<55> IOSTANDARD = SSTL2_II;
|
| 157 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<54> LOC=G27;
|
| 158 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<54> IOSTANDARD = SSTL2_II;
|
| 159 |
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|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<53> LOC=G28;
|
| 160 |
|
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<53> IOSTANDARD = SSTL2_II;
|
| 161 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<52> LOC=G30;
|
| 162 |
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|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<52> IOSTANDARD = SSTL2_II;
|
| 163 |
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|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<51> LOC=L23;
|
| 164 |
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|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<51> IOSTANDARD = SSTL2_II;
|
| 165 |
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|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<50> LOC=L24;
|
| 166 |
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<50> IOSTANDARD = SSTL2_II;
|
| 167 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<49> LOC=H27;
|
| 168 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<49> IOSTANDARD = SSTL2_II;
|
| 169 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<48> LOC=H28;
|
| 170 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<48> IOSTANDARD = SSTL2_II;
|
| 171 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<47> LOC=J27;
|
| 172 |
|
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Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<47> IOSTANDARD = SSTL2_II;
|
| 173 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<46> LOC=J28;
|
| 174 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<46> IOSTANDARD = SSTL2_II;
|
| 175 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<45> LOC=K29;
|
| 176 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<45> IOSTANDARD = SSTL2_II;
|
| 177 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<44> LOC=L29;
|
| 178 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<44> IOSTANDARD = SSTL2_II;
|
| 179 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<43> LOC=N23;
|
| 180 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<43> IOSTANDARD = SSTL2_II;
|
| 181 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<42> LOC=N24;
|
| 182 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<42> IOSTANDARD = SSTL2_II;
|
| 183 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<41> LOC=K27;
|
| 184 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<41> IOSTANDARD = SSTL2_II;
|
| 185 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<40> LOC=K28;
|
| 186 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<40> IOSTANDARD = SSTL2_II;
|
| 187 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<39> LOC=R22;
|
| 188 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<39> IOSTANDARD = SSTL2_II;
|
| 189 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<38> LOC=M27;
|
| 190 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<38> IOSTANDARD = SSTL2_II;
|
| 191 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<37> LOC=M28;
|
| 192 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<37> IOSTANDARD = SSTL2_II;
|
| 193 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<36> LOC=P30;
|
| 194 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<36> IOSTANDARD = SSTL2_II;
|
| 195 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<35> LOC=P23;
|
| 196 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<35> IOSTANDARD = SSTL2_II;
|
| 197 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<34> LOC=P24;
|
| 198 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<34> IOSTANDARD = SSTL2_II;
|
| 199 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<33> LOC=N27;
|
| 200 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<33> IOSTANDARD = SSTL2_II;
|
| 201 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<32> LOC=N28;
|
| 202 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<32> IOSTANDARD = SSTL2_II;
|
| 203 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<31> LOC=V27;
|
| 204 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II;
|
| 205 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<30> LOC=Y30;
|
| 206 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II;
|
| 207 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<29> LOC=U24;
|
| 208 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II;
|
| 209 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<28> LOC=U23;
|
| 210 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II;
|
| 211 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<27> LOC=V26;
|
| 212 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II;
|
| 213 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<26> LOC=V25;
|
| 214 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II;
|
| 215 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<25> LOC=Y29;
|
| 216 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II;
|
| 217 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<24> LOC=AA29;
|
| 218 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II;
|
| 219 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<23> LOC=Y26;
|
| 220 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II;
|
| 221 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<22> LOC=AA28;
|
| 222 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II;
|
| 223 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<21> LOC=AA27;
|
| 224 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II;
|
| 225 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<20> LOC=W24;
|
| 226 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II;
|
| 227 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<19> LOC=W23;
|
| 228 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II;
|
| 229 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<18> LOC=AB28;
|
| 230 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II;
|
| 231 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<17> LOC=AB27;
|
| 232 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II;
|
| 233 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<16> LOC=AC29;
|
| 234 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II;
|
| 235 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<15> LOC=AB25;
|
| 236 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II;
|
| 237 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<14> LOC=AE29;
|
| 238 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II;
|
| 239 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<13> LOC=AA24;
|
| 240 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II;
|
| 241 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<12> LOC=AA23;
|
| 242 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II;
|
| 243 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<11> LOC=AD28;
|
| 244 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II;
|
| 245 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<10> LOC=AD27;
|
| 246 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II;
|
| 247 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<9> LOC=AF30;
|
| 248 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II;
|
| 249 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<8> LOC=AF29;
|
| 250 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II;
|
| 251 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<7> LOC=AF25;
|
| 252 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II;
|
| 253 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<6> LOC=AG30;
|
| 254 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II;
|
| 255 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<5> LOC=AG29;
|
| 256 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II;
|
| 257 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<4> LOC=AD26;
|
| 258 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II;
|
| 259 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<3> LOC=AD25;
|
| 260 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II;
|
| 261 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<2> LOC=AG28;
|
| 262 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II;
|
| 263 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<1> LOC=AH27;
|
| 264 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II;
|
| 265 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<0> LOC=AH29;
|
| 266 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II;
|
| 267 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<2> LOC=AC27;
|
| 268 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<2> IOSTANDARD = SSTL2_II;
|
| 269 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<1> LOC=AD29;
|
| 270 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<1> IOSTANDARD = SSTL2_II;
|
| 271 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<0> LOC=AB23;
|
| 272 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<0> IOSTANDARD = SSTL2_II;
|
| 273 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<2> LOC=AC28;
|
| 274 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<2> IOSTANDARD = SSTL2_II;
|
| 275 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<1> LOC=AD30;
|
| 276 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<1> IOSTANDARD = SSTL2_II;
|
| 277 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<0> LOC=AB24;
|
| 278 |
|
|
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<0> IOSTANDARD = SSTL2_II;
|
| 279 |
|
|
|
| 280 |
|
|
#Net fpga_0_net_gnd_pin LOC=G12;
|
| 281 |
|
|
#Net fpga_0_net_gnd_pin IOSTANDARD = LVTTL;
|
| 282 |
|
|
#Net fpga_0_net_gnd_pin SLEW = SLOW;
|
| 283 |
|
|
#Net fpga_0_net_gnd_pin DRIVE = 6;
|
| 284 |
|
|
#Net fpga_0_net_gnd_1_pin LOC=D15;
|
| 285 |
|
|
#Net fpga_0_net_gnd_1_pin IOSTANDARD = LVTTL;
|
| 286 |
|
|
#Net fpga_0_net_gnd_1_pin SLEW = SLOW;
|
| 287 |
|
|
#Net fpga_0_net_gnd_1_pin DRIVE = 6;
|
| 288 |
|
|
#Net fpga_0_net_gnd_2_pin LOC=E15;
|
| 289 |
|
|
#Net fpga_0_net_gnd_2_pin IOSTANDARD = LVTTL;
|
| 290 |
|
|
#Net fpga_0_net_gnd_2_pin SLEW = SLOW;
|
| 291 |
|
|
#Net fpga_0_net_gnd_2_pin DRIVE = 6;
|
| 292 |
|
|
#Net fpga_0_net_gnd_3_pin LOC=G10;
|
| 293 |
|
|
#Net fpga_0_net_gnd_3_pin IOSTANDARD = LVTTL;
|
| 294 |
|
|
#Net fpga_0_net_gnd_3_pin SLEW = SLOW;
|
| 295 |
|
|
#Net fpga_0_net_gnd_3_pin DRIVE = 6;
|
| 296 |
|
|
#Net fpga_0_net_gnd_4_pin LOC=E10;
|
| 297 |
|
|
#Net fpga_0_net_gnd_4_pin IOSTANDARD = LVTTL;
|
| 298 |
|
|
#Net fpga_0_net_gnd_4_pin SLEW = SLOW;
|
| 299 |
|
|
#Net fpga_0_net_gnd_4_pin DRIVE = 6;
|
| 300 |
|
|
#Net fpga_0_net_gnd_5_pin LOC=G8;
|
| 301 |
|
|
#Net fpga_0_net_gnd_5_pin IOSTANDARD = LVTTL;
|
| 302 |
|
|
#Net fpga_0_net_gnd_5_pin SLEW = SLOW;
|
| 303 |
|
|
#Net fpga_0_net_gnd_5_pin DRIVE = 6;
|
| 304 |
|
|
#Net fpga_0_net_gnd_6_pin LOC=H9;
|
| 305 |
|
|
#Net fpga_0_net_gnd_6_pin IOSTANDARD = LVTTL;
|
| 306 |
|
|
#Net fpga_0_net_gnd_6_pin SLEW = SLOW;
|
| 307 |
|
|
#Net fpga_0_net_gnd_6_pin DRIVE = 6;
|
| 308 |
|
|
Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB;
|
| 309 |
|
|
TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 10000 ps;
|
| 310 |
|
|
|
| 311 |
|
|
##########################################################################
|
| 312 |
|
|
# Manually added
|
| 313 |
|
|
##########################################################################
|
| 314 |
|
|
|
| 315 |
|
|
NET myipif_0_LEDs_pin<0> LOC = "AC4" | IOSTANDARD = LVTTL ; # Led 0
|
| 316 |
|
|
NET myipif_0_LEDs_pin<1> LOC = "AC3" | IOSTANDARD = LVTTL ; # Led 1
|
| 317 |
|
|
NET myipif_0_LEDs_pin<2> LOC = "AA6" | IOSTANDARD = LVTTL ; # Led 2
|
| 318 |
|
|
NET myipif_0_LEDs_pin<3> LOC = "AA5" | IOSTANDARD = LVTTL ; # Led 3
|
| 319 |
|
|
|
| 320 |
|
|
NET "myipif_0_SWITCHEs_pin<0>" LOC = "AC11" | IOSTANDARD = LVCMOS25 ; # Switch 0
|
| 321 |
|
|
NET "myipif_0_SWITCHEs_pin<1>" LOC = "AD11" | IOSTANDARD = LVCMOS25 ; # Switch 1
|
| 322 |
|
|
NET "myipif_0_SWITCHEs_pin<2>" LOC = "AF8" | IOSTANDARD = LVCMOS25 ; # Switch 2
|
| 323 |
|
|
NET "myipif_0_SWITCHEs_pin<3>" LOC = "AF9" | IOSTANDARD = LVCMOS25 ; # Switch 3
|
| 324 |
|
|
|
| 325 |
|
|
NET "myipif_0_BUTTONs_pin<0>" LOC = "AH1" | IOSTANDARD = LVTTL ; # Button LEFT
|
| 326 |
|
|
NET "myipif_0_BUTTONs_pin<1>" LOC = "AH2" | IOSTANDARD = LVTTL ; # Button RIGHT
|
| 327 |
|
|
NET "myipif_0_BUTTONs_pin<2>" LOC = "AH4" | IOSTANDARD = LVTTL ; # Button UP
|
| 328 |
|
|
NET "myipif_0_BUTTONs_pin<3>" LOC = "AG3" | IOSTANDARD = LVTTL ; # Button DOWN
|
| 329 |
|
|
NET "myipif_0_BUTTONs_pin<4>" LOC = "AG5" | IOSTANDARD = LVTTL ; # Button CENTER
|
| 330 |
|
|
|
| 331 |
|
|
## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE XSGA
|
| 332 |
|
|
## VIDEO OUTPUT OF THE XUP-V2PRO DEVELOPMENT SYSTEM
|
| 333 |
|
|
## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004
|
| 334 |
|
|
NET "myipif_0_VGA_VSYNCH_pin" LOC = "D11";
|
| 335 |
|
|
NET "myipif_0_VGA_HSYNCH_pin" LOC = "B8";
|
| 336 |
|
|
NET "myipif_0_VGA_OUT_BLANK_Z_pin" LOC = "A8";
|
| 337 |
|
|
NET "myipif_0_VGA_COMP_SYNCH_pin" LOC = "G12";
|
| 338 |
|
|
NET "myipif_0_VGA_OUT_PIXEL_CLOCK_pin" LOC = "H12";
|
| 339 |
|
|
|
| 340 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[7]" LOC = "H10";
|
| 341 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[6]" LOC = "C7";
|
| 342 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[5]" LOC = "D7";
|
| 343 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[4]" LOC = "F10";
|
| 344 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[3]" LOC = "F9";
|
| 345 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[2]" LOC = "G9";
|
| 346 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[1]" LOC = "H9";
|
| 347 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[0]" LOC = "G8";
|
| 348 |
|
|
|
| 349 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[7]" LOC = "E11";
|
| 350 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[6]" LOC = "G11";
|
| 351 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[5]" LOC = "H11";
|
| 352 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[4]" LOC = "C8";
|
| 353 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[3]" LOC = "D8";
|
| 354 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[2]" LOC = "D10";
|
| 355 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[1]" LOC = "E10";
|
| 356 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[0]" LOC = "G10";
|
| 357 |
|
|
|
| 358 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[7]" LOC = "E14";
|
| 359 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[6]" LOC = "D14";
|
| 360 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[5]" LOC = "D13";
|
| 361 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[4]" LOC = "C13";
|
| 362 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[3]" LOC = "J15";
|
| 363 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[2]" LOC = "H15";
|
| 364 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[1]" LOC = "E15";
|
| 365 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[0]" LOC = "D15";
|
| 366 |
|
|
|
| 367 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[*]" IOSTANDARD = LVTTL;
|
| 368 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[*]" IOSTANDARD = LVTTL;
|
| 369 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[*]" IOSTANDARD = LVTTL;
|
| 370 |
|
|
|
| 371 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[*]" SLEW = SLOW;
|
| 372 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[*]" SLEW = SLOW;
|
| 373 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[*]" SLEW = SLOW;
|
| 374 |
|
|
|
| 375 |
|
|
NET "myipif_0_VGA_OUT_BLUE_pin[*]" DRIVE = 8;
|
| 376 |
|
|
NET "myipif_0_VGA_OUT_GREEN_pin[*]" DRIVE = 8;
|
| 377 |
|
|
NET "myipif_0_VGA_OUT_RED_pin[*]" DRIVE = 8;
|
| 378 |
|
|
|
| 379 |
|
|
NET "myipif_0_VGA_VSYNCH_pin" IOSTANDARD = LVTTL;
|
| 380 |
|
|
NET "myipif_0_VGA_OUT_PIXEL_CLOCK_pin" IOSTANDARD = LVTTL;
|
| 381 |
|
|
NET "myipif_0_VGA_HSYNCH_pin" IOSTANDARD = LVTTL;
|
| 382 |
|
|
NET "myipif_0_VGA_OUT_BLANK_Z_pin" IOSTANDARD = LVTTL;
|
| 383 |
|
|
NET "myipif_0_VGA_COMP_SYNCH_pin" IOSTANDARD = LVTTL;
|
| 384 |
|
|
NET "myipif_0_VGA_VSYNCH_pin" DRIVE = 12;
|
| 385 |
|
|
NET "myipif_0_VGA_OUT_PIXEL_CLOCK_pin" DRIVE = 12;
|
| 386 |
|
|
NET "myipif_0_VGA_HSYNCH_pin" DRIVE = 12;
|
| 387 |
|
|
NET "myipif_0_VGA_OUT_BLANK_Z_pin" DRIVE = 12;
|
| 388 |
|
|
NET "myipif_0_VGA_COMP_SYNCH_pin" DRIVE = 12;
|
| 389 |
|
|
|
| 390 |
|
|
NET "myipif_0_VGA_VSYNCH_pin" SLEW = SLOW;
|
| 391 |
|
|
NET "myipif_0_VGA_OUT_PIXEL_CLOCK_pin" SLEW = SLOW;
|
| 392 |
|
|
NET "myipif_0_VGA_HSYNCH_pin" SLEW = SLOW;
|
| 393 |
|
|
NET "myipif_0_VGA_OUT_BLANK_Z_pin" SLEW = SLOW;
|
| 394 |
|
|
NET "myipif_0_VGA_COMP_SYNCH_pin" SLEW = SLOW;
|
| 395 |
|
|
##########################################################################
|
| 396 |
|
|
|
