OpenCores
URL https://opencores.org/ocsvn/mjpeg-decoder/mjpeg-decoder/trunk

Subversion Repositories mjpeg-decoder

[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [implementation/] [jpeg_checkff_fifo_fifo_generator_v2_3_xst_1_blkmemdp_v6_2_xst.edn] - Blame information for rev 8

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1 2 smanz 
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
2 
(status (written (timeStamp 2008 1 31 19 30 37)
3 
   (author "Xilinx, Inc.")
4 
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i"))))
5 
   (comment "
6 
      This file is owned and controlled by Xilinx and must be used
7 
      solely for design, simulation, implementation and creation of
8 
      design files limited to Xilinx devices or technologies. Use
9 
      with non-Xilinx devices or technologies is expressly prohibited
10 
      and immediately terminates your license.
11 
 
12 
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
13 
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
14 
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
15 
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
16 
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
17 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
18 
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
19 
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
20 
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
21 
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
22 
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
23 
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 
      FOR A PARTICULAR PURPOSE.
25 
 
26 
      Xilinx products are not intended for use in life support
27 
      appliances, devices, or systems. Use in such applications are
28 
      expressly prohibited.
29 
 
30 
      (c) Copyright 1995-2006 Xilinx, Inc.
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      All rights reserved.
32 
 
33 
   ")
34 
   (comment "Core parameters: ")
35 
       (comment "c_reg_inputsb = 0 ")
36 
       (comment "c_reg_inputsa = 0 ")
37 
       (comment "c_has_ndb = 0 ")
38 
       (comment "c_has_nda = 0 ")
39 
       (comment "c_ytop_addr = 1024 ")
40 
       (comment "c_has_rfdb = 0 ")
41 
       (comment "c_has_rfda = 0 ")
42 
       (comment "c_ywea_is_high = 1 ")
43 
       (comment "c_yena_is_high = 1 ")
44 
       (comment "InstanceName = jpeg_checkff_fifo_fifo_generator_v2_3_xst_1_blkmemdp_v6_2_xst ")
45 
       (comment "c_yhierarchy = hierarchy1 ")
46 
       (comment "c_yclka_is_rising = 1 ")
47 
       (comment "c_family = virtex2p ")
48 
       (comment "c_ysinita_is_high = 1 ")
49 
       (comment "c_ybottom_addr = 0 ")
50 
       (comment "c_width_b = 12 ")
51 
       (comment "c_width_a = 12 ")
52 
       (comment "c_sinita_value = 0000 ")
53 
       (comment "c_sinitb_value = 000 ")
54 
       (comment "c_limit_data_pitch = 18 ")
55 
       (comment "c_write_modeb = 0 ")
56 
       (comment "c_write_modea = 0 ")
57 
       (comment "c_has_rdyb = 0 ")
58 
       (comment "c_yuse_single_primitive = 0 ")
59 
       (comment "c_has_rdya = 0 ")
60 
       (comment "c_addra_width = 11 ")
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       (comment "c_addrb_width = 11 ")
62 
       (comment "c_has_limit_data_pitch = 0 ")
63 
       (comment "c_default_data = 0000 ")
64 
       (comment "c_pipe_stages_b = 0 ")
65 
       (comment "c_yweb_is_high = 1 ")
66 
       (comment "c_yenb_is_high = 1 ")
67 
       (comment "c_pipe_stages_a = 0 ")
68 
       (comment "c_yclkb_is_rising = 1 ")
69 
       (comment "c_yydisable_warnings = 1 ")
70 
       (comment "c_enable_rlocs = 0 ")
71 
       (comment "c_ysinitb_is_high = 1 ")
72 
       (comment "c_has_web = 0 ")
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       (comment "c_has_default_data = 1 ")
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       (comment "c_has_wea = 1 ")
75 
       (comment "c_has_sinitb = 1 ")
76 
       (comment "c_has_sinita = 1 ")
77 
       (comment "c_has_dinb = 0 ")
78 
       (comment "c_has_dina = 1 ")
79 
       (comment "c_ymake_bmm = 0 ")
80 
       (comment "c_has_enb = 1 ")
81 
       (comment "c_has_ena = 0 ")
82 
       (comment "c_mem_init_file = mif_file_16_1 ")
83 
       (comment "c_depth_b = 2048 ")
84 
       (comment "c_depth_a = 2048 ")
85 
       (comment "c_has_doutb = 1 ")
86 
       (comment "c_has_douta = 0 ")
87 
       (comment "c_yprimitive_type = 4kx4 ")
88 
   (external xilinxun (edifLevel 0)
89 
      (technology (numberDefinition))
90 
       (cell VCC (cellType GENERIC)
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           (view view_1 (viewType NETLIST)
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               (interface
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                   (port P (direction OUTPUT))
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               )
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       )
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       (cell GND (cellType GENERIC)
98 
           (view view_1 (viewType NETLIST)
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101 
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102 
           )
103 
       )
104 
       (cell RAMB16_S4_S4 (cellType GENERIC)
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           (view view_1 (viewType NETLIST)
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                   (port WEA (direction INPUT))
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                   (port CLKA (direction INPUT))
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                   (port (rename DIA_0_ "DIA<0>") (direction INPUT))
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                   (port (rename DIA_1_ "DIA<1>") (direction INPUT))
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                   (port (rename DIA_2_ "DIA<2>") (direction INPUT))
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                   (port (rename DIA_3_ "DIA<3>") (direction INPUT))
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                   (port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
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                   (port (rename DOA_1_ "DOA<1>") (direction OUTPUT))
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                   (port (rename DOA_2_ "DOA<2>") (direction OUTPUT))
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                   (port (rename DOA_3_ "DOA<3>") (direction OUTPUT))
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                   (port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
120 
                   (port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
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                   (port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
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                   (port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
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                   (port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
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125 
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                   (port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
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                   (port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT))
130 
                   (port (rename ADDRA_11_ "ADDRA<11>") (direction INPUT))
131 
                   (port WEB (direction INPUT))
132 
                   (port ENB (direction INPUT))
133 
                   (port SSRB (direction INPUT))
134 
                   (port CLKB (direction INPUT))
135 
                   (port (rename DIB_0_ "DIB<0>") (direction INPUT))
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                   (port (rename DIB_1_ "DIB<1>") (direction INPUT))
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                   (port (rename DIB_2_ "DIB<2>") (direction INPUT))
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                   (port (rename DIB_3_ "DIB<3>") (direction INPUT))
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                   (port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
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                   (port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
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                   (port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
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                   (port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
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                   (port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
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                   (port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
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                   (port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
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148 
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                   (port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
150 
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151 
                   (port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
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                   (port (rename ADDRB_9_ "ADDRB<9>") (direction INPUT))
153 
                   (port (rename ADDRB_10_ "ADDRB<10>") (direction INPUT))
154 
                   (port (rename ADDRB_11_ "ADDRB<11>") (direction INPUT))
155 
               )
156 
           )
157 
       )
158 
       (cell RAMB16_S9_S9 (cellType GENERIC)
159 
           (view view_1 (viewType NETLIST)
160 
               (interface
161 
                   (port WEA (direction INPUT))
162 
                   (port ENA (direction INPUT))
163 
                   (port SSRA (direction INPUT))
164 
                   (port CLKA (direction INPUT))
165 
                   (port (rename DIA_0_ "DIA<0>") (direction INPUT))
166 
                   (port (rename DIA_1_ "DIA<1>") (direction INPUT))
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                   (port (rename DIA_2_ "DIA<2>") (direction INPUT))
168 
                   (port (rename DIA_3_ "DIA<3>") (direction INPUT))
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                   (port (rename DIA_4_ "DIA<4>") (direction INPUT))
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                   (port (rename DIA_7_ "DIA<7>") (direction INPUT))
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                   (port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
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                   (port (rename DOA_1_ "DOA<1>") (direction OUTPUT))
175 
                   (port (rename DOA_2_ "DOA<2>") (direction OUTPUT))
176 
                   (port (rename DOA_3_ "DOA<3>") (direction OUTPUT))
177 
                   (port (rename DOA_4_ "DOA<4>") (direction OUTPUT))
178 
                   (port (rename DOA_5_ "DOA<5>") (direction OUTPUT))
179 
                   (port (rename DOA_6_ "DOA<6>") (direction OUTPUT))
180 
                   (port (rename DOA_7_ "DOA<7>") (direction OUTPUT))
181 
                   (port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
182 
                   (port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
183 
                   (port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
184 
                   (port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
185 
                   (port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
186 
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187 
                   (port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
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                   (port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
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                   (port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
190 
                   (port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
191 
                   (port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT))
192 
                   (port (rename DIPA_0_ "DIPA<0>") (direction INPUT))
193 
                   (port (rename DOPA_0_ "DOPA<0>") (direction OUTPUT))
194 
                   (port WEB (direction INPUT))
195 
                   (port ENB (direction INPUT))
196 
                   (port SSRB (direction INPUT))
197 
                   (port CLKB (direction INPUT))
198 
                   (port (rename DIB_0_ "DIB<0>") (direction INPUT))
199 
                   (port (rename DIB_1_ "DIB<1>") (direction INPUT))
200 
                   (port (rename DIB_2_ "DIB<2>") (direction INPUT))
201 
                   (port (rename DIB_3_ "DIB<3>") (direction INPUT))
202 
                   (port (rename DIB_4_ "DIB<4>") (direction INPUT))
203 
                   (port (rename DIB_5_ "DIB<5>") (direction INPUT))
204 
                   (port (rename DIB_6_ "DIB<6>") (direction INPUT))
205 
                   (port (rename DIB_7_ "DIB<7>") (direction INPUT))
206 
                   (port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
207 
                   (port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
208 
                   (port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
209 
                   (port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
210 
                   (port (rename DOB_4_ "DOB<4>") (direction OUTPUT))
211 
                   (port (rename DOB_5_ "DOB<5>") (direction OUTPUT))
212 
                   (port (rename DOB_6_ "DOB<6>") (direction OUTPUT))
213 
                   (port (rename DOB_7_ "DOB<7>") (direction OUTPUT))
214 
                   (port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
215 
                   (port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
216 
                   (port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
217 
                   (port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT))
218 
                   (port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT))
219 
                   (port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT))
220 
                   (port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
221 
                   (port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT))
222 
                   (port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
223 
                   (port (rename ADDRB_9_ "ADDRB<9>") (direction INPUT))
224 
                   (port (rename ADDRB_10_ "ADDRB<10>") (direction INPUT))
225 
                   (port (rename DIPB_0_ "DIPB<0>") (direction INPUT))
226 
                   (port (rename DOPB_0_ "DOPB<0>") (direction OUTPUT))
227 
               )
228 
           )
229 
       )
230 
   )
231 
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
232 
(cell jpeg_checkff_fifo_fifo_generator_v2_3_xst_1_blkmemdp_v6_2_xst
233 
 (cellType GENERIC) (view view_1 (viewType NETLIST)
234 
  (interface
235 
   (port ( rename dina_11_ "dina<11>") (direction INPUT))
236 
   (port ( rename dina_10_ "dina<10>") (direction INPUT))
237 
   (port ( rename dina_9_ "dina<9>") (direction INPUT))
238 
   (port ( rename dina_8_ "dina<8>") (direction INPUT))
239 
   (port ( rename dina_7_ "dina<7>") (direction INPUT))
240 
   (port ( rename dina_6_ "dina<6>") (direction INPUT))
241 
   (port ( rename dina_5_ "dina<5>") (direction INPUT))
242 
   (port ( rename dina_4_ "dina<4>") (direction INPUT))
243 
   (port ( rename dina_3_ "dina<3>") (direction INPUT))
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   (port ( rename dina_2_ "dina<2>") (direction INPUT))
245 
   (port ( rename dina_1_ "dina<1>") (direction INPUT))
246 
   (port ( rename dina_0_ "dina<0>") (direction INPUT))
247 
   (port ( rename dinb_11_ "dinb<11>") (direction INPUT))
248 
   (port ( rename dinb_10_ "dinb<10>") (direction INPUT))
249 
   (port ( rename dinb_9_ "dinb<9>") (direction INPUT))
250 
   (port ( rename dinb_8_ "dinb<8>") (direction INPUT))
251 
   (port ( rename dinb_7_ "dinb<7>") (direction INPUT))
252 
   (port ( rename dinb_6_ "dinb<6>") (direction INPUT))
253 
   (port ( rename dinb_5_ "dinb<5>") (direction INPUT))
254 
   (port ( rename dinb_4_ "dinb<4>") (direction INPUT))
255 
   (port ( rename dinb_3_ "dinb<3>") (direction INPUT))
256 
   (port ( rename dinb_2_ "dinb<2>") (direction INPUT))
257 
   (port ( rename dinb_1_ "dinb<1>") (direction INPUT))
258 
   (port ( rename dinb_0_ "dinb<0>") (direction INPUT))
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   (port ( rename ena "ena") (direction INPUT))
260 
   (port ( rename enb "enb") (direction INPUT))
261 
   (port ( rename wea "wea") (direction INPUT))
262 
   (port ( rename web "web") (direction INPUT))
263 
   (port ( rename sinita "sinita") (direction INPUT))
264 
   (port ( rename sinitb "sinitb") (direction INPUT))
265 
   (port ( rename nda "nda") (direction INPUT))
266 
   (port ( rename ndb "ndb") (direction INPUT))
267 
   (port ( rename clka "clka") (direction INPUT))
268 
   (port ( rename clkb "clkb") (direction INPUT))
269 
   (port ( rename addra_10_ "addra<10>") (direction INPUT))
270 
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271 
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   (port ( rename addra_3_ "addra<3>") (direction INPUT))
277 
   (port ( rename addra_2_ "addra<2>") (direction INPUT))
278 
   (port ( rename addra_1_ "addra<1>") (direction INPUT))
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   (port ( rename addra_0_ "addra<0>") (direction INPUT))
280 
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281 
   (port ( rename addrb_9_ "addrb<9>") (direction INPUT))
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   (port ( rename addrb_8_ "addrb<8>") (direction INPUT))
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284 
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   (port ( rename addrb_4_ "addrb<4>") (direction INPUT))
287 
   (port ( rename addrb_3_ "addrb<3>") (direction INPUT))
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   (port ( rename addrb_2_ "addrb<2>") (direction INPUT))
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   (port ( rename addrb_1_ "addrb<1>") (direction INPUT))
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   (port ( rename addrb_0_ "addrb<0>") (direction INPUT))
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   (port ( rename rdya "rdya") (direction OUTPUT))
292 
   (port ( rename rdyb "rdyb") (direction OUTPUT))
293 
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294 
   (port ( rename rfdb "rfdb") (direction OUTPUT))
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   (port ( rename douta_2_ "douta<2>") (direction OUTPUT))
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   (port ( rename douta_1_ "douta<1>") (direction OUTPUT))
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   (port ( rename douta_0_ "douta<0>") (direction OUTPUT))
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   (port ( rename doutb_9_ "doutb<9>") (direction OUTPUT))
310 
   (port ( rename doutb_8_ "doutb<8>") (direction OUTPUT))
311 
   (port ( rename doutb_7_ "doutb<7>") (direction OUTPUT))
312 
   (port ( rename doutb_6_ "doutb<6>") (direction OUTPUT))
313 
   (port ( rename doutb_5_ "doutb<5>") (direction OUTPUT))
314 
   (port ( rename doutb_4_ "doutb<4>") (direction OUTPUT))
315 
   (port ( rename doutb_3_ "doutb<3>") (direction OUTPUT))
316 
   (port ( rename doutb_2_ "doutb<2>") (direction OUTPUT))
317 
   (port ( rename doutb_1_ "doutb<1>") (direction OUTPUT))
318 
   (port ( rename doutb_0_ "doutb<0>") (direction OUTPUT))
319 
   )
320 
  (contents
321 
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
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   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
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   (instance B8
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467 
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470 
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471 
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472 
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      (property WRITE_MODE_B (string "WRITE_FIRST"))
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476 
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477 
   (net N0
478 
    (joined
479 
      (portRef G (instanceRef GND))
480 
      (portRef WEB (instanceRef B8))
481 
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482 
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485 
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486 
      (portRef DIB_5_ (instanceRef B8))
487 
      (portRef DIB_6_ (instanceRef B8))
488 
      (portRef DIB_7_ (instanceRef B8))
489 
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490 
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491 
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492 
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493 
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494 
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495 
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496 
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497 
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498 
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499 
   )
500 
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501 
    (joined
502 
      (portRef P (instanceRef VCC))
503 
      (portRef ENA (instanceRef B8))
504 
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505 
    )
506 
   )
507 
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508 
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509 
      (portRef dina_11_)
510 
      (portRef DIA_2_ (instanceRef B12))
511 
    )
512 
   )
513 
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514 
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515 
      (portRef dina_10_)
516 
      (portRef DIA_1_ (instanceRef B12))
517 
    )
518 
   )
519 
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520 
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521 
      (portRef dina_9_)
522 
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523 
    )
524 
   )
525 
   (net (rename N5 "dina<8>")
526 
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527 
      (portRef dina_8_)
528 
      (portRef DIPA_0_ (instanceRef B8))
529 
    )
530 
   )
531 
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532 
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533 
      (portRef dina_7_)
534 
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535 
    )
536 
   )
537 
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538 
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539 
      (portRef dina_6_)
540 
      (portRef DIA_6_ (instanceRef B8))
541 
    )
542 
   )
543 
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544 
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545 
      (portRef dina_5_)
546 
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547 
    )
548 
   )
549 
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550 
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551 
      (portRef dina_4_)
552 
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553 
    )
554 
   )
555 
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556 
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557 
      (portRef dina_3_)
558 
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559 
    )
560 
   )
561 
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562 
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563 
      (portRef dina_2_)
564 
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565 
    )
566 
   )
567 
   (net (rename N12 "dina<1>")
568 
    (joined
569 
      (portRef dina_1_)
570 
      (portRef DIA_1_ (instanceRef B8))
571 
    )
572 
   )
573 
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574 
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575 
      (portRef dina_0_)
576 
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577 
    )
578 
   )
579 
   (net (rename N27 "enb")
580 
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581 
      (portRef enb)
582 
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583 
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584 
    )
585 
   )
586 
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587 
    (joined
588 
      (portRef wea)
589 
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590 
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591 
    )
592 
   )
593 
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594 
    (joined
595 
      (portRef sinita)
596 
      (portRef SSRA (instanceRef B8))
597 
      (portRef SSRA (instanceRef B12))
598 
    )
599 
   )
600 
   (net (rename N31 "sinitb")
601 
    (joined
602 
      (portRef sinitb)
603 
      (portRef SSRB (instanceRef B8))
604 
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605 
    )
606 
   )
607 
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608 
    (joined
609 
      (portRef clka)
610 
      (portRef CLKA (instanceRef B8))
611 
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612 
    )
613 
   )
614 
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615 
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616 
      (portRef clkb)
617 
      (portRef CLKB (instanceRef B8))
618 
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619 
    )
620 
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621 
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622 
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623 
      (portRef addra_10_)
624 
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625 
      (portRef ADDRA_10_ (instanceRef B12))
626 
    )
627 
   )
628 
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629 
    (joined
630 
      (portRef addra_9_)
631 
      (portRef ADDRA_9_ (instanceRef B8))
632 
      (portRef ADDRA_9_ (instanceRef B12))
633 
    )
634 
   )
635 
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636 
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637 
      (portRef addra_8_)
638 
      (portRef ADDRA_8_ (instanceRef B8))
639 
      (portRef ADDRA_8_ (instanceRef B12))
640 
    )
641 
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642 
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643 
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644 
      (portRef addra_7_)
645 
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646 
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647 
    )
648 
   )
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650 
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651 
      (portRef addra_6_)
652 
      (portRef ADDRA_6_ (instanceRef B8))
653 
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654 
    )
655 
   )
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657 
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658 
      (portRef addra_5_)
659 
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660 
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661 
    )
662 
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663 
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664 
    (joined
665 
      (portRef addra_4_)
666 
      (portRef ADDRA_4_ (instanceRef B8))
667 
      (portRef ADDRA_4_ (instanceRef B12))
668 
    )
669 
   )
670 
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671 
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672 
      (portRef addra_3_)
673 
      (portRef ADDRA_3_ (instanceRef B8))
674 
      (portRef ADDRA_3_ (instanceRef B12))
675 
    )
676 
   )
677 
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678 
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679 
      (portRef addra_2_)
680 
      (portRef ADDRA_2_ (instanceRef B8))
681 
      (portRef ADDRA_2_ (instanceRef B12))
682 
    )
683 
   )
684 
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685 
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686 
      (portRef addra_1_)
687 
      (portRef ADDRA_1_ (instanceRef B8))
688 
      (portRef ADDRA_1_ (instanceRef B12))
689 
    )
690 
   )
691 
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692 
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693 
      (portRef addra_0_)
694 
      (portRef ADDRA_0_ (instanceRef B8))
695 
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696 
    )
697 
   )
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699 
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700 
      (portRef addrb_10_)
701 
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702 
      (portRef ADDRB_10_ (instanceRef B12))
703 
    )
704 
   )
705 
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706 
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707 
      (portRef addrb_9_)
708 
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709 
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710 
    )
711 
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713 
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714 
      (portRef addrb_8_)
715 
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716 
      (portRef ADDRB_8_ (instanceRef B12))
717 
    )
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719 
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720 
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721 
      (portRef addrb_7_)
722 
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723 
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724 
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727 
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728 
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729 
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730 
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731 
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734 
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735 
      (portRef addrb_5_)
736 
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737 
      (portRef ADDRB_5_ (instanceRef B12))
738 
    )
739 
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740 
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741 
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742 
      (portRef addrb_4_)
743 
      (portRef ADDRB_4_ (instanceRef B8))
744 
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745 
    )
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749 
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750 
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751 
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756 
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757 
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762 
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763 
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764 
      (portRef ADDRB_1_ (instanceRef B8))
765 
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766 
    )
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769 
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770 
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771 
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772 
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773 
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777 
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778 
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779 
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780 
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783 
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784 
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785 
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789 
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790 
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791 
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795 
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801 
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802 
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807 
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813 
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814 
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815 
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819 
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821 
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825 
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826 
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831 
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832 
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833 
    )
834 
   )
835 
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837 
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838 
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839 
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843 
      (portRef doutb_0_)
844 
      (portRef DOB_0_ (instanceRef B8))
845 
    )
846 
   )
847 
))))
848 
(design jpeg_checkff_fifo_fifo_generator_v2_3_xst_1_blkmemdp_v6_2_xst (cellRef jpeg_checkff_fifo_fifo_generator_v2_3_xst_1_blkmemdp_v6_2_xst (libraryRef test_lib))
849 
  (property X_CORE_INFO (string "null"))
850 
  (property PART (string "XC2VP20-6-ff896") (owner "Xilinx")))
851 
)

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