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URL https://opencores.org/ocsvn/mjpeg-decoder/mjpeg-decoder/trunk

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[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [implementation/] [jpeg_qt_sr.edn] - Blame information for rev 2

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Line No. Rev Author Line
1 2 smanz
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
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(status (written (timeStamp 2008 4 25 17 32 0)
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   (author "Xilinx, Inc.")
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   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i"))))
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   (comment "
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      This file is owned and controlled by Xilinx and must be used
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      solely for design, simulation, implementation and creation of
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      design files limited to Xilinx devices or technologies. Use
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      with non-Xilinx devices or technologies is expressly prohibited
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      and immediately terminates your license.
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      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
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      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
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      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
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      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
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      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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      FOR A PARTICULAR PURPOSE.
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      Xilinx products are not intended for use in life support
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      appliances, devices, or systems. Use in such applications are
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      expressly prohibited.
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      (c) Copyright 1995-2006 Xilinx, Inc.
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      All rights reserved.
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   ")
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   (comment "Core parameters: ")
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       (comment "c_has_aset = 0 ")
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       (comment "c_elaboration_dir = /home/smanz/coregen/coregen/tmp/_cg/ ")
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       (comment "c_read_mif = 0 ")
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       (comment "c_has_a = 0 ")
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       (comment "c_sync_priority = 1 ")
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       (comment "c_opt_goal = 0 ")
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       (comment "c_has_sclr = 0 ")
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       (comment "c_width = 8 ")
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       (comment "c_enable_rlocs = 0 ")
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       (comment "c_default_data_radix = 1 ")
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       (comment "c_generate_mif = 0 ")
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       (comment "c_ainit_val = 0000000000000000 ")
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       (comment "c_has_ce = 1 ")
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       (comment "c_family = virtex2p ")
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       (comment "c_has_aclr = 0 ")
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       (comment "InstanceName = jpeg_qt_sr ")
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       (comment "c_mem_init_radix = 1 ")
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       (comment "c_sync_enable = 0 ")
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       (comment "c_depth = 64 ")
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       (comment "c_has_ainit = 0 ")
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       (comment "c_sinit_val = 0000000000000000 ")
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       (comment "c_has_sset = 0 ")
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       (comment "c_has_sinit = 0 ")
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       (comment "c_mem_init_file = no_coe_file_loaded ")
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       (comment "c_shift_type = 0 ")
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       (comment "c_default_data = 00000000 ")
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       (comment "c_reg_last_bit = 0 ")
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       (comment "c_addr_width = 4 ")
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   (external xilinxun (edifLevel 0)
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      (technology (numberDefinition))
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       (cell VCC (cellType GENERIC)
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           (view view_1 (viewType NETLIST)
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               (interface
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                   (port P (direction OUTPUT))
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               )
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           )
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       )
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       (cell GND (cellType GENERIC)
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           (view view_1 (viewType NETLIST)
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               (interface
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                   (port G (direction OUTPUT))
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               )
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           )
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       )
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   )
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   (external jpeg_qt_sr_c_shift_ram_v8_0_xst_1_lib (edifLevel 0)
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       (technology (numberDefinition))
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       (cell jpeg_qt_sr_c_shift_ram_v8_0_xst_1 (cellType GENERIC)
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           (view view_1 (viewType NETLIST)
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               (interface
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                   (port ( array ( rename a "a<3:0>") 4 ) (direction INPUT))
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                   (port ( array ( rename d "d<7:0>") 8 ) (direction INPUT))
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                   (port clk (direction INPUT))
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                   (port ce (direction INPUT))
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                   (port aclr (direction INPUT))
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                   (port aset (direction INPUT))
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                   (port ainit (direction INPUT))
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                   (port sclr (direction INPUT))
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                   (port sset (direction INPUT))
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                   (port sinit (direction INPUT))
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                   (port ( array ( rename q "q<7:0>") 8 ) (direction OUTPUT))
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               )
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           )
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       )
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   )
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(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
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(cell jpeg_qt_sr
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 (cellType GENERIC) (view view_1 (viewType NETLIST)
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  (interface
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   (port ( array ( rename d "d<7:0>") 8 ) (direction INPUT))
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   (port ( rename clk "clk") (direction INPUT))
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   (port ( rename ce "ce") (direction INPUT))
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   (port ( array ( rename q "q<7:0>") 8 ) (direction OUTPUT))
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   )
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  (contents
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   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
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   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
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   (instance BU2
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      (viewRef view_1 (cellRef jpeg_qt_sr_c_shift_ram_v8_0_xst_1 (libraryRef jpeg_qt_sr_c_shift_ram_v8_0_xst_1_lib)))
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   )
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   (net (rename N6 "d<7>")
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    (joined
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      (portRef (member d 0))
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      (portRef (member d 0) (instanceRef BU2))
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    )
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   )
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   (net (rename N7 "d<6>")
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    (joined
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      (portRef (member d 1))
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      (portRef (member d 1) (instanceRef BU2))
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    )
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   )
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   (net (rename N8 "d<5>")
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    (joined
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      (portRef (member d 2))
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      (portRef (member d 2) (instanceRef BU2))
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    )
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   )
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   (net (rename N9 "d<4>")
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    (joined
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      (portRef (member d 3))
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      (portRef (member d 3) (instanceRef BU2))
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    )
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   )
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   (net (rename N10 "d<3>")
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    (joined
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      (portRef (member d 4))
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      (portRef (member d 4) (instanceRef BU2))
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    )
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   )
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   (net (rename N11 "d<2>")
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    (joined
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      (portRef (member d 5))
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      (portRef (member d 5) (instanceRef BU2))
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    )
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   )
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   (net (rename N12 "d<1>")
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    (joined
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      (portRef (member d 6))
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      (portRef (member d 6) (instanceRef BU2))
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    )
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   )
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   (net (rename N13 "d<0>")
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    (joined
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      (portRef (member d 7))
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      (portRef (member d 7) (instanceRef BU2))
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    )
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   )
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   (net (rename N14 "clk")
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    (joined
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      (portRef clk)
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      (portRef clk (instanceRef BU2))
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    )
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   )
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   (net (rename N15 "ce")
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    (joined
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      (portRef ce)
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      (portRef ce (instanceRef BU2))
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    )
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   )
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   (net (rename N22 "q<7>")
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    (joined
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      (portRef (member q 0))
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      (portRef (member q 0) (instanceRef BU2))
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    )
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   )
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   (net (rename N23 "q<6>")
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    (joined
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      (portRef (member q 1))
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      (portRef (member q 1) (instanceRef BU2))
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    )
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   )
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   (net (rename N24 "q<5>")
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    (joined
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      (portRef (member q 2))
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      (portRef (member q 2) (instanceRef BU2))
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    )
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   )
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   (net (rename N25 "q<4>")
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    (joined
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      (portRef (member q 3))
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      (portRef (member q 3) (instanceRef BU2))
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    )
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   )
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   (net (rename N26 "q<3>")
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    (joined
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      (portRef (member q 4))
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      (portRef (member q 4) (instanceRef BU2))
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    )
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   )
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   (net (rename N27 "q<2>")
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    (joined
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      (portRef (member q 5))
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      (portRef (member q 5) (instanceRef BU2))
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    )
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   )
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   (net (rename N28 "q<1>")
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    (joined
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      (portRef (member q 6))
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      (portRef (member q 6) (instanceRef BU2))
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    )
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   )
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   (net (rename N29 "q<0>")
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    (joined
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      (portRef (member q 7))
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      (portRef (member q 7) (instanceRef BU2))
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    )
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   )
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))))
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(design jpeg_qt_sr (cellRef jpeg_qt_sr (libraryRef test_lib))
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  (property X_CORE_INFO (string "c_shift_ram_v8_0, Coregen 8.2.03i"))
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  (property PART (string "xc2vp30-ff896-7") (owner "Xilinx")))
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)

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